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| author | Padmarao Begari <padmarao.begari@amd.com> | 2025-04-09 21:55:53 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2025-04-16 15:39:48 +0200 |
| commit | 27d7d3cf43927698ec09c7410dc1c2b21d530504 (patch) | |
| tree | b7668d6770a695052345be1b88d8ba4006ddbf77 /tools/u_boot_pylib/test_util.py | |
| parent | 142a7c6cdfe6fa537fbcdcad3ff5b60b4384a53b (diff) | |
board: xilinx: Store board info data in data section
Line 171 in README is describing that before relocation no code
should use global variable because global variables are placed
to BSS section which is initialized to 0 after relocation.
In the case of ZynqMP, where DTB reselection is enabled, the EEPROM
is read again after relocation. This prevents the issue from being
observed. However, in Versal Gen 2, where DTB reselection is also
enabled, the EEPROM is not read after relocation because it is not
yet wired in board_init(). This leads to a situation where the code
accesses an incorrect memory location, because none is really
checking the board_info is valid or not. To fix, move the board_info
into the data section and also check whether it is valid or not.
Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250409162553.588285-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions