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| author | Hrushikesh Salunke <h-salunke@ti.com> | 2025-04-16 17:38:28 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-04-24 10:45:49 -0600 |
| commit | 29602a52903f34653081e6ecbaa4a5ab056409b9 (patch) | |
| tree | 7c3885407bd19eb4835d30309475fd15bca77074 /tools/u_boot_pylib/test_util.py | |
| parent | c5db8973d7df0573d5e72fa5b9154d3c0856ec3e (diff) | |
pci: pcie_cdns_ti: Include linux/sizes.h header
Driver uses macro SZ_4G to configure inbound base address register.
The macro is used without including the header file in which it is
defined. Fix this.
Fixes: 59ad5480098 ("pci: Add TI K3 Cadence PCIe Controller")
Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions