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| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2025-03-20 10:13:24 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2025-04-16 13:42:06 +0200 |
| commit | 5b8d6dcf7ce1b9629cec02e8d17db530776de5b4 (patch) | |
| tree | bc9ef54871690897dbd9cab6f5163795e6fa7f34 /tools/u_boot_pylib/test_util.py | |
| parent | cad8f6a506f4f66669a58f74428c36d8f1bfe4d4 (diff) | |
ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers
Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ee2d1ad2e07e96f1948ab6ffe8f3c50a3b8f9be9.1742462001.git.michal.simek@amd.com
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions