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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-01-26 19:48:22 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-04-12 09:42:35 +0300 |
| commit | 6bbe348bfccea3b967aa398a6d46bcb8439d093f (patch) | |
| tree | 6b98e4ed2b38de338966d6cc7cbc91ac19d6c6ec /tools/u_boot_pylib/test_util.py | |
| parent | 407d68638fe32418d61681407effba2a303bb9ee (diff) | |
spi: tegra20_slink: fix CS polarity setup
Add missing configuration of chip select polarity. Default polarity is LOW,
which satisfies most cases but some devices require HIGH polarity and will
not work.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions