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authorTom Rini <trini@konsulko.com>2025-04-22 07:59:38 -0600
committerTom Rini <trini@konsulko.com>2025-04-22 07:59:38 -0600
commit8ab3cd0229a0ebf204cb5fd94f8a09e62825ffb4 (patch)
tree4675ee039b4959d0a76614927068be99a4777fb1 /tools/u_boot_pylib/test_util.py
parent185fdf5e94731df05748b1c576effb52ff7a3ec5 (diff)
parent0415429935d7e19595d2997ee08415d0d8052d4d (diff)
Merge tag 'u-boot-socfpga-next-20250422' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request contains updates for the SoCFPGA platform, targeting the 2025.07 release cycle. Highlights include enhancements to Agilex5 support, improvements in DDR error handling, and bridge reset handling for SoC64 devices. Key updates: Agilex5 platform enhancements: * New MMU region mappings and memory layout updates using LMB_ARCH_MEM_MAP. * Fixes for bloblist configuration, kernel FIT image generation, and VAB flow enablement. * GPIO pin control added for SDIO selection. * Marvell PHY driver enabled in defconfig. Agilex5 / SoC64 DDR subsystem: * Added ECC debug improvements for IOSSM. * Introduced LPDDR inline ECC support. * Resolved size calculation overflow in memory driver. SoC64 improvements: * Enhanced mailbox communication with the SDM to reflect various boot stage transitions. * Implemented F2S bridge reset support and updated related reset manager registers. * Expanded SoC64 CPU info reporting. General maintenance: * Additional peripherals released from reset for Arria10. * Cleanup of legacy or incorrect Kconfig implications. This patch set has been tested on Agilex 5 devkit. Passing all pipeline tests at: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/25867
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