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| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | 2025-04-03 19:07:02 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-04-22 11:47:39 +0800 |
| commit | 9acad2b4c7214bb423a6221b67b0d7ea37edbdf7 (patch) | |
| tree | 97149ff2ca69eabffcd2b78b76d60eefd9dadd81 /tools/u_boot_pylib/test_util.py | |
| parent | ef16992e3eab0eaa3c194fffd65bd8cc89050388 (diff) | |
arm: socfpga: soc64: Update reset manager registers for F2S bridge
Add reset manager registers in preparation for F2S bridge reset
support as well as the mask support to enable/disable the bridges.
Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc
These bridges are available only in Stratix10:
BIT3: f2sdram0
BIT4: f2sdram1
BIT5: f2sdram2
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions