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| author | Michal Simek <michal.simek@amd.com> | 2025-03-13 13:23:46 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2025-04-16 13:42:06 +0200 |
| commit | b58d34064ca1424132d4d48385a62d987fc169b5 (patch) | |
| tree | 975566662bec0c8ae534f30b56f4f5925d9a2365 /tools/u_boot_pylib/test_util.py | |
| parent | 65f39ea20cde0b7e3d3018245c34f10896ed6085 (diff) | |
serial: Setup default base and frequency for Versal platforms
Add useful default debug uart values for all Versal platforms to simplify
and speed up debug uart enabling.
The similar change has been done for Zynq/ZynqMP by commit ad55d99e3cc3
("serial: Setup serial base and freq for zynq/zynqmp").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/86edf3dbb6de16337aac36f5121f306f83149fc0.1741868624.git.michal.simek@amd.com
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions