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| author | Tingting Meng <tingting.meng@altera.com> | 2025-04-15 14:50:51 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-04-22 11:47:40 +0800 |
| commit | c42ce8d8bd2ed0d20ae12517caccda6a04d7276d (patch) | |
| tree | 9a30b1de1ded72677f4c90cddfd2524a263b1d54 /tools/u_boot_pylib/test_util.py | |
| parent | 52891fda68977e321043c2c4e04f6f3d55352726 (diff) | |
ddr: altera: agilex5: LPDDRs in-line ECC support
In-line ECC support was added for LPDDR by reserving the last one-eighth
of the memory space for ECC data. Full memory initialization using the
BIST MEM INIT mailbox command, based on address and size, is required to
correctly generate ECC data and enable proper ECC logic verification.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions