diff options
26 files changed, 1970 insertions, 44 deletions
@@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ VERSION = 2025 -PATCHLEVEL = 07 +PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 NAME = # *DOCUMENTATION* diff --git a/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi new file mode 100644 index 00000000000..343f10cdf9a --- /dev/null +++ b/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7d65_curiosity-u-boot.dtsi - Device Tree Include file for + * SAMA7D65 CURIOSITY. + * + * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + */ + +/{ + aliases { + serial0 = &uart6; + }; + + chosen { + bootph-all; + }; + + clocks { + slow_rc_osc: slow_rc_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + cpu@0 { + clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 26>, <&main_xtal>; + clock-names = "cpu", "master", "xtal"; + }; + }; + + soc { + bootph-all; + }; +}; + +&clk32k { + clocks = <&slow_rc_osc>, <&slow_xtal>; +}; + +&main_xtal { + bootph-all; +}; + +&pioa { + bootph-all; +}; + +&pinctrl_uart6_default { + bootph-all; +}; + +&pit64b0 { + bootph-all; +}; + +&pmc { + bootph-all; +}; + +&sdmmc1 { + assigned-clock-parents = <&pmc PMC_TYPE_CORE 27>; /* MCK1 div */ + microchip,sdcal-inverted; + no-1-8-v; +}; + +&slow_rc_osc { + bootph-all; +}; + +&slow_xtal { + bootph-all; +}; + +&uart6 { + bootph-all; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index d21534ce883..7d00f1650b4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -52,6 +52,11 @@ config SAMA7G5 select CPU_V7A select AT91RESET_EXTRST +config SAMA7D65 + bool + select CPU_V7A + select AT91RESET_EXTRST + config SAMA5D2 bool select CPU_V7A @@ -299,6 +304,13 @@ config TARGET_SAMA7G54_CURIOSITY 4Gbit SLC nand-flash, MCP16502 PMIC, 2 x Mikrobus connectors, 1 x SD-Card connector, 1 x M.2 slot, 3 x USB +config TARGET_SAMA7D65_CURIOSITY + bool "SAMA7D65 CURIOSITY board" + select SAMA7D65 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply OF_UPSTREAM + config TARGET_TAURUS bool "Support taurus" select AT91SAM9G20 @@ -365,6 +377,7 @@ source "board/atmel/sam9x60_curiosity/Kconfig" source "board/atmel/sam9x75_curiosity/Kconfig" source "board/atmel/sama7g5ek/Kconfig" source "board/atmel/sama7g54_curiosity/Kconfig" +source "board/atmel/sama7d65_curiosity/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 6da1cdffef6..4303a60e0e3 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o clock.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o clock.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o +obj-$(CONFIG_SAMA7D65) += sama7d65_devices.o obj-y += cpu.o ifneq ($(CONFIG_ATMEL_TCB_TIMER),y) ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) diff --git a/arch/arm/mach-at91/armv7/sama7d65_devices.c b/arch/arm/mach-at91/armv7/sama7d65_devices.c new file mode 100644 index 00000000000..6c6ae751b1a --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama7d65_devices.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology, Inc. + */ + +#include <asm/arch/sama7d65.h> + +char *get_cpu_name(void) +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama7d65()) + switch (extension_id) { + case ARCH_EXID_SAMA7D65: + return "SAMA7D65"; + case ARCH_EXID_SAMA7D65_DD2: + return "SAMA7D65 DDR2"; + case ARCH_EXID_SAMA7D65_D1G: + return "SAMA7D65 1Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_D2G: + return "SAMA7D65 2Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_D4G: + return "SAMA7D65 4Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_TA: + return "SAMA7D65 TA1000 SiP"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type10"; +} diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index de89714b097..0b2ddbab3be 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -27,6 +27,8 @@ # include <asm/arch/sam9x7.h> #elif defined(CONFIG_SAMA7G5) # include <asm/arch/sama7g5.h> +#elif defined(CONFIG_SAMA7D65) +# include <asm/arch/sama7d65.h> #elif defined(CONFIG_SAMA5D2) # include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) diff --git a/arch/arm/mach-at91/include/mach/sama7d65.h b/arch/arm/mach-at91/include/mach/sama7d65.h new file mode 100644 index 00000000000..8adc5c9a733 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7d65.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAMA7D65 SoC + * + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + */ + +#ifndef __SAMA7D65_H__ +#define __SAMA7D65_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FLEXCOM0 34 +#define ATMEL_ID_FLEXCOM1 35 +#define ATMEL_ID_FLEXCOM2 36 +#define ATMEL_ID_FLEXCOM3 37 +#define ATMEL_ID_FLEXCOM4 38 +#define ATMEL_ID_FLEXCOM5 39 +#define ATMEL_ID_FLEXCOM6 40 +#define ATMEL_ID_FLEXCOM7 41 +#define ATMEL_ID_FLEXCOM8 42 + +#define ATMEL_ID_SDMMC0 75 +#define ATMEL_ID_SDMMC1 76 +#define ATMEL_ID_SDMMC2 77 + +#define ATMEL_ID_PIT64B0 66 +#define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0 + +#define ATMEL_CHIPID_CIDR 0xe0020000 +#define ATMEL_CHIPID_EXID 0xe0020004 +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_PIOA 0xe0014000 +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) +#define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40) + +#define ATMEL_PIO_PORTS 5 + +#define CPU_HAS_PCR + +#define ATMEL_BASE_PMC 0xe0018000 + +#define ATMEL_BASE_WDT 0xe001c000 +#define ATMEL_BASE_RSTC 0xe001d100 +#define ATMEL_BASE_WDTS 0xe001d180 +#define ATMEL_BASE_SCKCR 0xe001d500 + +#define ATMEL_BASE_SDMMC0 0xe1204000 +#define ATMEL_BASE_SDMMC1 0xe1208000 + +#define ATMEL_BASE_PIT64B0 0xe1800000 + +#define ATMEL_BASE_FLEXCOM0 0xe1820000 +#define ATMEL_BASE_FLEXCOM1 0xe1824000 +#define ATMEL_BASE_FLEXCOM2 0xe1828000 +#define ATMEL_BASE_FLEXCOM3 0xe182c000 +#define ATMEL_BASE_FLEXCOM4 0xe2018000 +#define ATMEL_BASE_FLEXCOM5 0xe201C000 +#define ATMEL_BASE_FLEXCOM6 0xe2020000 +#define ATMEL_BASE_FLEXCOM7 0xe2024000 +#define ATMEL_BASE_FLEXCOM8 0xe281C000 + +#define ATMEL_BASE_TZC400 0xe3000000 + +#define ATMEL_BASE_UMCTL2 0xe3800000 +#define ATMEL_BASE_UMCTL2_MP 0xe38003f8 +#define ATMEL_BASE_PUBL 0xe3804000 + +#define ATMEL_NUM_FLEXCOM 11 +#define ATMEL_PIO_PORTS 5 + +#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 + +#define ARCH_ID_SAMA7D65 0x80262100 +#define ARCH_EXID_SAMA7D65 0x00000080 +#define ARCH_EXID_SAMA7D65_DD2 0x00000010 +#define ARCH_EXID_SAMA7D65_D1G 0x00000018 +#define ARCH_EXID_SAMA7D65_D2G 0x00000020 +#define ARCH_EXID_SAMA7D65_D4G 0x00000028 +#define ARCH_EXID_SAMA7D65_TA 0x00000040 + +#define cpu_is_sama7d65() (get_chip_id() == ARCH_ID_SAMA7D65) +#define cpu_is_sama7d65_S() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65)) +#define cpu_is_sama7d65_DD2() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_DD2)) +#define cpu_is_sama7d65_D1G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D1G)) +#define cpu_is_sama7d65_D2G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D2G)) +#define cpu_is_sama7d65_D4G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D4G)) +#define cpu_is_sama7d65_TA() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_TA)) + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +char *get_cpu_name(void); +#endif + +#endif /* #ifndef __SAMA7D65_H__ */ diff --git a/board/atmel/sama7d65_curiosity/Kconfig b/board/atmel/sama7d65_curiosity/Kconfig new file mode 100644 index 00000000000..21ff432f2c1 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA7D65_CURIOSITY + +config SYS_BOARD + default "sama7d65_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama7d65_curiosity" + +endif diff --git a/board/atmel/sama7d65_curiosity/MAINTAINERS b/board/atmel/sama7d65_curiosity/MAINTAINERS new file mode 100644 index 00000000000..054af3c6541 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/MAINTAINERS @@ -0,0 +1,6 @@ +SAMA7D65 CURIOSITY BOARD +M: Ryan Wanner <ryan.wanner@microchip.com> +S: Maintained +F: board/atmel/sama7d65_curiosity.c +F: include/configs/sama7d65_curiosity.h +F: configs/sama7d65_curiosity_mmc1_defconfig diff --git a/board/atmel/sama7d65_curiosity/Makefile b/board/atmel/sama7d65_curiosity/Makefile new file mode 100644 index 00000000000..56d011d1d81 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries +# +# Author: Ryan Wanner <ryan.wanner@microchip.com> + +obj-y += sama7d65_curiosity.o diff --git a/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c new file mode 100644 index 00000000000..713b1b9d959 --- /dev/null +++ b/board/atmel/sama7d65_curiosity/sama7d65_curiosity.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + * + */ + +#include <debug_uart.h> +#include <init.h> +#include <fdtdec.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama7d65.h> +#include <asm/mach-types.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void board_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 21, 0); /* LED BLUE */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 17, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 15, 1); /* LED GREEN */ +} + +int board_late_init(void) +{ + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_uart0_hw_init(void) +{ + /* FLEXCOM6 IO0 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 18, 0); + /* FLEXCOM6 IO1 */ + atmel_pio4_set_b_periph(AT91_PIO_PORTD, 19, 0); + + at91_periph_clk_enable(ATMEL_ID_FLEXCOM6); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + board_leds_init(); + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/cmd/tlv_eeprom.c b/cmd/tlv_eeprom.c index d7c229e5441..3127660dd9e 100644 --- a/cmd/tlv_eeprom.c +++ b/cmd/tlv_eeprom.c @@ -41,7 +41,7 @@ static int set_date(char *buf, const char *string); static int set_bytes(char *buf, const char *string, int *converted_accum); static void show_tlv_devices(int current_dev); -/* The EERPOM contents after being read into memory */ +/* The EEPROM contents after being read into memory */ static u8 eeprom[TLV_INFO_MAX_LEN]; static struct udevice *tlv_devices[MAX_TLV_DEVICES]; @@ -430,7 +430,7 @@ int do_tlv_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) static int has_been_read; int ret; - // If no arguments, read the EERPOM and display its contents + // If no arguments, read the EEPROM and display its contents if (argc == 1) { if (!has_been_read) { ret = read_eeprom(current_dev, eeprom); @@ -560,7 +560,7 @@ U_BOOT_CMD(tlv_eeprom, 4, 1, do_tlv_eeprom, /** * tlvinfo_find_tlv * - * This function finds the TLV with the supplied code in the EERPOM. + * This function finds the TLV with the supplied code in the EEPROM. * An offset from the beginning of the EEPROM is returned in the * eeprom_index parameter if the TLV is found. */ @@ -631,7 +631,7 @@ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval) char data[MAX_TLV_VALUE_LEN]; int eeprom_index; - // Encode each TLV type into the format to be stored in the EERPOM + // Encode each TLV type into the format to be stored in the EEPROM switch (tcode) { case TLV_CODE_PRODUCT_NAME: case TLV_CODE_PART_NUMBER: @@ -691,7 +691,7 @@ static bool tlvinfo_add_tlv(u8 *eeprom, int tcode, char *strval) // Is there room for this TLV? if ((be16_to_cpu(eeprom_hdr->totallen) + ENT_SIZE + new_tlv_len) > TLV_TOTAL_LEN_MAX) { - printf("ERROR: There is not enough room in the EERPOM to save data.\n"); + printf("ERROR: There is not enough room in the EEPROM to save data.\n"); return false; } @@ -1033,10 +1033,8 @@ int mac_read_from_eeprom(void) struct tlvinfo_header *eeprom_hdr = to_header(eeprom); int devnum = 0; // TODO: support multiple EEPROMs - puts("EEPROM: "); - if (read_eeprom(devnum, eeprom)) { - printf("Read failed.\n"); + log_err("EEPROM: read failed\n"); return -1; } @@ -1082,8 +1080,8 @@ int mac_read_from_eeprom(void) } } - printf("%s v%u len=%u\n", eeprom_hdr->signature, eeprom_hdr->version, - be16_to_cpu(eeprom_hdr->totallen)); + log_debug("EEPROM: %s v%u len=%u\n", eeprom_hdr->signature, eeprom_hdr->version, + be16_to_cpu(eeprom_hdr->totallen)); return 0; } diff --git a/common/spl/spl.c b/common/spl/spl.c index d8e26605d20..ed443c645a7 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -634,7 +634,7 @@ static int boot_from_devices(struct spl_image_info *spl_image, if (CONFIG_IS_ENABLED(SHOW_ERRORS)) ret = -ENXIO; for (loader = drv; loader != drv + n_ents; loader++) { - if (bootdev != loader->boot_device) + if (loader && bootdev != loader->boot_device) continue; if (!CONFIG_IS_ENABLED(SILENT_CONSOLE)) { if (loader) diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 65aca43e8b9..60a61086bb5 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -2,48 +2,41 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_KWD_CONFIG="board/raidsonic/ib62x0/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_IB62X0=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-ib62x0" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" +CONFIG_LTO=y +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:rootfs; ubifsload 0x800000 ${kernel}; ubifsload 0x700000 ${fdt}; ubifsumount; fdt addr 0x700000; fdt resize; fdt chosen; bootz 0x800000 - 0x700000" CONFIG_USE_PREBOOT=y CONFIG_SYS_PBSIZE=1051 # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " CONFIG_SYS_MAXARGS=32 -CONFIG_CMD_BOOTZ=y CONFIG_CMD_IDE=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -58,6 +51,5 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_LZMA=y CONFIG_BZIP2=y diff --git a/configs/sama7d65_curiosity_mmc1_defconfig b/configs/sama7d65_curiosity_mmc1_defconfig new file mode 100644 index 00000000000..e819e51b458 --- /dev/null +++ b/configs/sama7d65_curiosity_mmc1_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TEXT_BASE=0x66f00000 +CONFIG_SYS_MALLOC_F_LEN=0x11000 +CONFIG_TARGET_SAMA7D65_CURIOSITY=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60014ef0 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x70000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="microchip/at91-sama7d65_curiosity" +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xe2020200 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_LOAD_ADDR=0x62000000 +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7d65_curiosity.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_CMD_IMI=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_STRINGS=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_WGET=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DNS=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ARP_TIMEOUT=200 +CONFIG_NET_RETRY_COUNT=50 +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_DM_MTD=y +CONFIG_DM_NAND_ATMEL=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_DM_SPI_FLASH=n +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=133000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=n +CONFIG_SPI_FLASH_SOFT_RESET=n +CONFIG_SPI_FLASH_MACRONIX=n +CONFIG_SPI_FLASH_MX66LM1G45G=n +CONFIG_SPI_FLASH_SST=n +CONFIG_SPI_FLASH_MTD=n +CONFIG_DM_ETH=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH_PHY=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_RESET=y +CONFIG_RESET_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=n +# CONFIG_ATMEL_SPI is not set +CONFIG_TIMER=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_RESET=y +CONFIG_SYSRESET_AT91=y +CONFIG_MCHP_PIT64B_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER_HII is not set +CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index f2ffcf3d331..7aa36166a5d 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -55,7 +55,7 @@ Current Status * U-Boot v2025.07 was released on Monday, 07 July 2025. -* The Merge Window for the next release (|next_ver|) is **open** until the -rc1 +* The Merge Window for the next release (|next_ver|) is **closed** with the -rc1 release on Monday, 28 July 2025. * The next branch is now **closed** until the -rc2 release on Monday, 11 August @@ -69,9 +69,9 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -.. For the next scheduled release, release candidates were made on:: +For the next scheduled release, release candidates were made on:: -.. * U-Boot |next_ver|-rc1 was released on Mon 28 July 2025. +* U-Boot |next_ver|-rc1 was released on Mon 28 July 2025. .. * U-Boot |next_ver|-rc2 was released on Mon 11 August 2025. diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index d544ffb5ffb..e992a1aa822 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -99,7 +99,7 @@ static int atibios_debug_mode(BE_VGAInfo *vga_info, RMREGS *regs, regs->e.edi = buffer_adr; info = buffer; memset(info, '\0', sizeof(*info)); - strcpy(info->signature, "VBE2"); + memcpy(info->signature, "VBE2", 4); BE_int86(0x10, regs, regs); if (regs->e.eax != 0x4f) { debug("VESA_GET_INFO: error %x\n", regs->e.eax); diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 1ff27b2af95..29a166f7fe9 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -66,7 +66,7 @@ void x86emuOp2_illegal_op( END_OF_INSTR(); } -#define xorl(a,b) ((a) && !(b)) || (!(a) && (b)) +#define xorl(a, b) (((a) && !(b)) || (!(a) && (b))) /**************************************************************************** REMARKS: diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 6cca861f81c..96cc2bc3abc 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_AT91_UTMI) += clk-utmi.o obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o obj-$(CONFIG_AT91_SAM9X60_USB) += clk-sam9x60-usb.o obj-$(CONFIG_SAMA7G5) += sama7g5.o +obj-$(CONFIG_SAMA7D65) += sama7d65.o obj-$(CONFIG_SAM9X60) += sam9x60.o obj-$(CONFIG_SAM9X7) += sam9x7.o else diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index d28775d64d3..cdc5271fa83 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -37,7 +37,7 @@ #define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK) -#define MASTER_MAX_ID 4 +#define MASTER_MAX_ID 10 struct clk_master { void __iomem *base; diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index df8172bccac..65be2775ac3 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -32,7 +32,7 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) -#define PLL_MAX_ID 7 +#define PLL_MAX_ID 8 struct sam9x60_pll { void __iomem *base; diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c new file mode 100644 index 00000000000..8d2c25e6fa9 --- /dev/null +++ b/drivers/clk/at91/sama7d65.c @@ -0,0 +1,1451 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SAMA7D65 PMC clock support. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <Ryan.Wanner@microchip.com> + * + */ + +#include <clk-uclass.h> +#include <dm.h> +#include <dt-bindings/clock/at91.h> +#include <linux/clk-provider.h> + +#include "pmc.h" + +/** + * Clock identifiers to be used in conjunction with macros like + * AT91_TO_CLK_ID() + * + * @ID_MD_SLCK: TD slow clock identifier + * @ID_TD_SLCK: MD slow clock identifier + * @ID_MAIN_XTAL: Main Xtal clock identifier + * @ID_MAIN_RC: Main RC clock identifier + * @ID_MAIN_RC_OSC: Main RC Oscillator clock identifier + * @ID_MAIN_OSC: Main Oscillator clock identifier + * @ID_MAINCK: MAINCK clock identifier + * @ID_PLL_CPU_FRAC: CPU PLL fractional clock identifier + * @ID_PLL_CPU_DIV: CPU PLL divider clock identifier + * @ID_PLL_SYS_FRAC: SYS PLL fractional clock identifier + * @ID_PLL_SYS_DIV: SYS PLL divider clock identifier + * @ID_PLL_DDR_FRAC: DDR PLL fractional clock identifier + * @ID_PLL_DDR_DIV: DDR PLL divider clock identifier + * @ID_PLL_GPU_FRAC: GPU PLL fractional clock identifier + * @ID_PLL_GPU_DIV: GPU PLL divider clock identifier + * @ID_PLL_BAUD_FRAC: Baud PLL fractional clock identifier + * @ID_PLL_BAUD_DIV: Baud PLL divider clock identifier + * @ID_PLL_AUDIO_FRAC: Audio PLL fractional clock identifier + * @ID_PLL_AUDIO_DIVPMC: Audio PLL PMC divider clock identifier + * @ID_PLL_AUDIO_DIVIO: Audio PLL IO divider clock identifier + * @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier + * @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier + * @ID_PLL_LVDS_FRAC: LVDS PLL fractional clock identifier + * @ID_PLL_LVDS_DIV: LVDS PLL divider clock identifier + * @ID_PLL_USB_FRAC: USB PLL fractional clock identifier + * @ID_PLL_USB_DIV: USB PLL divider clock identifier + + * @ID_MCK0_PRES: MCK0 PRES clock identifier + * @ID_MCK0_DIV: MCK0 DIV clock identifier + * @ID_MCK1: MCK1 clock identifier + * @ID_MCK2: MCK2 clock identifier + * @ID_MCK3: MCK3 clock identifier + * @ID_MCK4: MCK4 clock identifier + + * @ID_UTMI: UTMI clock identifier + + * @ID_PROG0: Programmable 0 clock identifier + * @ID_PROG1: Programmable 1 clock identifier + * @ID_PROG2: Programmable 2 clock identifier + * @ID_PROG3: Programmable 3 clock identifier + * @ID_PROG4: Programmable 4 clock identifier + * @ID_PROG5: Programmable 5 clock identifier + * @ID_PROG6: Programmable 6 clock identifier + * @ID_PROG7: Programmable 7 clock identifier + + * @ID_PCK0: System clock 0 clock identifier + * @ID_PCK1: System clock 1 clock identifier + * @ID_PCK2: System clock 2 clock identifier + * @ID_PCK3: System clock 3 clock identifier + * @ID_PCK4: System clock 4 clock identifier + * @ID_PCK5: System clock 5 clock identifier + * @ID_PCK6: System clock 6 clock identifier + * @ID_PCK7: System clock 7 clock identifier + */ +enum pmc_clk_ids { + ID_MD_SLCK = 0, + ID_TD_SLCK = 1, + ID_MAIN_XTAL = 2, + ID_MAIN_RC = 3, + ID_MAIN_RC_OSC = 4, + ID_MAIN_OSC = 5, + ID_MAINCK = 6, + + ID_PLL_CPU_FRAC = 7, + ID_PLL_CPU_DIV = 8, + ID_PLL_SYS_FRAC = 9, + ID_PLL_SYS_DIV = 10, + ID_PLL_DDR_FRAC = 11, + ID_PLL_DDR_DIV = 12, + ID_PLL_GPU_FRAC = 13, + ID_PLL_GPU_DIV = 14, + ID_PLL_BAUD_FRAC = 15, + ID_PLL_BAUD_DIV = 16, + ID_PLL_AUDIO_FRAC = 17, + ID_PLL_AUDIO_DIVPMC = 18, + ID_PLL_AUDIO_DIVIO = 19, + ID_PLL_ETH_FRAC = 20, + ID_PLL_ETH_DIV = 21, + ID_PLL_LVDS_FRAC = 22, + ID_PLL_LVDS_DIV = 23, + ID_PLL_USB_FRAC = 24, + ID_PLL_USB_DIV = 25, + + ID_MCK0_DIV = 26, + ID_MCK1 = 27, + ID_MCK2 = 28, + ID_MCK3 = 29, + ID_MCK4 = 30, + ID_MCK5 = 31, + ID_MCK6 = 32, + ID_MCK7 = 33, + ID_MCK8 = 34, + ID_MCK9 = 35, + + ID_UTMI = 36, + + ID_PROG0 = 37, + ID_PROG1 = 38, + ID_PROG2 = 39, + ID_PROG3 = 40, + ID_PROG4 = 41, + ID_PROG5 = 42, + ID_PROG6 = 43, + ID_PROG7 = 44, + + ID_PCK0 = 45, + ID_PCK1 = 46, + ID_PCK2 = 47, + ID_PCK3 = 48, + ID_PCK4 = 49, + ID_PCK5 = 50, + ID_PCK6 = 51, + ID_PCK7 = 52, + + ID_MCK0_PRES = 53, + + ID_MAX, +}; + +/** + * PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +/* Clock names used as parents for multiple clocks. */ +static const char *clk_names[] = { + [ID_MAIN_RC] = "main_rc", + [ID_MAIN_RC_OSC] = "main_rc_osc", + [ID_MAIN_OSC] = "main_osc", + [ID_MAINCK] = "mainck", + [ID_PLL_CPU_DIV] = "cpupll_divpmcck", + [ID_PLL_SYS_DIV] = "syspll_divpmcck", + [ID_PLL_DDR_DIV] = "ddrpll_divpmcck", + [ID_PLL_GPU_DIV] = "gpupll_divpmcck", + [ID_PLL_BAUD_DIV] = "baudpll_divpmcck", + [ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck", + [ID_PLL_AUDIO_DIVIO] = "audiopll_diviock", + [ID_PLL_ETH_DIV] = "ethpll_divpmcck", + [ID_PLL_LVDS_DIV] = "lvdspll_divpmcck", + [ID_PLL_USB_DIV] = "usbpll_divpmcck", + [ID_MCK0_DIV] = "mck0_div", + [ID_MCK0_PRES] = "mck0_pres", +}; + +/* Fractional PLL output range. */ +static const struct clk_range pll_outputs[] = { + { .min = 2343750, .max = 1200000000 }, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] = { + { .min = 600000000, .max = 1200000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics pll_characteristics = { + .input = { .min = 12000000, .max = 50000000 }, + .num_output = ARRAY_SIZE(pll_outputs), + .output = pll_outputs, + .core_output = core_outputs, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_layout_frac = { + .mul_mask = GENMASK(31, 24), + .frac_mask = GENMASK(21, 0), + .mul_shift = 24, + .frac_shift = 0, +}; + +/* Layout for DIVPMC dividers. */ +static const struct clk_pll_layout pll_layout_divpmc = { + .div_mask = GENMASK(7, 0), + .endiv_mask = BIT(29), + .div_shift = 0, + .endiv_shift = 29, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_layout_divio = { + .div_mask = GENMASK(19, 12), + .endiv_mask = BIT(30), + .div_shift = 12, + .endiv_shift = 30, +}; + +/* MCK0 characteristics. */ +static const struct clk_master_characteristics mck0_characteristics = { + .output = { .min = 140000000, .max = 200000000 }, + .divisors = { 1, 2, 4, 3, 5 }, + .have_div3_pres = 1, +}; + +/* MCK0 layout. */ +static const struct clk_master_layout mck0_layout = { + .mask = 0x773, + .pres_shift = 4, + .offset = 0x28, +}; + +/* Programmable clock layout. */ +static const struct clk_programmable_layout programmable_layout = { + .pres_mask = 0xff, + .pres_shift = 8, + .css_mask = 0x1f, + .have_slck_mck = 0, + .is_pres_direct = 1, +}; + +/* Peripheral clock layout. */ +static const struct clk_pcr_layout sama7d65_pcr_layout = { + .offset = 0x88, + .cmd = BIT(31), + .gckcss_mask = GENMASK(12, 8), + .pid_mask = GENMASK(6, 0), +}; + +/** + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: true if clock is critical and cannot be disabled + * @id: clock id corresponding to PLL driver + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + u8 c; + u8 id; + u8 cid; +} sama7d65_plls[] = { + { + .n = "cpupll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 0, + .cid = ID_PLL_CPU_FRAC, + }, + + { + .n = "cpupll_divpmcck", + .p = "cpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 0, + .cid = ID_PLL_CPU_DIV, + }, + + { + .n = "syspll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 1, + .cid = ID_PLL_SYS_FRAC, + }, + + { + .n = "syspll_divpmcck", + .p = "syspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 1, + .cid = ID_PLL_SYS_DIV, + }, + + { + .n = "ddrpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .c = 1, + .id = 2, + .cid = ID_PLL_DDR_FRAC, + }, + + { + .n = "ddrpll_divpmcck", + .p = "ddrpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .c = 1, + .id = 2, + .cid = ID_PLL_DDR_DIV, + }, + + { + .n = "gpupll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 3, + .cid = ID_PLL_GPU_FRAC, + }, + + { + .n = "gpupll_divpmcck", + .p = "gpupll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 3, + .cid = ID_PLL_GPU_DIV + }, + + { + .n = "baudpll_fracck", + .p = "mainck", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 4, + .cid = ID_PLL_BAUD_FRAC, + }, + + { + .n = "baudpll_divpmcck", + .p = "baudpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 4, + .cid = ID_PLL_BAUD_DIV, + }, + + { + .n = "audiopll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 5, + .cid = ID_PLL_AUDIO_FRAC, + }, + + { + .n = "audiopll_divpmcck", + .p = "audiopll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 5, + .cid = ID_PLL_AUDIO_DIVPMC, + }, + + { + .n = "audiopll_diviock", + .p = "audiopll_fracck", + .l = &pll_layout_divio, + .t = PLL_TYPE_DIV, + .id = 5, + .cid = ID_PLL_AUDIO_DIVIO, + }, + + { + .n = "ethpll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 6, + .cid = ID_PLL_ETH_FRAC, + }, + + { + .n = "ethpll_divpmcck", + .p = "ethpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 6, + .cid = ID_PLL_ETH_DIV, + }, + { + .n = "lvdspll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 7, + .cid = ID_PLL_LVDS_FRAC, + }, + { + .n = "lvdspll_divpmcck", + .p = "lvdspll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 7, + .cid = ID_PLL_LVDS_DIV, + }, + { + .n = "usbpll_fracck", + .p = "main_osc", + .l = &pll_layout_frac, + .t = PLL_TYPE_FRAC, + .id = 8, + .cid = ID_PLL_USB_FRAC, + }, + { + .n = "usbpll_divmpcck", + .p = "usbpll_fracck", + .l = &pll_layout_divpmc, + .t = PLL_TYPE_DIV, + .id = 8, + .cid = ID_PLL_USB_DIV, + }, +}; + +/** + * Master clock (MCK[1..9]) description + * @n: clock name + * @ep: extra parents names array + * @ep_chg_chg_id: index in parents array that specifies the changeable + * parent + * @ep_count: extra parents count + * @ep_mux_table: mux table for extra parents + * @ep_clk_mux_table: mux table to deal with subsystem clock ids + * @id: clock id corresponding to MCK driver + * @cid: clock id corresponding to clock subsystem + * @c: true if clock is critical and cannot be disabled + */ +static const struct { + const char *n; + const char *ep[4]; + u8 ep_count; + u8 ep_mux_table[4]; + u8 ep_clk_mux_table[4]; + u8 id; + u8 cid; + u8 c; +} sama7d65_mckx[] = { + { + .n = "mck1", + .id = 1, + .cid = ID_MCK1, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck2", + .id = 2, + .cid = ID_MCK2, + .ep = { "syspll_divpmcck", "ddrpll_divpmcck", }, + .ep_mux_table = { 5, 6, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_DDR_DIV, }, + .ep_count = 2, + .c = 1, + }, + + { + .n = "mck3", + .id = 3, + .cid = ID_MCK3, + .ep = { "syspll_divpmcck", "ddrpll_divpmcck", }, + .ep_mux_table = { 5, 6, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_DDR_DIV, }, + .ep_count = 2, + }, + + { + .n = "mck4", + .id = 4, + .cid = ID_MCK4, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck5", + .id = 5, + .cid = ID_MCK5, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + }, + + { + .n = "mck6", + .id = 6, + .cid = ID_MCK6, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck7", + .id = 7, + .cid = ID_MCK7, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck8", + .id = 8, + .cid = ID_MCK8, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + .c = 1, + }, + + { + .n = "mck9", + .id = 9, + .cid = ID_MCK9, + .ep = { "syspll_divpmcck", }, + .ep_mux_table = { 5, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, }, + .ep_count = 1, + }, + +}; + +/** + * Programmable clock description + * @n: clock name + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + u8 cid; +} sama7d65_prog[] = { + { .n = "prog0", .cid = ID_PROG0, }, + { .n = "prog1", .cid = ID_PROG1, }, + { .n = "prog2", .cid = ID_PROG2, }, + { .n = "prog3", .cid = ID_PROG3, }, + { .n = "prog4", .cid = ID_PROG4, }, + { .n = "prog5", .cid = ID_PROG5, }, + { .n = "prog6", .cid = ID_PROG6, }, + { .n = "prog7", .cid = ID_PROG7, }, +}; + +/* Mux table for programmable clocks. */ +static u32 sama7d65_prog_mux_table[] = { 0, 1, 2, 3, 5, 7, 8, 9, 10, 12, }; + +/** + * System clock description + * @n: clock name + * @p: parent clock name + * @id: clock id corresponding to system clock driver + * @cid: clock id corresponding to clock subsystem + */ +static const struct { + const char *n; + const char *p; + u8 id; + u8 cid; +} sama7d65_systemck[] = { + { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, + { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, + { .n = "pck2", .p = "prog2", .id = 10, .cid = ID_PCK2, }, + { .n = "pck3", .p = "prog3", .id = 11, .cid = ID_PCK3, }, + { .n = "pck4", .p = "prog4", .id = 12, .cid = ID_PCK4, }, + { .n = "pck5", .p = "prog5", .id = 13, .cid = ID_PCK5, }, + { .n = "pck6", .p = "prog6", .id = 14, .cid = ID_PCK6, }, + { .n = "pck7", .p = "prog7", .id = 15, .cid = ID_PCK7, }, +}; + +/** + * Peripheral clock description + * @n: clock name + * @p: clock parent name + * @r: clock range values + * @id: clock id + */ +static const struct { + const char *n; + const char *p; + struct clk_range r; + u8 id; +} sama7d65_periphck[] = { + { .n = "pioA_clk", .p = "mck0_div", .id = 10, }, + { .n = "sfr_clk", .p = "mck7", .id = 18, }, + { .n = "hsmc_clk", .p = "mck5", .id = 20, }, + { .n = "xdmac0_clk", .p = "mck6", .id = 21, }, + { .n = "xdmac1_clk", .p = "mck6", .id = 22, }, + { .n = "xdmac2_clk", .p = "mck1", .id = 23, }, + { .n = "acc_clk", .p = "mck7", .id = 24, }, + { .n = "aes_clk", .p = "mck6", .id = 26, }, + { .n = "tzaesbasc_clk", .p = "mck8", .id = 27, }, + { .n = "asrc_clk", .p = "mck9", .id = 29, .r = { .max = 200000000, }, }, + { .n = "cpkcc_clk", .p = "mck0_div", .id = 30, }, + { .n = "eic_clk", .p = "mck7", .id = 33, }, + { .n = "flex0_clk", .p = "mck7", .id = 34, }, + { .n = "flex1_clk", .p = "mck7", .id = 35, }, + { .n = "flex2_clk", .p = "mck7", .id = 36, }, + { .n = "flex3_clk", .p = "mck7", .id = 37, }, + { .n = "flex4_clk", .p = "mck8", .id = 38, }, + { .n = "flex5_clk", .p = "mck8", .id = 39, }, + { .n = "flex6_clk", .p = "mck8", .id = 40, }, + { .n = "flex7_clk", .p = "mck8", .id = 41, }, + { .n = "flex8_clk", .p = "mck9", .id = 42, }, + { .n = "flex9_clk", .p = "mck9", .id = 43, }, + { .n = "flex10_clk", .p = "mck9", .id = 44, }, + { .n = "gmac0_clk", .p = "mck6", .id = 46, }, + { .n = "gmac1_clk", .p = "mck6", .id = 47, }, + { .n = "gmac0_tsu_clk", .p = "mck1", .id = 49, }, + { .n = "gmac1_tsu_clk", .p = "mck1", .id = 50, }, + { .n = "icm_clk", .p = "mck5", .id = 53, }, + { .n = "i2smcc0_clk", .p = "mck9", .id = 54, .r = { .max = 200000000, }, }, + { .n = "i2smcc1_clk", .p = "mck9", .id = 55, .r = { .max = 200000000, }, }, + { .n = "matrix_clk", .p = "mck5", .id = 57, }, + { .n = "mcan0_clk", .p = "mck5", .id = 58, .r = { .max = 200000000, }, }, + { .n = "mcan1_clk", .p = "mck5", .id = 59, .r = { .max = 200000000, }, }, + { .n = "mcan2_clk", .p = "mck5", .id = 60, .r = { .max = 200000000, }, }, + { .n = "mcan3_clk", .p = "mck5", .id = 61, .r = { .max = 200000000, }, }, + { .n = "mcan4_clk", .p = "mck5", .id = 62, .r = { .max = 200000000, }, }, + { .n = "pdmc0_clk", .p = "mck9", .id = 64, .r = { .max = 200000000, }, }, + { .n = "pdmc1_clk", .p = "mck9", .id = 65, .r = { .max = 200000000, }, }, + { .n = "pit64b0_clk", .p = "mck7", .id = 66, }, + { .n = "pit64b1_clk", .p = "mck7", .id = 67, }, + { .n = "pit64b2_clk", .p = "mck7", .id = 68, }, + { .n = "pit64b3_clk", .p = "mck8", .id = 69, }, + { .n = "pit64b4_clk", .p = "mck8", .id = 70, }, + { .n = "pit64b5_clk", .p = "mck8", .id = 71, }, + { .n = "pwm_clk", .p = "mck7", .id = 72, }, + { .n = "qspi0_clk", .p = "mck5", .id = 73, }, + { .n = "qspi1_clk", .p = "mck5", .id = 74, }, + { .n = "sdmmc0_clk", .p = "mck1", .id = 75, }, + { .n = "sdmmc1_clk", .p = "mck1", .id = 76, }, + { .n = "sdmmc2_clk", .p = "mck1", .id = 77, }, + { .n = "sha_clk", .p = "mck6", .id = 78, }, + { .n = "spdifrx_clk", .p = "mck9", .id = 79, .r = { .max = 200000000, }, }, + { .n = "spdiftx_clk", .p = "mck9", .id = 80, .r = { .max = 200000000, }, }, + { .n = "ssc0_clk", .p = "mck7", .id = 81, .r = { .max = 200000000, }, }, + { .n = "ssc1_clk", .p = "mck8", .id = 82, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch0_clk", .p = "mck8", .id = 83, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch1_clk", .p = "mck8", .id = 84, .r = { .max = 200000000, }, }, + { .n = "tcb0_ch2_clk", .p = "mck8", .id = 85, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch0_clk", .p = "mck5", .id = 86, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch1_clk", .p = "mck5", .id = 87, .r = { .max = 200000000, }, }, + { .n = "tcb1_ch2_clk", .p = "mck5", .id = 88, .r = { .max = 200000000, }, }, + { .n = "tcpca_clk", .p = "mck5", .id = 89, }, + { .n = "tcpcb_clk", .p = "mck5", .id = 90, }, + { .n = "tdes_clk", .p = "mck6", .id = 91, }, + { .n = "trng_clk", .p = "mck6", .id = 92, }, + { .n = "udphsa_clk", .p = "mck5", .id = 99, }, + { .n = "udphsb_clk", .p = "mck5", .id = 100, }, + { .n = "uhphs_clk", .p = "mck5", .id = 101, }, +}; + +/** + * Generic clock description + * @n: clock name + * @ep: extra parents names + * @ep_mux_table: extra parents mux table + * @ep_clk_mux_table: extra parents clock mux table (for CCF) + * @r: clock output range + * @ep_count: extra parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *ep[8]; + const char ep_mux_table[8]; + const char ep_clk_mux_table[8]; + struct clk_range r; + u8 ep_count; + u8 id; +} sama7d65_gck[] = { + { + .n = "adc_gclk", + .id = 25, + .r = { .max = 100000000, }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", }, + .ep_mux_table = { 8, 9, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 2, + }, + + { + .n = "asrc_gclk", + .id = 29, + .r = { .max = 200000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "flex0_gclk", + .id = 34, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex1_gclk", + .id = 35, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex2_gclk", + .id = 36, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex3_gclk", + .id = 37, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex4_gclk", + .id = 38, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex5_gclk", + .id = 39, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex6_gclk", + .id = 40, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex7_gclk", + .id = 41, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex8_gclk", + .id = 42, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex9_gclk", + .id = 43, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "flex10_gclk", + .id = 44, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", }, + .ep_mux_table = { 8,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, }, + .ep_count = 1, + }, + + { + .n = "gmac0_gclk", + .id = 46, + .r = { .max = 125000000}, + .ep = { "ethpll_divpmcck", }, + .ep_clk_mux_table = { ID_PLL_ETH_DIV, }, + .ep_mux_table = { 10, }, + .ep_count = 1, + }, + + { + .n = "gmac1_gclk", + .id = 47, + .r = { .max = 125000000}, + .ep = { "ethpll_divpmcck", }, + .ep_mux_table = { 10, }, + .ep_clk_mux_table = { ID_PLL_ETH_DIV, }, + .ep_count = 1, + }, + + { + .n = "gmac0_tsu_gclk", + .id = 49, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 5, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "gmac1_tsu_gclk", + .id = 50, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 5, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_AUDIO_DIVPMC, ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "i2smcc0_gclk", + .id = 54, + .r = { .max = 100000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "i2smcc1_gclk", + .id = 55, + .r = { .max = 100000000 }, + .ep = {"audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "mcan0_gclk", + .id = 58, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV }, + .ep_count = 1, + }, + + { + .n = "mcan1_gclk", + .id = 59, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan2_gclk", + .id = 60, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan3_gclk", + .id = 61, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "mcan4_gclk", + .id = 62, + .r = { .max = 80000000 }, + .ep = { "usbpll_divpmcck", }, + .ep_mux_table = { 12, }, + .ep_clk_mux_table = { ID_PLL_USB_DIV, }, + .ep_count = 1, + }, + + { + .n = "pdmc0_gclk", + .id = 64, + .r = { .max = 80000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "pdmc1_gclk", + .id = 65, + .r = { .max = 80000000, }, + .ep = { "audiopll_divpmcck",}, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "pit64b0_gclk", + .id = 66, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b1_gclk", + .id = 67, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = { ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b2_gclk", + .id = 68, + .r = { .max = 34000000 }, + .ep = { "baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b3_gclk", + .id = 69, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b4_gclk", + .id = 70, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "pit64b5_gclk", + .id = 71, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "qspi0_gclk", + .id = 73, + .r = { .max = 400000000 }, + .ep = { "syspll_divpmcck", "baudpll_divpmcck", }, + .ep_mux_table = { 5, 8, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, }, + .ep_count = 2, + }, + + { + .n = "qspi1_gclk", + .id = 74, + .r = { .max = 266000000 }, + .ep = { "syspll_divpmcck", "baudpll_divpmcck", }, + .ep_mux_table = { 5, 8, }, + .ep_clk_mux_table = { ID_PLL_SYS_DIV, ID_PLL_BAUD_DIV, }, + .ep_count = 2, + }, + + { + .n = "sdmmc0_gclk", + .id = 75, + .r = { .max = 208000000 }, + .ep = {"baudpll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV,}, + .ep_count = 2, + }, + + { + .n = "sdmmc1_gclk", + .id = 76, + .r = { .max = 208000000 }, + .ep = { "baudpll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 10,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV, }, + .ep_count = 2, + }, + + { + .n = "sdmmc2_gclk", + .id = 77, + .r = { .max = 208000000 }, + .ep = {"baudpll_divpmcck", "ethpll_divpmcck",}, + .ep_mux_table = {8, 10,}, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_ETH_DIV,}, + .ep_count = 2, + }, + + { + .n = "spdifrx_gclk", + .id = 79, + .r = { .max = 150000000 }, + .ep = {"audiopll_divpmcck", }, + .ep_mux_table = { 9, }, + .ep_clk_mux_table = { ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "spdiftx_gclk", + .id = 80, + .r = { .max = 25000000 }, + .ep = { "audiopll_divpmcck", }, + .ep_mux_table = {9, }, + .ep_clk_mux_table = {ID_PLL_AUDIO_DIVPMC, }, + .ep_count = 1, + }, + + { + .n = "tcb0_ch0_gclk", + .id = 83, + .r = { .max = 34000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = { 8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "tcb1_ch0_gclk", + .id = 86, + .r = { .max = 67000000 }, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, + + { + .n = "DSI_gclk", + .id = 103, + .r = {.max = 27000000}, + .ep = {"syspll_divpmcck"}, + .ep_mux_table = {5}, + .ep_clk_mux_table = {ID_PLL_SYS_DIV}, + .ep_count = 1, + }, + + { + .n = "I3CC_gclk", + .id = 105, + .r = {.max = 125000000}, + .ep = {"baudpll_divpmcck", "audiopll_divpmcck", "ethpll_divpmcck", }, + .ep_mux_table = {8, 9, 10, }, + .ep_clk_mux_table = {ID_PLL_BAUD_DIV, ID_PLL_AUDIO_DIVPMC, + ID_PLL_ETH_DIV, }, + .ep_count = 3, + }, +}; + +/* Clock setup description */ +static const struct pmc_clk_setup sama7d65_clk_setup[] = { + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_FRAC), + .rate = 625000000, + }, + + { + .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV), + .rate = 625000000, + }, +}; + +#define SAMA7D65_MAX_MUX_ALLOCS (64) + +#define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label) \ + do { \ + int _i; \ + if ((_index) >= SAMA7D65_MAX_MUX_ALLOCS) { \ + debug("%s(): AT91: MUX: insufficient space\n", \ + __func__); \ + goto _label; \ + } \ + (_dst) = kzalloc(sizeof(*(_dst)) * (_num), GFP_KERNEL); \ + if (!(_dst)) \ + goto _label; \ + (_allocs)[(_index)++] = (_dst); \ + for (_i = 0; _i < (_num); _i++) \ + (_dst)[_i] = (_src)[_i]; \ + } while (0) + +static int sama7d65_clk_probe(struct udevice *dev) +{ + void __iomem *base = (void *)devfdt_get_addr(dev); + unsigned int *clkmuxallocs[SAMA7D65_MAX_MUX_ALLOCS]; + unsigned int *muxallocs[SAMA7D65_MAX_MUX_ALLOCS]; + const char *p[12]; + unsigned int cm[12], m[12], *tmpclkmux, *tmpmux; + struct clk clk, *c; + bool main_osc_bypass; + int ret, muxallocindex = 0, clkmuxallocindex = 0, i, j; + + if (IS_ERR(base)) + return PTR_ERR(base); + + memset(muxallocs, 0, ARRAY_SIZE(muxallocs)); + memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs)); + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + ret = clk_get_by_id(clk.id, &c); + if (ret) + return ret; + clk_names[ID_TD_SLCK] = kmemdup(clk_hw_get_name(c), + strlen(clk_hw_get_name(c)) + 1, + GFP_KERNEL); + if (!clk_names[ID_TD_SLCK]) + return -ENOMEM; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return ret; + ret = clk_get_by_id(clk.id, &c); + if (ret) + return ret; + clk_names[ID_MD_SLCK] = kmemdup(clk_hw_get_name(c), + strlen(clk_hw_get_name(c)) + 1, + GFP_KERNEL); + if (!clk_names[ID_MD_SLCK]) + return -ENOMEM; + + ret = clk_get_by_index(dev, 2, &clk); + if (ret) + return ret; + clk_names[ID_MAIN_XTAL] = kmemdup(clk_hw_get_name(&clk), + strlen(clk_hw_get_name(&clk)) + 1, + GFP_KERNEL); + if (!clk_names[ID_MAIN_XTAL]) + return -ENOMEM; + + main_osc_bypass = dev_read_bool(dev, "atmel,main-osc-bypass"); + + /* Register main rc oscillator. */ + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC), + at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC], + NULL)); + + /* Register main oscillator. */ + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC), + at91_clk_main_osc(base, clk_names[ID_MAIN_OSC], + clk_names[ID_MAIN_XTAL], main_osc_bypass)); + + /* Register mainck. */ + p[0] = clk_names[ID_MAIN_RC_OSC]; + p[1] = clk_names[ID_MAIN_OSC]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, + fail); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK), + at91_clk_sam9x5_main(base, clk_names[ID_MAINCK], p, 2, + tmpclkmux, PMC_TYPE_CORE)); + + /* Register PLL fracs clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_plls); i++) { + if (sama7d65_plls[i].t != PLL_TYPE_FRAC) + continue; + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_plls[i].cid), + sam9x60_clk_register_frac_pll(base, sama7d65_plls[i].n, + sama7d65_plls[i].p, + sama7d65_plls[i].id, + &pll_characteristics, + sama7d65_plls[i].l, + sama7d65_plls[i].c)); + } + + /* Register PLL div clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_plls); i++) { + if (sama7d65_plls[i].t != PLL_TYPE_DIV) + continue; + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_plls[i].cid), + sam9x60_clk_register_div_pll(base, sama7d65_plls[i].n, + sama7d65_plls[i].p, + sama7d65_plls[i].id, + &pll_characteristics, + sama7d65_plls[i].l, + sama7d65_plls[i].c)); + } + + /* Register MCK0_PRES clock. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_MAINCK]; + p[2] = clk_names[ID_PLL_CPU_DIV]; + p[3] = clk_names[ID_PLL_SYS_DIV]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_CPU_DIV); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, + fail); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES), + at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], + p, 4, &mck0_layout, + &mck0_characteristics, + tmpclkmux)); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV), + at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV], + clk_names[ID_MCK0_PRES], + &mck0_layout, + &mck0_characteristics)); + + /* Register MCK1-9 clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK0_DIV]; + m[0] = 0; + m[1] = 1; + m[2] = 2; + m[3] = 3; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + for (i = 0; i < ARRAY_SIZE(sama7d65_mckx); i++) { + for (j = 0; j < sama7d65_mckx[i].ep_count; j++) { + p[4 + j] = sama7d65_mckx[i].ep[j]; + m[4 + j] = sama7d65_mckx[i].ep_mux_table[j]; + cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE, + sama7d65_mckx[i].ep_clk_mux_table[j]); + } + + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 4 + sama7d65_mckx[i].ep_count, fail); + prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, + 4 + sama7d65_mckx[i].ep_count, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_mckx[i].cid), + at91_clk_sama7g5_register_master(base, sama7d65_mckx[i].n, p, + 4 + sama7d65_mckx[i].ep_count, + tmpmux, tmpclkmux, + sama7d65_mckx[i].c, + sama7d65_mckx[i].id)); + } + + /* Register programmable clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK0_DIV]; + p[4] = clk_names[ID_PLL_SYS_DIV]; + p[5] = clk_names[ID_PLL_GPU_DIV]; + p[6] = clk_names[ID_PLL_BAUD_DIV]; + p[7] = clk_names[ID_PLL_AUDIO_DIVPMC]; + p[8] = clk_names[ID_PLL_ETH_DIV]; + p[9] = clk_names[ID_PLL_USB_DIV]; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); + cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); + cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_GPU_DIV); + cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_BAUD_DIV); + cm[7] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_AUDIO_DIVPMC); + cm[8] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_ETH_DIV); + cm[9] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_USB_DIV); + + for (i = 0; i < ARRAY_SIZE(sama7d65_prog); i++) { + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 10, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sama7d65_prog[i].cid), + at91_clk_register_programmable(base, sama7d65_prog[i].n, + p, 10, i, + &programmable_layout, + tmpclkmux, + sama7d65_prog_mux_table)); + } + + /* System clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_systemck); i++) { + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_SYSTEM, sama7d65_systemck[i].cid), + at91_clk_register_system(base, sama7d65_systemck[i].n, + sama7d65_systemck[i].p, + sama7d65_systemck[i].id)); + } + + /* Peripheral clocks. */ + for (i = 0; i < ARRAY_SIZE(sama7d65_periphck); i++) { + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_PERIPHERAL, sama7d65_periphck[i].id), + at91_clk_register_sam9x5_peripheral(base, + &sama7d65_pcr_layout, + sama7d65_periphck[i].n, + sama7d65_periphck[i].p, + sama7d65_periphck[i].id, + &sama7d65_periphck[i].r)); + } + + /* Generic clocks. */ + p[0] = clk_names[ID_MD_SLCK]; + p[1] = clk_names[ID_TD_SLCK]; + p[2] = clk_names[ID_MAINCK]; + p[3] = clk_names[ID_MCK1]; + m[0] = 0; + m[1] = 1; + m[2] = 2; + m[3] = 3; + cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); + cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); + cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK1); + for (i = 0; i < ARRAY_SIZE(sama7d65_gck); i++) { + for (j = 0; j < sama7d65_gck[i].ep_count; j++) { + p[4 + j] = sama7d65_gck[i].ep[j]; + m[4 + j] = sama7d65_gck[i].ep_mux_table[j]; + cm[4 + j] = AT91_TO_CLK_ID(PMC_TYPE_CORE, + sama7d65_gck[i].ep_clk_mux_table[j]); + } + + prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, + 4 + sama7d65_gck[i].ep_count, fail); + prepare_mux_table(muxallocs, muxallocindex, tmpmux, m, + 4 + sama7d65_gck[i].ep_count, fail); + + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sama7d65_gck[i].id), + at91_clk_register_generic(base, &sama7d65_pcr_layout, + sama7d65_gck[i].n, p, + tmpclkmux, tmpmux, + 4 + sama7d65_gck[i].ep_count, + sama7d65_gck[i].id, + &sama7d65_gck[i].r)); + } + + /* Setup clocks. */ + ret = at91_clk_setup(sama7d65_clk_setup, ARRAY_SIZE(sama7d65_clk_setup)); + if (ret) + goto fail; + + return 0; + +fail: + for (i = 0; i < ARRAY_SIZE(muxallocs); i++) + kfree(muxallocs[i]); + + for (i = 0; i < ARRAY_SIZE(clkmuxallocs); i++) + kfree(clkmuxallocs[i]); + + return -ENOMEM; +} + +static const struct udevice_id sama7d65_clk_ids[] = { + { .compatible = "microchip,sama7d65-pmc" }, + { /* Sentinel. */ }, +}; + +U_BOOT_DRIVER(at91_sama7d65_pmc) = { + .name = "at91-sama7d65-pmc", + .id = UCLASS_CLK, + .of_match = sama7d65_clk_ids, + .ops = &at91_clk_ops, + .probe = sama7d65_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c b/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c index 31b6209416b..84156a1e8ad 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c +++ b/drivers/ddr/marvell/a38x/mv_ddr4_training_calibration.c @@ -64,7 +64,7 @@ static u8 center_high_element_get(u8 dir, u8 pbs_element, u16 lambda, u8 pbs_max static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*copt)[MAX_BUS_NUM], u8 (*pbs_result)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS], u8 (*vw_size)[MAX_BUS_NUM], u8 mode, u16 param0, u8 param1); -static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs); +static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, s8 delta, u8 *copt, u8 *dqs_pbs); static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_result, u8 *copt); static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 mode, u8 *vw_l, u8 *vw_h, u8 *vw_v, u8 vw_num, u8 *v_opt, u8 *t_opt); @@ -659,7 +659,7 @@ static int mv_ddr4_centralization(u8 dev_num, u16 (*lambda)[MAX_BUS_NUM][BUS_WID } /* if_id */ /* restore cs enable value*/ - for (if_id = 0; if_id < MAX_INTERFACE_NUM - 1; if_id++) { + for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DUAL_DUNIT_CFG_REG, cs_ena_reg_val[if_id], MASK_ALL_BITS); @@ -895,7 +895,7 @@ static int mv_ddr4_copt_get(u8 dir, u16 *lambda, u8 *vw_l, u8 *vw_h, u8 *pbs_res * It provides with a solution for a single subphy (8 bits). * The calling function is responsible for any additional pbs taps for dqs */ -static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, char delta, u8 *copt, u8 *dqs_pbs) +static int mv_ddr4_dqs_reposition(u8 dir, u16 *lambda, u8 *pbs_result, s8 delta, u8 *copt, u8 *dqs_pbs) { u8 dq_idx; u32 pbs_max_val = 0; @@ -952,7 +952,8 @@ static int mv_ddr4_center_of_mass_calc(u8 dev_num, u8 if_id, u8 subphy_num, u8 m int t_opt_temp = 0, v_opt_temp = 0; int vw_avg = 0, v_avg = 0; int s0 = 0, s1 = 0, s2 = 0, slope = 1, r_sq = 0; - u32 d_min = 10000, reg_val = 0; + u32 reg_val = 0; + int d_min = 10000; int status; /* @@ -2189,7 +2190,7 @@ int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BI for (dq = 0; dq < BUS_WIDTH_IN_BITS; dq++) { idx = dq + subphy * BUS_WIDTH_IN_BITS; reg_val = new_dq_pbs[dq] - dq_pbs_diff; - if (reg_val < 0) { + if (new_dq_pbs[dq] < dq_pbs_diff) { DEBUG_DM_TUNING(DEBUG_LEVEL_ERROR, ("unexpected negative value found\n")); return MV_FAIL; @@ -2267,7 +2268,7 @@ int mv_ddr4_dm_tuning(u32 cs, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BI idx = dq + subphy * BUS_WIDTH_IN_BITS; pad = dq_map_table[idx]; reg_val = new_dq_pbs[dq] - dq_pbs_diff; - if (reg_val < 0) { + if (new_dq_pbs[dq] < dq_pbs_diff) { DEBUG_DM_TUNING(DEBUG_LEVEL_ERROR, ("unexpected negative value found\n")); return MV_FAIL; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a3513f0a3ef..1ae36b5a348 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -351,6 +351,8 @@ config MTK_SPIM config MVEBU_A3700_SPI bool "Marvell Armada 3700 SPI driver" + depends on ARCH_MVEBU && ARM64 + select CLK_MVEBU select CLK_ARMADA_3720 help Enable the Marvell Armada 3700 SPI driver. This driver can be diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index e1b62f78b21..01ab6edb05f 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright (C) 2025 Tony Dinh <mibodhi@gmail.com> * Copyright (C) 2011-2012 * Gerald Kerma <dreagle@doukki.net> * Luka Perkov <luka@openwrt.org> @@ -11,19 +12,34 @@ #include "mv-common.h" /* - * Environment variables configuration - */ - -/* - * Default environment variables + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros */ +#include "mv-common.h" -#define CFG_EXTRA_ENV_SETTINGS \ +#define EXTRA_ENV_SETTINGS_LEGACY \ "console=console=ttyS0,115200\0" \ "kernel=/boot/zImage\0" \ "fdt=/boot/ib62x0.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" +#define KERNEL_ADDR_R __stringify(0x800000) +#define FDT_ADDR_R __stringify(0x2c00000) +#define RAMDISK_ADDR_R __stringify(0x01100000) +#define SCRIPT_ADDR_R __stringify(0x200000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS_LEGACY \ + LOAD_ADDRESS_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" + /* * SATA driver configuration */ diff --git a/include/configs/sama7d65_curiosity.h b/include/configs/sama7d65_curiosity.h new file mode 100644 index 00000000000..9316b104ee3 --- /dev/null +++ b/include/configs/sama7d65_curiosity.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA7D65 Curiosity Board. + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +/* SDRAM */ +#define CFG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 + +#endif |