diff options
587 files changed, 18542 insertions, 13413 deletions
@@ -48,6 +48,11 @@ Greg Malysa <malysagreg@gmail.com> <greg.malysa@timesys.com> Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com> Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com> Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com> +Heiko Schocher <hs@nabladev.com> <hs@denx.de> +Heiko Schocher <hs@nabladev.com> <hs@pollux.denx.de> +Heiko Schocher <hs@nabladev.com> <heiko.schocher@invitel.hu> +Heiko Schocher <hs@nabladev.com> <[hs@denx.de]> +Heiko Schocher <hs@nabladev.com> <hs@pollux.(none)> Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com> Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de> Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com> @@ -552,7 +552,7 @@ config BOARD_SIZE_LIMIT Maximum size of the U-Boot image. When defined, the build system checks that the actual size does not exceed it. This does not include SPL nor TPL, on platforms that use that functionality, they - have a separate option to restict size. + have separate options to restrict size. config SYS_CUSTOM_LDSCRIPT bool "Use a custom location for the U-Boot linker script" diff --git a/MAINTAINERS b/MAINTAINERS index cae855da60e..3fb163aa1db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -152,13 +152,14 @@ ARM ALTERA SOCFPGA M: Marek Vasut <marex@denx.de> M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> M: Tien Fong Chee <tien.fong.chee@altera.com> -M: Tingting Meng <tingting.meng@altera.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git +F: arch/arm/dts/socfpga_* +F: arch/arm/mach-socfpga/ +F: board/intel/agilex-socdk/ +F: configs/socfpga_* F: drivers/ddr/altera/ F: drivers/power/domain/altr-pmgr-agilex5.c -F: arch/arm/mach-socfpga/ -F: configs/socfpga_agilex5_vab_defconfig F: drivers/sysreset/sysreset_socfpga* ARM AMLOGIC SOC SUPPORT @@ -1244,11 +1245,18 @@ F: drivers/misc/gsc.c F: include/gsc.h I2C -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git F: drivers/i2c/ +I3C +M: Dinesh <dinesh.maniyam@altera.com> +S: Maintained +T: git https://source.denx.de/u-boot/u-boot.git +F: cmd/i3c.c +F: drivers/i3c/ + KWBIMAGE / KWBOOT TOOLS M: Pali Rohár <pali@kernel.org> M: Marek Behún <kabel@kernel.org> @@ -1491,7 +1499,7 @@ F: drivers/pci_endpoint/ F: include/pci_ep.h PCI MPC85xx -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: drivers/pci/pci_mpc85xx.c @@ -1788,7 +1796,7 @@ F: lib/optee UBI M: Kyungmin Park <kmpark@infradead.org> -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git F: drivers/mtd/ubi/ @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc4 NAME = # *DOCUMENTATION* @@ -1574,7 +1574,6 @@ u-boot-nodtb.bin: u-boot FORCE $(BOARD_SIZE_CHECK) u-boot.ldr: u-boot - $(CREATE_LDR_ENV) $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) @@ -2131,6 +2130,11 @@ $(filter-out tools, $(u-boot-dirs)): tools # is "yes"), so compile examples after U-Boot is compiled. examples: $(filter-out examples, $(u-boot-dirs)) +ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y) +# lib/efi_loader apps depend on arch/$(ARCH)/lib for lib.a +lib: $(filter arch/$(ARCH)/lib, $(u-boot-dirs)) +endif + # The setlocalversion script comes from linux and expects a # KERNELVERSION variable in the environment for figuring out which # annotated tags are relevant. Pass UBOOTVERSION. @@ -2465,7 +2469,8 @@ CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h include/bmp_logo_data.h \ mkimage.rom.mkimage mkimage-in-simple-bin* rom.map simple-bin* \ idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb \ Test* capsule*.*.efi-capsule capsule*.map mkimage.imx-boot.spl \ - mkimage.imx-boot.u-boot mkimage-out.imx-boot.spl mkimage-out.imx-boot.u-boot + mkimage.imx-boot.u-boot mkimage-out.imx-boot.spl mkimage-out.imx-boot.u-boot \ + imx9image* m33-oei-ddrfw* # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include/generated spl tpl vpl \ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4e7593616d8..16db046f4b8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -30,7 +30,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 + default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -833,6 +833,7 @@ config ARCH_K3 select FIT select REGEX select FIT_SIGNATURE if ARM64 + select DMA_ADDR_T_64BIT select LTO imply TI_SECURE_DEVICE imply DM_RNG if ARM64 @@ -1173,8 +1174,9 @@ config ARCH_SOCFPGA select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ - TARGET_SOCFPGA_SOC64 + TARGET_SOCFPGA_SOC64 select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 + select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c index 492353c93df..f4009e89a98 100644 --- a/arch/arm/cpu/armv8/spl_data.c +++ b/arch/arm/cpu/armv8/spl_data.c @@ -11,15 +11,15 @@ char __data_save_end[0] __section(".__data_save_end"); u32 cold_reboot_flag = 1; -u32 __weak reset_flag(void) +u32 __weak reset_flag(u32 flag) { - return 1; + return flag; } void spl_save_restore_data(void) { u32 data_size = __data_save_end - __data_save_start; - cold_reboot_flag = reset_flag(); + cold_reboot_flag = reset_flag(cold_reboot_flag); if (cold_reboot_flag == 1) { /* Save data section to data_save section */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0dc7e190eb9..7c8cf3a5a1d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,6 +92,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra20-motorola-olympus.dtb \ tegra20-paz00.dtb \ tegra20-plutux.dtb \ + tegra20-samsung-bose.dtb \ + tegra20-samsung-n1.dtb \ tegra20-seaboard.dtb \ tegra20-tec.dtb \ tegra20-trimslice.dtb \ @@ -117,10 +119,13 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-lg-p895.dtb \ tegra30-microsoft-surface-rt.dtb \ tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb \ tegra30-tec-ng.dtb \ tegra30-wexler-qc750.dtb \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ + tegra114-microsoft-surface-2-0b.dtb \ + tegra114-microsoft-surface-2-13.dtb \ tegra114-nvidia-tegratab.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ @@ -445,7 +450,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ - socfpga_agilex_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ @@ -646,11 +650,6 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-oka40i-c.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN8I_V3S) += \ - sun8i-s3-elimo-initium.dtb \ - sun8i-s3-pinecube.dtb \ - sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN8I_R528) += \ sun8i-t113s-mangopi-mq-r-t113.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 59453dc36d3..eb5b95a1fda 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -164,7 +164,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -176,9 +175,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif binman_fip: fip { arch = "arm64"; @@ -208,11 +207,7 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 96a6df94c6c..4a4498b36b0 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -240,7 +240,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -252,9 +251,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif binman_fip: fip { arch = "arm64"; @@ -284,11 +283,7 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 6de9ab5d37c..9ede98a11e4 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -185,7 +185,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -197,9 +196,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif @fdt-SEQ { description = "NAME"; @@ -220,11 +219,7 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 8a536b16e8f..93e2ef27f7c 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -144,7 +144,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -156,9 +155,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif fdt { compression = "none"; @@ -180,11 +179,7 @@ fdt = "fdt"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi index 9bf8f9834c9..de74398fdfe 100644 --- a/arch/arm/dts/imx95-u-boot.dtsi +++ b/arch/arm/dts/imx95-u-boot.dtsi @@ -52,15 +52,47 @@ pad-byte = <0x00>; spl { - align = <0x400>; - align-size = <0x400>; - type = "mkimage"; - args = "-n spl/u-boot-spl.cfgout -T imx8image"; + type = "nxp-imx9image"; + cfg-path = "spl/u-boot-spl.cfgout"; + args; + +#ifndef CONFIG_IMX95_A0 + cntr-version = <2>; +#endif + boot-from = "sd"; + soc-type = "IMX9"; +#ifdef CONFIG_IMX95_A0 + append = "mx95a0-ahab-container.img"; +#else + append = "mx95b0-ahab-container.img"; +#endif + container; +#ifndef CONFIG_IMX95_A0 + dummy-ddr; +#endif + image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000"; + hold = <0x10000>; +#ifdef CONFIG_IMX95_A0 + image1 = "oei", "oei-m33-tcm.bin", "0x1ffc0000"; +#endif + image2 = "m33", "m33_image.bin", "0x1ffc0000"; + image3 = "a55", "spl/u-boot-spl.bin", "0x20480000"; + dummy-v2x = <0x8b000000>; }; u-boot { - type = "mkimage"; - args = "-n u-boot-container.cfgout -T imx8image"; + type = "nxp-imx9image"; + cfg-path = "u-boot-container.cfgout"; + args; + +#ifndef CONFIG_IMX95_A0 + cntr-version = <2>; +#endif + boot-from = "sd"; + soc-type = "IMX9"; + container; + image0 = "a55", "bl31.bin", "0x8a200000"; + image1 = "a55", "u-boot.bin", "0x90200000"; }; }; }; diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts index 135e8d49b91..95cd9b707c7 100644 --- a/arch/arm/dts/k3-am62-r5-lp-sk.dts +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts @@ -64,7 +64,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index f4b2cd8904e..bba69871fd2 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -70,7 +70,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts index 7132fae36fa..03dc81a4afa 100644 --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts @@ -69,7 +69,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 34c501dd51b..67589f941ba 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -64,7 +64,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 39e8ab8158e..fb431c96337 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -53,7 +53,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index 9bcdf74ffe4..a284226320c 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -101,43 +101,6 @@ }; }; -&binman { - tiboot3-am62ax-gp-phycore-som.bin { - filename = "tiboot3-am62ax-gp-phycore-som.bin"; - ti-secure-rom { - content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, - <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; - combined; - dm-data; - content-sbl = <&u_boot_spl_unsigned>; - load = <CONFIG_SPL_TEXT_BASE>; - content-sysfw = <&ti_fs_gp>; - load-sysfw = <0x40000>; - content-sysfw-data = <&combined_tifs_cfg_gp>; - load-sysfw-data = <0x67000>; - content-dm-data = <&combined_dm_cfg_gp>; - load-dm-data = <0x43c3a800>; - sw-rev = <1>; - keyfile = "ti-degenerate-key.pem"; - }; - u_boot_spl_unsigned: u-boot-spl { - no-expanded; - }; - ti_fs_gp: ti-fs-gp.bin { - filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; - type = "blob-ext"; - }; - combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { - filename = "combined-tifs-cfg.bin"; - type = "blob-ext"; - }; - combined_dm_cfg_gp: combined-dm-cfg-gp.bin { - filename = "combined-dm-cfg.bin"; - type = "blob-ext"; - }; - }; -}; - #include "k3-binman-capsule-r5.dtsi" &capsule_tiboot3 { @@ -197,23 +160,6 @@ }; - tifsstub-gp { - filename = "tifsstub.bin_gp"; - ti-secure-rom { - content = <&tifsstub_gp>; - core = "secure"; - load = <0x60000>; - sw-rev = <CONFIG_K3_X509_SWRV>; - keyfile = "ti-degenerate-key.pem"; - tifsstub; - }; - tifsstub_gp: tifsstub-gp.bin { - filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; - type = "blob-ext"; - optional; - }; - }; - ti-spl { insert-template = <&ti_spl_template>; @@ -245,18 +191,6 @@ }; }; - tifsstub-gp { - description = "TIFSSTUB"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; dm { ti-secure { content = <&dm>; @@ -289,7 +223,7 @@ description = "k3-am62a7-phyboard-lyra-rdk"; firmware = "atf"; loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; + "tifsstub-hs", "tifsstub-fs"; fdt = "fdt-0"; }; }; @@ -403,120 +337,6 @@ }; }; -&binman { - ti-spl_unsigned { - insert-template = <&ti_spl_unsigned_template>; - - fit { - images { - tifsstub-hs { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-hs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_hs"; - }; - }; - - tifsstub-fs { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-fs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_fs"; - }; - }; - - tifsstub-gp { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; - dm { - ti-dm { - filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - }; - }; - - fdt-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - spl_am62a7_phyboard_lyra_dtb_unsigned: blob { - filename = SPL_AM62A7_PHYBOARD_LYRA_DTB; - }; - }; - }; - - configurations { - default = "conf-0"; - - conf-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - firmware = "atf"; - loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; - fdt = "fdt-0"; - }; - }; - }; - }; -}; - -&binman { - u-boot_unsigned { - insert-template = <&u_boot_unsigned_template>; - - fit { - images { - uboot { - description = "U-Boot for AM62Ax board"; - }; - - fdt-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = AM62A7_PHYBOARD_LYRA_DTB; - }; - hash { - algo = "crc32"; - }; - }; - }; - - configurations { - default = "conf-0"; - - conf-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-0"; - }; - }; - }; - }; -}; - #include "k3-binman-capsule.dtsi" &capsule_tispl { diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 0685bdd7e0c..e64c165ecbf 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -98,43 +98,6 @@ }; }; -&binman { - tiboot3-am62ax-gp-evm.bin { - filename = "tiboot3-am62ax-gp-evm.bin"; - ti-secure-rom { - content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, - <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; - combined; - dm-data; - content-sbl = <&u_boot_spl_unsigned>; - load = <CONFIG_SPL_TEXT_BASE>; - content-sysfw = <&ti_fs_gp>; - load-sysfw = <0x40000>; - content-sysfw-data = <&combined_tifs_cfg_gp>; - load-sysfw-data = <0x67000>; - content-dm-data = <&combined_dm_cfg_gp>; - load-dm-data = <0x43c3a800>; - sw-rev = <1>; - keyfile = "ti-degenerate-key.pem"; - }; - u_boot_spl_unsigned: u-boot-spl { - no-expanded; - }; - ti_fs_gp: ti-fs-gp.bin { - filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; - type = "blob-ext"; - }; - combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { - filename = "combined-tifs-cfg.bin"; - type = "blob-ext"; - }; - combined_dm_cfg_gp: combined-dm-cfg-gp.bin { - filename = "combined-dm-cfg.bin"; - type = "blob-ext"; - }; - }; -}; - #endif #ifdef CONFIG_TARGET_AM62A7_A53_EVM @@ -181,23 +144,6 @@ }; - tifsstub-gp { - filename = "tifsstub.bin_gp"; - ti-secure-rom { - content = <&tifsstub_gp>; - core = "secure"; - load = <0x60000>; - sw-rev = <CONFIG_K3_X509_SWRV>; - keyfile = "ti-degenerate-key.pem"; - tifsstub; - }; - tifsstub_gp: tifsstub-gp.bin { - filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; - type = "blob-ext"; - optional; - }; - }; - ti-spl { insert-template = <&ti_spl_template>; @@ -229,18 +175,6 @@ }; }; - tifsstub-gp { - description = "TIFSSTUB"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; dm { ti-secure { content = <&dm>; @@ -275,7 +209,7 @@ description = "k3-am62a7-sk"; firmware = "atf"; loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; + "tifsstub-hs", "tifsstub-fs"; fdt = "fdt-0"; }; }; @@ -326,117 +260,4 @@ }; }; -&binman { - ti-spl_unsigned { - insert-template = <&ti_spl_unsigned_template>; - - fit { - images { - tifsstub-hs { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-hs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_hs"; - }; - }; - - tifsstub-fs { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-fs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_fs"; - }; - }; - - tifsstub-gp { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; - dm { - ti-dm { - filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - }; - }; - - fdt-0 { - description = "k3-am62a7-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = SPL_AM62A7_SK_DTB; - }; - }; - }; - - configurations { - default = "conf-0"; - - conf-0 { - description = "k3-am62a7-sk"; - firmware = "atf"; - loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; - fdt = "fdt-0"; - }; - }; - }; - }; -}; - -&binman { - u-boot_unsigned { - insert-template = <&u_boot_unsigned_template>; - - fit { - images { - uboot { - description = "U-Boot for AM62Ax Board"; - }; - - fdt-0 { - description = "k3-am62a7-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = AM62A7_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; - }; - - configurations { - default = "conf-0"; - - conf-0 { - description = "k3-am62a7-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-0"; - }; - }; - }; - }; -}; #endif diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts index 63b7864a469..96860e80e9a 100644 --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -70,7 +70,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index 49e62533a95..64923c2c710 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -63,7 +63,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts index b18b4ce1272..e45d2bf6a0b 100644 --- a/arch/arm/dts/k3-am62p5-r5-sk.dts +++ b/arch/arm/dts/k3-am62p5-r5-sk.dts @@ -69,7 +69,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am62p5-verdin-r5.dts b/arch/arm/dts/k3-am62p5-verdin-r5.dts index 983a3bfe670..17739086935 100644 --- a/arch/arm/dts/k3-am62p5-verdin-r5.dts +++ b/arch/arm/dts/k3-am62p5-verdin-r5.dts @@ -57,7 +57,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 933f75095b1..67b8587d3b2 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -43,7 +43,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts index 40c25d5dbb6..32a10b24327 100644 --- a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts @@ -63,7 +63,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 6e31dfd97c5..cfc548a1cea 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -43,7 +43,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index ab5195eb15c..99eb8a2d442 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -47,7 +47,7 @@ &cbass_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts index 664be358a97..45d104e8e3f 100644 --- a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts +++ b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts @@ -69,7 +69,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 9ac29110324..e35b767a7e3 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -69,7 +69,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index c775432505b..e4f799dfb27 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -52,6 +52,7 @@ }; &hbmc { + status = "okay"; reg = <0x0 0x47040000 0x0 0x100>, <0x0 0x50000000 0x0 0x8000000>; ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi index 786a41c5e90..7398f9b05ec 100644 --- a/arch/arm/dts/k3-j721e-r5.dtsi +++ b/arch/arm/dts/k3-j721e-r5.dtsi @@ -66,7 +66,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { bootph-pre-ram; - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; }; diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index a820f516015..c1c12e217d2 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -63,7 +63,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts index 286ab50d3da..02a3494a877 100644 --- a/arch/arm/dts/k3-j722s-r5-evm.dts +++ b/arch/arm/dts/k3-j722s-r5-evm.dts @@ -68,7 +68,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi index a1394115b8b..78444dc4e14 100644 --- a/arch/arm/dts/k3-j784s4-r5.dtsi +++ b/arch/arm/dts/k3-j784s4-r5.dtsi @@ -61,7 +61,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 157d0ea6930..2f726b0aaba 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -27,6 +27,10 @@ }; }; +&otp { + bootph-some-ram; +}; + &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi index c9f302799f1..dff0355150d 100644 --- a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi @@ -7,6 +7,13 @@ #include "r8a779g0-u-boot.dtsi" +&avb0_pins { + pins-vddq18-25-avb { + pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; + power-source = <1800>; + }; +}; + /* Page 31 / FAN */ &gpio1 { pwm-fan-hog { @@ -44,7 +51,16 @@ &rpc { flash@0 { + /* + * EVTA1 is populated with Spansion S25FS512S + * EVTB1 is populated with Winbond W77Q51NW + */ + compatible = "jedec,spi-nor"; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; + +&vcc_sdhi { + states = <1800000 0>, <3300000 1>; +}; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 582d6ba49b4..c47d29c59de 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -4,7 +4,7 @@ */ #include "rk3328-u-boot.dtsi" -#include "rk3328-sdram-ddr4-666.dtsi" +#include "rk3328-sdram-ddr4-1600.dtsi" / { smbios { diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi new file mode 100644 index 00000000000..9594bb42839 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xA + 0x2 + 0x1 + 0x0 + 0x0 + 0x11 + 0x0 + 0x11 + 0x0 + 0 + + 0x94496354 + 0x00000000 + 0x0000002a + 0x000004e2 + 0x00000015 + 0x0000034a + 0x000000ff + + 800 + 0 + 1 + 0 + 0 + + 0x00000000 + 0x43041010 + 0x00000064 + 0x0061008c + 0x000000d0 + 0x000200c5 + 0x000000d4 + 0x00500000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x03140401 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00110000 + 0x000000e8 + 0x00000420 + 0x000000ec + 0x00000400 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x0c0e1b0e + 0x00000104 + 0x00030314 + 0x00000108 + 0x0506050b + 0x0000010c + 0x0040400c + 0x00000110 + 0x06030307 + 0x00000114 + 0x04040302 + 0x00000120 + 0x06060b06 + 0x00000124 + 0x00020308 + 0x00000180 + 0x01000040 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07040003 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x0600060c + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000c + 0x00000028 + 0x0000000c + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000009 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi index cc830b51456..9e1fb2a7eef 100644 --- a/arch/arm/dts/rk3528-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi @@ -1,12 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3528-u-boot.dtsi" - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - no-mmc; - no-sdio; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index 3f6f0bed108..637ca03325e 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3528 with eMMC enabled + * Minimal generic DT for RK3528 with eMMC and SD-card enabled */ /dts-v1/; @@ -10,6 +10,12 @@ model = "Generic RK3528"; compatible = "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:1500000n8"; }; @@ -25,6 +31,15 @@ status = "okay"; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0m0_xfer>; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 1372d8f1e38..16c47e6b9a9 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -6,11 +6,10 @@ mmc-hs200-1_8v; }; -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc_3v3>; - status = "okay"; +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; }; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi index eb6a55cd5c9..a18d33b3d36 100644 --- a/arch/arm/dts/rk3528-u-boot.dtsi +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -27,24 +27,6 @@ compatible = "rockchip,rk3528-otp"; reg = <0x0 0xffce0000 0x0 0x4000>; }; - - sdmmc: mmc@ffc30000 { - compatible = "rockchip,rk3528-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffc30000 0x0 0x4000>; - clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, - <&sdmmc_det>; - resets = <&cru SRST_H_SDMMC0>; - reset-names = "reset"; - rockchip,default-sample-phase = <90>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi new file mode 100644 index 00000000000..7e0530d85d1 --- /dev/null +++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; +}; + +&red_led { + default-state = "on"; +}; + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi new file mode 100644 index 00000000000..632fabb6af5 --- /dev/null +++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts new file mode 100644 index 00000000000..123be5378d9 --- /dev/null +++ b/arch/arm/dts/rk3576-generic.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "rk3576.dtsi" + +/ { + model = "Generic RK3576"; + compatible = "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index be99a48a630..fb5a107f47d 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -49,6 +49,10 @@ bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi index f67301d87a6..853ed58cfe5 100644 --- a/arch/arm/dts/rk3588-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -1,21 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3588s-u-boot.dtsi" - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index 95d757676f1..6740f9866f1 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -39,7 +39,23 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi new file mode 100644 index 00000000000..1ab31a4ec5a --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim1_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 4d7680455b7..770f6cad292 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -3,20 +3,40 @@ * U-Boot additions * * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ +#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi" /{ - memory { + aliases { + spi0 = &qspi; + i2c0 = &i2c1; + sysmgr = &sysmgr; + freeze_br0 = &freeze_controller; + }; + + memory@0 { + device_type = "memory"; #address-cells = <2>; #size-cells = <2>; bootph-all; }; - soc { + pmu { + compatible = "arm,armv8-pmuv3"; + }; + + soc@0 { bootph-all; + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; + ccu: cache-controller@f7000000 { compatible = "arteris,ncore-ccu"; reg = <0xf7000000 0x100900>; @@ -29,11 +49,39 @@ bootph-all; }; +&gmac0 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX_EMAC0_CLK>; + clock-names = "stmmaceth"; + phy-mode = "rgmii"; + max-frame-size = <0x2328>; + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + &gmac1 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reset-names = "stmmaceth", "stmmaceth-ocp"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + clocks = <&clkmgr AGILEX_EMAC1_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; altr,sysmgr-syscon = <&sysmgr 0x48 0>; }; &gmac2 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reset-names = "stmmaceth", "stmmaceth-ocp"; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + clocks = <&clkmgr AGILEX_EMAC2_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; altr,sysmgr-syscon = <&sysmgr 0x4c 0>; }; @@ -43,6 +91,7 @@ &i2c1 { reset-names = "i2c"; + status = "okay"; }; &i2c2 { @@ -67,6 +116,15 @@ &qspi { bootph-all; + compatible = "cdns,qspi-nor"; + flash0: flash@0 { + }; +}; + +&flash0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; }; &rst { @@ -84,6 +142,79 @@ bootph-all; }; +&socfpga_l3interconnect_firewall { + CCU_coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* Disable ocram security at CCU for non secure access */ + <0x0000004 0x8000ffff 0xe003ffff>, + <0x0000008 0x8000ffff 0xe003ffff>, + <0x000000c 0x8000ffff 0xe003ffff>, + <0x0000010 0x8000ffff 0xe003ffff>; + bootph-all; + }; + + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>, + /* Disable MPFE firewall for HMC adapter */ + <0x00000004 0x00000001 0x00010101>; + bootph-all; + }; + + /* + * Below are all fpga2sdram firewall settings with default + * reset value for the sake of easy reference by users. + * Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 { + reg = <0xf8020100 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000 0x0000000f>, + <0x0000004 0x00000000 0x0000000f>, + <0x0000008 0x00000000 0x0000000f>, + <0x0000010 0x00000000 0xffff0000>, + <0x0000014 0x00000000 0x000000ff>, + <0x0000018 0x00000000 0xffff0000>, + <0x000001c 0x00000000 0x000000ff>, + <0x0000020 0x00000000 0xffff0000>, + <0x0000024 0x00000000 0x000000ff>, + <0x0000028 0x00000000 0xffff0000>, + <0x000002c 0x00000000 0x000000ff>, + <0x0000030 0x00000000 0xffff0000>, + <0x0000034 0x00000000 0x000000ff>, + <0x0000038 0x00000000 0xffff0000>, + <0x000003c 0x00000000 0x000000ff>, + <0x0000040 0x00000000 0xffff0000>, + <0x0000044 0x00000000 0x000000ff>, + <0x0000048 0x00000000 0xffff0000>, + <0x000004c 0x00000000 0x000000ff>; + bootph-all; + }; + + /* + * Example of ccu_mem0_I_main QOS settings with + * default reset value for the sake of easy reference + * by users. Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 { + reg = <0xf8022080 0x0000001c>; + intel,offset-settings = + <0x0000008 0x00000200 0x00000303>, + <0x000000c 0x00000003 0x00000003>, + <0x0000010 0x00000BFE 0x00007fff>, + <0x0000014 0x00000008 0x000003ff>, + <0x0000018 0x00000000 0x0000000f>; + bootph-all; + }; +}; + &sysmgr { compatible = "altr,sys-mgr", "syscon"; bootph-all; @@ -91,8 +222,51 @@ &uart0 { bootph-all; + clock-frequency = <100000000>; }; &watchdog0 { bootph-all; }; + +&nand { + clocks = <&clkmgr AGILEX_NAND_CLK>, + <&clkmgr AGILEX_NAND_X_CLK>; + clock-names = "nand", "nand_x"; +}; + +&usb0 { + compatible = "snps,dwc2"; +}; + +&usb1 { + compatible = "snps,dwc2"; +}; + +&spi0 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; +}; + +&spi1 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; +}; + +&pdma { + #dma-channels = <8>; + #dma-requests = <32>; +}; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&binman { + /delete-node/ kernel; +}; +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +&sdr { + compatible = "intel,sdr-ctl-agilex7m"; + reg = <0xf8020000 0x100>; +}; +#endif diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi deleted file mode 100644 index 712304d07a4..00000000000 --- a/arch/arm/dts/socfpga_agilex.dtsi +++ /dev/null @@ -1,624 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> - */ - -/dts-v1/; -#include <dt-bindings/reset/altr,rst-mgr-s10.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/agilex-clock.h> - -/ { - compatible = "intel,socfpga-agilex"; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x2000000>; - alignment = <0x1000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 170 4>, - <0 171 4>, - <0 172 4>, - <0 173 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - intc: intc@fffc1000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0xfffc1000 0x0 0x1000>, - <0x0 0xfffc2000 0x0 0x2000>, - <0x0 0xfffc4000 0x0 0x2000>, - <0x0 0xfffc6000 0x0 0x2000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges = <0 0 0 0xffffffff>; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - clkmgr: clock-controller@ffd10000 { - compatible = "intel,agilex-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; - - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff800000 0x2000>; - interrupts = <0 90 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 1>; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - clocks = <&clkmgr AGILEX_EMAC0_CLK>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff802000 0x2000>; - interrupts = <0 91 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 8>; - clocks = <&clkmgr AGILEX_EMAC1_CLK>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff804000 0x2000>; - interrupts = <0 92 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 16>; - clocks = <&clkmgr AGILEX_EMAC2_CLK>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - - gpio0: gpio@ffc03200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03200 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 110 4>; - }; - }; - - gpio1: gpio@ffc03300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03300 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 111 4>; - }; - }; - - i2c0: i2c@ffc02800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02800 0x100>; - interrupts = <0 103 4>; - resets = <&rst I2C0_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c1: i2c@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02900 0x100>; - interrupts = <0 104 4>; - resets = <&rst I2C1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c2: i2c@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02a00 0x100>; - interrupts = <0 105 4>; - resets = <&rst I2C2_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c3: i2c@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02b00 0x100>; - interrupts = <0 106 4>; - resets = <&rst I2C3_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c4: i2c@ffc02c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02c00 0x100>; - interrupts = <0 107 4>; - resets = <&rst I2C4_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 96 4>; - fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; - clocks = <&clkmgr AGILEX_L4_MP_CLK>, - <&clkmgr AGILEX_SDMMC_CLK>; - clock-names = "biu", "ciu"; - iommus = <&smmu 5>; - status = "disabled"; - }; - - nand: nand@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x10000>, - <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 97 4>; - resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - pdma: pdma@ffda0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda0000 0x1000>; - interrupts = <0 81 4>, - <0 82 4>, - <0 83 4>, - <0 84 4>, - <0 85 4>, - <0 86 4>, - <0 87 4>, - <0 88 4>, - <0 89 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - clock-names = "apb_pclk"; - }; - - rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; - reg = <0xffd11000 0x100>; - }; - - smmu: iommu@fa000000 { - compatible = "arm,mmu-500", "arm,smmu-v2"; - reg = <0xfa000000 0x40000>; - #global-interrupts = <2>; - #iommu-cells = <1>; - interrupt-parent = <&intc>; - interrupts = <0 128 4>, /* Global Secure Fault */ - <0 129 4>, /* Global Non-secure Fault */ - /* Non-secure Context Interrupts (32) */ - <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, - <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, - <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; - stream-match-mask = <0x7ff0>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "intel,agilex-spi", - "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x1000>; - interrupts = <0 99 4>; - resets = <&rst SPIM0_RESET>; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "intel,agilex-spi", - "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x1000>; - interrupts = <0 100 4>; - resets = <&rst SPIM1_RESET>; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd12000 { - compatible = "altr,sys-mgr-s10","altr,sys-mgr"; - reg = <0xffd12000 0x500>; - }; - - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - timer0: timer0@ffc03000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 113 4>; - reg = <0xffc03000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer1: timer1@ffc03100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 114 4>; - reg = <0xffc03100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 4>; - reg = <0xffd00000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 4>; - reg = <0xffd00100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 108 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART0_RESET>; - status = "disabled"; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-frequency = <100000000>; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 109 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0x40000>; - interrupts = <0 93 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr AGILEX_USB_CLK>; - iommus = <&smmu 6>; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0x40000>; - interrupts = <0 94 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - iommus = <&smmu 7>; - clocks = <&clkmgr AGILEX_USB_CLK>; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 117 4>; - resets = <&rst WATCHDOG0_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 118 4>; - resets = <&rst WATCHDOG1_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog2: watchdog@ffd00400 { - compatible = "snps,dw-wdt"; - reg = <0xffd00400 0x100>; - interrupts = <0 125 4>; - resets = <&rst WATCHDOG2_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog3: watchdog@ffd00500 { - compatible = "snps,dw-wdt"; - reg = <0xffd00500 0x100>; - interrupts = <0 126 4>; - resets = <&rst WATCHDOG3_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - sdr: sdr@f8011100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xf8011100 0xc0>; - }; - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager", - "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc", - "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8cc000 0x100>; - altr,ecc-parent = <&ocram>; - interrupts = <1 4>; - }; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc", - "altr,socfpga-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 4>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; - }; - - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - - qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff8d2000 0x100>, - <0xff900000 0x100000>; - interrupts = <0 3 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - - status = "disabled"; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 9bc3864022b..7f4266dd5f1 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -596,4 +596,8 @@ }; }; }; + + aliases { + sysmgr = &sysmgr; + }; }; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 63df28e8364..6f2fe7bf746 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -3,41 +3,139 @@ * U-Boot additions * * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_agilex-u-boot.dtsi" +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX /{ - aliases { - spi0 = &qspi; - i2c0 = &i2c1; - freeze_br0 = &freeze_controller; + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand; }; - soc { - freeze_controller: freeze_controller@f9000450 { - compatible = "altr,freeze-bridge-controller"; - reg = <0xf9000450 0x00000010>; - status = "disabled"; - }; - }; - - memory { + memory@0 { /* 8GB */ reg = <0 0x00000000 0 0x80000000>, <2 0x80000000 1 0x80000000>; }; }; -&flash0 { - compatible = "jedec,spi-nor"; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - bootph-all; +&qspi { + status = "okay"; +}; +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +/{ + model = "SoCFPGA Agilex7-M SoCDK"; + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc; + }; + + memory@0 { + /* + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>, + * <0x1 0x00000000 0x1 0x80000000>; + * }; + * + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x00000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>, + * <0x1 0x00000000 0x1 0x40000000>; + * }; + */ + + /* Default memory size is 2GB */ + reg = <0x0 0x00000000 0x0 0x80000000>; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy2: ethernet-phy@2 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&socfpga_l3interconnect_firewall { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>; + }; +}; +#endif + +&gmac0 { + mdio0 { + ethernet_phy0: ethernet-phy@0 { + reg = <4>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + rxd0-skew-ps = <0x1a4>; + rxd1-skew-ps = <0x1a4>; + rxd2-skew-ps = <0x1a4>; + rxd3-skew-ps = <0x1a4>; + txen-skew-ps = <0>; + txc-skew-ps = <0x384>; + rxdv-skew-ps = <0x1a4>; + rxc-skew-ps = <0x690>; + }; + }; }; -&i2c1 { +&nand { status = "okay"; + nand-bus-width = <16>; + bootph-all; }; &mmc { @@ -47,9 +145,39 @@ }; &qspi { - status = "okay"; + /delete-property/ clocks; }; -&watchdog0 { +&flash0 { + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <100000000>; bootph-all; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + /delete-property/ cdns,read-delay; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; + }; + }; }; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts deleted file mode 100644 index bcdeecc0e02..00000000000 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ -#include "socfpga_agilex.dtsi" - -/ { - model = "SoCFPGA Agilex SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&mmc { - status = "okay"; - cap-sd-highspeed; - broken-cd; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&qspi { - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mt25qu02g"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; - }; - - qspi_rootfs: partition@34B0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; - }; - }; - }; -}; diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 00000000000..ce5b37ef547 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +/ { + soc@0 { + socfpga-system-mgr-firewall { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + i_sys_mgr_core@ffd12000 { + reg = <0xffd12000 0x00000230>; + intel,offset-settings = + /* Enable non-secure interface to DMA */ + <0x00000020 0xff010000 0xff010011>, + /* Enable non-secure interface to DMA periph */ + <0x00000024 0xffffffff 0xffffffff>; + bootph-all; + }; + }; + + socfpga_l3interconnect_firewall:socfpga-l3interconnect-firewall { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + noc_fw_l4_per_l4_per_scr@ffd21000 { + reg = <0xffd21000 0x00000074>; + intel,offset-settings = + /* Disable L4 periphs firewall */ + <0x00000000 0x01010001 0x01010001>, + <0x00000004 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010101>, + <0x00000020 0x01010001 0x01010101>, + <0x00000024 0x01010001 0x01010101>, + <0x00000028 0x01010001 0x01010101>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010101>, + <0x00000048 0x01010001 0x01010101>, + <0x00000050 0x01010001 0x01010101>, + <0x00000054 0x01010001 0x01010101>, + <0x00000058 0x01010001 0x01010101>, + <0x0000005c 0x01010001 0x01010101>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>; + bootph-all; + }; + + noc_fw_l4_sys_l4_sys_scr@ffd21100 { + reg = <0xffd21100 0x00000098>; + intel,offset-settings = + /* Disable L4 system firewall */ + <0x00000008 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x00000014 0x01010001 0x01010001>, + <0x00000018 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010001>, + <0x00000020 0x01010001 0x01010001>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000038 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010001>, + <0x00000048 0x01010001 0x01010001>, + <0x0000004c 0x01010001 0x01010001>, + <0x00000054 0x01010001 0x01010001>, + <0x00000058 0x01010001 0x01010001>, + <0x0000005c 0x01010001 0x01010001>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>, + <0x00000074 0x01010001 0x01010101>, + <0x00000078 0x01010001 0x03010001>, + <0x00000090 0x01010001 0x01010001>, + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 { + reg = <0xffd21200 0x00000004>; + /* Disable soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 { + reg = <0xffd21300 0x00000004>; + /* Disable lightweight soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + /* Disable DMA ECC security access, for SMMU use */ + intel,offset-settings = <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_priv_MemoryMap_priv@ffd24800 { + reg = <0xffd24800 0x0000000c>; + intel,offset-settings = + /* Enable non-prviledged access to various periphs */ + <0x00000000 0xfff73ffb 0xfff73ffb>; + bootph-all; + }; + }; + + socfpga_smmu_secure_config: socfpga-smmu-secure-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* TCU */ + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + intel,offset-settings = + <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + + /* System manager */ + i_sys_mgt_sysmgr_csr@ffd12000 { + reg = <0xffd12000 0x00000500>; + intel,offset-settings = + /* i_sys_mgr_core_emac0 */ + <0x00000044 0x0a000000 0xffff0103>, + /* i_sys_mgr_core_emac1 */ + <0x00000048 0x0a000000 0xffff0103>, + /* i_sys_mgr_core_emac2 */ + <0x0000004c 0x0a000000 0xffff0103>, + /* i_sys_mgr_core_nand_l3master */ + <0x00000034 0x00220000 0x007733ff>, + /* i_sys_mgr_core_sdmmc_l3master */ + <0x0000002c 0x00000020 0x03ff03ff>, + /* i_sys_mgr_core_usb0_l3master */ + <0x00000038 0x00000200 0x03ff30ff>, + /* i_sys_mgr_core_usb1_l3master */ + <0x0000003c 0x00000200 0x03ff30ff>; + bootph-all; + }; + }; + }; +}; diff --git a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi deleted file mode 100644 index 052b010a560..00000000000 --- a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io> - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Elimo Impetus SoM"; - compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-s3-elimo-initium.dts b/arch/arm/dts/sun8i-s3-elimo-initium.dts deleted file mode 100644 index 039677c2cc6..00000000000 --- a/arch/arm/dts/sun8i-s3-elimo-initium.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io> - */ - -/dts-v1/; -#include "sun8i-s3-elimo-impetus.dtsi" - -/ { - model = "Elimo Initium"; - compatible = "elimo,initium", "elimo,impetus", "sochip,s3", - "allwinner,sun8i-v3"; - - aliases { - serial1 = &uart1; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pg_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts deleted file mode 100644 index d18192d51d1..00000000000 --- a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Sipeed Lichee Zero Plus"; - compatible = "sipeed,lichee-zero-plus", "sochip,s3", - "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts deleted file mode 100644 index e0d4404b595..00000000000 --- a/arch/arm/dts/sun8i-s3-pinecube.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2019 Icenowy Zheng <icenowy@aosc.io> - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "PineCube IP Camera"; - compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "pine64:ir:led1"; - gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ - }; - - led2 { - label = "pine64:ir:led2"; - gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vcc_wifi: vcc-wifi { - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ - vin-supply = <®_dcdc3>; - startup-delay-us = <200000>; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ - post-power-on-delay-ms = <200>; - }; -}; - -&csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&csi1_8bit_pins>; - status = "okay"; - - port { - csi1_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pe_pins>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&csi1_mclk_pin>; - clocks = <&ccu CLK_CSI1_MCLK>; - clock-names = "xclk"; - - AVDD-supply = <®_ldo3>; - DOVDD-supply = <®_ldo3>; - DVDD-supply = <®_ldo4>; - reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ - powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ - - port { - ov5640_ep: endpoint { - remote-endpoint = <&csi1_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Setup"; - linux,code = <KEY_SETUP>; - channel = <0>; - voltage = <190000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc_wifi>; - vqmmc-supply = <®_dcdc3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_dcdc3>; - vcc-pe-supply = <®_ldo3>; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-sys-cpu-ephy"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-dovdd-2v8-csi"; - regulator-soft-start; - regulator-ramp-delay = <1600>; -}; - -®_ldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-1v8-csi"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/dts/sun8i-v3-sl631-imx179.dts deleted file mode 100644 index 117aeece4e5..00000000000 --- a/arch/arm/dts/sun8i-v3-sl631-imx179.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2020 Paul Kocialkowski <contact@paulk.fr> - */ - -#include "sun8i-v3-sl631.dtsi" - -/ { - model = "SL631 Action Camera with IMX179"; - compatible = "allwinner,sl631-imx179", "allwinner,sl631", - "allwinner,sun8i-v3"; -}; diff --git a/arch/arm/dts/sun8i-v3-sl631.dtsi b/arch/arm/dts/sun8i-v3-sl631.dtsi deleted file mode 100644 index 6f93f8c49f8..00000000000 --- a/arch/arm/dts/sun8i-v3-sl631.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2020 Paul Kocialkowski <contact@paulk.fr> - */ - -/dts-v1/; - -#include "sun8i-v3.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "SL631 Action Camera"; - compatible = "allwinner,sl631", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pb_pins>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-174 { - label = "Down"; - linux,code = <KEY_DOWN>; - channel = <0>; - voltage = <174603>; - }; - - button-384 { - label = "Up"; - linux,code = <KEY_UP>; - channel = <0>; - voltage = <384126>; - }; - - button-593 { - label = "OK"; - linux,code = <KEY_OK>; - channel = <0>; - voltage = <593650>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - vmmc-supply = <®_dcdc3>; - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_dcdc3>; - vcc-pe-supply = <®_dcdc3>; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-sys-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vdd-3v3"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pg_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi deleted file mode 100644 index 186c30cbe6e..00000000000 --- a/arch/arm/dts/sun8i-v3.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> - * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org> - */ - -#include "sun8i-v3s.dtsi" - -/ { - soc { - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-v3-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins>; - resets = <&ccu RST_BUS_I2S0>; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun8i-v3-ccu"; -}; - -&codec_analog { - compatible = "allwinner,sun8i-v3-codec-analog", - "allwinner,sun8i-h3-codec-analog"; -}; - -&emac { - /delete-property/ phy-handle; - /delete-property/ phy-mode; -}; - -&mdio_mux { - external_mdio: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&pio { - compatible = "allwinner,sun8i-v3-pinctrl"; - - i2s0_pins: i2s0-pins { - pins = "PG10", "PG11", "PG12", "PG13"; - function = "i2s"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; -}; diff --git a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts b/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts deleted file mode 100644 index f34dfdf1566..00000000000 --- a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include <dt-bindings/input/linux-event-codes.h> -#include "sun8i-v3s.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Anbernic RG Nano"; - compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; - - aliases { - rtc0 = &pcf8563; - rtc1 = &rtc; - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; - default-brightness-level = <11>; - power-supply = <®_vcc5v0>; - pwms = <&pwm 0 40000 1>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - button-a { - gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-A"; - linux,code = <BTN_EAST>; - }; - - button-b { - gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-B"; - linux,code = <BTN_SOUTH>; - }; - - button-down { - gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-DOWN"; - linux,code = <BTN_DPAD_DOWN>; - }; - - button-left { - gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-LEFT"; - linux,code = <BTN_DPAD_LEFT>; - }; - - button-right { - gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-RIGHT"; - linux,code = <BTN_DPAD_RIGHT>; - }; - - button-se { - gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-SELECT"; - linux,code = <BTN_SELECT>; - }; - - button-st { - gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-START"; - linux,code = <BTN_START>; - }; - - button-tl { - gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-L"; - linux,code = <BTN_TL>; - }; - - button-tr { - gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-R"; - linux,code = <BTN_TR>; - }; - - button-up { - gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-UP"; - linux,code = <BTN_DPAD_UP>; - }; - - button-x { - gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-X"; - linux,code = <BTN_NORTH>; - }; - - button-y { - gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-Y"; - linux,code = <BTN_WEST>; - }; - }; -}; - -&codec { - allwinner,audio-routing = "Speaker", "HP", - "MIC1", "Mic", - "Mic", "HBIAS"; - allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */ - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - gpio_expander: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ - vcc-supply = <®_vcc3v3>; - }; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&pio>; - interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */ - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&battery_power_supply { - status = "okay"; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - disable-wp; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pio { - vcc-pb-supply = <®_vcc3v3>; - vcc-pc-supply = <®_vcc3v3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-pg-supply = <®_vcc3v3>; - - spi0_no_miso_pins: spi0-no-miso-pins { - pins = "PC1", "PC2", "PC3"; - function = "spi0"; - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_pin>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ -®_dcdc2 { - regulator-always-on; - regulator-max-microvolt = <1250000>; - regulator-min-microvolt = <1250000>; - regulator-name = "vdd-cpu"; -}; - -/* DCDC3 wired into every 3.3v input that isn't the RTC. */ -®_dcdc3 { - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "vcc-io"; -}; - -/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */ -®_ldo1 { - regulator-always-on; - regulator-name = "vcc-rtc"; -}; - -/* LDO2 wired into VCC-PLL and audio codec. */ -®_ldo2 { - regulator-always-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - regulator-name = "vcc-pll"; -}; - -/* LDO3, LDO4, and LDO5 unused. */ -®_ldo3 { - status = "disabled"; -}; - -®_ldo4 { - status = "disabled"; -}; - -/* RTC uses internal oscillator */ -&rtc { - /delete-property/ clocks; -}; - -&spi0 { - pinctrl-0 = <&spi0_no_miso_pins>; - pinctrl-names = "default"; - status = "okay"; - - display@0 { - compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; - reg = <0>; - backlight = <&backlight>; - dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ - reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - spi-max-frequency = <100000000>; - - height-mm = <39>; - width-mm = <39>; - - /* Set hb-porch to compensate for non-visible area */ - panel-timing { - hactive = <240>; - vactive = <240>; - hback-porch = <80>; - vback-porch = <0>; - clock-frequency = <0>; - hfront-porch = <0>; - hsync-len = <0>; - vfront-porch = <0>; - vsync-len = <0>; - }; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */ - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts deleted file mode 100644 index 752ad05c8f8..00000000000 --- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-v3s-licheepi-zero.dts" - -#include <dt-bindings/input/input.h> - -/ { - model = "Lichee Pi Zero with Dock"; - compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", - "allwinner,sun8i-v3s"; - - aliases { - ethernet0 = &emac; - }; - - leds { - /* The LEDs use PG0~2 pins, which conflict with MMC1 */ - status = "disabled"; - }; -}; - -&emac { - allwinner,leds-active-low; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; - - button-600 { - label = "Select"; - linux,code = <KEY_SELECT>; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Start"; - linux,code = <KEY_OK>; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc1 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts deleted file mode 100644 index 2e4587d26ce..00000000000 --- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-v3s.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Lichee Pi Zero"; - compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue_led { - label = "licheepi:blue:usr"; - gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - }; - - green_led { - label = "licheepi:green:usr"; - gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - default-state = "on"; - }; - - red_led { - label = "licheepi:red:usr"; - gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ - }; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi deleted file mode 100644 index b3a32534762..00000000000 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ /dev/null @@ -1,656 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/sun6i-rtc.h> -#include <dt-bindings/clock/sun8i-v3s-ccu.h> -#include <dt-bindings/reset/sun8i-v3s-ccu.h> -#include <dt-bindings/clock/sun8i-de2.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer0-lcd0"; - clocks = <&display_clocks CLK_MIXER0>, - <&ccu CLK_TCON0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-v3s-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext-osc32k"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-v3s-de2-clk"; - reg = <0x01000000 0x10000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-v3s-de2-mixer"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks 0>, - <&display_clocks 6>; - clock-names = "bus", - "mod"; - resets = <&display_clocks 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_mixer0>; - }; - }; - }; - }; - - syscon: system-control@1c00000 { - compatible = "allwinner,sun8i-v3s-system-control", - "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0xd0>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - nmi_intc: interrupt-controller@1c000d0 { - compatible = "allwinner,sun8i-v3s-nmi", - "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c000d0 0x0c>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-v3s-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-v3s-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON0>, - <&ccu CLK_TCON0>; - clock-names = "ahb", - "tcon-ch0"; - clock-output-names = "tcon-data-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - crypto@1c15000 { - compatible = "allwinner,sun8i-v3s-crypto", - "allwinner,sun8i-a33-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "ahb", "mod"; - dmas = <&dma 16>, <&dma 16>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_CE>; - reset-names = "ahb"; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-h3-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-v3s-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu0"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb0_phy"; - resets = <&ccu RST_USB_PHY0>; - reset-names = "usb0_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci: usb@1c1a000 { - compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci: usb@1c1a400 { - compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-v3s-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rtc: rtc@1c20400 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-v3-rtc"; - reg = <0x01c20400 0x54>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc32k>; - clock-output-names = "osc32k", "osc32k-out"; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-v3s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - /omit-if-no-ref/ - csi0_mclk_pin: csi0-mclk-pin { - pins = "PE20"; - function = "csi_mipi"; - }; - - /omit-if-no-ref/ - csi1_8bit_pins: csi1-8bit-pins { - pins = "PE0", "PE2", "PE3", "PE8", "PE9", - "PE10", "PE11", "PE12", "PE13", "PE14", - "PE15"; - function = "csi"; - }; - - /omit-if-no-ref/ - csi1_mclk_pin: csi1-mclk-pin { - pins = "PE1"; - function = "csi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB6", "PB7"; - function = "i2c0"; - }; - - /omit-if-no-ref/ - i2c1_pb_pins: i2c1-pb-pins { - pins = "PB8", "PB9"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - i2c1_pe_pins: i2c1-pe-pins { - pins = "PE21", "PE22"; - function = "i2c1"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB8", "PB9"; - function = "uart0"; - }; - - uart2_pins: uart2-pins { - pins = "PB0", "PB1"; - function = "uart2"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - pwm0_pin: pwm0-pin { - pins = "PB4"; - function = "pwm0"; - }; - - /omit-if-no-ref/ - pwm1_pin: pwm1-pin { - pins = "PB5"; - function = "pwm1"; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-v3s-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun8i-v3s-pwm", - "allwinner,sun7i-a20-pwm"; - reg = <0x01c21400 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x400>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-v3s-codec"; - reg = <0x01c22c00 0x400>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "codec"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,codec-analog-controls = <&codec_analog>; - status = "disabled"; - }; - - codec_analog: codec-analog@1c23000 { - compatible = "allwinner,sun8i-v3s-codec-analog"; - reg = <0x01c23000 0x4>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART2>; - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-v3s-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x10000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - - mdio_mux: mdio-mux { - compatible = "allwinner,sun8i-h3-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - - mdio-parent-bus = <&mdio>; - /* Only one MDIO is usable at the time */ - internal_mdio: mdio@1 { - compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; - }; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - csi1: camera@1cb4000 { - compatible = "allwinner,sun8i-v3s-csi"; - reg = <0x01cb4000 0x3000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts b/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts new file mode 100644 index 00000000000..2007aae8737 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra114-microsoft-surface-2-common.dtsi" + +/ { + backlight: backlight { + enable-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-13.dts b/arch/arm/dts/tegra114-microsoft-surface-2-13.dts new file mode 100644 index 00000000000..da121d5a101 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-13.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra114-microsoft-surface-2-common.dtsi" + +/ { + backlight: backlight { + enable-gpios = <&gpio TEGRA_GPIO(EE, 3) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi new file mode 100644 index 00000000000..f8f71262538 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi @@ -0,0 +1,905 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> +#include "tegra114.dtsi" + +/ { + model = "Microsoft Surface 2"; + compatible = "microsoft,surface-2", "nvidia,tegra114"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel@0 { + compatible = "samsung,ltl106hl02-001"; + reg = <0>; + + vdd-supply = <&tps65090_fet4>; + + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* ULPI pinmux */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data3_po4", + "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi-data1 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi-data2 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi-data7 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2S pinmux */ + dap1-din { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1-dout { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap2-i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3-i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4-din { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap4-dout { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC1 pinmux */ + sdmmc1-wp-clk { + nvidia,pins = "sdmmc1_wp_n_pv3", + "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-clk-lb-out { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi-int { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + + /* UARTA pinmux */ + uarta-out { + nvidia,pins = "pu0", "pu3"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uarta-in { + nvidia,pins = "pu1", "pu2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UARTB pinmux */ + uart2-txd-pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UARTC pinmux */ + uart3-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UARTD pinmux */ + uartd-out { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uartd-in { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GMI section */ + gmi-a17 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_iordy_pi5", + "kb_col1_pq1", + "kb_row8_ps0", + "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-wp-n { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_cs0_n_pj0", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_oe_n_pi1", + "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad8 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad9 { + nvidia,pins = "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad15_ph7", + "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad12 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gpio_x1_aud_px1", + "pcc1", + "clk3_req_pee1", + "clk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad14 { + nvidia,pins = "gmi_ad14_ph6", + "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-wr-n { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-cs6-n { + nvidia,pins = "gmi_cs6_n_pi3", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-rst-n { + nvidia,pins = "gmi_rst_n_pi4", + "spdif_out_pk5", + "spdif_in_pk6", + "clk2_out_pw5", + "dvfs_pwm_px0", + "dvfs_clk_px2", + "pbb7", + "pcc2", + "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-wait { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-cs1-n { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-dqs-p { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-adv-n { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-clk { + nvidia,pins = "gmi_clk_pk1", + "gmi_cs2_n_pk3", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC pinmux */ + kb-col0 { + nvidia,pins = "kb_col0_pq0", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-col2 { + nvidia,pins = "kb_col2_pq2", + "kb_col6_pq6", + "kb_col7_pq7", + "kb_row0_pr0", + "kb_row2_pr2", + "pv0", + "sys_clk_req_pz5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-col5 { + nvidia,pins = "kb_col5_pq5", + "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row3 { + nvidia,pins = "kb_row3_pr3", + "kb_row9_ps1"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row7 { + nvidia,pins = "kb_row7_pr7", + "pbb3", + "pbb4", + "pbb5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row10 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* CORE pinmux */ + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUD pinmux */ + gpio-w2-aud { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-w3-aud { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x3-aud { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x4-aud { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio-x5-aud { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x6-aud { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb0 { + nvidia,pins = "pbb0", + "cam_mclk_pcc0"; + nvidia,function = "vi_alt1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* USB pinmux */ + usb-vbus-en0 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + usb-vbus-en1 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65090 PMIC */ + tps65090@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + regulators { + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + regulator-boot-on; + }; + + tps65090_fet4: fet4 { + regulator-name = "vdd_lcd"; + regulator-boot-on; + }; + + tps65090_fet6: fet6 { + regulator-name = "vdd_usd"; + regulator-boot-on; + }; + }; + }; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <5000>; + }; + + avdd_dsi_csi: ldo3 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&tps65090_fet6>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d000000 { + status = "okay"; + + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + power-supply = <&tps65090_fet1>; + pwms = <&pwm 0 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + linux,code = <SW_LID>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power Button"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-windows { + label = "Windows Button"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + }; +}; diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts index 0c301483180..4afde766330 100644 --- a/arch/arm/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts @@ -40,6 +40,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra20-asus-sl101.dts b/arch/arm/dts/tegra20-asus-sl101.dts index b4709c3e9a4..9f78b0febf3 100644 --- a/arch/arm/dts/tegra20-asus-sl101.dts +++ b/arch/arm/dts/tegra20-asus-sl101.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Slider SL101"; compatible = "asus,sl101", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-tablet-mode { + label = "Tablet Mode"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = <SW_TABLET_MODE>; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-tf101.dts b/arch/arm/dts/tegra20-asus-tf101.dts index 7c734fb5b19..03ba78c5dc2 100644 --- a/arch/arm/dts/tegra20-asus-tf101.dts +++ b/arch/arm/dts/tegra20-asus-tf101.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Transformer TF101"; compatible = "asus,tf101", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-tf101g.dts b/arch/arm/dts/tegra20-asus-tf101g.dts index f49a358a267..44d5fdfc2b5 100644 --- a/arch/arm/dts/tegra20-asus-tf101g.dts +++ b/arch/arm/dts/tegra20-asus-tf101g.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Transformer TF101G"; compatible = "asus,tf101g", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-transformer.dtsi b/arch/arm/dts/tegra20-asus-transformer.dtsi index 49efabbfd92..df078a6fcdc 100644 --- a/arch/arm/dts/tegra20-asus-transformer.dtsi +++ b/arch/arm/dts/tegra20-asus-transformer.dtsi @@ -36,6 +36,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -493,12 +497,6 @@ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_UP>; }; - - switch-dock-hall-sensor { - label = "Lid sensor"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,code = <SW_LID>; - }; }; panel: panel { diff --git a/arch/arm/dts/tegra20-lg-star.dts b/arch/arm/dts/tegra20-lg-star.dts index 3045bc3135f..083598b1b92 100644 --- a/arch/arm/dts/tegra20-lg-star.dts +++ b/arch/arm/dts/tegra20-lg-star.dts @@ -46,6 +46,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi index f00707c2859..db2cce1cc0d 100644 --- a/arch/arm/dts/tegra20-motorola-mot.dtsi +++ b/arch/arm/dts/tegra20-motorola-mot.dtsi @@ -62,6 +62,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra20-samsung-bose.dts b/arch/arm/dts/tegra20-samsung-bose.dts new file mode 100644 index 00000000000..5bb9a33adf2 --- /dev/null +++ b/arch/arm/dts/tegra20-samsung-bose.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-samsung-n1-common.dtsi" + +/ { + model = "Samsung Captivate Glide (SGH-i927)"; + compatible = "samsung,bose", "nvidia,tegra20"; + + aliases { + spi0 = &panel_spi; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&panel_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + conf-dtf { + nvidia,pins = "dtf", "spdi", "spib", "spih"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-gpv { + nvidia,pins = "gpv"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-kbcd { + nvidia,pins = "kbcd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + drive-dap { + nvidia,pins = "drive_dap2", "drive_dap3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + + panel_spi: spi@7000d800 { + status = "okay"; + spi-max-frequency = <1000000>; + + panel: panel@2 { + /* 480x800 AMOLED panel */ + compatible = "samsung,bose-panel", "samsung,s6e63m0"; + reg = <2>; + + spi-max-frequency = <1000000>; + + spi-cpol; + spi-cpha; + + reset-gpios = <&gpio TEGRA_GPIO(C, 1) GPIO_ACTIVE_LOW>; + + vdd3-supply = <&vlcd_1v8_reg>; + vci-supply = <&vlcd_3v0_reg>; + + panel-width-mm = <52>; + panel-height-mm = <87>; + + port { + panel_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + }; + }; + + sdhci@c8000400 { + broken-cd; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-hall { + label = "Keyboard Slide"; + gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; + linux,input-type = <EV_SW>; + linux,code = <SW_KEYPAD_SLIDE>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-kbd { + label = "Keyboard backlight"; + gpios = <&gpio TEGRA_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; diff --git a/arch/arm/dts/tegra20-samsung-n1-common.dtsi b/arch/arm/dts/tegra20-samsung-n1-common.dtsi new file mode 100644 index 00000000000..8223c5ece54 --- /dev/null +++ b/arch/arm/dts/tegra20-samsung-n1-common.dtsi @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> +#include "tegra20.dtsi" + +/ { + chosen { + stdout-path = &uartb; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata", "atc", "atd", "ate", + "gmb", "gmd", "irrx", "irtx", + "spid", "spie"; + nvidia,function = "gmi"; + }; + + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + + spif { + nvidia,pins = "spif", "uac"; + nvidia,function = "rsvd4"; + }; + + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + gpu { + nvidia,pins = "gpu", "uaa", "uab"; + nvidia,function = "uarta"; + }; + + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + + hdint { + nvidia,pins = "hdint", "spdi", "spdo"; + nvidia,function = "rsvd2"; + }; + + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + lcsn { + nvidia,pins = "lcsn", "lsck", "lsda", "lsdi"; + nvidia,function = "spi3"; + }; + + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldc", "ldi", + "lhp0", "lhp1", "lhp2", "lhs", "lm0", + "lm1", "lpp", "lpw0", "lpw1", "lpw2", + "lsc0", "lsc1", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + + owc { + nvidia,pins = "owc"; + nvidia,function = "owr"; + }; + + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "sdio3"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spi4"; + }; + + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + uda { + nvidia,pins = "uda"; + nvidia,function = "spi1"; + }; + + spia { + nvidia,pins = "spia", "spib", "spic"; + nvidia,function = "spi2"; + }; + + conf-cdev1 { + nvidia,pins = "cdev1", "cdev2", "dap1", "dap2", + "dap3", "dap4", "ddc", "dte", "gma", + "gmc", "gmd", "gme", "gpu7", "hdint", + "i2cp", "lcsn", "lhs", "lm0", "lm1", + "lpw1", "lsc0", "lsck", "lsda", "lsdi", + "lspi", "lvs", "pmc", "pta", "rm", + "sdb", "sdio1", "uac", "uda", "ck32", + "ddrc", "pmca", "pmcb", "pmcc", "pmcd", + "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-crtp { + nvidia,pins = "crtp", "lvp0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-csus { + nvidia,pins = "csus", "spid"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-ata { + nvidia,pins = "ata", "atb", "atc", "ate", + "gmb", "gpu", "irrx", "irtx", + "kbca", "kbcc", "kbce", "kbcf", + "ldc", "lpw0", "lpw2", "lsc1", "sdc", + "sdd", "spig", "uaa", "uab", + "uad", "uca", "ucb", "pmce"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-owc { + nvidia,pins = "owc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-atd { + nvidia,pins = "atd", "dta", "dtb", "dtc", "dtd", + "kbcb", "ld0", "ld1", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", "ld16", + "ld17", "ld2", "ld3", "ld4", "ld5", + "ld6", "ld7", "ld8", "ld9", "ldi", + "lhp0", "lhp1", "lhp2", "lpp", "lvp1", + "slxa", "slxc", "slxd", "slxk", "spdo", + "spia", "spic", "spie", "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + drive-ao1 { + nvidia,pins = "drive_ao1", "drive_at1", "drive_dbg", + "drive_vi1", "drive_vi2"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + drive-ddc { + nvidia,pins = "drive_ddc"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartb: serial@70006040 { + clocks = <&tegra_car 7>; + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max8907@3c { + compatible = "maxim,max8907"; + reg = <0x3c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + maxim,system-power-controller; + + regulators { + vlcd_1v8_reg: ldo3 { + regulator-name = "vlcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + usb_phy_reg: ldo4 { + regulator-name = "vap_usb_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vlcd_3v0_reg: ldo12 { + regulator-name = "vlcd_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vmmc_usd_reg: ldo16 { + regulator-name = "vmmc_usd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + + micro_usb: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&usb_phy_reg>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + vmmc-supply = <&vmmc_usd_reg>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + /* 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(U, 5) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; diff --git a/arch/arm/dts/tegra20-samsung-n1.dts b/arch/arm/dts/tegra20-samsung-n1.dts new file mode 100644 index 00000000000..930a3195aa0 --- /dev/null +++ b/arch/arm/dts/tegra20-samsung-n1.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-samsung-n1-common.dtsi" + +/ { + model = "Samsung Galaxy R (GT-I9103)"; + compatible = "samsung,n1", "nvidia,tegra20"; + + aliases { + i2c10 = &cmc_i2c; + spi0 = &panel_spi; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + conf-dtf { + nvidia,pins = "dtf", "spdi", "spih"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-gpv { + nvidia,pins = "gpv", "spib"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-kbcd { + nvidia,pins = "kbcd"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + i2c@7000d000 { + max8907@3c { + regulators { + vcmc623_io_1v8: ldo15 { + regulator-name = "vcmc623_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + cmc_i2c: i2c-10 { + compatible = "i2c-gpio"; + + sda-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + + i2c-gpio,scl-output-only; + i2c-gpio,delay-us = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + cmc623: bridge@38 { + compatible = "samsung,cmc623"; + reg = <0x38>; + + enable-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(J, 6) GPIO_ACTIVE_HIGH>; + + bypass-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>; + sleep-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + vdd3v0-supply = <&vcmc623_3v0>; + vdd1v2-supply = <&vcmc623_1v2>; + vddio1v8-supply = <&vcmc623_io_1v8>; + + cmc623_backlight: backlight { + compatible = "samsung,cmc623-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; + + panel_spi: spi@7000d800 { + status = "okay"; + spi-max-frequency = <1000000>; + + panel: panel@2 { + /* 480x800 TFT LCD panel */ + compatible = "sony,l4f00430t01"; + reg = <2>; + + spi-max-frequency = <1000000>; + + spi-cpol; + spi-cpha; + + reset-gpios = <&gpio TEGRA_GPIO(C, 1) GPIO_ACTIVE_LOW>; + + vdd1v8-supply = <&vlcd_1v8_reg>; + vdd3v0-supply = <&vlcd_3v0_reg>; + + panel-width-mm = <55>; + panel-height-mm = <91>; + + backlight = <&cmc623_backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; + + sdhci@c8000400 { + /* battery blocks the sdcard slot and the device lacks CD pin */ + non-removable; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + }; + + vcmc623_3v0: regulator-cmc623-3v0 { + compatible = "regulator-fixed"; + regulator-name = "vcmc623_3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcmc623_1v2: regulator-cmc623-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vcmc623_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpio TEGRA_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 275b3432bd8..4a40edfdfbe 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -249,6 +249,35 @@ */ }; + /* Audio Bitstream Engine */ + bsea@60011000 { + compatible = "nvidia,tegra20-bsea"; + reg = <0x60011000 0x1000>, <0x4000c000 0x4000>; + reg-names = "bsea", "iram-buffer"; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsea"; + clocks = <&tegra_car TEGRA20_CLK_BSEA>; + resets = <&tegra_car 62>; + reset-names = "bsea"; + status = "disabled"; + }; + + /* Video Bitstream Engine */ + bsev@6001b000 { + compatible = "nvidia,tegra20-bsev"; + reg = <0x6001b000 0x1000>, <0x40008000 0x4000>; + reg-names = "bsev", "iram-buffer"; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsev"; + clocks = <&tegra_car TEGRA20_CLK_BSEV>, + <&tegra_car TEGRA20_CLK_VDE>; + clock-names = "bsev", "vde"; + resets = <&tegra_car 63>, + <&tegra_car 61>; + reset-names = "bsev", "vde"; + status = "disabled"; + }; + apbmisc@70000800 { compatible = "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */ diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts index 9ef744ac8b0..ddeeb232de2 100644 --- a/arch/arm/dts/tegra210-p3450-0000.dts +++ b/arch/arm/dts/tegra210-p3450-0000.dts @@ -124,7 +124,14 @@ spi@70410000 { status = "okay"; - spi-max-frequency = <80000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; }; usb@7d000000 { diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index 28ecd2b467a..92eb4f67bf5 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -762,10 +762,10 @@ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_QSPI>; - clock-names = "qspi"; + clocks = <&tegra_car TEGRA210_CLK_QSPI>, + <&tegra_car TEGRA210_CLK_QSPI_PM>; + clock-names = "qspi", "qspi_out"; resets = <&tegra_car 211>; - reset-names = "qspi"; dmas = <&apbdma 5>, <&apbdma 5>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index d437ddc4dce..ddacdbb85c8 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -44,6 +44,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 58f1499cb92..31cbef1b93c 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -50,6 +50,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index 1b5729c65f4..5135b8c666c 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -53,6 +53,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index 032fb3d00ac..47a44fbc9dd 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -37,6 +37,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index db8ac457880..79f423bd22a 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -60,6 +60,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts index 876fac7b661..53f42089d30 100644 --- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts +++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts @@ -43,6 +43,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 40b0ee07787..09c5d04a225 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -42,6 +42,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts index 04453eb2432..e6b2824d783 100644 --- a/arch/arm/dts/tegra30-ouya.dts +++ b/arch/arm/dts/tegra30-ouya.dts @@ -56,6 +56,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-pegatron-chagall.dts b/arch/arm/dts/tegra30-pegatron-chagall.dts new file mode 100644 index 00000000000..98eb369f7a8 --- /dev/null +++ b/arch/arm/dts/tegra30-pegatron-chagall.dts @@ -0,0 +1,1291 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra30.dtsi" + +/ { + model = "Pegatron Chagall"; + compatible = "pegatron,chagall", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + /* HDMI-CEC pinmux */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-B */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2S pinmux */ + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_pwr2_pc6", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_sdin_pz2", + "lcd_wr_n_pz3", + "lcd_sck_pz4", + "lcd_cs1_n_pw0", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row7_pr7", + "kb_row10_ps2", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs4_n_pk2"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_ad12_ph4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI hot-plug-detect */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv2 { + nvidia,pins = "pv2", + "kb_row5_pr5"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <5>; + nvidia,pull-up-strength = <5>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + drive_lcd2 { + nvidia,pins = "drive_lcd2"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8_vio: vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-boot-on; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + sdmmc1: sdhci@78000000 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb3: usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + display-panel { + compatible = "hannstar,hsd101pww2", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + backlight = <&backlight>; + + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + + hactive = <1280>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + + vactive = <800>; + vfront-porch = <3>; + vback-porch = <12>; + vsync-len = <5>; + }; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + /* Texas Instruments SN75LVDS83B LVDS Transmitter */ + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts index b376b91a7fa..ededbf579fd 100644 --- a/arch/arm/dts/tegra30-wexler-qc750.dts +++ b/arch/arm/dts/tegra30-wexler-qc750.dts @@ -44,6 +44,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index d5de1ecaf05..82e843d05be 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -373,6 +373,35 @@ */ }; + /* Audio Bitstream Engine */ + bsea@60011000 { + compatible = "nvidia,tegra30-bsea"; + reg = <0x60011000 0x1000>, <0x4000c000 0x4000>; + reg-names = "bsea", "iram-buffer"; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsea"; + clocks = <&tegra_car TEGRA30_CLK_BSEA>; + resets = <&tegra_car 62>; + reset-names = "bsea"; + status = "disabled"; + }; + + /* Video Bitstream Engine */ + bsev@6001b000 { + compatible = "nvidia,tegra30-bsev"; + reg = <0x6001b000 0x1000>, <0x40008000 0x4000>; + reg-names = "bsev", "iram-buffer"; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsev"; + clocks = <&tegra_car TEGRA30_CLK_BSEV>, + <&tegra_car TEGRA30_CLK_VDE>; + clock-names = "bsev", "vde"; + resets = <&tegra_car 63>, + <&tegra_car 61>; + reset-names = "bsev", "vde"; + status = "disabled"; + }; + apbmisc@70000800 { compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 0d915d496ca..60ac5085f73 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -20,6 +20,11 @@ "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; model = "ZynqMP KR260 revB"; + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index df2148a53c7..455aa95339e 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -18,6 +18,7 @@ enum imx9_soc_voltage_mode { void soc_power_init(void); bool m33_is_rom_kicked(void); int m33_prepare(void); +int low_drive_freq_update(void *blob); enum imx9_soc_voltage_mode soc_target_voltage_mode(void); diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index b2d87524f70..e4005b94b54 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -17,25 +17,6 @@ #define CFG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } -/* NAND */ -#if defined(CONFIG_NAND_LPC32XX_SLC) -#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 -#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 - -#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) -#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } -#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) -#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } -#else -#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" -#endif - -#define CFG_SYS_NAND_ECCSIZE 0x100 -#define CFG_SYS_NAND_ECCBYTES 3 -#endif /* CONFIG_NAND_LPC32XX_SLC */ - /* NOR Flash */ /* USB OHCI */ diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index b922b2d30ea..295c3287737 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -55,6 +55,13 @@ int tegra_get_chip_sku(void); int tegra_get_chip(void); /** + * Returns the pure SOC major version from the HIDREV register + * + * Return: SOC major version + */ +u32 tegra_get_major_version(void); + +/** * Returns the SKU ID from the sku_info register * * Return: SKU ID - see SKU_ID_Txx... diff --git a/arch/arm/include/asm/arch-tegra/crypto.h b/arch/arm/include/asm/arch-tegra/crypto.h index 7646163b97b..930bc842039 100644 --- a/arch/arm/include/asm/arch-tegra/crypto.h +++ b/arch/arm/include/asm/arch-tegra/crypto.h @@ -7,41 +7,36 @@ #ifndef _CRYPTO_H_ #define _CRYPTO_H_ -/** - * Sign a block of data - * - * \param source Source data - * \param length Size of source data - * \param signature Destination address for signature, AES_KEY_LENGTH bytes - */ -int sign_data_block(u8 *source, unsigned int length, u8 *signature); +#define TEGRA_AES_SLOT_SBK 0 /** - * Sign an encrypted block of data + * sign_data_block - Sign a block of data * - * \param source Source data - * \param length Size of source data - * \param signature Destination address for signature, AES_KEY_LENGTH bytes - * \param key AES128 encryption key + * @source Source data + * @length Size of source data in bytes + * @signature Destination address for signature, AES_KEY_LENGTH bytes + * Return: 0 on success, negative value on failure */ -int sign_enc_data_block(u8 *source, unsigned int length, u8 *signature, u8 *key); +int sign_data_block(u8 *source, unsigned int length, u8 *signature); /** - * Encrypt a block of data + * encrypt_data_block - Encrypt a block of data * - * \param source Source data - * \param length Size of source data - * \param key AES128 encryption key + * @source Source data + * @dest Destination data + * @length Size of source data in bytes + * Return: 0 on success, negative value on failure */ -int encrypt_data_block(u8 *source, unsigned int length, u8 *key); +int encrypt_data_block(u8 *source, u8 *dest, unsigned int length); /** - * Decrypt a block of data + * decrypt_data_block - Decrypt a block of data * - * \param source Source data - * \param length Size of source data - * \param key AES128 encryption key + * @source Source data + * @dest Destination data + * @length Size of source data in bytes + * Return: 0 on success, negative value on failure */ -int decrypt_data_block(u8 *source, unsigned int length, u8 *key); +int decrypt_data_block(u8 *source, u8 *dest, unsigned int length); #endif /* #ifndef _CRYPTO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index ab12cc9c7d0..22f8f977cc6 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -448,6 +448,9 @@ enum win_color_depth_id { #define LVS_OUTPUT_POLARITY_LOW BIT(28) #define LSC0_OUTPUT_POLARITY_LOW BIT(24) +/* DC_COM_PIN_OUTPUT_POLARITY3 0x309 */ +#define LSPI_OUTPUT_POLARITY_LOW BIT(8) + /* DC_COM_PIN_OUTPUT_SELECT6 0x31a */ #define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */ diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h index f3f2ad8e3f2..631ebbb283c 100644 --- a/arch/arm/include/asm/arch-tegra/fuse.h +++ b/arch/arm/include/asm/arch-tegra/fuse.h @@ -17,8 +17,22 @@ struct fuse_regs { u32 fa; /* 0x148: FUSE_FA */ u32 reserved3[21]; /* 0x14C - 0x19C: */ u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ + u32 sbk[4]; /* 0x1A4 - 0x1B4 */ }; +/* Defines the supported operating modes */ +enum fuse_operating_mode { + MODE_UNDEFINED = 0, + MODE_PRODUCTION = 3, + MODE_ODM_PRODUCTION_SECURE = 4, + MODE_ODM_PRODUCTION_OPEN = 5, +}; + +/** + * Initializes fuse hardware + */ +void tegra_fuse_init(void); + /** * Calculate SoC UID * @@ -26,4 +40,11 @@ struct fuse_regs { */ unsigned long long tegra_chip_uid(void); +/** + * Gives the current operating mode from fuses + * + * @return current operating mode + */ +enum fuse_operating_mode tegra_fuse_get_operation_mode(void); + #endif /* ifndef _FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index 9a53456370f..4352f1dc5e8 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h @@ -10,12 +10,6 @@ #define STRAP_OPT_A_RAM_CODE_SHIFT 4 #define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) -/* Defines the supported operating modes */ -enum fuse_operating_mode { - MODE_PRODUCTION = 3, - MODE_UNDEFINED, -}; - /* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ enum { HASH_LENGTH = 4 @@ -125,7 +119,6 @@ union scratch3_reg { int warmboot_save_sdram_params(void); int warmboot_prepare_code(u32 seg_address, u32 seg_length); -int sign_data_block(u8 *source, u32 length, u8 *signature); void wb_start(void); /* Start of WB assembly code */ void wb_end(void); /* End of WB assembly code */ diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 7eb764e1f4e..ca4cec61f22 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -183,7 +183,7 @@ __weak void setup_board_tags(struct tag **in_params) {} static void do_nonsec_virt_switch(void) { smp_kick_all_cpus(); - dcache_disable(); /* flush cache before swtiching to EL2 */ + dcache_disable(); /* flush cache before switching to EL2 */ } #endif diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 28193039cb8..2cd67d02386 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -88,7 +88,7 @@ config TARGET_S5PC210_UNIVERSAL select MISC_COMMON config TARGET_ORIGEN - bool "Exynos4412 Origen board" + bool "Exynos4210 Origen board" select EXYNOS4210 select SUPPORT_SPL diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 48c325190d5..ed46ea03355 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -32,7 +32,7 @@ static void exynos5_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < start + count; i++) { @@ -63,7 +63,7 @@ static void exynos5420_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } @@ -97,12 +97,12 @@ static int exynos5_mmc_config(int peripheral, int flags) start_ext = 0; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", - peripheral); + debug("SDMMC device %d does not support 8bit mode\n", + peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { @@ -145,12 +145,12 @@ static int exynos5420_mmc_config(int peripheral, int flags) break; default: start = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", + debug("SDMMC device %d does not support 8bit mode\n", peripheral); return -1; } @@ -453,7 +453,7 @@ void exynos5420_spi_config(int peripheral) default: cfg = 0; pin = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } @@ -522,7 +522,7 @@ static int exynos5_pinmux_config(int peripheral, int flags) gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2)); break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -570,7 +570,7 @@ static int exynos5420_pinmux_config(int peripheral, int flags) gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2)); break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -683,7 +683,7 @@ static void exynos4_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < (start + count); i++) { @@ -797,7 +797,7 @@ static void exynos4x12_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < (start + count); i++) { @@ -834,7 +834,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) debug("SDMMC device %d not implemented\n", peripheral); return -1; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -869,7 +869,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) debug("SDMMC device %d not implemented\n", peripheral); return -1; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -902,7 +902,7 @@ static int exynos4_pinmux_decode_periph_id(const void *blob, int node) u32 cell[3]; err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); + ARRAY_SIZE(cell)); if (err) { debug(" invalid peripheral id\n"); return PERIPH_ID_NONE; @@ -917,7 +917,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node) u32 cell[3]; err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); + ARRAY_SIZE(cell)); if (err) return PERIPH_ID_NONE; diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8bd85e889ab..fa2cdaba144 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,6 +223,10 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) +ifneq ($(and $(CONFIG_IMX95),$(CONFIG_BINMAN)),) +SPL: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) +else quiet_cmd_cpp_cfg_imx9_check = CHECK $@ cmd_cpp_cfg_imx9_check = $(CPP) $(cpp_flags) -D__ASSEMBLY__ -x c -o $@ $< && $(srctree)/tools/imx9_image.sh $@ @@ -244,6 +248,7 @@ u-boot-container.cfgout: $(IMX_CONTAINER_CFG) FORCE flash.bin: spl/u-boot-spl-ddr.bin container.cfgout FORCE $(call if_changed,mkimage) endif +endif else MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d5745f67262..77c8efc7899 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -55,16 +55,16 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), - PLL_1443X_RATE(900000000U, 300, 8, 0, 0), - PLL_1443X_RATE(800000000U, 300, 9, 0, 0), - PLL_1443X_RATE(750000000U, 250, 8, 0, 0), + PLL_1443X_RATE(900000000U, 300, 2, 2, 0), + PLL_1443X_RATE(800000000U, 200, 3, 1, 0), + PLL_1443X_RATE(750000000U, 250, 2, 2, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(600000000U, 300, 3, 2, 0), PLL_1443X_RATE(594000000U, 99, 1, 2, 0), - PLL_1443X_RATE(400000000U, 300, 9, 1, 0), - PLL_1443X_RATE(266000000U, 400, 9, 2, 0), + PLL_1443X_RATE(400000000U, 400, 3, 3, 0), + PLL_1443X_RATE(266000000U, 266, 3, 3, 0), PLL_1443X_RATE(167000000U, 334, 3, 4, 0), - PLL_1443X_RATE(100000000U, 300, 9, 3, 0), + PLL_1443X_RATE(100000000U, 200, 3, 4, 0), }; static int fracpll_configure(enum pll_clocks pll, u32 freq) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 4e0e194690b..b6acbb20ff0 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -25,6 +25,9 @@ config IMX91 select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS +config IMX95_A0 + bool "Support for i.MX95 A0 silicon version" + config IMX95 bool select ARCH_MISC_INIT @@ -33,7 +36,7 @@ config IMX95 select DM_MAILBOX select SCMI_FIRMWARE select SPL_IMX_CONTAINER_USE_TRAMPOLINE - select IMX_PQC_SUPPORT + select IMX_PQC_SUPPORT if !IMX95_A0 config SYS_SOC default "imx9" diff --git a/arch/arm/mach-imx/imx9/scmi/container.cfg b/arch/arm/mach-imx/imx9/scmi/container.cfg deleted file mode 100644 index b25f3b726c5..00000000000 --- a/arch/arm/mach-imx/imx9/scmi/container.cfg +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2025 NXP - */ - -CNTR_VERSION 2 -BOOT_FROM SD -SOC_TYPE IMX9 -CONTAINER -IMAGE A55 bl31.bin 0x8a200000 -IMAGE A55 u-boot.bin CONFIG_TEXT_BASE diff --git a/arch/arm/mach-imx/imx9/scmi/imximage.cfg b/arch/arm/mach-imx/imx9/scmi/imximage.cfg deleted file mode 100644 index c2c92174c1c..00000000000 --- a/arch/arm/mach-imx/imx9/scmi/imximage.cfg +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2025 NXP - */ - -CNTR_VERSION 2 -BOOT_FROM SD -SOC_TYPE IMX9 -APPEND mx95b0-ahab-container.img -CONTAINER -DUMMY_DDR -IMAGE OEI m33-oei-ddrfw.bin 0x1ffc0000 -HOLD 0x10000 -IMAGE M33 m33_image.bin 0x1ffc0000 -IMAGE A55 spl/u-boot-spl.bin 0x20480000 -DUMMY_V2X 0x8b000000 diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 13f13ca7d10..f973652d0cb 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -635,7 +635,8 @@ enum env_location env_get_location(enum env_operation op, int prio) switch (dev) { case QSPI_BOOT: - env_loc = ENVL_SPI_FLASH; + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + env_loc = ENVL_SPI_FLASH; break; case SD1_BOOT: case SD2_BOOT: @@ -643,10 +644,16 @@ enum env_location env_get_location(enum env_operation op, int prio) case MMC1_BOOT: case MMC2_BOOT: case MMC3_BOOT: - env_loc = ENVL_MMC; + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + env_loc = ENVL_MMC; break; default: - env_loc = ENVL_NOWHERE; + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + env_loc = ENVL_NOWHERE; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + env_loc = ENVL_SPI_FLASH; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + env_loc = ENVL_MMC; break; } diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 02db7cc97ba..3f7dafdcce5 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -641,12 +641,10 @@ static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32 n return -ENOENT; } -static int low_drive_freq_update(void *blob) +int low_drive_freq_update(void *blob) { - int nodeoff, ret; - int i; + int nodeoff, ret, i; - /* Update kernel dtb clocks for low drive mode */ struct low_drive_freq_entry table[] = { {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, @@ -658,8 +656,8 @@ static int low_drive_freq_update(void *blob) if (nodeoff >= 0) { ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk, table[i].new_rate); - if (!ret) - printf("%s freq updated\n", table[i].node_path); + if (ret) + printf("freq update failed for %s\n", table[i].node_path); } } @@ -671,23 +669,8 @@ static int low_drive_freq_update(void *blob) int board_fix_fdt(void *fdt) { /* Update dtb clocks for low drive mode */ - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - int nodeoff; - int i; - - struct low_drive_freq_entry table[] = { - {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, - {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, - {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, - }; - - for (i = 0; i < ARRAY_SIZE(table); i++) { - nodeoff = fdt_path_offset(fdt, table[i].node_path); - if (nodeoff >= 0) - low_drive_fdt_fix_clock(fdt, nodeoff, table[i].clk, - table[i].new_rate); - } - } + if (is_voltage_mode(VOLT_LOW_DRIVE)) + low_drive_freq_update(fdt); return 0; } @@ -826,7 +809,13 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_FAT; return ENVL_NOWHERE; default: - return ENVL_NOWHERE; + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + return ENVL_MMC; + return ENVL_UNKNOWN; } } diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8ce9ac561f0..5a5c119328f 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,10 +2,14 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ + +#define LOG_CATEGORY LOGC_ARCH + #include <clk.h> #include <dm.h> #include <fdt_support.h> #include <init.h> +#include <misc.h> #include <spl.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> @@ -15,6 +19,7 @@ #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_px30.h> #include <dt-bindings/clock/px30-cru.h> +#include <linux/bitfield.h> const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", @@ -442,3 +447,59 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ + +#define PX30_OTP_SPECIFICATION_OFFSET 0x06 + +#define DDR_GRF_BASE_ADDR 0xff630000 +#define DDR_GRF_CON(n) (0 + (n) * 4) + +int checkboard(void) +{ + struct udevice *dev; + u8 specification; + u32 base_soc; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */ + ret = misc_read(dev, 0, &base_soc, 4); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (base_soc != 0x26334b52 && base_soc != 0x30335850) { + log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc); + return 0; + } + + /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */ + ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (specification == 0x2b) { + printf("SoC: PX30K\n"); + return 0; + } + + /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */ + specification = FIELD_GET(GENMASK(15, 14), + readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1))); + log_debug("DDR specification is %d\n", specification); + printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30", + specification == 0x3 ? "S" : ""); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index 4892ff6ba9d..f9bfc445b85 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -9,6 +9,9 @@ #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> +#define VPU_GRF_BASE 0xff340000 +#define USB3OTG_CON1 0x44 + #define FIREWALL_DDR_BASE 0xff2e0000 #define FW_DDR_MST6_REG 0x58 #define FW_DDR_MST7_REG 0x5c @@ -69,6 +72,9 @@ int arch_cpu_init(void) val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */ + writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1); + return 0; } diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS new file mode 100644 index 00000000000..94ef74d429f --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -0,0 +1,11 @@ +GENERIC-RK3576 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3576-generic* +F: configs/generic-rk3576_defconfig + +SIGE5-RK3576 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3576-armsom-sige5* +F: configs/sige5-rk3576_defconfig diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index ba5c94b4b3d..a6c2fbdc484 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -3,6 +3,10 @@ * Copyright (c) 2024 Rockchip Electronics Co., Ltd */ +#define LOG_CATEGORY LOGC_ARCH + +#include <dm.h> +#include <misc.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> @@ -29,6 +33,9 @@ #define SGRF_DOMAIN_CON4 0x10 #define SGRF_DOMAIN_CON5 0x14 +#define USB_GRF_BASE 0x2601E000 +#define USB3OTG0_CON1 0x0030 + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", @@ -151,5 +158,52 @@ int arch_cpu_init(void) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + + return 0; +} + +#define RK3576_OTP_CPU_CODE_OFFSET 0x02 +#define RK3576_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x76 */ + ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3576J */ + ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3576J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + return 0; } diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 4e7942ada87..9fbe3f225aa 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588 - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector +config TARGET_GAMEFORCE_ACE_RK3588S + bool "GameForce Ace" + help + The GameForce Ace is a handheld game console from GameForce with + the Rockchip RK3588S SoC. + + Hardware features: + - Rockchip RK3588S SoC + - 12GB LPDDR4x RAM + - 128GB eMMC + - MicroSD card slot + - 1x USB 3.0 Type-C with DP AltMode support + - 1x HDMI 2.1 micro-HDMI out + - 1920x1080 touchscreen MIPI-DSI panel + - Analog joysticks and L/R triggers + - 16 digital buttons + config TARGET_GENBOOK_CM5_RK3588 bool "Cool Pi CM5 GenBook" help @@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" +source "board/gameforce/ace-rk3588s/Kconfig" source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" source "board/khadas/khadas-edge2-rk3588s/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index e2278ff792b..c01a4002089 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -15,6 +15,10 @@ #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/ioc_rk3588.h> +#define USB_GRF_BASE 0xfd5ac000 +#define USB3OTG0_CON1 0x001c +#define USB3OTG1_CON1 0x0034 + #define FIREWALL_DDR_BASE 0xfe030000 #define FW_DDR_MST5_REG 0x54 #define FW_DDR_MST13_REG 0x74 @@ -184,6 +188,10 @@ int arch_cpu_init(void) /* Disable JTAG exposed on SDMMC */ rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); #endif + + /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1); #endif return 0; diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index fc921a4be26..5fb3240acc5 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -534,8 +534,7 @@ int board_late_init(void) env_set_hex("ramdisk_addr_r", addr) : 1; status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? env_set_hex("kernel_comp_addr_r", addr) : 1; - status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? - env_set_hex("kernel_comp_size", addr) : 1; + status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); status |= !lmb_alloc(SZ_4M, &addr) ? env_set_hex("scriptaddr", addr) : 1; status |= !lmb_alloc(SZ_4M, &addr) ? @@ -544,9 +543,13 @@ int board_late_init(void) if (IS_ENABLED(CONFIG_FASTBOOT)) { status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ? env_set_hex("fastboot_addr_r", addr) : 1; - /* override loadaddr for memory rich soc */ - status |= !lmb_alloc(SZ_128M, &addr) ? - env_set_hex("loadaddr", addr) : 1; + /* + * Override loadaddr for memory rich soc since ${loadaddr} and + * ${kernel_addr_r} need to be different for the Android boot image + * flow. It's typically safe for ${loadaddr} to be the same address + * as the fastboot buffer. + */ + status |= env_set_hex("loadaddr", addr); } fdt_status |= !lmb_alloc(SZ_2M, &addr) ? diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 156cfbbcf3b..f2e959b5662 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -60,6 +60,18 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX7M + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV2 + select NCORE_CACHE + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF @@ -149,6 +161,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX +config TARGET_SOCFPGA_AGILEX7M_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" + select TARGET_SOCFPGA_AGILEX7M + config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 @@ -226,6 +242,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -248,6 +265,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK @@ -271,6 +289,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index c43fdee4a48..4e85bfb00d4 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -54,6 +54,7 @@ obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +obj-y += altera-sysmgr.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 @@ -72,6 +73,22 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o +obj-y += wrap_handoff_soc64.o +obj-y += wrap_pll_config_soc64.o +obj-y += altera-sysmgr.o +endif + ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o @@ -115,6 +132,9 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += spl_soc64.o obj-y += spl_agilex5.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += spl_agilex7m.o +endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 5ac868a281b..074b9691af8 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ @@ -45,8 +46,10 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 @@ -75,6 +78,7 @@ #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 #define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 #define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 49f3fb2e705..f0431c081d8 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2024 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2025 Altera Corporation <www.altera.com> */ #ifndef _CLOCK_MANAGER_H_ @@ -28,7 +28,7 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include <asm/arch/clock_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/clock_manager_s10.h> -#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #include <asm/arch/clock_manager_agilex.h> #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #include <asm/arch/clock_manager_agilex5.h> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 04203cceb8a..9ef82cf46c0 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -18,7 +18,7 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 -#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524D #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 #else @@ -30,9 +30,19 @@ #define SOC64_HANDOFF_SIZE 4096 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x634) +/* DDR handoff */ +#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_DDR_LEN 5 +#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0) +#define SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK BIT(0) +#else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#endif #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index ab46415168f..0b80e952131 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -41,7 +41,8 @@ void socfpga_sdram_remap_zero(void); #endif #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) + defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX7M) int is_fpga_config_ready(void); #endif @@ -52,7 +53,7 @@ bool is_periph_program_force(void); void set_regular_boot(unsigned int status); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); -void socfpga_get_sys_mgr_addr(const char *compat); +void socfpga_get_sys_mgr_addr(void); int qspi_flash_software_reset(void); #endif /* _SOCFPGA_MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c2ca0a50e35..054a28d845d 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -141,6 +141,27 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[19] store ATF CPU0 ON OFF value. + * + * Bit[18] reserved for SDM to configure ACF + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) + */ +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK BIT(18) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18 + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 8926c2d1d9c..b39565f591d 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -12,15 +12,110 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ +#ifdef CONFIG_XPL_BUILD + /* Check for L2 reset magic word */ + ldr x4, =L2_RESET_DONE_REG + ldr x5, [x4] + ldr x1, =L2_RESET_DONE_STATUS + cmp x1, x5 + /* No L2 reset, skip warm reset */ + b.ne skipwarmreset + /* Put all slaves CPUs into WFI mode */ + branch_if_slave x0, put_cpu_in_wfi + /* L2 reset completed */ + str xzr, [x4] + /* Clear previous CPU release address */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + /* Master CPU (CPU0) request for warm reset */ + mrs x1, rmr_el3 + orr x1, x1, #0x02 + msr rmr_el3, x1 + isb + dsb sy +put_cpu_in_wfi: + wfi + b put_cpu_in_wfi +skipwarmreset: +#endif + #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) + + /* + * In ATF flow, need to clear the old CPU address when cold reset + * being triggered, but shouldn't clear CPU address if it is reset + * by CPU-ON, so that the core can correctly jump to ATF code after + * reset by CPU-ON. CPU-ON trigger the reset via mpumodrst. + * + * Hardware will set 1 to core*_irq in mpurststat register in + * reset manager if the core is reset by mpumodrst. + * + * The following code will check the mpurststat to identify if the + * core is reset by mpumodrst, and it will skip CPU address clearing + * if the core is reset by mpumodrst. At last, the code need to clear + * the core*_irq by set it to 1. So that it can reflect the correct + * and latest status in next reset. + */ + + /* Check if it is a master core off/on from kernel using boot scratch + * cold register 8 bit 19. This bit is set by ATF. + */ + ldr x4, =BOOT_SCRATCH_COLD8 + ldr x5, [x4] + and x6, x5, #0x80000 + cbnz x6, wait_for_atf_master + + /* Retrieve mpurststat register in reset manager */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + ldr w5, [x4, #0x04] + + /* Set mask based on current core id */ + mrs x0, mpidr_el1 + and x1, x0, #0xF + ldr x2, =0x00000100 + lsl x2, x2, x1 + + /* Skip if core*_irq register is set */ + and x6, x5, x2 + cbnz x6, skip_clear_cpu_address + + /* + * Reach here means core*_irq is 0, means the core is + * reset by cold, warm or watchdog reset. + * Clear previous CPU release address + */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + b skip_clear_core_irq + +skip_clear_cpu_address: + /* Clear core*_irq register by writing 1 */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + str w2, [x4, #0x04] + +skip_clear_core_irq: + /* Master CPU (CPU0) does not need to wait for atf */ + branch_if_master x0, master_cpu + wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] cbz x5, slave_wait_atf br x5 + slave_wait_atf: branch_if_slave x0, wait_for_atf + +wait_for_atf_master: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, master_wait_atf + br x5 +master_wait_atf: + branch_if_master x0, wait_for_atf_master + +master_cpu: #else branch_if_slave x0, 1f #endif diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 97e01140513..76747c2196a 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -11,6 +11,7 @@ #include <hang.h> #include <watchdog.h> #include <fdtdec.h> +#include <dm/ofnode.h> #include <linux/libfdt.h> #include <linux/printk.h> #include <miiphy.h> @@ -222,8 +223,8 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" + "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" "" ); @@ -260,13 +261,12 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)) - ret = socfpga_get_base_addr("intel,agilex-clkmgr", - &socfpga_clkmgr_base); else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); - else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); @@ -274,17 +274,24 @@ void socfpga_get_managers_addr(void) hang(); } -void socfpga_get_sys_mgr_addr(const char *compat) +void socfpga_get_sys_mgr_addr(void) { int ret; - struct udevice *sysmgr_dev; + struct udevice *dev; + + ofnode node = ofnode_get_aliases_node("sysmgr"); + + if (!ofnode_valid(node)) { + printf("'sysmgr' alias not found in device tree\n"); + hang(); + } - ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev); + ret = uclass_get_device_by_ofnode(UCLASS_NOP, node, &dev); if (ret) { printf("Altera system manager init failed: %d\n", ret); hang(); } else { - socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev); + socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(dev); } } diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 91c27a5543d..48f258a37b4 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -18,20 +19,42 @@ #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <watchdog.h> +#include <wdt.h> #include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; +u32 reset_flag(u32 flag) +{ + /* Check rstmgr.stat for warm reset status */ + u32 status = readl(SOCFPGA_RSTMGR_ADDRESS); + + /* Check whether any L4 watchdogs or SDM had triggered warm reset */ + u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK; + + if (status & warm_reset_mask) + return 0; + + return 1; +} + void board_init_f(ulong dummy) { int ret; struct udevice *dev; + /* Enable Async */ + asm volatile("msr daifclr, #4"); + +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) + spl_save_restore_data(); +#endif + ret = spl_early_init(); if (ret) hang(); + socfpga_get_sys_mgr_addr(); socfpga_get_managers_addr(); /* Ensure watchdog is paused when debugging is happening */ @@ -62,11 +85,30 @@ void board_init_f(ulong dummy) hang(); } + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + preloader_console_init(); print_reset_info(); cm_print_clock_quick_summary(); - firewall_setup(); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev); + if (ret) { + printf("System manager firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev); + if (ret) { + printf("L3 interconnect firewall configuration failed: %d\n", ret); + hang(); + } + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { debug("CCU init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 2a13301802d..1be347360f5 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; -u32 reset_flag(void) +u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ u32 status = readl(SOCFPGA_RSTMGR_ADDRESS); @@ -51,7 +51,7 @@ void board_init_f(ulong dummy) if (ret) hang(); - socfpga_get_sys_mgr_addr("sysmgr@10d12000"); + socfpga_get_sys_mgr_addr(); socfpga_get_managers_addr(); sysmgr_pinmux_init(); diff --git a/arch/arm/mach-socfpga/spl_agilex7m.c b/arch/arm/mach-socfpga/spl_agilex7m.c new file mode 100644 index 00000000000..90065ccee6f --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex7m.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <wdt.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + /* Enable Async */ + asm volatile("msr daifclr, #4"); + +#ifdef CONFIG_XPL_BUILD + spl_save_restore_data(); +#endif + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_sys_mgr_addr(); + socfpga_get_managers_addr(); + + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); + + /* ensure all processors are not released prior Linux boot */ + writeq(0, CPU_RELEASE_ADDR); + + timer_init(); + + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + + sysmgr_pinmux_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + + preloader_console_init(); + print_reset_info(); + cm_print_clock_quick_summary(); + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev); + if (ret) { + printf("System manager firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev); + if (ret) { + printf("L3 interconnect firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); + if (ret) { + debug("CCU init failed: %d\n", ret); + hang(); + } + + if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } + } + + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) + mbox_qspi_open(); +} diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 6a511c4fd39..b04ec671696 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -487,6 +487,7 @@ config MACH_SUN8I_V3S select SUNXI_DRAM_DW_16BIT select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + imply OF_UPSTREAM config MACH_SUN9I bool "sun9i (Allwinner A80)" @@ -718,9 +719,9 @@ config DRAM_CLK int "sunxi dram clock speed" default 792 if MACH_SUN9I default 648 if MACH_SUN8I_R40 - default 312 if MACH_SUN6I || MACH_SUN8I default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ MACH_SUN8I_V3S + default 312 if MACH_SUN6I || MACH_SUN8I default 672 if MACH_SUN50I default 744 if MACH_SUN50I_H6 default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index fb4837c2082..432b1c10f92 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -476,8 +476,8 @@ void board_init_f(ulong dummy) /* Enable non-secure access to some peripherals */ tzpc_init(); - clock_init(); timer_init(); + clock_init(); gpio_init(); spl_init(); diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c index 3a231141168..1496f99624d 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_a133.c +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c @@ -416,7 +416,7 @@ static void mctl_com_init(const struct dram_para *para, static void mctl_drive_odt_config(const struct dram_para *para) { u32 val; - u64 base; + ulong base; u32 i; /* DX drive */ diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 877181016f3..3345c9b8e82 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -1078,18 +1078,18 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); break; case SUNXI_DRAM_TYPE_LPDDR3: - writel(mr0, &mctl_ctl->mrctrl1); - writel(0x800000f0, &mctl_ctl->mrctrl0); - mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - - writel(4, &mctl_ctl->mrctrl1); + /* MR0 is read-only */ + /* MR1: nWR=14, BL8 */ + writel(0x183, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - writel(mr2, &mctl_ctl->mrctrl1); + /* MR2: no WR leveling, WL set A, use nWR>9, nRL=14/nWL=8 */ + writel(0x21c, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + /* MR3: 34.3 Ohm pull-up/pull-down resistor */ writel(0x301, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index c3c352eceb1..32cdfebfc01 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -17,7 +17,9 @@ config TEGRA_CLKRST config TEGRA_CRYPTO bool "Tegra AES128 crypto module" + select DM_AES select AES + select TEGRA_AES config TEGRA_GP_PADCTRL bool diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index f35bdba4d48..a7938ed7910 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -37,6 +37,14 @@ int tegra_get_chip(void) return rev; } +u32 tegra_get_major_version(void) +{ + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + + return (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> HIDREV_MAJORPREV_SHIFT; +} + int tegra_get_sku_info(void) { int sku_id; diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 006aae3d070..5477423f4d0 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -71,6 +71,7 @@ void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); int tegra_get_chip(void); +u32 tegra_get_major_version(void); int tegra_get_sku_info(void); int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); diff --git a/arch/arm/mach-tegra/crypto.c b/arch/arm/mach-tegra/crypto.c index 49e6a45243a..1005c815b36 100644 --- a/arch/arm/mach-tegra/crypto.c +++ b/arch/arm/mach-tegra/crypto.c @@ -4,164 +4,68 @@ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com> */ +#include <dm.h> #include <log.h> #include <linux/errno.h> #include <asm/arch-tegra/crypto.h> #include "uboot_aes.h" -static u8 zero_key[16]; - -#define AES_CMAC_CONST_RB 0x87 /* from RFC 4493, Figure 2.2 */ - -enum security_op { - SECURITY_SIGN = 1 << 0, /* Sign the data */ - SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */ - SECURITY_DECRYPT = 1 << 2, /* Dectypt the data */ -}; - -/** - * Shift a vector left by one bit - * - * \param in Input vector - * \param out Output vector - * \param size Length of vector in bytes - */ -static void left_shift_vector(u8 *in, u8 *out, int size) +int sign_data_block(u8 *source, unsigned int length, u8 *signature) { - int carry = 0; - int i; - - for (i = size - 1; i >= 0; i--) { - out[i] = (in[i] << 1) | carry; - carry = in[i] >> 7; /* get most significant bit */ + struct udevice *dev; + int ret; + + /* Only one AES engine should be present */ + ret = uclass_get_device(UCLASS_AES, 0, &dev); + if (ret) { + log_err("%s: failed to get tegra_aes: %d\n", __func__, ret); + return ret; } -} - -/** - * Sign a block of data, putting the result into dst. - * - * \param key Input AES key, length AES128_KEY_LENGTH - * \param key_schedule Expanded key to use - * \param src Source data of length 'num_aes_blocks' blocks - * \param dst Destination buffer, length AES128_KEY_LENGTH - * \param num_aes_blocks Number of AES blocks to encrypt - */ -static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, - u32 num_aes_blocks) -{ - u8 tmp_data[AES128_KEY_LENGTH]; - u8 iv[AES128_KEY_LENGTH] = {0}; - u8 left[AES128_KEY_LENGTH]; - u8 k1[AES128_KEY_LENGTH]; - u8 *cbc_chain_data; - unsigned int i; - cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ + ret = dm_aes_select_key_slot(dev, 128, TEGRA_AES_SLOT_SBK); + if (ret) + return ret; - /* compute K1 constant needed by AES-CMAC calculation */ - for (i = 0; i < AES128_KEY_LENGTH; i++) - tmp_data[i] = 0; - - aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, - tmp_data, left, 1); - - left_shift_vector(left, k1, sizeof(left)); - - if ((left[0] >> 7) != 0) /* get MSB of L */ - k1[AES128_KEY_LENGTH - 1] ^= AES_CMAC_CONST_RB; - - /* compute the AES-CMAC value */ - for (i = 0; i < num_aes_blocks; i++) { - /* Apply the chain data */ - aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data); - - /* for the final block, XOR K1 into the IV */ - if (i == num_aes_blocks - 1) - aes_apply_cbc_chain_data(tmp_data, k1, tmp_data); - - /* encrypt the AES block */ - aes_encrypt(AES128_KEY_LENGTH, tmp_data, - key_schedule, dst); - - debug("sign_obj: block %d of %d\n", i, num_aes_blocks); - - /* Update pointers for next loop. */ - cbc_chain_data = dst; - src += AES128_KEY_LENGTH; - } + return dm_aes_cmac(dev, source, signature, + DIV_ROUND_UP(length, AES_BLOCK_LENGTH)); } -/** - * Decrypt, encrypt or sign a block of data (depending on security mode). - * - * \param key Input AES key, length AES128_KEY_LENGTH - * \param oper Security operations mask to perform (enum security_op) - * \param src Source data - * \param length Size of source data - * \param sig_dst Destination address for signature, AES128_KEY_LENGTH bytes - */ -static int tegra_crypto_core(u8 *key, enum security_op oper, u8 *src, - u32 length, u8 *sig_dst) +int encrypt_data_block(u8 *source, u8 *dest, unsigned int length) { - u32 num_aes_blocks; - u8 key_schedule[AES128_EXPAND_KEY_LENGTH]; - u8 iv[AES128_KEY_LENGTH] = {0}; - - debug("%s: length = %d\n", __func__, length); - - aes_expand_key(key, AES128_KEY_LENGTH, key_schedule); - - num_aes_blocks = (length + AES128_KEY_LENGTH - 1) / AES128_KEY_LENGTH; - - if (oper & SECURITY_DECRYPT) { - /* Perform this in place, resulting in src being decrypted. */ - debug("%s: begin decryption\n", __func__); - aes_cbc_decrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src, - src, num_aes_blocks); - debug("%s: end decryption\n", __func__); - } - - if (oper & SECURITY_ENCRYPT) { - /* Perform this in place, resulting in src being encrypted. */ - debug("%s: begin encryption\n", __func__); - aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src, - src, num_aes_blocks); - debug("%s: end encryption\n", __func__); - } - - if (oper & SECURITY_SIGN) { - /* encrypt the data, overwriting the result in signature. */ - debug("%s: begin signing\n", __func__); - sign_object(key, key_schedule, src, sig_dst, num_aes_blocks); - debug("%s: end signing\n", __func__); + struct udevice *dev; + int ret; + + /* Only one AES engine should be present */ + ret = uclass_get_device(UCLASS_AES, 0, &dev); + if (ret) { + log_err("%s: failed to get tegra_aes: %d\n", __func__, ret); + return ret; } - return 0; -} + ret = dm_aes_select_key_slot(dev, 128, TEGRA_AES_SLOT_SBK); + if (ret) + return ret; -/** - * Tegra crypto group - */ -int sign_data_block(u8 *source, unsigned int length, u8 *signature) -{ - return tegra_crypto_core(zero_key, SECURITY_SIGN, source, - length, signature); + return dm_aes_cbc_encrypt(dev, (u8 *)AES_ZERO_BLOCK, source, dest, + DIV_ROUND_UP(length, AES_BLOCK_LENGTH)); } -int sign_enc_data_block(u8 *source, unsigned int length, u8 *signature, u8 *key) +int decrypt_data_block(u8 *source, u8 *dest, unsigned int length) { - return tegra_crypto_core(key, SECURITY_SIGN, source, - length, signature); -} + struct udevice *dev; + int ret; + + /* Only one AES engine should be present */ + ret = uclass_get_device(UCLASS_AES, 0, &dev); + if (ret) { + log_err("%s: failed to get tegra_aes: %d\n", __func__, ret); + return ret; + } -int encrypt_data_block(u8 *source, unsigned int length, u8 *key) -{ - return tegra_crypto_core(key, SECURITY_ENCRYPT, source, - length, NULL); -} + ret = dm_aes_select_key_slot(dev, 128, TEGRA_AES_SLOT_SBK); + if (ret) + return ret; -int decrypt_data_block(u8 *source, unsigned int length, u8 *key) -{ - return tegra_crypto_core(key, SECURITY_DECRYPT, source, - length, NULL); + return dm_aes_cbc_decrypt(dev, (u8 *)AES_ZERO_BLOCK, source, dest, + DIV_ROUND_UP(length, AES_BLOCK_LENGTH)); } diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index e9b5259ac70..abdf6504161 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -39,7 +39,7 @@ static u32 tegra_fuse_readl(unsigned long offset) return readl(NV_PA_FUSE_BASE + offset); } -static void tegra_fuse_init(void) +void tegra_fuse_init(void) { u32 reg; @@ -49,8 +49,11 @@ static void tegra_fuse_init(void) * this bit fuse region will not work. */ reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48); - reg |= BIT(28); - writel(reg, NV_PA_CLK_RST_BASE + 0x48); + + if (reg & BIT(28)) + return; + + writel(reg | BIT(28), NV_PA_CLK_RST_BASE + 0x48); clock_enable(PERIPH_ID_FUSE); udelay(2); @@ -148,3 +151,57 @@ unsigned long long tegra_chip_uid(void) return uid; } + +static int tegra_is_production_mode_fuse_set(struct fuse_regs *fuse) +{ + return readl(&fuse->production_mode); +} + +static int tegra_is_odm_production_mode_fuse_set(struct fuse_regs *fuse) +{ + return readl(&fuse->security_mode); +} + +static int tegra_is_failure_analysis_mode(struct fuse_regs *fuse) +{ + return readl(&fuse->fa); +} + +static int tegra_is_sbk_zeroes(struct fuse_regs *fuse) +{ + int i; + + for (i = 0; i < 4; i++) + if (readl(&fuse->sbk[i])) + return 0; + + return 1; +} + +static int tegra_is_production_mode(struct fuse_regs *fuse) +{ + if (!tegra_get_major_version()) + return 1; + + return !tegra_is_failure_analysis_mode(fuse) && + tegra_is_production_mode_fuse_set(fuse); +} + +enum fuse_operating_mode tegra_fuse_get_operation_mode(void) +{ + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + + tegra_fuse_init(); + + if (tegra_is_production_mode(fuse)) { + if (!tegra_is_odm_production_mode_fuse_set(fuse)) + return MODE_PRODUCTION; + else + if (tegra_is_sbk_zeroes(fuse)) + return MODE_ODM_PRODUCTION_OPEN; + else + return MODE_ODM_PRODUCTION_SECURE; + } + + return MODE_UNDEFINED; +} diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 98f1d0e71c1..43dd59fb113 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,6 +8,10 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_SURFACE_2 + bool "Microsoft Surface 2" + select BOARD_LATE_INIT + config TARGET_TEGRATAB bool "NVIDIA Tegra114 TegraTab evaluation board" select BOARD_LATE_INIT @@ -22,6 +26,7 @@ config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/microsoft/surface-2/Kconfig" source "board/nvidia/tegratab/Kconfig" source "board/asus/transformer-t114/Kconfig" diff --git a/arch/arm/mach-tegra/tegra124/bct.c b/arch/arm/mach-tegra/tegra124/bct.c index 4dc4b7138ab..676b68dc5de 100644 --- a/arch/arm/mach-tegra/tegra124/bct.c +++ b/arch/arm/mach-tegra/tegra124/bct.c @@ -9,12 +9,10 @@ #include <vsprintf.h> #include <linux/string.h> #include <asm/arch-tegra/crypto.h> +#include <asm/arch-tegra/fuse.h> #include "bct.h" #include "uboot_aes.h" -/* Device with "sbk burned: false" will expose zero key */ -const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; - /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -26,29 +24,25 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) struct nvboot_config_table *bct_tbl = NULL; u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; u8 bct_hash[AES128_KEY_LENGTH] = { 0 }; - u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *sbct = bct + UBCT_LENGTH; bool encrypted; int ret; ebt_size = roundup(ebt_size, EBT_ALIGNMENT); - memcpy(sbk, (u8 *)(bct + UBCT_LENGTH + SBCT_LENGTH), - NVBOOT_CMAC_AES_HASH_LENGTH * 4); - - encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); + encrypted = tegra_fuse_get_operation_mode() == MODE_ODM_PRODUCTION_SECURE; if (encrypted) { - ret = decrypt_data_block(sbct, SBCT_LENGTH, sbk); + ret = decrypt_data_block(sbct, sbct, SBCT_LENGTH); if (ret) return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); + ret = encrypt_data_block(ebt, ebt, ebt_size); if (ret) return 1; } - ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); + ret = sign_data_block(ebt, ebt_size, ebt_hash); if (ret) return 1; @@ -61,12 +55,12 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].length = ebt_size; if (encrypted) { - ret = encrypt_data_block(sbct, SBCT_LENGTH, sbk); + ret = encrypt_data_block(sbct, sbct, SBCT_LENGTH); if (ret) return 1; } - ret = sign_enc_data_block(sbct, SBCT_LENGTH, bct_hash, sbk); + ret = sign_data_block(sbct, SBCT_LENGTH, bct_hash); if (ret) return 1; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index bedbedade7b..b07b5a15585 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -54,6 +54,10 @@ config TARGET_SEABOARD select TEGRA_LP0 select TEGRA_PMU +config TARGET_SAMSUNG_N1 + bool "Samsung Tegra20 N1 board" + select BOARD_LATE_INIT + config TARGET_STAR bool "LG Tegra20 Star board" select BOARD_LATE_INIT @@ -92,6 +96,7 @@ source "board/compal/paz00/Kconfig" source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" source "board/nvidia/seaboard/Kconfig" +source "board/samsung/n1/Kconfig" source "board/lg/star/Kconfig" source "board/avionic-design/tec/Kconfig" source "board/asus/transformer-t20/Kconfig" diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index 253cb243676..0270cf592c1 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -9,12 +9,10 @@ #include <vsprintf.h> #include <linux/string.h> #include <asm/arch-tegra/crypto.h> +#include <asm/arch-tegra/fuse.h> #include "bct.h" #include "uboot_aes.h" -/* Device with "sbk burned: false" will expose zero key */ -const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; - /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -25,7 +23,6 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) { struct nvboot_config_table *bct_tbl = NULL; u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; - u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *bct_hash = bct; bool encrypted; int ret; @@ -34,22 +31,19 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) ebt_size = roundup(ebt_size, EBT_ALIGNMENT); - memcpy(sbk, (u8 *)(bct + BCT_LENGTH), - NVBOOT_CMAC_AES_HASH_LENGTH * 4); - - encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); + encrypted = tegra_fuse_get_operation_mode() == MODE_ODM_PRODUCTION_SECURE; if (encrypted) { - ret = decrypt_data_block(bct, BCT_LENGTH, sbk); + ret = decrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); + ret = encrypt_data_block(ebt, ebt, ebt_size); if (ret) return 1; } - ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); + ret = sign_data_block(ebt, ebt_size, ebt_hash); if (ret) return 1; @@ -62,12 +56,12 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].length = ebt_size; if (encrypted) { - ret = encrypt_data_block(bct, BCT_LENGTH, sbk); + ret = encrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; } - ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk); + ret = sign_data_block(bct, BCT_LENGTH, bct_hash); if (ret) return 1; diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 18034c83a1c..3fd39fe3c1a 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -19,6 +19,7 @@ #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/warmboot.h> +#include <asm/arch-tegra/crypto.h> DECLARE_GLOBAL_DATA_PTR; @@ -182,98 +183,36 @@ int warmboot_save_sdram_params(void) return 0; } -static u32 get_major_version(void) +static void determine_crypto_options(int *is_encrypted, int *is_signed) { - u32 major_id; - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - - major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> - HIDREV_MAJORPREV_SHIFT; - return major_id; -} - -static int is_production_mode_fuse_set(struct fuse_regs *fuse) -{ - return readl(&fuse->production_mode); -} - -static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse) -{ - return readl(&fuse->security_mode); -} - -static int is_failure_analysis_mode(struct fuse_regs *fuse) -{ - return readl(&fuse->fa); -} - -static int ap20_is_odm_production_mode(void) -{ - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - - if (!is_failure_analysis_mode(fuse) && - is_odm_production_mode_fuse_set(fuse)) - return 1; - else - return 0; -} - -static int ap20_is_production_mode(void) -{ - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - - if (get_major_version() == 0) - return 1; - - if (!is_failure_analysis_mode(fuse) && - is_production_mode_fuse_set(fuse) && - !is_odm_production_mode_fuse_set(fuse)) - return 1; - else - return 0; -} - -static enum fuse_operating_mode fuse_get_operation_mode(void) -{ - u32 chip_id; - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - - chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> - HIDREV_CHIPID_SHIFT; - if (chip_id == CHIPID_TEGRA20) { - if (ap20_is_odm_production_mode()) { - printf("!! odm_production_mode is not supported !!\n"); - return MODE_UNDEFINED; - } else - if (ap20_is_production_mode()) - return MODE_PRODUCTION; - else - return MODE_UNDEFINED; - } - return MODE_UNDEFINED; -} - -static void determine_crypto_options(int *is_encrypted, int *is_signed, - int *use_zero_key) -{ - switch (fuse_get_operation_mode()) { + switch (tegra_fuse_get_operation_mode()) { + case MODE_ODM_PRODUCTION_SECURE: + *is_encrypted = 1; + *is_signed = 1; + break; + case MODE_ODM_PRODUCTION_OPEN: case MODE_PRODUCTION: *is_encrypted = 0; *is_signed = 1; - *use_zero_key = 1; break; case MODE_UNDEFINED: default: *is_encrypted = 0; *is_signed = 0; - *use_zero_key = 0; break; } } -static int sign_wb_code(u32 start, u32 length, int use_zero_key) +static int encrypt_wb_code(u8 *source, u8 *destination, u32 length) +{ + source += offsetof(struct wb_header, random_aes_block); + destination += offsetof(struct wb_header, random_aes_block); + length -= offsetof(struct wb_header, random_aes_block); + + return encrypt_data_block(source, destination, length); +} + +static int sign_wb_code(u32 start, u32 length) { int err; u8 *source; /* Pointer to source */ @@ -295,10 +234,9 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) struct wb_header *dst_header; /* Pointer to dest WB header */ int is_encrypted; /* Segment is encrypted */ int is_signed; /* Segment is signed */ - int use_zero_key; /* Use key of all zeros */ /* Determine crypto options. */ - determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key); + determine_crypto_options(&is_encrypted, &is_signed); /* Get the actual code limits. */ length = roundup(((u32)wb_end - (u32)wb_start), 16); @@ -346,18 +284,15 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) dst_header->entry_point = NV_WB_RUN_ADDRESS; dst_header->code_length = length; - if (is_encrypted) { - printf("!!!! Encryption is not supported !!!!\n"); - dst_header->length_insecure = 0; - err = -EACCES; - goto fail; - } else - /* copy the wb code directly following dst_header. */ - memcpy((char *)(dst_header+1), (char *)wb_start, length); + if (is_encrypted) + encrypt_wb_code((u8 *)wb_start, (u8 *)dst_header, + length + sizeof(struct wb_header)); + else + /* copy the wb code directly following dst_header */ + memcpy((char *)(dst_header + 1), (char *)wb_start, length); if (is_signed) - err = sign_wb_code(seg_address, dst_header->length_insecure, - use_zero_key); + err = sign_wb_code(seg_address, dst_header->length_insecure); fail: if (err) diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index b5099ce67fc..4da67b19990 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -16,6 +16,10 @@ config TARGET_CARDHU bool "NVIDIA Tegra30 Cardhu evaluation board" select BOARD_LATE_INIT +config TARGET_CHAGALL + bool "Pegatron Tegra30 Chagall board" + select BOARD_LATE_INIT + config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" select BOARD_LATE_INIT @@ -64,6 +68,7 @@ config SYS_SOC source "board/toradex/apalis_t30/Kconfig" source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" +source "board/pegatron/chagall/Kconfig" source "board/toradex/colibri_t30/Kconfig" source "board/htc/endeavoru/Kconfig" source "board/asus/grouper/Kconfig" diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index 398ba1de386..de668214517 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -9,12 +9,10 @@ #include <vsprintf.h> #include <linux/string.h> #include <asm/arch-tegra/crypto.h> +#include <asm/arch-tegra/fuse.h> #include "bct.h" #include "uboot_aes.h" -/* Device with "sbk burned: false" will expose zero key */ -const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; - /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -25,7 +23,6 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) { struct nvboot_config_table *bct_tbl = NULL; u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; - u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *bct_hash = bct; bool encrypted; int ret; @@ -34,22 +31,19 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) ebt_size = roundup(ebt_size, EBT_ALIGNMENT); - memcpy(sbk, (u8 *)(bct + BCT_LENGTH), - NVBOOT_CMAC_AES_HASH_LENGTH * 4); - - encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); + encrypted = tegra_fuse_get_operation_mode() == MODE_ODM_PRODUCTION_SECURE; if (encrypted) { - ret = decrypt_data_block(bct, BCT_LENGTH, sbk); + ret = decrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); + ret = encrypt_data_block(ebt, ebt, ebt_size); if (ret) return 1; } - ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); + ret = sign_data_block(ebt, ebt_size, ebt_hash); if (ret) return 1; @@ -62,12 +56,12 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].length = ebt_size; if (encrypted) { - ret = encrypt_data_block(bct, BCT_LENGTH, sbk); + ret = encrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; } - ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk); + ret = sign_data_block(bct, BCT_LENGTH, bct_hash); if (ret) return 1; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8c6feae5735..04eb0e6f23c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350" +config TARGET_ANDES_VOYAGER + bool "Support Andes Voyager Board" + config TARGET_BANANAPI_F3 bool "Support BananaPi F3 Board" @@ -101,6 +104,7 @@ config SPL_ZERO_MEM_BEFORE_USE # board-specific options below source "board/andestech/ae350/Kconfig" +source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 15c4e14599d..d5123e4b7d9 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -608,14 +608,14 @@ static inline bool supports_extension(char ext) static int riscv_cpu_probe(void) { -#ifdef CONFIG_CPU - int ret; + if (CONFIG_IS_ENABLED(CPU)) { + int ret; - /* probe cpus so that RISC-V timer can be bound */ - ret = cpu_probe_all(); - if (ret) - return log_msg_ret("RISC-V cpus probe failed\n", ret); -#endif + /* probe cpus so that RISC-V timer can be bound */ + ret = cpu_probe_all(); + if (ret) + return log_msg_ret("RISC-V cpus probe failed\n", ret); + } return 0; } diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 2b10c2d6c01..a637727b76b 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb @@ -14,6 +15,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/qilai-voyager.dts b/arch/riscv/dts/qilai-voyager.dts new file mode 100644 index 00000000000..44933529f89 --- /dev/null +++ b/arch/riscv/dts/qilai-voyager.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "binman.dtsi" +#include "voyager-u-boot.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "andestech,voyager", "andestech,qilai"; + model = "Voyager"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlycon=sbi debug loglevel=7"; + stdout-path = "uart0:115200n8"; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + timebase-frequency = <0x3938700>; + + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU0_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU1_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU2_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU3_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + L2: l2-cache@200000 { + compatible = "cache"; + cache-level = <0x2>; + cache-size = <0x40000>; + reg = <0x0 0x00200000 0x0 0x100000>; + andes,inst-prefetch = <0x3>; + andes,data-prefetch = <0x3>; + andes,tag-ram-ctl = <0x0 0x0>; + andes,data-ram-ctl = <0x0 0x0>; + }; + + memory@400000000 { + device_type = "memory"; + reg = <0x04 0x00000000 0x0 0x40000000>; + }; + + soc { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "simple-bus"; + ranges; + + plic0: interrupt-controller@2000000 { + compatible = "riscv,plic0"; + #address-cells = <0x2>; + #interrupt-cells = <0x2>; + interrupt-controller; + reg = <0x0 0x02000000 0x0 0x2000000>; + riscv,ndev = <0x47>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 + &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 + &CPU3_intc 11 &CPU3_intc 9>; + }; + + plic1: interrupt-controller@400000 { + compatible = "andestech,plicsw"; + #address-cells = <0x2>; + #interrupt-cells = <0x2>; + interrupt-controller; + reg = <0x0 0x00400000 0x0 0x400000>; + riscv,ndev = <0x1>; + interrupts-extended = <&CPU0_intc 3 + &CPU1_intc 3 + &CPU2_intc 3 + &CPU3_intc 3>; + }; + + plmt0@100000 { + compatible = "andestech,plmt0"; + reg = <0x0 0x00100000 0x0 0x100000>; + interrupts-extended = <&CPU0_intc 7 + &CPU1_intc 7 + &CPU2_intc 7 + &CPU3_intc 7>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0x0>; + compatible = "fixed-clock"; + clock-frequency = <0x5f5e100>; + }; + + serial0: serial@30300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x0 0x30300000 0x0 0x1000>; + interrupts = <0x9 0x4>; + clock-frequency = <0x12c0000>; + reg-shift = <0x2>; + reg-offset = <0x20>; + no-loopback-test = <0x1>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@30c00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <0x5f5e100>; + clock-freq-min-max = <0x61a80 0x5f5e100>; + fifo-depth = <0x10>; + reg = <0x0 0x30c00000 0x0 0x1000>; + interrupts = <0x12 0x4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + dma-coherent; + }; + + spi: spi@30900000 { + compatible = "andestech,atcspi200"; + reg = <0x0 0x30900000 0x0 0x100000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + num-cs = <0x1>; + clocks = <&spiclk>; + interrupts = <0x4 0x4>; + interrupt-parent = <&plic0>; + + flash@0 { + compatible = "mx25u1635e", "jedec,spi-nor"; + spi-max-frequency = <0x2faf080>; + reg = <0x0>; + spi-cpol; + spi-cpha; + }; + }; +}; diff --git a/arch/riscv/dts/voyager-u-boot.dtsi b/arch/riscv/dts/voyager-u-boot.dtsi new file mode 100644 index 00000000000..cef0aa08b37 --- /dev/null +++ b/arch/riscv/dts/voyager-u-boot.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + cpus { + bootph-pre-ram; + CPU0: cpu@0 { + bootph-pre-ram; + CPU0_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU1: cpu@1 { + bootph-pre-ram; + CPU1_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU2: cpu@2 { + bootph-pre-ram; + CPU2_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU3: cpu@3 { + bootph-pre-ram; + CPU3_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + }; + + memory@0 { + bootph-pre-ram; + }; + + soc { + bootph-pre-ram; + + plic1: interrupt-controller@400000 { + bootph-pre-ram; + }; + + plmt0@100000 { + bootph-pre-ram; + }; + }; + + serial0: serial@30300000 { + bootph-pre-ram; + }; + +}; diff --git a/arch/riscv/dts/xilinx-binman.dts b/arch/riscv/dts/xilinx-binman.dts new file mode 100644 index 00000000000..715080ed763 --- /dev/null +++ b/arch/riscv/dts/xilinx-binman.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * binman file for AMD MicroBlaze V + * + * (C) Copyright 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "binman.dtsi" diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 4050ce2f051..f7a3e076fd5 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -2,15 +2,13 @@ /* * dts file for AMD MicroBlaze V * - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <1>; #size-cells = <1>; @@ -26,6 +24,7 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv32imafdc"; + mmu-type = "riscv,sv39"; i-cache-size = <32768>; d-cache-size = <32768>; clock-frequency = <100000000>; @@ -70,7 +69,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts index 4d65d338ecb..e6235ed2f52 100644 --- a/arch/riscv/dts/xilinx-mbv64.dts +++ b/arch/riscv/dts/xilinx-mbv64.dts @@ -2,15 +2,13 @@ /* * dts file for AMD MicroBlaze V * - * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <2>; #size-cells = <2>; @@ -26,6 +24,7 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; i-cache-size = <32768>; d-cache-size = <32768>; clock-frequency = <100000000>; @@ -70,7 +69,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S index 9884077c933..e5479bbe84e 100644 --- a/arch/riscv/lib/memcpy.S +++ b/arch/riscv/lib/memcpy.S @@ -125,6 +125,14 @@ WEAK(memcpy) .copy_end: ret +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define M_SLL sll +#define M_SRL srl +#else +#define M_SLL srl +#define M_SRL sll +#endif + .Lmisaligned_word_copy: /* * Misaligned word-wise copy. @@ -144,10 +152,10 @@ WEAK(memcpy) addi t0, t0, -(SZREG-1) /* At least one iteration will be executed here, no check */ 1: - srl a4, a5, t3 + M_SRL a4, a5, t3 REG_L a5, SZREG(a1) addi a1, a1, SZREG - sll a2, a5, t4 + M_SLL a2, a5, t4 or a2, a2, a4 REG_S a2, 0(a0) addi a0, a0, SZREG diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S index fbe6701dbe4..b2c1c736713 100644 --- a/arch/riscv/lib/memmove.S +++ b/arch/riscv/lib/memmove.S @@ -91,6 +91,14 @@ WEAK(memmove) mv a0, t0 ret +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define M_SLL sll +#define M_SRL srl +#else +#define M_SLL srl +#define M_SRL sll +#endif + .Lmisaligned_word_copy: /* * Misaligned word-wise copy. @@ -110,10 +118,10 @@ WEAK(memmove) addi t0, t0, SZREG-1 /* At least one iteration will be executed here, no check */ 1: - sll a4, a5, t4 + M_SLL a4, a5, t4 addi a1, a1, -SZREG REG_L a5, 0(a1) - srl a2, a5, t3 + M_SRL a2, a5, t3 or a2, a2, a4 addi a0, a0, -SZREG REG_S a2, 0(a0) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index bb696c5ef7f..a2c739a2044 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -936,6 +936,14 @@ }; }; + i3c0 { + compatible = "sandbox,i3c"; + }; + + i3c1 { + compatible = "sandbox,i3c"; + }; + bootcount@0 { compatible = "u-boot,bootcount-rtc"; rtc = <&rtc_1>; diff --git a/board/andestech/voyager/Kconfig b/board/andestech/voyager/Kconfig new file mode 100644 index 00000000000..b2e212c3fee --- /dev/null +++ b/board/andestech/voyager/Kconfig @@ -0,0 +1,44 @@ +if TARGET_ANDES_VOYAGER + +config SYS_CPU + default "andes" + +config SYS_BOARD + default "voyager" + +config SYS_VENDOR + default "andestech" + +config SYS_SOC + default "qilai" + +config SYS_CONFIG_NAME + default "voyager" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x1F0000 if ENV_IS_IN_SPI_FLASH + +config SPL_TEXT_BASE + default 0x400800000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x400000000 + +config SYS_FDT_BASE + hex + default 0x81E0000 if OF_SEPARATE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RISCV_ANDES + select SUPPORT_SPL + select BINMAN if SPL + imply SMP + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE + imply OF_HAS_PRIOR_STAGE + +endif diff --git a/board/andestech/voyager/MAINTAINERS b/board/andestech/voyager/MAINTAINERS new file mode 100644 index 00000000000..b87026ee383 --- /dev/null +++ b/board/andestech/voyager/MAINTAINERS @@ -0,0 +1,8 @@ +Andestech Voyager BOARD +M: Randolph <randolph@andestech.com> +S: Maintained +F: board/andestech/voyager/ +F: configs/voyager_spl_defconfig +F: doc/board/andestech/voyager.rst +F: include/configs/qilai.h + diff --git a/board/andestech/voyager/Makefile b/board/andestech/voyager/Makefile new file mode 100644 index 00000000000..d293e3e2d89 --- /dev/null +++ b/board/andestech/voyager/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Andes Technology Corporation. +# Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + +obj-y := voyager.o diff --git a/board/andestech/voyager/voyager.c b/board/andestech/voyager/voyager.c new file mode 100644 index 00000000000..dc8f1347775 --- /dev/null +++ b/board/andestech/voyager/voyager.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Andes Technology Corporation + * Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + */ + +#include <asm/csr.h> +#include <asm/global_data.h> +#include <asm/sbi.h> +#include <config.h> +#include <cpu_func.h> +#include <dm.h> +#include <env.h> +#include <fdtdec.h> +#include <flash.h> +#include <image.h> +#include <init.h> +#include <linux/io.h> +#include <net.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r(void) +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_RAM_SUPPORT + BOOT_DEVICE_RAM, +#endif +#ifdef CONFIG_SPL_MMC + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index c81bef9cb7c..77d7b1614c8 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -1,5 +1,5 @@ ARISTAINETOS BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h diff --git a/board/asus/transformer-t20/configs/sl101.config b/board/asus/transformer-t20/configs/sl101.config index 4f639e1b412..87c6f7a216d 100644 --- a/board/asus/transformer-t20/configs/sl101.config +++ b/board/asus/transformer-t20/configs/sl101.config @@ -1 +1,2 @@ +CONFIG_ENV_SOURCE_FILE="sl101" CONFIG_DEFAULT_DEVICE_TREE="tegra20-asus-sl101" diff --git a/board/asus/transformer-t20/sl101.env b/board/asus/transformer-t20/sl101.env new file mode 100644 index 00000000000..f2bf298a997 --- /dev/null +++ b/board/asus/transformer-t20/sl101.env @@ -0,0 +1,15 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS index 58104cc1318..a30c672e1d6 100644 --- a/board/bosch/shc/MAINTAINERS +++ b/board/bosch/shc/MAINTAINERS @@ -1,5 +1,5 @@ SHC BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/bosch/shc F: include/configs/am335x_shc.h diff --git a/board/dhelectronics/common/dh_common.c b/board/dhelectronics/common/dh_common.c index 8c052c45007..6101ecc7ebc 100644 --- a/board/dhelectronics/common/dh_common.c +++ b/board/dhelectronics/common/dh_common.c @@ -88,9 +88,9 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) /* Validate header ID */ if (eip->hdr.id[0] != 'D' || eip->hdr.id[1] != 'H' || eip->hdr.id[2] != 'E') { printf("%s: Error validating header ID! (got %c%c%c (0x%02x 0x%02x 0x%02x) != expected DHE)\n", - __func__, isprint(eip->hdr.id[0]) ? eip->hdr.id[0] : '.', - isprint(eip->hdr.id[1]) ? eip->hdr.id[1] : '.', - isprint(eip->hdr.id[2]) ? eip->hdr.id[2] : '.', + __func__, (isascii(eip->hdr.id[0]) && isprint(eip->hdr.id[0])) ? eip->hdr.id[0] : '.', + (isascii(eip->hdr.id[1]) && isprint(eip->hdr.id[1])) ? eip->hdr.id[1] : '.', + (isascii(eip->hdr.id[2]) && isprint(eip->hdr.id[2])) ? eip->hdr.id[2] : '.', eip->hdr.id[0], eip->hdr.id[1], eip->hdr.id[2]); return -EINVAL; } @@ -131,14 +131,17 @@ int dh_read_eeprom_id_page(u8 *eeprom_buffer, const char *alias) int dh_get_value_from_eeprom_buffer(enum eip_request_values request, u8 *data, int data_len, struct eeprom_id_page *eip) { - const char fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? - DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; - const u8 soc_coded = eip->pl.item_prefix & 0xf; + char fin_chr; + u8 soc_coded; char soc_chr; if (!eip) return -EINVAL; + fin_chr = (eip->pl.item_prefix & DH_ITEM_PREFIX_FIN_BIT) ? + DH_ITEM_PREFIX_FIN_FLASHED_CHR : DH_ITEM_PREFIX_FIN_HALF_CHR; + soc_coded = eip->pl.item_prefix & 0xf; + /* Copy requested data */ switch (request) { case DH_MAC0: diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index a50763e1926..eb9bc93d973 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -49,6 +49,10 @@ (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define OTG_PAD_CTRL \ + (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = { .dram_sdclk_0 = 0x00020030, .dram_sdclk_1 = 0x00020030, @@ -509,7 +513,7 @@ int board_mmc_init(struct bd_info *bis) /* USB */ static iomux_v3_cfg_t const usb_pads[] = { - IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)), + IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_PAD_CTRL)), IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index f7347bbb826..bd9326d6b1b 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -85,6 +85,9 @@ static bool dh_stm32_mac_is_in_ks8851(void) if (!ofnode_valid(node)) return false; + if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) + return false; + ret = ofnode_get_path(node, path, sizeof(path)); if (ret) return false; @@ -93,9 +96,6 @@ static bool dh_stm32_mac_is_in_ks8851(void) if (ret) return false; - if (!ofnode_device_is_compatible(node, "micrel,ks8851-mll")) - return false; - /* * KS8851 with EEPROM may use custom MAC from EEPROM, read * out the KS8851 CCR register to determine whether EEPROM diff --git a/board/freescale/imx95_evk/MAINTAINERS b/board/freescale/imx95_evk/MAINTAINERS index 5caf763e0cc..9d5c4e41b65 100644 --- a/board/freescale/imx95_evk/MAINTAINERS +++ b/board/freescale/imx95_evk/MAINTAINERS @@ -3,4 +3,5 @@ M: Alice Guo <alice.guo@nxp.com> S: Maintained F: board/freescale/imx95_evk/ F: include/configs/imx95_evk.h +F: configs/imx95_a0_19x19_evk_defconfig F: configs/imx95_19x19_evk_defconfig diff --git a/board/gameforce/ace-rk3588s/Kconfig b/board/gameforce/ace-rk3588s/Kconfig new file mode 100644 index 00000000000..52f98ccf897 --- /dev/null +++ b/board/gameforce/ace-rk3588s/Kconfig @@ -0,0 +1,9 @@ +if TARGET_GAMEFORCE_ACE_RK3588S + +config SYS_BOARD + default "gameforce-ace-rk3588s" + +config SYS_VENDOR + default "GameForce" + +endif diff --git a/board/gameforce/ace-rk3588s/MAINTAINERS b/board/gameforce/ace-rk3588s/MAINTAINERS new file mode 100644 index 00000000000..dc18e7c8849 --- /dev/null +++ b/board/gameforce/ace-rk3588s/MAINTAINERS @@ -0,0 +1,5 @@ +GAMEFORCE-ACE-RK3588S +M: Chris Morgan <macromorgan@hotmail.com> +S: Maintained +F: board/gameforce/ace-rk3588s/ +F: configs/gameforce-ace-rk3588s_defconfig diff --git a/board/intel/agilex-socdk/Makefile b/board/intel/agilex-socdk/Makefile new file mode 100644 index 00000000000..306a8cf5f0b --- /dev/null +++ b/board/intel/agilex-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/agilex-socdk/socfpga.c b/board/intel/agilex-socdk/socfpga.c new file mode 100644 index 00000000000..60c8704b391 --- /dev/null +++ b/board/intel/agilex-socdk/socfpga.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <asm/arch/misc.h> + +int board_early_init_f(void) +{ + socfpga_get_sys_mgr_addr(); + return 0; +} diff --git a/board/intel/agilex5-socdk/socfpga.c b/board/intel/agilex5-socdk/socfpga.c index d6628cfc696..60c8704b391 100644 --- a/board/intel/agilex5-socdk/socfpga.c +++ b/board/intel/agilex5-socdk/socfpga.c @@ -7,6 +7,6 @@ int board_early_init_f(void) { - socfpga_get_sys_mgr_addr("sysmgr@10d12000"); + socfpga_get_sys_mgr_addr(); return 0; } diff --git a/board/intel/agilex7m-socdk/MAINTAINERS b/board/intel/agilex7m-socdk/MAINTAINERS new file mode 100644 index 00000000000..9a5b80ae4df --- /dev/null +++ b/board/intel/agilex7m-socdk/MAINTAINERS @@ -0,0 +1,10 @@ +SOCFPGA BOARD +M: Tien Fong Chee <tien.fong.chee@altera.com> +M: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> +S: Maintained +F: arch/arm/dts/socfpga_soc64_u-boot.dtsi +F: arch/arm/dts/socfpga_agilex7m* +F: arch/arm/mach-socfpga/spl_agilex7m.c +F: board/intel/agilex7m-socdk/ +F: include/configs/socfpga_agilex7m_socdk.h +F: configs/socfpga_agilex7m_sdmmc_defconfig diff --git a/board/intel/agilex7m-socdk/Makefile b/board/intel/agilex7m-socdk/Makefile new file mode 100644 index 00000000000..306a8cf5f0b --- /dev/null +++ b/board/intel/agilex7m-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2025 Altera Corporation <www.altera.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/agilex7m-socdk/socfpga.c b/board/intel/agilex7m-socdk/socfpga.c new file mode 100644 index 00000000000..60c8704b391 --- /dev/null +++ b/board/intel/agilex7m-socdk/socfpga.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <asm/arch/misc.h> + +int board_early_init_f(void) +{ + socfpga_get_sys_mgr_addr(); + return 0; +} diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index 8822e5d9155..af0d6afb2b4 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -1,6 +1,6 @@ KM83XX BOARD M: Holger Brunck <holger.brunck@hitachienergy.com> -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/keymile/km83xx/ F: board/keymile/common/ diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 6e8c479e955..760dffc488b 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -59,5 +59,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply MTD_SPI_NAND imply CMD_MTD imply CMD_MTDPARTS + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER endif diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index ba622e38ee5..739a9b6cd76 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -4,52 +4,21 @@ * Padmarao Begari <padmarao.begari@microchip.com> */ -#include <dm.h> -#include <env.h> -#include <init.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/sections.h> +#include <dm.h> +#include <dm/devres.h> +#include <env.h> +#include <linux/compat.h> +#include <mpfs-mailbox.h> DECLARE_GLOBAL_DATA_PTR; -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) -#define MPFS_SYS_SERVICE_CR ((unsigned int *)0x37020050) -#define MPFS_SYS_SERVICE_SR ((unsigned int *)0x37020054) -#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800) - +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) #define PERIPH_RESET_VALUE 0x1e8u -#define SERVICE_CR_REQ 0x1u -#define SERVICE_SR_BUSY 0x2u -static void read_device_serial_number(u8 *response, u8 response_size) -{ - u8 idx; - u8 *response_buf; - unsigned int val; - - response_buf = (u8 *)response; - - writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR); - /* - * REQ bit will remain set till the system controller starts - * processing. - */ - do { - val = readl(MPFS_SYS_SERVICE_CR); - } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ)); - - /* - * Once system controller starts processing the busy bit will - * go high and service is completed when busy bit is gone low - */ - do { - val = readl(MPFS_SYS_SERVICE_SR); - } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY)); - - for (idx = 0; idx < response_size; idx++) - response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx); -} +static unsigned char mac_addr[6]; #if defined(CONFIG_MULTI_DTB_FIT) int board_fit_config_name_match(const char *name) @@ -145,13 +114,35 @@ int board_late_init(void) { u32 ret; int node; - u8 idx; - u8 device_serial_number[16] = { 0 }; - unsigned char mac_addr[6]; - char icicle_mac_addr[20]; + u8 device_serial_number[16] = {0}; void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; - read_device_serial_number(device_serial_number, 16); + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } /* Update MAC address with device serial number */ mac_addr[0] = 0x00; @@ -170,19 +161,6 @@ int board_late_init(void) } } - icicle_mac_addr[0] = '['; - - sprintf(&icicle_mac_addr[1], "%pM", mac_addr); - - icicle_mac_addr[18] = ']'; - icicle_mac_addr[19] = '\0'; - - for (idx = 0; idx < 20; idx++) { - if (icicle_mac_addr[idx] == ':') - icicle_mac_addr[idx] = ' '; - } - env_set("icicle_mac_addr0", icicle_mac_addr); - mac_addr[5] = device_serial_number[0] + 1; node = fdt_path_offset(blob, "/soc/ethernet@20110000"); @@ -194,18 +172,33 @@ int board_late_init(void) } } - icicle_mac_addr[0] = '['; + return 0; +} - sprintf(&icicle_mac_addr[1], "%pM", mac_addr); +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 ret; + int node; - icicle_mac_addr[18] = ']'; - icicle_mac_addr[19] = '\0'; + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mac_addr[5] -= 1; - for (idx = 0; idx < 20; idx++) { - if (icicle_mac_addr[idx] == ':') - icicle_mac_addr[idx] = ' '; + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } } - env_set("icicle_mac_addr1", icicle_mac_addr); return 0; } diff --git a/board/microsoft/surface-2/Kconfig b/board/microsoft/surface-2/Kconfig new file mode 100644 index 00000000000..8573666dc92 --- /dev/null +++ b/board/microsoft/surface-2/Kconfig @@ -0,0 +1,13 @@ +if TARGET_SURFACE_2 + +config SYS_BOARD + default "surface-2" + +config SYS_VENDOR + default "microsoft" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Microsoft Surface 2" + +endif diff --git a/board/microsoft/surface-2/MAINTAINERS b/board/microsoft/surface-2/MAINTAINERS new file mode 100644 index 00000000000..57747d304cd --- /dev/null +++ b/board/microsoft/surface-2/MAINTAINERS @@ -0,0 +1,7 @@ +SURFACE_2 BOARD +M: Jonas Schwöbel <jonasschwoebel@yahoo.de> +S: Maintained +F: arch/arm/dts/tegra114-microsoft-surface-2* +F: board/microsoft/surface-2/ +F: configs/surface-2_defconfig +F: doc/board/microsoft/surface-2.rst diff --git a/board/microsoft/surface-2/Makefile b/board/microsoft/surface-2/Makefile new file mode 100644 index 00000000000..43bf6c66db2 --- /dev/null +++ b/board/microsoft/surface-2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + +obj-$(CONFIG_XPL_BUILD) += surface-2-spl.o +obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o diff --git a/board/microsoft/surface-2/board-info.c b/board/microsoft/surface-2/board-info.c new file mode 100644 index 00000000000..95a4accdc90 --- /dev/null +++ b/board/microsoft/surface-2/board-info.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2025 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <stdio.h> +#include <env.h> +#include <spl_gpio.h> + +#include <asm/gpio.h> +#include <asm/arch/pinmux.h> +#include <linux/string.h> + +static int id_gpio_get_value(u32 pingrp, u32 pin) +{ + /* Configure pinmux */ + pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); + pinmux_tristate_enable(pingrp); + pinmux_set_io(pingrp, PMUX_PIN_INPUT); + + /* + * Since this function may be called + * during DM reload we should use SPL + * GPIO functions which do not depend + * on DM. + */ + spl_gpio_input(NULL, pin); + return spl_gpio_get_value(NULL, pin); +} + +static int get_board_id(void) +{ + u32 pcb_id0, pcb_id1, pcb_id2, pcb_id3, pcb_id4, board_id; + + pcb_id0 = id_gpio_get_value(PMUX_PINGRP_KB_COL0_PQ0, TEGRA_GPIO(Q, 0)); + pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_COL1_PQ1, TEGRA_GPIO(Q, 1)); + pcb_id2 = id_gpio_get_value(PMUX_PINGRP_KB_COL2_PQ2, TEGRA_GPIO(Q, 2)); + pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL3_PQ3, TEGRA_GPIO(Q, 3)); + pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_COL4_PQ4, TEGRA_GPIO(Q, 4)); + + /* Construct board ID */ + board_id = pcb_id4 << 4 | pcb_id3 << 3 | pcb_id2 << 2 | pcb_id1 << 1 | pcb_id0; + + log_debug("[SURFACE-2]: Board ID %02x\n", board_id); + + return board_id & 0x1f; +} + +int board_fit_config_name_match(const char *name) +{ + char dt_name[64] = { 0 }; + + snprintf(dt_name, sizeof(dt_name), "tegra114-microsoft-surface-2-%02x.dtb", + get_board_id()); + + if (!strcmp(name, dt_name)) + return 0; + + return -1; +} + +void nvidia_board_late_init(void) +{ + char dt_path[64] = { 0 }; + + snprintf(dt_path, sizeof(dt_path), "tegra114-microsoft-surface-2-%02x.dtb", + get_board_id()); + env_set("fdtfile", dt_path); +} diff --git a/board/microsoft/surface-2/surface-2-spl.c b/board/microsoft/surface-2/surface-2-spl.c new file mode 100644 index 00000000000..16f4373c7f0 --- /dev/null +++ b/board/microsoft/surface-2/surface-2-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Surface 2 SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2023 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} diff --git a/board/microsoft/surface-2/surface-2.env b/board/microsoft/surface-2/surface-2.env new file mode 100644 index 00000000000..a77885a7c6d --- /dev/null +++ b/board/microsoft/surface-2/surface-2.env @@ -0,0 +1,8 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_4=power off=reset +bootmenu_delay=-1 diff --git a/board/pegatron/chagall/Kconfig b/board/pegatron/chagall/Kconfig new file mode 100644 index 00000000000..8c229d0e333 --- /dev/null +++ b/board/pegatron/chagall/Kconfig @@ -0,0 +1,13 @@ +if TARGET_CHAGALL + +config SYS_BOARD + default "chagall" + +config SYS_VENDOR + default "pegatron" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Pegatron Chagall" + +endif diff --git a/board/pegatron/chagall/MAINTAINERS b/board/pegatron/chagall/MAINTAINERS new file mode 100644 index 00000000000..5ebd5940f42 --- /dev/null +++ b/board/pegatron/chagall/MAINTAINERS @@ -0,0 +1,7 @@ +CHAGALL BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: arch/arm/dts/tegra30-pegatron-chagall.dts +F: board/pegatron/chagall/ +F: configs/chagall_defconfig +F: doc/board/pegatron/chagall.rst diff --git a/board/pegatron/chagall/Makefile b/board/pegatron/chagall/Makefile new file mode 100644 index 00000000000..17cfef50987 --- /dev/null +++ b/board/pegatron/chagall/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2021 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-$(CONFIG_XPL_BUILD) += chagall-spl.o + +obj-y += chagall.o diff --git a/board/pegatron/chagall/chagall-spl.c b/board/pegatron/chagall/chagall-spl.c new file mode 100644 index 00000000000..6c271973ada --- /dev/null +++ b/board/pegatron/chagall/chagall-spl.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Chagall SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <asm/arch/tegra.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include <linux/delay.h> + +#define TPS65911_I2C_ADDR (0x2D << 1) +#define TPS65911_VDDCTRL_OP_REG 0x28 +#define TPS65911_VDDCTRL_SR_REG 0x27 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) +#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) + +#define TPS62361B_I2C_ADDR (0x60 << 1) +#define TPS62361B_SET3_REG 0x03 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) + +void pmic_enable_cpu_vdd(void) +{ + /* Set VDD_CORE to 1.200V. */ + tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA); + + udelay(1000); + + /* + * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. + * First set VDD to 1.0125V, then enable the VDD regulator. + */ + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA); + udelay(10 * 1000); +} diff --git a/board/pegatron/chagall/chagall.c b/board/pegatron/chagall/chagall.c new file mode 100644 index 00000000000..1412c4f9b60 --- /dev/null +++ b/board/pegatron/chagall/chagall.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2021 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +/* Chagall derives from Cardhu board */ + +#include <fdt_support.h> + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif diff --git a/board/pegatron/chagall/chagall.env b/board/pegatron/chagall/chagall.env new file mode 100644 index 00000000000..68bf51bdc3c --- /dev/null +++ b/board/pegatron/chagall/chagall.env @@ -0,0 +1,9 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu + +bootmenu_0=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_1=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_2=reboot RCM=enterrcm +bootmenu_3=reboot=reset +bootmenu_4=power off=poweroff +bootmenu_delay=-1 diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env index 797904013dc..ff4ab8c87b8 100644 --- a/board/phytec/phycore_am62ax/phycore_am62ax.env +++ b/board/phytec/phycore_am62ax/phycore_am62ax.env @@ -25,5 +25,9 @@ spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 +#ifdef CONFIG_BOOTMETH_RAUC +bootmeths=rauc script efi extlinux pxe +#else bootmeths=script efi extlinux pxe +#endif boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env index 797904013dc..ff4ab8c87b8 100644 --- a/board/phytec/phycore_am62x/phycore_am62x.env +++ b/board/phytec/phycore_am62x/phycore_am62x.env @@ -25,5 +25,9 @@ spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 +#ifdef CONFIG_BOOTMETH_RAUC +bootmeths=rauc script efi extlinux pxe +#else bootmeths=script efi extlinux pxe +#endif boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env index 36ab16e2f7a..cbaf45b3ace 100644 --- a/board/phytec/phycore_am64x/phycore_am64x.env +++ b/board/phytec/phycore_am64x/phycore_am64x.env @@ -24,5 +24,9 @@ spi_fdt_addr=0x700000 spi_image_addr=0x800000 spi_ramdisk_addr=0x2200000 +#ifdef CONFIG_BOOTMETH_RAUC +bootmeths=rauc script efi extlinux pxe +#else bootmeths=script efi extlinux pxe +#endif boot_targets=mmc1 mmc0 spi_flash dhcp diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index 8d2caf8bbef..fab66caf2a1 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -79,6 +79,10 @@ int board_fix_fdt(void *blob) emmc_fixup(blob, &data); + /* Update dtb clocks for low drive mode */ + if (is_voltage_mode(VOLT_LOW_DRIVE)) + low_drive_freq_update(blob); + return 0; } @@ -86,5 +90,10 @@ int ft_board_setup(void *blob, struct bd_info *bd) { emmc_fixup(blob, NULL); + /** + * NOTE: VOLT_LOW_DRIVE fixup is done by the ft_system_setup() + * in arch/arm/mach-imx/imx9/soc.c for Linux device-tree. + */ + return 0; } diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index 7b5d38d438f..beaa536c600 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -52,8 +52,7 @@ void spl_dram_init(void) int ret; enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; - /* NOTE: In SPL lpi2c3 is mapped to bus 0 */ - ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR); + ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR); if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) goto out; diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index 8e72b5424d1..58de7f25cbd 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -6,8 +6,12 @@ #include <asm/io.h> #include <compiler.h> #include <dbsc5.h> +#include <spi.h> +#include <spi_flash.h> #include <spl.h> +#include "../../../drivers/mtd/spi/sf_internal.h" + #if defined(CONFIG_XPL_BUILD) static const struct renesas_dbsc5_board_config @@ -112,12 +116,134 @@ dbsc5_get_board_data(struct udevice *dev, const u32 modemr0) * Use MD[19] setting to discern 8 GiB and 16 GiB DRAM Sparrow Hawk * board variants from each other automatically. */ - if (modemr0 & BIT(19)) + if ((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19))) return &renesas_v4h_sparrowhawk_16g_5500_dbsc5_board_config; else return &renesas_v4h_sparrowhawk_8g_6400_dbsc5_board_config; } +static bool renesas_v4h_sparrowhawk_is_evta1 = false; + +unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash) +{ + const u8 sf_ids_evta1[6] = { 0x01, 0x02, 0x20, 0x4d, 0x00, 0x81 }; + + renesas_v4h_sparrowhawk_is_evta1 = !memcmp(sf_ids_evta1, flash->info->id, + sizeof(sf_ids_evta1)); + + return CONFIG_SYS_SPI_U_BOOT_OFFS; +} + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + void *blob = spl_image_fdt_addr(spl_image); + int err, offs; + u32 size; + + if (!renesas_v4h_sparrowhawk_is_evta1) + return; + + printf("EVTA1 board detected\n"); + + /* + * MicroSD voltage switch is not populated on Sparrow Hawk EVTA1, + * rewrite MicroSD slot regulator to only support 3V3 and disable + * UHS modes in MicroSD slot node. + */ + if (!blob) + return; + + err = fdt_check_header(blob); + if (err < 0) { + printf("Invalid FDT header: %s\n", fdt_strerror(err)); + return; + } + + size = fdt_totalsize(blob); + err = fdt_open_into(blob, blob, size + 64); + if (err < 0) { + printf("Failed to expand DT\n"); + return; + } + + offs = fdt_path_offset(blob, "/regulator-vcc-sdhi"); + if (offs < 0) { + printf("Failed to locate MicroSD regulator node: %d\n", offs); + return; + } + + err = fdt_setprop_string(blob, offs, "compatible", "regulator-fixed"); + if (err < 0) { + printf("Failed to set fixed MicroSD regulator: %d\n", err); + return; + } + + err = fdt_setprop_u32(blob, offs, "regulator-min-microvolt", 3300000); + if (err < 0) { + printf("Failed to set MicroSD regulator minimum voltage: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "gpios"); + if (err < 0) { + printf("Failed to remove MicroSD regulator gpios: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "gpios-states"); + if (err < 0) { + printf("Failed to remove MicroSD regulator gpio states: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "states"); + if (err < 0) { + printf("Failed to remove MicroSD regulator states: %d\n", err); + return; + } + + offs = fdt_path_offset(blob, "/soc/mmc@ee140000"); + if (offs < 0) { + printf("Failed to locate MicroSD device node: %d\n", offs); + return; + } + + err = fdt_nop_property(blob, offs, "sd-uhs-sdr50"); + if (err < 0) { + printf("Failed to disable SDR50 mode in MicroSD node: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "sd-uhs-sdr104"); + if (err < 0) { + printf("Failed to disable SDR104 mode in MicroSD node: %d\n", err); + return; + } + + err = fdt_setprop_string(blob, offs, "pinctrl-names", "default"); + if (err < 0) { + printf("Failed to set fixed MicroSD pin names: %d\n", err); + return; + } + + err = fdt_nop_property(blob, offs, "pinctrl-1"); + if (err < 0) { + printf("Failed to disable UHS pins in MicroSD node: %d\n", err); + return; + } + + offs = fdt_path_offset(blob, "/soc/pinctrl@e6050000/avb0/pins-vddq18-25-avb"); + if (offs < 0) { + printf("Failed to locate AVB pinctrl node: %d\n", offs); + return; + } + + err = fdt_setprop_u32(blob, offs, "power-source", 2500); + if (err < 0) { + printf("Failed to set AVB IO voltage: %d\n", err); + return; + } +} #endif #define RST_MODEMR0 0xe6160000 @@ -130,7 +256,7 @@ void renesas_dram_init_banksize(void) int bank; /* 8 GiB device, do nothing. */ - if (!(modemr0 & BIT(19))) + if (!((renesas_get_cpu_rev_integer() >= 3) && (modemr0 & BIT(19)))) return; /* 16 GiB device, adjust memory map. */ diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS index 1232f05a387..379c85f48a4 100644 --- a/board/rockchip/evb_rk3588/MAINTAINERS +++ b/board/rockchip/evb_rk3588/MAINTAINERS @@ -48,3 +48,9 @@ S: Maintained F: configs/orangepi-5-plus-rk3588_defconfig F: arch/arm/dts/rk3588-orangepi-5-plus.dts F: arch/arm/dts/rk3588-orangepi-5-plus-u-boot.dtsi + +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong <zhihong@nzhnb.com> +S: Maintained +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile index 71d46ea3d2b..76b8d47994e 100644 --- a/board/samsung/e850-96/Makefile +++ b/board/samsung/e850-96/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2024, Linaro Limited # Sam Protsenko <semen.protsenko@linaro.org> -obj-y := e850-96.o fw.o +obj-y := e850-96.o fw.o acpm.o pmic.o diff --git a/board/samsung/e850-96/acpm.c b/board/samsung/e850-96/acpm.c new file mode 100644 index 00000000000..1cc5c6d0e4a --- /dev/null +++ b/board/samsung/e850-96/acpm.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * ACPM (Active Clock and Power Management) is an IPC protocol for communicating + * with APM (Active Power Management) core. The message exchange between AP + * (Application Processor) and APM is happening by using shared memory in SRAM + * (iRAM) and generating interrupts using Mailbox block. By using this IPC + * interface it's possible to offload power management tasks to APM core, which + * acts as a supervisor for CPU. One of the main tasks of APM is controlling + * PMIC chip over I3C bus. So in order to access PMIC chip registers it's + * recommended to do so by sending corresponding commands to APM via ACPM IPC + * protocol. The IPC interaction sequence looks like this: + * + * AP (CPU) <-> ACPM IPC (Mailbox + SRAM) <-> APM <-> I3C <-> PMIC + * + * This file contains functions for accessing I3C bus via APM block using + * ACPM IPC. + */ + +#include <linux/iopoll.h> +#include <linux/time.h> +#include <asm/io.h> +#include "acpm.h" + +/* Mailbox registers */ +#define MBOX_INTGR0 0x8 /* Interrupt Generation */ +#define MBOX_INTCR1 0x20 /* Interrupt Clear */ +#define MBOX_INTSR1 0x28 /* Interrupt Status */ +#define MBOX_INTGR_OFFSET 16 +#define MBOX_TIMEOUT (1 * USEC_PER_SEC) + +/* APM shared memory registers */ +#define SHMEM_SR0 0x0 +#define SHMEM_SR1 0x4 +#define SHMEM_SR2 0x8 +#define SHMEM_SR3 0xc + +/* IPC functions */ +#define IPC_FUNC_READ 0x0 +#define IPC_FUNC_WRITE 0x1 +/* Command 0 shifts and masks */ +#define IPC_REG_SHIFT 0 +#define IPC_REG_MASK 0xff +#define IPC_TYPE_SHIFT 8 +#define IPC_TYPE_MASK 0xf +#define IPC_CHANNEL_SHIFT 12 +#define IPC_CHANNEL_MASK 0xf +/* Command 1 shifts and masks */ +#define IPC_FUNC_SHIFT 0 +#define IPC_FUNC_MASK 0xff +#define IPC_WRITE_VAL_SHIFT 8 +#define IPC_WRITE_VAL_MASK 0xff +/* Command 3 shifts and masks */ +#define IPC_DEST_SHIFT 8 +#define IPC_DEST_MASK 0xff +#define IPC_RETURN_SHIFT 24 +#define IPC_RETURN_MASK 0xff + +/** + * acpm_ipc_send_data_async() - Send data to I3C block over ACPM IPC + * @acpm: ACPM data + * @cmd0: Command 0 value to send + * @cmd1: Command 1 value to send + */ +static void acpm_ipc_send_data_async(struct acpm *acpm, u32 cmd0, u32 cmd1) +{ + u32 irq_bit = 1 << acpm->ipc_ch; + u32 intgr = irq_bit << MBOX_INTGR_OFFSET; + + /* Write data to the shared memory */ + writel(cmd0, acpm->sram_base + SHMEM_SR0); + writel(cmd1, acpm->sram_base + SHMEM_SR1); + dsb(); + + /* Generate interrupt for I3C block */ + writel(intgr, acpm->mbox_base + MBOX_INTGR0); +} + +/** + * acpm_ipc_wait_resp() - Read response data from I3C block over ACPM IPC + * @acpm: ACPM data + * @cmd2: Will contain read value for command 2 + * @cmd3: Will contain read value for command 3 + * + * Return: 0 on success or negative value on error. + */ +static int acpm_ipc_wait_resp(struct acpm *acpm, u32 *cmd2, u32 *cmd3) +{ + u32 irq_bit = 1 << acpm->ipc_ch; + u32 reg; + int ret; + + /* Wait for the interrupt from I3C block */ + ret = readl_poll_timeout(acpm->mbox_base + MBOX_INTSR1, reg, + reg & irq_bit, MBOX_TIMEOUT); + if (ret < 0) + return ret; + + /* Clear the interrupt */ + writel(irq_bit, acpm->mbox_base + MBOX_INTCR1); + + /* Read data from the shared memory */ + *cmd2 = readl(acpm->sram_base + SHMEM_SR2); + *cmd3 = readl(acpm->sram_base + SHMEM_SR3); + + return 0; +} + +/** + * acpm_i3c_read() - Read an I3C register of some I3C slave device + * @acpm: ACPM data + * @ch: I3C channel (bus) number (0-15) + * @addr: I3C address of slave device (0-15) + * @reg: Address of I3C register in the slave device to read from + * @val: Will contain the read value + * + * Return: 0 on success or non-zero code on error (may be positive). + */ +int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val) +{ + u32 cmd[4] = { 0 }; + u8 ret; + + cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT | + (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT | + (reg & IPC_REG_MASK) << IPC_REG_SHIFT; + cmd[1] = IPC_FUNC_READ << IPC_FUNC_SHIFT; + + acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]); + ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]); + if (ret) + return ret; + + *val = (cmd[3] >> IPC_DEST_SHIFT) & IPC_DEST_MASK; + ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK; + return ret; +} + +/** + * acpm_i3c_write() - Write an I3C register of some I3C slave device + * @acpm: ACPM data + * @ch: I3C channel (bus) number (0-15) + * @addr: I3C address of slave device (0-15) + * @reg: Address of I3C register in the slave device to write into + * @val: Value to write + * + * Return: 0 on success or non-zero code on error (may be positive). + */ +int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val) +{ + u32 cmd[4] = { 0 }; + u8 ret; + + cmd[0] = (ch & IPC_CHANNEL_MASK) << IPC_CHANNEL_SHIFT | + (addr & IPC_TYPE_MASK) << IPC_TYPE_SHIFT | + (reg & IPC_REG_MASK) << IPC_REG_SHIFT; + cmd[1] = IPC_FUNC_WRITE << IPC_FUNC_SHIFT | + (val & IPC_WRITE_VAL_MASK) << IPC_WRITE_VAL_SHIFT; + + acpm_ipc_send_data_async(acpm, cmd[0], cmd[1]); + ret = acpm_ipc_wait_resp(acpm, &cmd[2], &cmd[3]); + if (ret) + return ret; + + ret = (cmd[3] >> IPC_RETURN_SHIFT) & IPC_RETURN_MASK; + return ret; +} diff --git a/board/samsung/e850-96/acpm.h b/board/samsung/e850-96/acpm.h new file mode 100644 index 00000000000..9373969209f --- /dev/null +++ b/board/samsung/e850-96/acpm.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#ifndef __E850_96_ACPM_H +#define __E850_96_ACPM_H + +#include <linux/types.h> + +/** + * struct acpm - Data for I3C communication over ACPM IPC protocol + * @mbox_base: Base address of APM mailbox block + * @sram_base: Base address of shared memory used for APM messages + * @ipc_ch: Mailbox channel number used for communication with I3C block (0-15) + */ +struct acpm { + void __iomem *mbox_base; + void __iomem *sram_base; + u8 ipc_ch; +}; + +int acpm_i3c_read(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 *val); +int acpm_i3c_write(struct acpm *acpm, u8 ch, u8 addr, u8 reg, u8 val); + +#endif /* __E850_96_ACPM_H */ diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index a6c264d1248..3df241edde2 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -8,13 +8,28 @@ #include <env.h> #include <init.h> #include <mapmem.h> +#include <net.h> +#include <usb.h> #include <asm/io.h> #include "fw.h" +#include "pmic.h" /* OTP Controller base address and register offsets */ -#define EXYNOS850_OTP_BASE 0x10000000 -#define OTP_CHIPID0 0x4 -#define OTP_CHIPID1 0x8 +#define EXYNOS850_OTP_BASE 0x10000000 +#define OTP_CHIPID0 0x4 +#define OTP_CHIPID1 0x8 + +/* ACPM and PMIC definitions */ +#define EXYNOS850_MBOX_APM2AP_BASE 0x11900000 +#define EXYNOS850_APM_SRAM_BASE 0x02039000 /* in iRAM */ +#define EXYNOS850_APM_SHMEM_OFFSET 0x3200 +#define EXYNOS850_IPC_AP_I3C 10 + +/* LDFW firmware definitions */ +#define LDFW_NWD_ADDR 0x88000000 +#define EMMC_IFNAME "mmc" +#define EMMC_DEV_NUM 0 +#define EMMC_ESP_PART 1 struct efi_fw_image fw_images[] = { { @@ -55,6 +70,13 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; +static struct acpm acpm = { + .mbox_base = (void __iomem *)EXYNOS850_MBOX_APM2AP_BASE, + .sram_base = (void __iomem *)(EXYNOS850_APM_SRAM_BASE + + EXYNOS850_APM_SHMEM_OFFSET), + .ipc_ch = EXYNOS850_IPC_AP_I3C, +}; + int dram_init(void) { return fdtdec_setup_mem_size_base(); @@ -92,19 +114,74 @@ static void setup_serial(void) env_set("serial#", serial_str); } -int board_late_init(void) +static void setup_ethaddr(void) +{ + u64 serial_num; + u32 mac_hi, mac_lo; + u8 mac_addr[6]; + + if (env_get("ethaddr")) + return; + + serial_num = get_chip_id(); + mac_lo = (u32)serial_num; /* OTP_CHIPID0 */ + mac_hi = (u32)(serial_num >> 32UL); /* OTP_CHIPID1 */ + mac_addr[0] = (mac_hi >> 8) & 0xff; + mac_addr[1] = mac_hi & 0xff; + mac_addr[2] = (mac_lo >> 24) & 0xff; + mac_addr[3] = (mac_lo >> 16) & 0xff; + mac_addr[4] = (mac_lo >> 8) & 0xff; + mac_addr[5] = mac_lo & 0xff; + mac_addr[0] &= ~0x1; /* make sure it's not a multicast address */ + if (is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); +} + +/* + * Call this in board_late_init() to avoid probing block devices before + * efi_init_early(). + */ +void load_firmware(void) { + const char *ifname; + ulong dev, part; int err; + ifname = env_get("bootdev"); + if (!ifname) + ifname = EMMC_IFNAME; + dev = env_get_ulong("bootdevnum", 10, EMMC_DEV_NUM); + part = env_get_ulong("bootdevpart", 10, EMMC_ESP_PART); + + if (!strcmp(ifname, "usb")) { + printf("Starting USB (bootdev=usb)...\n"); + err = usb_init(); + if (err) + return; + } + + printf("Loading LDFW firmware (from %s %ld)...\n", ifname, dev); + err = load_ldfw(ifname, dev, part, LDFW_NWD_ADDR); + if (err) + printf("ERROR: LDFW loading failed (%d)\n", err); +} + +int board_late_init(void) +{ setup_serial(); + setup_ethaddr(); + load_firmware(); - /* - * Do this in board_late_init() to make sure MMC is not probed before - * efi_init_early(). - */ - err = load_ldfw(); + return 0; +} + +int power_init_board(void) +{ + int err; + + err = pmic_init(&acpm); if (err) - printf("ERROR: LDFW loading failed (%d)\n", err); + printf("ERROR: Failed to configure PMIC (%d)\n", err); return 0; } diff --git a/board/samsung/e850-96/e850-96.env b/board/samsung/e850-96/e850-96.env index aed7a71046d..992318b0ab2 100644 --- a/board/samsung/e850-96/e850-96.env +++ b/board/samsung/e850-96/e850-96.env @@ -5,7 +5,7 @@ fdt_addr_r=0x8c000000 scriptaddr=0x8c100000 pxefile_addr_r=0x8c200000 ramdisk_addr_r=0x8c300000 -fdtfile=CONFIG_DEFAULT_FDT_FILE +fdtfile=exynos/exynos850-e850-96.dtb dfu_alt_info= rawemmc raw 0 0x747c000 mmcpart 1; diff --git a/board/samsung/e850-96/fw.c b/board/samsung/e850-96/fw.c index 8f64e759b43..64235c01a25 100644 --- a/board/samsung/e850-96/fw.c +++ b/board/samsung/e850-96/fw.c @@ -11,13 +11,9 @@ #include <linux/arm-smccc.h> #include "fw.h" -#define EMMC_IFACE "mmc" -#define EMMC_DEV_NUM 0 #define LDFW_RAW_PART "ldfw" -#define LDFW_FAT_PART "esp" #define LDFW_FAT_PATH "/EFI/firmware/ldfw.bin" -#define LDFW_NWD_ADDR 0x88000000 #define LDFW_MAGIC 0x10adab1e #define SMC_CMD_LOAD_LDFW -0x500 #define SDM_HW_RESET_STATUS 0x1230 @@ -39,19 +35,23 @@ struct ldfw_header { }; /* Load LDFW binary as a file from FAT partition */ -static int read_fw_from_fat(const char *part_name, const char *path, void *buf) +static int read_fw_from_fat(const char *ifname, int dev, int part, + const char *path, void *buf) { - char dev_part_str[8]; + struct blk_desc *blk_desc; loff_t len_read; int err; - snprintf(dev_part_str, sizeof(dev_part_str), "%d#%s", EMMC_DEV_NUM, - LDFW_FAT_PART); + blk_desc = blk_get_dev(ifname, dev); + if (!blk_desc) { + debug("%s: Can't get block device\n", __func__); + return -ENODEV; + } - err = fs_set_blk_dev(EMMC_IFACE, dev_part_str, FS_TYPE_FAT); + err = fs_set_blk_dev_with_part(blk_desc, part); if (err) { - debug("%s: Can't set block device\n", __func__); - return -ENODEV; + debug("%s: Can't set partition\n", __func__); + return -ENOENT; } err = fs_read(path, (ulong)buf, 0, 0, &len_read); @@ -64,16 +64,17 @@ static int read_fw_from_fat(const char *part_name, const char *path, void *buf) } /* Load LDFW binary from raw partition on block device into RAM buffer */ -static int read_fw_from_raw(const char *part_name, void *buf) +static int read_fw_from_raw(const char *ifname, int dev, const char *part_name, + void *buf) { struct blk_desc *blk_desc; struct disk_partition part; unsigned long cnt; int part_num; - blk_desc = blk_get_dev(EMMC_IFACE, EMMC_DEV_NUM); + blk_desc = blk_get_dev(ifname, dev); if (!blk_desc) { - debug("%s: Can't get eMMC device\n", __func__); + debug("%s: Can't get block device\n", __func__); return -ENODEV; } @@ -92,9 +93,17 @@ static int read_fw_from_raw(const char *part_name, void *buf) return 0; } -int load_ldfw(void) +/** + * load_ldfw - Load the loadable firmware (LDFW) + * @ifname: Interface name of the block device to load the firmware from + * @dev: Device number + * @part: Partition number + * @addr: Temporary memory (Normal World) to use for loading the firmware + * + * Return: 0 on success or a negative value on error. + */ +int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr) { - const phys_addr_t addr = (phys_addr_t)LDFW_NWD_ADDR; struct ldfw_header *hdr; struct arm_smccc_res res; void *buf = (void *)addr; @@ -102,9 +111,9 @@ int load_ldfw(void) int err, i; /* First try to read LDFW from EFI partition, then from the raw one */ - err = read_fw_from_fat(LDFW_FAT_PART, LDFW_FAT_PATH, buf); + err = read_fw_from_fat(ifname, dev, part, LDFW_FAT_PATH, buf); if (err) { - err = read_fw_from_raw(LDFW_RAW_PART, buf); + err = read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf); if (err) return err; } diff --git a/board/samsung/e850-96/fw.h b/board/samsung/e850-96/fw.h index 472664e4ed2..73d9615d4a9 100644 --- a/board/samsung/e850-96/fw.h +++ b/board/samsung/e850-96/fw.h @@ -7,6 +7,8 @@ #ifndef __E850_96_FW_H #define __E850_96_FW_H -int load_ldfw(void); +#include <asm/types.h> + +int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr); #endif /* __E850_96_FW_H */ diff --git a/board/samsung/e850-96/pmic.c b/board/samsung/e850-96/pmic.c new file mode 100644 index 00000000000..037fd4844c5 --- /dev/null +++ b/board/samsung/e850-96/pmic.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Linaro Ltd. + * Author: Sam Protsenko <semen.protsenko@linaro.org> + * + * This file contains functions for S2MPU12 PMIC regulators configuration. + * + * Example of voltage calculation for LDO24 and LDO32: + * - V_min = 1800 mV + * - V_step = 25 mV + * - V_wanted = 3300 mV + * - register value: (V_wanted - V_min) / V_step = 60 = 0x3c + * + * NOTE: 0x3c value might mean different voltage for other LDOs. + */ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include "pmic.h" + +/* PMIC definitions */ +#define S2MPU12_CHANNEL 0 /* I3C bus number of PMIC */ +#define S2MPU12_PM_ADDR 0x1 /* I3C slave addr of PM part */ + +/* PMIC I3C registers */ +#define S2MPU12_PM_LDO1_CTRL 0x2b +#define S2MPU12_PM_LDO_CTRL(n) (S2MPU12_PM_LDO1_CTRL + (n) - 1) + +/* LDOx_CTRL values */ +#define S2MPU12_LDO_CTRL_OUT_MASK (0x3 << 6) +#define S2MPU12_LDO_CTRL_OUT_ALWAYS_ON (0x3 << 6) + +struct pmic_ldo { + u8 num; /* LDO number */ + u8 en; /* "enable" bits value in LDOx_CTRL register */ + u8 out; /* "output voltage" bits value in LDOx_CTRL register */ +}; + +/* List of LDOs to enable only */ +static u8 pmic_ldos_en[] = { + 2, /* 1.8V/450mA: multiple lines */ + 11, /* 3.0V/150mA: AVDD33_USB20 */ + 23, /* 2.85V/800mA: VDD_EMMC_2P85 */ + 27, /* 3.0V/150mA: MIPI_SWITCH_3V3 */ + 28, /* 1.8V/150mA: HDMI_CONV_1V8 */ + 30, /* 1.8V/150mA: NPU_VDD18 */ +}; + +/* List of LDOs to enable and set output voltage */ +static struct pmic_ldo pmic_ldos_en_out[] = { + { + .num = 24, /* 3.0V/800mA: VDD_LAN (LAN9514) */ + .en = S2MPU12_LDO_CTRL_OUT_ALWAYS_ON, + .out = 0x3c, /* means 3.3V for LDO24 */ + }, { + .num = 32, /* 3.3V/300mA: CAM_VDD (RPi camera module) */ + .en = S2MPU12_LDO_CTRL_OUT_ALWAYS_ON, + .out = 0x3c, /* means 3.3V for LDO32 */ + }, +}; + +/* Enable specified LDO */ +static int pmic_ldo_set_en(struct acpm *acpm, u8 ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo); + u8 val; + int err; + + err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val); + if (err) + return err; + + val &= ~S2MPU12_LDO_CTRL_OUT_MASK; + val |= S2MPU12_LDO_CTRL_OUT_ALWAYS_ON; + + return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val); +} + +/* Enable specified LDO and set its voltage to 0xc0 value */ +static int pmic_ldo_set_en_out(struct acpm *acpm, struct pmic_ldo *ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo->num); + const u8 val = ldo->en | ldo->out; + + return acpm_i3c_write(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, val); +} + +#ifdef DEBUG +static void pmic_trace_ldo(struct acpm *acpm, u8 ldo) +{ + const u8 reg = S2MPU12_PM_LDO_CTRL(ldo); + u8 val; + int err; + + err = acpm_i3c_read(acpm, S2MPU12_CHANNEL, S2MPU12_PM_ADDR, reg, &val); + if (err) + printf(" S2MPU12_PM_LDO%u_CTRL: Read error!\n", ldo); + else + printf(" S2MPU12_PM_LDO%u_CTRL: 0x%x\n", ldo, val); +} + +static void pmic_trace_ldos(struct acpm *acpm) +{ + size_t i; + + printf("Tracing LDOs...\n"); + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i) + pmic_trace_ldo(acpm, pmic_ldos_en[i]); + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i) + pmic_trace_ldo(acpm, pmic_ldos_en_out[i].num); +} +#endif + +/** + * pmic_init() - Enable power regulators in S2MPU12 PMIC. + * @acpm: Data for I3C communication with PMIC over ACPM protocol + * + * Enable LDOs needed for devices used in the bootloader and kernel. + * + * Return: 0 on success or non-zero code on error. + */ +int pmic_init(struct acpm *acpm) +{ + size_t i; + int err; + + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en); ++i) { + err = pmic_ldo_set_en(acpm, pmic_ldos_en[i]); + if (err) + return -EIO; + } + + for (i = 0; i < ARRAY_SIZE(pmic_ldos_en_out); ++i) { + err = pmic_ldo_set_en_out(acpm, &pmic_ldos_en_out[i]); + if (err) + return -EIO; + } + +#ifdef DEBUG + pmic_trace_ldos(acpm); +#endif + + return 0; +} diff --git a/board/samsung/e850-96/pmic.h b/board/samsung/e850-96/pmic.h new file mode 100644 index 00000000000..46624c2ebd4 --- /dev/null +++ b/board/samsung/e850-96/pmic.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2025 Linaro Ltd. + * Sam Protsenko <semen.protsenko@linaro.org> + */ + +#ifndef __E850_96_PMIC_H +#define __E850_96_PMIC_H + +#include "acpm.h" + +int pmic_init(struct acpm *acpm); + +#endif /* __E850_96_PMIC_H */ diff --git a/board/samsung/n1/Kconfig b/board/samsung/n1/Kconfig new file mode 100644 index 00000000000..a5e5edda9e2 --- /dev/null +++ b/board/samsung/n1/Kconfig @@ -0,0 +1,13 @@ +if TARGET_SAMSUNG_N1 + +config SYS_BOARD + default "n1" + +config SYS_VENDOR + default "samsung" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Samsung N1" + +endif diff --git a/board/samsung/n1/MAINTAINERS b/board/samsung/n1/MAINTAINERS new file mode 100644 index 00000000000..798cb56cd37 --- /dev/null +++ b/board/samsung/n1/MAINTAINERS @@ -0,0 +1,9 @@ +N1 BOARD +M: Ion Agorria <ion@agorria.com> +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: arch/arm/dts/tegra20-samsung-bose.dts +F: arch/arm/dts/tegra20-samsung-n1.dts +F: board/samsung/n1/ +F: configs/n1_defconfig +F: doc/board/samsung/n1.rst diff --git a/board/samsung/n1/bose.config b/board/samsung/n1/bose.config new file mode 100644 index 00000000000..6d6d9d3f2ce --- /dev/null +++ b/board/samsung/n1/bose.config @@ -0,0 +1,6 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-samsung-bose" +CONFIG_SYS_PROMPT="Tegra20 (Bose) # " +# CONFIG_VIDEO_BRIDGE_SAMSUNG_CMC623 is not set +# CONFIG_BACKLIGHT_SAMSUNG_CMC623 is not set +# CONFIG_VIDEO_LCD_SONY_L4F00430T01 is not set +CONFIG_VIDEO_LCD_SAMSUNG_S6E63M0=y diff --git a/board/samsung/n1/n1.env b/board/samsung/n1/n1.env new file mode 100644 index 00000000000..e2b883dbc10 --- /dev/null +++ b/board/samsung/n1/n1.env @@ -0,0 +1,16 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu + +boot_block_size_r=0x80000 +boot_block_size=0x400 +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/board/siemens/capricorn/MAINTAINERS b/board/siemens/capricorn/MAINTAINERS index 9c8c7a6ecdc..6c253983cf0 100644 --- a/board/siemens/capricorn/MAINTAINERS +++ b/board/siemens/capricorn/MAINTAINERS @@ -1,6 +1,6 @@ CAPRICORN BOARD M: Alexander Sverdlin <alexander.sverdlin@siemens.com> -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> M: Walter Schweizer <walter.schweizer@siemens.com> S: Maintained F: arch/arm/dts/imx8-capricorn-cxg3.dts diff --git a/board/siemens/corvus/MAINTAINERS b/board/siemens/corvus/MAINTAINERS index 59176aae575..4471cf3ce3c 100644 --- a/board/siemens/corvus/MAINTAINERS +++ b/board/siemens/corvus/MAINTAINERS @@ -1,5 +1,5 @@ CORVUS BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/siemens/corvus/ F: include/configs/corvus.h diff --git a/board/siemens/smartweb/MAINTAINERS b/board/siemens/smartweb/MAINTAINERS index 51298ffb5d6..09d7667241c 100644 --- a/board/siemens/smartweb/MAINTAINERS +++ b/board/siemens/smartweb/MAINTAINERS @@ -1,5 +1,5 @@ SMARTWEB_HW BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/siemens/smartweb F: include/configs/smartweb.h diff --git a/board/siemens/taurus/MAINTAINERS b/board/siemens/taurus/MAINTAINERS index 74e3518e0d9..c17bd51a0de 100644 --- a/board/siemens/taurus/MAINTAINERS +++ b/board/siemens/taurus/MAINTAINERS @@ -1,5 +1,5 @@ TAURUS BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/siemens/taurus/ F: include/configs/taurus.h diff --git a/board/socrates/MAINTAINERS b/board/socrates/MAINTAINERS index 2b27a73c18c..d5571b0da4f 100644 --- a/board/socrates/MAINTAINERS +++ b/board/socrates/MAINTAINERS @@ -1,5 +1,5 @@ SOCRATES BOARD -M: Heiko Schocher <hs@denx.de> +M: Heiko Schocher <hs@nabladev.com> S: Maintained F: board/socrates/ F: include/configs/socrates.h diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 3dfa931b655..9dfe0bea5f1 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -126,19 +126,11 @@ int board_fit_config_name_match(const char *name) !strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { return 0; } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.2a") && - !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) { - switch (get_pcb_revision_from_eeprom()) { - case 'a': - case 'A': - return 0; - } + !strncmp(get_product_id_from_eeprom(), "VF7110A", 7)) { + return 0; } else if (!strcmp(name, "starfive/jh7110-starfive-visionfive-2-v1.3b") && - !strncmp(get_product_id_from_eeprom(), "VF7110", 6)) { - switch (get_pcb_revision_from_eeprom()) { - case 'b': - case 'B': - return 0; - } + !strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { + return 0; } return -EINVAL; diff --git a/board/starfive/visionfive2/starfive_visionfive2.c b/board/starfive/visionfive2/starfive_visionfive2.c index bfbb11a2ee7..6271974b9c7 100644 --- a/board/starfive/visionfive2/starfive_visionfive2.c +++ b/board/starfive/visionfive2/starfive_visionfive2.c @@ -59,20 +59,10 @@ static void set_fdtfile(void) fdtfile = "starfive/jh7110-milkv-mars.dtb"; } else if (!strncmp(get_product_id_from_eeprom(), "STAR64", 6)) { fdtfile = "starfive/jh7110-pine64-star64.dtb"; - } else if (!strncmp(get_product_id_from_eeprom(), "VF7110", 6)) { - switch (get_pcb_revision_from_eeprom()) { - case 'a': - case 'A': - fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; - break; - case 'b': - case 'B': - fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; - break; - default: - log_err("Unknown revision\n"); - return; - } + } else if (!strncmp(get_product_id_from_eeprom(), "VF7110A", 7)) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; + } else if (!strncmp(get_product_id_from_eeprom(), "VF7110B", 7)) { + fdtfile = "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; } else { log_err("Unknown product\n"); return; diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index 010e386e64d..17a44020bcf 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -275,7 +275,7 @@ static int prog_eeprom(unsigned int size) if (is_match_magic()) { printf("MAGIC ERROR, Please check the data@%p.\n", pbuf.buf); - return -1; + return CMD_RET_FAILURE; } ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, @@ -285,7 +285,7 @@ static int prog_eeprom(unsigned int size) if (ret) { printf("Get i2c bus:%d addr:%d fail.\n", CONFIG_SYS_EEPROM_BUS_NUM, CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; + return CMD_RET_FAILURE; } for (i = 0, p = (u8 *)pbuf.buf; i < size; ) { @@ -314,11 +314,11 @@ static int prog_eeprom(unsigned int size) if (ret) { has_been_read = -1; printf("Programming failed.\n"); - return -1; + return CMD_RET_FAILURE; } printf("Programming passed.\n"); - return 0; + return CMD_RET_SUCCESS; } /** diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c index a6d44f10db3..3f484646701 100644 --- a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c +++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c @@ -51,3 +51,22 @@ int rockchip_early_misc_init_r(void) return 0; } + +#define GPIO0B7_PU_EN BIT(15) + +void spl_board_init(void) +{ + /* + * GPIO0_B7 is routed to CAN TX. This SoC pin has a pull-down per default. + * So on power-up, we block the CAN bus with a dominant zero. We want to keep + * this blocking time to a minimum, so we want to get this pin high in SPL. + * + * The CAN driver in Linux disables the pull-down and sets the pin to + * output high. We don't have a CAN driver in U-Boot and don't need one, + * so we just use the easiest way to get the pin high, which is setting a + * pull-up. + */ + struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE; + + rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN); +} diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig index 0c566820158..b6943938391 100644 --- a/board/ti/am57xx/Kconfig +++ b/board/ti/am57xx/Kconfig @@ -9,6 +9,18 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "am57xx_evm" +config ENV_SOURCE_FILE + default "am57xx" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_DRA7XX_EVM + +config ENV_SOURCE_FILE + default "am57xx" + source "board/ti/common/Kconfig" endif diff --git a/board/ti/am57xx/am57xx.env b/board/ti/am57xx/am57xx.env new file mode 100644 index 00000000000..a7cbbced099 --- /dev/null +++ b/board/ti/am57xx/am57xx.env @@ -0,0 +1,162 @@ +#include <env/ti/ti_common.env> +#include <env/ti/mmc.env> +#include <env/ti/dfu.env> + +bootpart=0:2 +bootdir=/boot +get_name_kern= + if test $boot_fit -eq 1; then + setenv bootfile fitImage; + else + setenv bootfile zImage; + fi +get_fit_config=setexpr name_fit_config gsub "ti/omap/" "" ${fdtfile} +console=ttyS2,115200n8 +fdtfile=undefined +finduuid=part uuid mmc 0:2 uuid +usbtty=cdc_acm +vram=16M + +#if CONFIG_CMD_AVB +avb_verify=avb init 1; avb verify $slot_suffix; +#endif + +partitions=uuid_disk=${uuid_gpt_disk}; + name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader}; + name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs} + partitions_android= + uuid_disk=${uuid_gpt_disk}; + name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader}; + name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader}; + name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved}; + name=misc,size=128K,uuid=${uuid_gpt_misc}; + name=boot_a,size=20M,uuid=${uuid_gpt_boot_a}; + name=boot_b,size=20M,uuid=${uuid_gpt_boot_b}; + name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a}; + name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b}; + name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a}; + name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b}; + name=recovery,size=64M,uuid=${uuid_gpt_recovery}; + name=super,size=2560M,uuid=${uuid_gpt_super}; + name=metadata,size=16M,uuid=${uuid_gpt_metadata}; + name=userdata,size=-,uuid=${uuid_gpt_userdata} +optargs= +dofastboot=0 +emmc_android_boot= + setenv mmcdev 1; + mmc dev $mmcdev; + mmc rescan; +#if CONFIG_CMD_BCB +#if CONFIG_ANDROID_AB + if part number mmc 1 misc control_part_number; then + echo "misc partition number:${control_part_number};" + bcb ab_select slot_name mmc ${mmcdev}:${control_part_number}; + else + echo "misc partition not found;" + exit; + fi; + setenv slot_suffix _${slot_name}; +#endif +#endif +if bcb load CONFIG_FASTBOOT_FLASH_MMC_DEV misc; then + setenv ardaddr -; + if bcb test command = bootonce-bootloader; then + echo "Android: Bootloader boot..."; + bcb clear command; bcb store; + fastboot 1; + exit; + elif bcb test command = boot-recovery; then + echo "Android: Recovery boot..."; + setenv ardaddr $loadaddr; + setenv apart recovery; + else + echo "Android: Normal boot..."; + setenv ardaddr $loadaddr; + setenv apart boot${slot_suffix}; + fi; +else + echo "Warning: BCB is corrupted or does not exist"; + echo "Android: Normal boot..."; +fi; +setenv eval_bootargs setenv bootargs $bootargs; +run eval_bootargs; +setenv machid fe6; +#if CONFIG_CMD_AVB +if run avb_verify; then + echo "AVB verification OK."; + set bootargs $bootargs $avb_bootargs; +else + echo "AVB verification failed."; + exit; +fi; +#endif +#if CONFIG_CMD_BCB +#if CONFIG_ANDROID_AB +setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; +echo "A/B cmdline addition: ${bootargs_ab}"; +setenv bootargs ${bootargs} ${bootargs_ab}; +#endif +#endif +if part start mmc $mmcdev $apart boot_start; then + part size mmc $mmcdev $apart boot_size; + mmc read $loadaddr $boot_start $boot_size; + echo "Preparing FDT..."; + if test $board_name = am57xx_evm_reva3; then + echo " Reading DTBO partition..."; + part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; + part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; + mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; + echo " Reading DTB for AM57x EVM RevA3..."; + abootimg get dtb --index=0 dtb_start dtb_size; + cp.b $dtb_start $fdtaddr $dtb_size; + fdt addr $fdtaddr 0x80000; + echo " Applying DTBOs for AM57x EVM RevA3..."; + adtimg addr $dtboaddr; + adtimg get dt --index=0 dtbo0_addr dtbo0_size; + fdt apply $dtbo0_addr; + adtimg get dt --index=1 dtbo1_addr dtbo1_size; + fdt apply $dtbo1_addr; + elif test $board_name = beagle_x15_revc; then + echo " Reading DTB for Beagle X15 RevC..."; + abootimg get dtb --index=0 dtb_start dtb_size; + cp.b $dtb_start $fdtaddr $dtb_size; + fdt addr $fdtaddr 0x80000; + else + echo "Error: Android boot is not supported for $board_name"; + exit; + fi; + bootm $loadaddr $ardaddr $fdtaddr; +else + echo "$apart partition not found"; + exit; +fi; +get_overlay_mmc= + fdt address ${fdtaddr}; + fdt resize 0x100000; + for overlay in $name_overlays; + do; + load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay}; + fdt apply ${dtboaddr}; + done; +#if CONFIG_CMD_NET +static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off +nfsopts=nolock +rootpath=/export/rootfs +netloadimage=tftp ${loadaddr} ${bootfile} +netloadfdt=tftp ${fdtaddr} ${fdtfile} +netargs=setenv bootargs console=${console} ${optargs} + root=/dev/nfs + nfsroot=${serverip}:${rootpath},${nfsopts} rw + ip=dhcp +netboot=echo Booting from network ...; + setenv autoload no; + dhcp; + run netloadimage; + run netloadfdt; + run netargs; + bootz ${loadaddr} - ${fdtaddr} +#endif +#if CONFIG_MTD_RAW_NAND +#include <env/ti/nand.env> +#endif +dfu_bufsiz=0x10000 diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index fc0d87daae4..4091601d4f2 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -42,6 +42,7 @@ #include "../common/board_detect.h" #include "../common/cape_detect.h" +#include "../common/fdt_ops.h" #include "mux_data.h" #ifdef CONFIG_SUPPORT_EMMC_BOOT @@ -577,6 +578,18 @@ void do_board_detect(void) "Board: %s REV %s\n", bname, board_ti_get_rev()); } +static struct ti_fdt_map ti_omap_am57_evm_fdt_map[] = { + {"beagle_x15", "ti/omap/am57xx-beagle-x15.dtb"}, + {"beagle_x15_revb1", "ti/omap/am57xx-beagle-x15-revb1.dtb"}, + {"beagle_x15_revc", "ti/omap/am57xx-beagle-x15-revc.dtb"}, + {"am5729_beagleboneai", "ti/omap/am5729-beagleboneai.dtb"}, + {"am572x_idk", "ti/omap/am572x-idk.dtb"}, + {"am574x_idk", "ti/omap/am574x-idk.dtb"}, + {"am57xx_evm", "ti/omap/am57xx-beagle-x15.dtb"}, + {"am57xx_evm_reva3", "ti/omap/am57xx-beagle-x15.dtb"}, + {"am571x_idk", "ti/omap/am571x-idk.dtb"}, +}; + static void setup_board_eeprom_env(void) { char *name = "beagle_x15"; @@ -614,6 +627,7 @@ static void setup_board_eeprom_env(void) invalid_eeprom: set_board_info_env(name); + ti_set_fdt_env(name, ti_omap_am57_evm_fdt_map); } #endif /* CONFIG_XPL_BUILD */ diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 98d63e14e29..0966db2bb62 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -38,6 +38,7 @@ #include "mux_data.h" #include "../common/board_detect.h" +#include "../common/fdt_ops.h" #define board_is_dra76x_evm() board_ti_is("DRA76/7x") #define board_is_dra74x_evm() board_ti_is("5777xCPU") @@ -665,6 +666,15 @@ static int device_okay(const char *path) } #endif +static struct ti_fdt_map ti_omap_dra7_evm_fdt_map[] = { + {"omap5_uevm", "ti/omap/omap5-uevm.dtb"}, + {"dra7xx", "ti/omap/dra7-evm.dtb"}, + {"dra72x-revc", "ti/omap/dra72-evm-revc.dtb"}, + {"dra72x", "ti/omap/dra72-evm.dtb"}, + {"dra71x", "ti/omap/dra71-evm.dtb"}, + {"dra76x_acd", "ti/omap/dra76-evm.dtb"}, +}; + int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -686,6 +696,7 @@ int board_late_init(void) } set_board_info_env(name); + ti_set_fdt_env(name, ti_omap_dra7_evm_fdt_map); /* * Default FIT boot on HS devices. Non FIT images are not allowed diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index c52ba1870b0..68acd8955ae 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS imply SPL_RAM_DEVICE imply CMD_SBI imply CMD_PING - imply OF_HAS_PRIOR_STAGE source "board/xilinx/Kconfig" diff --git a/board/xunlong/orangepi-5-ultra-rk3588/Kconfig b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig new file mode 100644 index 00000000000..43fc96b04c0 --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ORANGEPI_5_ULTRA_RK3588 + +config SYS_BOARD + default "orangepi-5-ultra-rk3588" + +config SYS_VENDOR + default "xunlong" + +config SYS_CONFIG_NAME + default "evb_rk3588" + +endif diff --git a/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS new file mode 100644 index 00000000000..be9c93f6b9d --- /dev/null +++ b/board/xunlong/orangepi-5-ultra-rk3588/MAINTAINERS @@ -0,0 +1,6 @@ +ORANGEPI-5-RK3588-ULTRA +M: Niu Zhihong <zhihong@nzhnb.com> +S: Maintained +F: board/xunlong/orangepi-5-rk3588-ultra +F: configs/orangepi-5-ultra-rk3588_defconfig +F: arch/arm/dts/rk3588-orangepi-5-ultra.dts diff --git a/boot/Kconfig b/boot/Kconfig index 2ff6f003738..2993cd7f9ba 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -869,7 +869,6 @@ config EXPO config BOOTMETH_RAUC bool "Bootdev support for RAUC A/B systems" depends on CMDLINE - select BOOTMETH_GLOBAL select HUSH_PARSER help Enables support for booting RAUC A/B systems from MMC devices. This @@ -1057,7 +1056,7 @@ config SYS_BOOTM_LEN hex "Maximum size of a decompresed OS image" depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \ LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT - default 0x4000000 if PPC || ARM64 + default 0x4000000 if PPC || ARM64 || RISCV default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 default 0x800000 help diff --git a/boot/bootmeth_rauc.c b/boot/bootmeth_rauc.c index cc6180221ed..81a73046e83 100644 --- a/boot/bootmeth_rauc.c +++ b/boot/bootmeth_rauc.c @@ -52,6 +52,18 @@ struct distro_rauc_priv { struct distro_rauc_slot **slots; }; +static void distro_rauc_priv_free(struct distro_rauc_priv *priv) +{ + int i; + + for (i = 0; priv->slots[i]; i++) { + free(priv->slots[i]->name); + free(priv->slots[i]); + } + free(priv->slots); + free(priv); +} + static struct distro_rauc_slot *get_slot(struct distro_rauc_priv *priv, const char *slot_name) { @@ -187,13 +199,8 @@ static int distro_rauc_read_bootflow(struct udevice *dev, struct bootflow *bflow ret = distro_rauc_scan_parts(bflow); if (ret < 0) { - for (i = 0; priv->slots[i]->name; i++) { - free(priv->slots[i]->name); - free(priv->slots[i]); - } - free(priv); + distro_rauc_priv_free(priv); free(boot_order_copy); - bflow->bootmeth_priv = NULL; return ret; } @@ -402,6 +409,8 @@ static int distro_rauc_boot(struct udevice *dev, struct bootflow *bflow) if (ret) return log_msg_ret("boot", ret); + distro_rauc_priv_free(priv); + return 0; } @@ -410,7 +419,7 @@ static int distro_rauc_bootmeth_bind(struct udevice *dev) struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev); plat->desc = "RAUC distro boot from MMC"; - plat->flags = BOOTMETHF_GLOBAL; + plat->flags = BOOTMETHF_ANY_PART; return 0; } diff --git a/cmd/Kconfig b/cmd/Kconfig index b3b5be1ea79..29de857ba7c 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1343,6 +1343,13 @@ config CMD_I2C help I2C support. +config CMD_I3C + bool "i3c" + depends on I3C + help + Enable command to list i3c devices connected to the i3c controller + and perform read and write on the connected i3c devices. + config CMD_W1 depends on W1 default y if W1 @@ -2110,7 +2117,7 @@ config CMD_DHCP config CMD_DNS bool "dns" - select PROT_DNS_LWIP if NET_LWIP + select DNS help Lookup the IP of a hostname diff --git a/cmd/Makefile b/cmd/Makefile index 12e948fd1b9..36e79cc3c28 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_CMD_GPIO) += gpio.o obj-$(CONFIG_CMD_HISTORY) += history.o obj-$(CONFIG_CMD_HVC) += smccc.o obj-$(CONFIG_CMD_I2C) += i2c.o +obj-$(CONFIG_CMD_I3C) += i3c.o obj-$(CONFIG_CMD_IOTRACE) += iotrace.o obj-$(CONFIG_CMD_HASH) += hash.o obj-$(CONFIG_CMD_IDE) += ide.o disk.o diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index ae9e1923eac..20c8c97f0cd 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -46,6 +46,7 @@ void bdinfo_print_num_ll(const char *name, unsigned long long value) static void print_eth(void) { const int idx = eth_get_dev_index(); + char ipstr[] = "ipaddr\0\0"; uchar enetaddr[6]; char name[10]; int ret; @@ -62,7 +63,11 @@ static void print_eth(void) printf("%-12s= (not set)\n", name); else printf("%-12s= %pM\n", name, enetaddr); - printf("IP addr = %s\n", env_get("ipaddr")); + + if (idx > 0) + sprintf(ipstr, "ipaddr%d", idx); + + printf("IP addr = %s\n", env_get(ipstr)); } void bdinfo_print_mhz(const char *name, unsigned long hz) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 8e8752127ed..b8f5bb35950 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -136,22 +136,39 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, { efi_status_t ret; char *p; - void *fdt, *image_buf; - unsigned long addr, size; + void *fdt, *initrd = NULL, *image_buf; + unsigned long addr, size, rd_len = 0, fdt_addr = 0; void *image_addr; size_t image_size; + int fdt_arg = 2; if (argc < 2) return CMD_RET_USAGE; if (argc > 2) { - uintptr_t fdt_addr; + ulong rd_addr = 0; + char *end = strchr(argv[2], ':'); - fdt_addr = hextoul(argv[2], NULL); + if (end) { + rd_addr = hextoul(argv[2], NULL); + if (!rd_addr) + return CMD_RET_USAGE; + + rd_len = hextoul(++end, NULL); + initrd = map_sysmem(rd_addr, rd_len); + ++fdt_arg; + } + } + + if (argc > fdt_arg + 1) + return CMD_RET_USAGE; + if (argc == fdt_arg + 1) + fdt_addr = hextoul(argv[fdt_arg], NULL); + + if (fdt_addr) fdt = map_sysmem(fdt_addr, 0); - } else { + else fdt = EFI_FDT_USE_INTERNAL; - } if (IS_ENABLED(CONFIG_CMD_BOOTEFI_BOOTMGR) && !strcmp(argv[1], "bootmgr")) { @@ -215,7 +232,7 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, } } - ret = efi_binary_run(image_buf, size, fdt, NULL, 0); + ret = efi_binary_run(image_buf, size, fdt, initrd, rd_len); if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; @@ -224,7 +241,7 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, } U_BOOT_LONGHELP(bootefi, - "<image address>[:<image size>] [<fdt address>]\n" + "<image address>[:<size>] [<initrd address>:<size>] [<fdt address>]\n" " - boot EFI payload\n" #ifdef CONFIG_CMD_BOOTEFI_HELLO "bootefi hello\n" diff --git a/cmd/i2c.c b/cmd/i2c.c index f0aae93073f..e021067e68a 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -299,7 +299,8 @@ static int do_i2c_write(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { uint chip; - uint devaddr, length; + uint devaddr; + int length; int alen; u_char *memaddr; int ret; diff --git a/cmd/i3c.c b/cmd/i3c.c new file mode 100644 index 00000000000..08957f4d447 --- /dev/null +++ b/cmd/i3c.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <bootretry.h> +#include <cli.h> +#include <command.h> +#include <console.h> +#include <dm.h> +#include <dw-i3c.h> +#include <edid.h> +#include <errno.h> +#include <hexdump.h> +#include <log.h> +#include <malloc.h> +#include <asm/byteorder.h> +#include <linux/compiler.h> +#include <linux/delay.h> +#include <u-boot/crc.h> +#include <linux/i3c/master.h> +#include <linux/printk.h> +#include <linux/types.h> + +static struct udevice *currdev; +static struct udevice *prevdev; +static struct dw_i3c_master *master; + +static void low_to_high_bytes(void *data, size_t size) +{ + u8 *byte_data = data; + size_t start = 0; + size_t end = size - 1; + + while (start < end) { + u8 temp = byte_data[start]; + + byte_data[start] = byte_data[end]; + byte_data[end] = temp; + start++; + end--; + } +} + +static int handle_i3c_select(const char *name) +{ + struct uclass *uc; + struct udevice *dev_list; + int ret = uclass_get_device_by_name(UCLASS_I3C, name, &currdev); + + if (ret) { + currdev = prevdev; + if (!currdev) { + ret = uclass_get(UCLASS_I3C, &uc); + if (ret) + return CMD_RET_FAILURE; + + uclass_foreach_dev(dev_list, uc) + printf("%s (%s)\n", dev_list->name, dev_list->driver->name); + + printf("i3c: Host controller not initialized: %s\n", name); + return CMD_RET_FAILURE; + } + } else { + master = dev_get_priv(currdev); + printf("i3c: Current controller: %s\n", currdev->name); + prevdev = currdev; + } + + return CMD_RET_SUCCESS; +} + +static int handle_i3c_list(void) +{ + struct uclass *uc; + struct udevice *dev_list; + int ret = uclass_get(UCLASS_I3C, &uc); + + if (ret) + return CMD_RET_FAILURE; + + uclass_foreach_dev(dev_list, uc) + printf("%s (%s)\n", dev_list->name, dev_list->driver->name); + + return CMD_RET_SUCCESS; +} + +static int handle_i3c_current(void) +{ + if (!currdev) + printf("i3c: No current controller selected\n"); + else + printf("i3c: Current controller: %s\n", currdev->name); + + return CMD_RET_SUCCESS; +} + +static int handle_i3c_device_list(void) +{ + if (!master) { + printf("i3c: No controller active\n"); + return CMD_RET_FAILURE; + } + + for (int i = 0; i < master->num_i3cdevs; i++) { + struct i3c_device_info *info = &master->i3cdev[i]->info; + + printf("Device %d:\n", i); + printf(" Static Address : 0x%02X\n", info->static_addr); + printf(" Dynamic Address : 0x%X\n", info->dyn_addr); + printf(" PID : %016llx\n", info->pid); + printf(" BCR : 0x%X\n", info->bcr); + printf(" DCR : 0x%X\n", info->dcr); + printf(" Max Read DS : 0x%X\n", info->max_read_ds); + printf(" Max Write DS : 0x%X\n", info->max_write_ds); + printf("\n"); + } + + return CMD_RET_SUCCESS; +} + +static int handle_i3c_write(int argc, char *const argv[]) +{ + u32 mem_addr, num_bytes, dev_num_val; + u8 device_num; + u8 *data; + int ret; + + if (argc < 5) + return CMD_RET_USAGE; + + if (!currdev) { + printf("i3c: No I3C controller selected\n"); + return CMD_RET_FAILURE; + } + + mem_addr = hextoul(argv[2], NULL); + num_bytes = hextoul(argv[3], NULL); + dev_num_val = hextoul(argv[4], NULL); + + if (num_bytes == 0 || num_bytes > 4) { + printf("i3c: Length must be between 1 and 4\n"); + return CMD_RET_USAGE; + } + + if (dev_num_val > 0xFF) { + printf("i3c: Device number 0x%x exceeds valid u8 range\n", dev_num_val); + return CMD_RET_USAGE; + } + + device_num = dev_num_val; + data = malloc(num_bytes); + + if (!data) { + printf("i3c: Memory allocation failed\n"); + return -ENOMEM; + } + + memcpy(data, (void *)(uintptr_t)mem_addr, num_bytes); + low_to_high_bytes(data, num_bytes); + + ret = dm_i3c_write(currdev, device_num, data, num_bytes); + + if (ret) + printf("i3c: Write failed: %d\n", ret); + + free(data); + return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +static int handle_i3c_read(int argc, char *const argv[]) +{ + u32 mem_addr, read_len, dev_num_val; + u8 device_num; + u8 *rdata; + int ret; + + if (argc < 5) + return CMD_RET_USAGE; + + if (!currdev) { + printf("i3c: No I3C controller selected\n"); + return CMD_RET_FAILURE; + } + + mem_addr = hextoul(argv[2], NULL); + read_len = hextoul(argv[3], NULL); + dev_num_val = hextoul(argv[4], NULL); + + if (read_len == 0) { + printf("i3c: Read length must be greater than 0\n"); + return CMD_RET_USAGE; + } + + if (dev_num_val > 0xFF) { + printf("i3c: Device number 0x%x exceeds valid u8 range\n", dev_num_val); + return CMD_RET_USAGE; + } + + device_num = dev_num_val; + rdata = malloc(read_len); + + if (!rdata) { + printf("i3c: Memory allocation failed\n"); + return -ENOMEM; + } + + ret = dm_i3c_read(currdev, device_num, rdata, read_len); + + if (ret) { + printf("i3c: Read failed: %d\n", ret); + free(rdata); + return CMD_RET_FAILURE; + } + + memcpy((void *)(uintptr_t)mem_addr, rdata, read_len); + print_hex_dump("i3c read: ", DUMP_PREFIX_OFFSET, 16, 1, + (void *)(uintptr_t)mem_addr, read_len, false); + + free(rdata); + return CMD_RET_SUCCESS; +} + +static bool is_i3c_subcommand(const char *cmd) +{ + return !strcmp(cmd, "write") || + !strcmp(cmd, "read") || + !strcmp(cmd, "device_list") || + !strcmp(cmd, "list") || + !strcmp(cmd, "current"); +} + +static int do_i3c(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + + const char *subcmd = argv[1]; + + if (!is_i3c_subcommand(subcmd)) + return handle_i3c_select(subcmd); + + if (!currdev) { + printf("i3c: No I3C controller selected\n"); + return CMD_RET_FAILURE; + } + + if (!strcmp(subcmd, "list")) + return handle_i3c_list(); + else if (!strcmp(subcmd, "current")) + return handle_i3c_current(); + else if (!strcmp(subcmd, "device_list")) + return handle_i3c_device_list(); + else if (!strcmp(subcmd, "write")) + return handle_i3c_write(argc, argv); + else if (!strcmp(subcmd, "read")) + return handle_i3c_read(argc, argv); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + i3c, 5, 1, do_i3c, + "access the system i3c", + "i3c write <mem_addr> <length> <device_number> - write from memory to device\n" + "i3c read <mem_addr> <length> <device_number> - read from device to memory\n" + "i3c device_list - List valid target devices\n" + "i3c <host_controller> - Select i3c controller\n" + "i3c list - List all available i3c controllers\n" + "i3c current - Show current i3c controller" +); diff --git a/cmd/lwip/dns.c b/cmd/lwip/dns.c index b5fccc7433e..3eb698b3f82 100644 --- a/cmd/lwip/dns.c +++ b/cmd/lwip/dns.c @@ -2,115 +2,7 @@ /* Copyright (C) 2024 Linaro Ltd. */ #include <command.h> -#include <console.h> -#include <env.h> -#include <lwip/dns.h> -#include <lwip/timeouts.h> #include <net.h> -#include <time.h> U_BOOT_CMD(dns, 3, 1, do_dns, "lookup the IP of a hostname", "hostname [envvar]"); - -#define DNS_RESEND_MS 1000 -#define DNS_TIMEOUT_MS 10000 - -struct dns_cb_arg { - ip_addr_t host_ipaddr; - const char *var; - bool done; -}; - -static void do_dns_tmr(void *arg) -{ - dns_tmr(); -} - -static void dns_cb(const char *name, const ip_addr_t *ipaddr, void *arg) -{ - struct dns_cb_arg *dns_cb_arg = arg; - char *ipstr = ip4addr_ntoa(ipaddr); - - dns_cb_arg->done = true; - - if (!ipaddr) { - printf("DNS: host not found\n"); - dns_cb_arg->host_ipaddr.addr = 0; - return; - } - - dns_cb_arg->host_ipaddr.addr = ipaddr->addr; - - if (dns_cb_arg->var) - env_set(dns_cb_arg->var, ipstr); -} - -static int dns_loop(struct udevice *udev, const char *name, const char *var) -{ - struct dns_cb_arg dns_cb_arg = { }; - struct netif *netif; - ip_addr_t ipaddr; - ulong start; - int ret; - - dns_cb_arg.var = var; - - netif = net_lwip_new_netif(udev); - if (!netif) - return CMD_RET_FAILURE; - - if (net_lwip_dns_init()) { - net_lwip_remove_netif(netif); - return CMD_RET_FAILURE; - } - - dns_cb_arg.done = false; - - ret = dns_gethostbyname(name, &ipaddr, dns_cb, &dns_cb_arg); - - if (ret == ERR_OK) { - dns_cb(name, &ipaddr, &dns_cb_arg); - } else if (ret == ERR_INPROGRESS) { - start = get_timer(0); - sys_timeout(DNS_RESEND_MS, do_dns_tmr, NULL); - do { - net_lwip_rx(udev, netif); - if (dns_cb_arg.done) - break; - if (ctrlc()) { - printf("\nAbort\n"); - break; - } - } while (get_timer(start) < DNS_TIMEOUT_MS); - sys_untimeout(do_dns_tmr, NULL); - } - - net_lwip_remove_netif(netif); - - if (dns_cb_arg.done && dns_cb_arg.host_ipaddr.addr != 0) { - if (!var) - printf("%s\n", ipaddr_ntoa(&ipaddr)); - return CMD_RET_SUCCESS; - } - - return CMD_RET_FAILURE; -} - -int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - char *name; - char *var = NULL; - - if (argc == 1 || argc > 3) - return CMD_RET_USAGE; - - name = argv[1]; - - if (argc == 3) - var = argv[2]; - - if (net_lwip_eth_start() < 0) - return CMD_RET_FAILURE; - - return dns_loop(eth_get_dev(), name, var); -} diff --git a/cmd/lwip/ping.c b/cmd/lwip/ping.c index 87f8e958e48..6d090fc530d 100644 --- a/cmd/lwip/ping.c +++ b/cmd/lwip/ping.c @@ -170,6 +170,7 @@ int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (net_lwip_dns_resolve(argv[1], &addr)) return CMD_RET_USAGE; + net_try_count = 1; restart: if (net_lwip_eth_start() < 0 || ping_loop(eth_get_dev(), &addr) < 0) { if (net_start_again() == 0) diff --git a/cmd/lwip/sntp.c b/cmd/lwip/sntp.c index ae02bb11040..608345c873b 100644 --- a/cmd/lwip/sntp.c +++ b/cmd/lwip/sntp.c @@ -79,7 +79,6 @@ static int sntp_loop(struct udevice *udev, ip_addr_t *srvip) sys_timeout(SNTP_TIMEOUT, no_response, NULL); while (sntp_state == NOT_DONE) { net_lwip_rx(udev, netif); - sys_check_timeouts(); if (ctrlc()) { printf("\nAbort\n"); sntp_state = ABORTED; diff --git a/cmd/meminfo.c b/cmd/meminfo.c index acdb38dcba0..aa3b5bafe17 100644 --- a/cmd/meminfo.c +++ b/cmd/meminfo.c @@ -93,7 +93,7 @@ static int do_meminfo(struct cmd_tbl *cmdtp, int flag, int argc, print_region("stack", stk_bot, CONFIG_STACK_SIZE, &upto); if (IS_ENABLED(CONFIG_LMB)) show_lmb(lmb_get(), &upto); - print_region("free", gd->ram_base, upto, &upto); + print_region("free", gd->ram_base, upto - gd->ram_base, &upto); return 0; } diff --git a/cmd/mtd.c b/cmd/mtd.c index c25997cfb24..2520b89eed2 100644 --- a/cmd/mtd.c +++ b/cmd/mtd.c @@ -17,6 +17,7 @@ #include <malloc.h> #include <mapmem.h> #include <mtd.h> +#include <time.h> #include <dm/devres.h> #include <linux/err.h> @@ -466,8 +467,9 @@ static int mtd_special_write_oob(struct mtd_info *mtd, u64 off, static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - bool dump, read, raw, woob, write_empty_pages, has_pages = false; + bool dump, read, raw, woob, benchmark, write_empty_pages, has_pages = false; u64 start_off, off, len, remaining, default_len; + unsigned long bench_start, bench_end; struct mtd_oob_ops io_op = {}; uint user_addr = 0, npages; const char *cmd = argv[0]; @@ -490,6 +492,7 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc, read = dump || !strncmp(cmd, "read", 4); raw = strstr(cmd, ".raw"); woob = strstr(cmd, ".oob"); + benchmark = strstr(cmd, ".benchmark"); write_empty_pages = !has_pages || strstr(cmd, ".dontskipff"); argc -= 2; @@ -559,6 +562,9 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc, led_activity_blink(); + if (benchmark) + bench_start = timer_get_us(); + /* Loop over the pages to do the actual read/write */ while (remaining) { /* Skip the block if it is bad */ @@ -586,6 +592,13 @@ static int do_mtd_io(struct cmd_tbl *cmdtp, int flag, int argc, io_op.oobbuf += io_op.oobretlen; } + if (benchmark && bench_start) { + bench_end = timer_get_us(); + printf("%s speed: %lukiB/s\n", + read ? "Read" : "Write", + ((io_op.len * 1000000) / (bench_end - bench_start)) / 1024); + } + led_activity_off(); if (!ret && dump) diff --git a/cmd/nand.c b/cmd/nand.c index 2f785deeb7f..b5678b0a008 100644 --- a/cmd/nand.c +++ b/cmd/nand.c @@ -37,6 +37,7 @@ #include <asm/byteorder.h> #include <jffs2/jffs2.h> #include <nand.h> +#include <display_options.h> #include "legacy-mtd-utils.h" @@ -159,7 +160,7 @@ free_memory: } static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob, - int repeat) + int ecc, int repeat) { int i; u_char *datbuf, *oobbuf, *p; @@ -191,39 +192,30 @@ static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob, ops.oobbuf = oobbuf; ops.len = mtd->writesize; ops.ooblen = mtd->oobsize; - ops.mode = MTD_OPS_RAW; + if (ecc) + ops.mode = MTD_OPS_PLACE_OOB; + else + ops.mode = MTD_OPS_RAW; i = mtd_read_oob(mtd, addr, &ops); if (i < 0) { - printf("Error (%d) reading page %08lx\n", i, off); + printf("Error reading page at offset %08lx, %d %s\n", + off, i, i == -EUCLEAN ? "correctable" : + "uncorrectable, dumping raw data"); ret = 1; - goto free_all; } - printf("Page %08lx dump:\n", off); + printf("\nPage at offset %08lx dump:\n", off); if (!only_oob) { - i = mtd->writesize >> 4; + i = mtd->writesize; p = datbuf; - - while (i--) { - printf("\t%02x %02x %02x %02x %02x %02x %02x %02x" - " %02x %02x %02x %02x %02x %02x %02x %02x\n", - p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], - p[8], p[9], p[10], p[11], p[12], p[13], p[14], - p[15]); - p += 16; - } + print_buffer(off, p, 1, i, 16); } - puts("OOB:\n"); - i = mtd->oobsize >> 3; + puts("\nOOB:\n"); + i = mtd->oobsize; p = oobbuf; - while (i--) { - printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n", - p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); - p += 8; - } + print_buffer(0, p, 1, i, 8); -free_all: free(oobbuf); free_dat: free(datbuf); @@ -412,7 +404,7 @@ int do_nand_env_oob(struct cmd_tbl *cmdtp, int argc, char *const argv[]) } ops.datbuf = NULL; - ops.mode = MTD_OOB_AUTO; + ops.mode = MTD_OPS_AUTO_OOB; ops.ooboffs = 0; ops.ooblen = ENV_OFFSET_SIZE; ops.oobbuf = (void *) oob_buf; @@ -708,11 +700,19 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int argc, } if (strncmp(cmd, "dump", 4) == 0) { + int only_oob, ecc; + if (argc < 3) goto usage; + only_oob = !strcmp(&cmd[4], ".oob") || !strcmp(&cmd[4], ".ecc.oob") || + !strcmp(&cmd[4], ".oob.ecc"); + + ecc = !strcmp(&cmd[4], ".ecc") || !strcmp(&cmd[4], ".ecc.oob") || + !strcmp(&cmd[4], ".oob.ecc"); + off = (int)hextoul(argv[2], NULL); - ret = nand_dump(mtd, off, !strcmp(&cmd[4], ".oob"), repeat); + ret = nand_dump(mtd, off, only_oob, ecc, repeat); return ret == 0 ? 1 : 0; } @@ -1026,8 +1026,8 @@ U_BOOT_LONGHELP(nand, "nand write - addr off|partition size\n" " read/write 'size' bytes starting at offset 'off'\n" " to/from memory address 'addr', skipping bad blocks.\n" - "nand read.raw - addr off|partition [count]\n" - "nand write.raw[.noverify] - addr off|partition [count]\n" + "nand read.raw - addr off|partition [pages]\n" + "nand write.raw[.noverify] - addr off|partition [pages]\n" " Use read.raw/write.raw to avoid ECC and access the flash as-is.\n" #ifdef CONFIG_CMD_NAND_TRIMFFS "nand write.trimffs - addr off|partition size\n" @@ -1042,7 +1042,7 @@ U_BOOT_LONGHELP(nand, "nand erase.part [clean] partition - erase entire mtd partition'\n" "nand erase.chip [clean] - erase entire chip'\n" "nand bad - show bad blocks\n" - "nand dump[.oob] off - dump page\n" + "nand dump[.oob][.ecc] off - dump raw (default) or ecc corrected page at offset\n" #ifdef CONFIG_CMD_NAND_WATCH "nand watch <off> <size> - check an area for bitflips\n" "nand watch.part <part> - check a partition for bitflips\n" diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ab05536bd02..f34b96efc02 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1141,7 +1141,7 @@ config SPL_DM_SPI config SPL_DM_SPI_FLASH bool "Support SPI DM FLASH drivers in SPL" - depends on SPL_DM + depends on SPL_DM_SPI help Enable support for SPI DM flash drivers in SPL. diff --git a/common/spl/spl.c b/common/spl/spl.c index ed443c645a7..55ad497c86d 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -278,8 +278,8 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) } else { spl_image->entry_point = CONFIG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; - log_debug("Default load addr %x (u_boot_pos=%lx)\n", - CONFIG_TEXT_BASE, u_boot_pos); + log_debug("Default load addr %lx (u_boot_pos=%lx)\n", + spl_image->load_addr, u_boot_pos); } spl_image->os = IH_OS_U_BOOT; spl_image->name = xpl_name(xpl_next_phase()); diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 00dbd3011f0..c2b188371c2 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -80,7 +80,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, spl_load_init(&load, spl_spi_fit_read, flash, 1); #if CONFIG_IS_ENABLED(OS_BOOT) - if (spl_start_uboot()) { + if (!spl_start_uboot()) { int err = spl_load(spl_image, bootdev, &load, 0, CONFIG_SYS_SPI_KERNEL_OFFS); diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index f885fc01e6e..da0bb6683d0 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_I2C1_ENABLE=y +CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index c37c49ccbb1..7460548461d 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -1,8 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun8i-v3s-licheepi-zero" CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y -CONFIG_DRAM_CLK=360 # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_NO_NET=y diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 467d61d73df..e87782005f1 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -7,7 +7,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig index 66b809d2376..f1d88f8560f 100644 --- a/configs/ae350_rv32_falcon_defconfig +++ b/configs/ae350_rv32_falcon_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig index a2f8d4cd236..2355bac5019 100644 --- a/configs/ae350_rv32_falcon_xip_defconfig +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 098cf7686d6..6655cbd4a96 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 23927888c87..44a6b6534b8 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 75eb0618454..15f3b5c378b 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -7,7 +7,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 932739e5dec..78b9fc439ac 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -6,7 +6,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig index c9417175ce7..81bebb1a1d4 100644 --- a/configs/ae350_rv64_falcon_defconfig +++ b/configs/ae350_rv64_falcon_defconfig @@ -8,7 +8,6 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig index e072f7c2ae9..8e1b8e20052 100644 --- a/configs/ae350_rv64_falcon_xip_defconfig +++ b/configs/ae350_rv64_falcon_xip_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 83ce28077f0..7950074642e 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -8,7 +8,6 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 5ad1751686c..d5882af1de1 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 5ec2cba670b..46ce063c484 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -6,7 +6,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y diff --git a/configs/avaota-a1_defconfig b/configs/avaota-a1_defconfig index 55457edd3b3..a4582c00d5b 100644 --- a/configs/avaota-a1_defconfig +++ b/configs/avaota-a1_defconfig @@ -22,6 +22,8 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_PHY_REALTEK=y +CONFIG_SUN8I_EMAC=y CONFIG_REGULATOR_AXP=y CONFIG_AXP717_POWER=y CONFIG_AXP_I2C_ADDRESS=0x35 diff --git a/configs/chagall_defconfig b/configs/chagall_defconfig new file mode 100644 index 00000000000..3acb7d53727 --- /dev/null +++ b/configs/chagall_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="chagall" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra30-pegatron-chagall" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA30=y +CONFIG_TARGET_CHAGALL=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2084 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra30 (Chagall) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_TPS65910=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_TPS65911=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_TPS65910=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_LVDS_CODEC=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index dfb97a3d302..b49fc80167b 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="coreboot" CONFIG_PRE_CON_BUF_ADDR=0x100000 CONFIG_VENDOR_COREBOOT=y CONFIG_TARGET_COREBOOT=y +CONFIG_X86_LOAD_FROM_32_BIT=y CONFIG_SYS_MONITOR_BASE=0x01110000 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index b4066d87460..8f9659ce050 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -19,7 +19,6 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_FULL=y -CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y @@ -30,6 +29,8 @@ CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y # CONFIG_CMD_DATE is not set CONFIG_CMD_RTC=y @@ -41,7 +42,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 -CONFIG_NO_NET=y +CONFIG_NET_LWIP=y CONFIG_CLK_EXYNOS850=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y @@ -64,8 +65,13 @@ CONFIG_SYSRESET=y CONFIG_SYSRESET_SYSCON=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_SMSC95XX=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Samsung" CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 diff --git a/configs/eDPU_defconfig b/configs/eDPU_defconfig index b50e3815178..0b7815c78a3 100644 --- a/configs/eDPU_defconfig +++ b/configs/eDPU_defconfig @@ -51,7 +51,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y -CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MV=y diff --git a/configs/gameforce-ace-rk3588s_defconfig b/configs/gameforce-ace-rk3588s_defconfig new file mode 100644 index 00000000000..ec725a8df40 --- /dev/null +++ b/configs/gameforce-ace-rk3588s_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588s-gameforce-ace" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-gameforce-ace.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NO_NET=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_BUTTON_GPIO=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +# CONFIG_RAM_ROCKCHIP_DEBUG is not set +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3576_defconfig b/configs/generic-rk3576_defconfig new file mode 100644 index 00000000000..5e25653820c --- /dev/null +++ b/configs/generic-rk3576_defconfig @@ -0,0 +1,50 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rk3576-generic" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-generic.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NO_NET=y +# CONFIG_ADC is not set +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig index ed2f936b324..dfa8efabe6b 100644 --- a/configs/generic-rk3588_defconfig +++ b/configs/generic-rk3588_defconfig @@ -53,7 +53,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_USBDP=y CONFIG_SPL_PINCTRL=y CONFIG_SPL_RAM=y CONFIG_BAUDRATE=1500000 diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index f5bb28cb0c7..19fb14887c6 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN3=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a774a1-hihope-rzg2m-ex" diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index f088aec8716..8e8259f291d 100644 --- a/configs/ibex-ast2700_defconfig +++ b/configs/ibex-ast2700_defconfig @@ -15,7 +15,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_TEXT_BASE=0x14bc0080 CONFIG_SPL_BSS_START_ADDR=0x14bd7800 CONFIG_SPL_BSS_MAX_SIZE=0x800 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x83000000 CONFIG_SPL_SIZE_LIMIT=0x16000 CONFIG_SPL=y diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 6210be64672..af149128ed4 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -92,6 +92,7 @@ CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK_IMX93=y CONFIG_CLK_IMX93=y CONFIG_DFU_MMC=y diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig index 73818a82627..542b71f5c07 100644 --- a/configs/imx95_19x19_evk_defconfig +++ b/configs/imx95_19x19_evk_defconfig @@ -1,152 +1 @@ -CONFIG_ARM=y -CONFIG_ARCH_IMX9=y -CONFIG_TEXT_BASE=0x90200000 -CONFIG_SYS_MALLOC_LEN=0x2000000 -CONFIG_SYS_MALLOC_F_LEN=0x10000 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SOURCE_FILE="imx95_19x19_evk" -CONFIG_SF_DEFAULT_SPEED=40000000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x700000 -CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/scmi/imximage.cfg" -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="freescale/imx95-19x19-evk" -CONFIG_TARGET_IMX95_19X19_EVK=y -CONFIG_OF_LIBFDT_OVERLAY=y -CONFIG_SYS_MONITOR_LEN=524288 -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL_DRIVERS_MISC=y -CONFIG_SPL_TEXT_BASE=0x20480000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x204d6000 -CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x90400000 -CONFIG_SPL=y -CONFIG_SPL_RECOVER_DATA_SECTION=y -CONFIG_PCI=y -CONFIG_SYS_MEMTEST_START=0x90000000 -CONFIG_SYS_MEMTEST_END=0xA0000000 -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_SYSTEM_SETUP=y -CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" -CONFIG_DEFAULT_FDT_FILE="imx95-19x19-evk.dtb" -CONFIG_SYS_CBSIZE=2048 -CONFIG_SYS_PBSIZE=2074 -CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_BOARD_INIT is not set -CONFIG_BOARD_LATE_INIT=y -CONFIG_PCI_INIT_R=y -CONFIG_SPL_MAX_SIZE=0x20000 -CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_LOAD_IMX_CONTAINER=y -CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg" -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 -CONFIG_SPL_SYS_MMCSD_RAW_MODE=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 -CONFIG_SPL_I2C=y -CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_POWER=y -CONFIG_SPL_WATCHDOG=y -CONFIG_SYS_PROMPT="u-boot=> " -CONFIG_CMD_ERASEENV=y -CONFIG_CMD_NVEDIT_EFI=y -CONFIG_CRC32_VERIFY=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DFU=y -CONFIG_CMD_FUSE=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_GPT=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_POWEROFF=y -CONFIG_CMD_SNTP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EFIDEBUG=y -CONFIG_CMD_RTC=y -CONFIG_CMD_TIME=y -CONFIG_CMD_GETTIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_REGULATOR=y -CONFIG_CMD_HASH=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_NOWHERE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_MMC_DEVICE_INDEX=1 -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_USE_ETHPRIME=y -CONFIG_ETHPRIME="eth0" -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SYS_RX_ETH_BUFFER=8 -CONFIG_SPL_DM=y -CONFIG_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_OF_TRANSLATE=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_SPL_CLK_CCF=y -CONFIG_CLK_CCF=y -CONFIG_CLK_SCMI=y -CONFIG_SPL_CLK_SCMI=y -CONFIG_DFU_MMC=y -CONFIG_DFU_RAM=y -CONFIG_SPL_FIRMWARE=y -# CONFIG_SCMI_AGENT_SMCCC is not set -CONFIG_IMX_RGPIO2P=y -CONFIG_DM_PCA953X=y -CONFIG_ADP5585_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_IMX_LPI2C=y -CONFIG_IMX_MU_MBOX=y -CONFIG_SUPPORT_EMMC_BOOT=y -CONFIG_MMC_IO_VOLTAGE=y -CONFIG_MMC_UHS_SUPPORT=y -CONFIG_MMC_HS400_ES_SUPPORT=y -CONFIG_MMC_HS400_SUPPORT=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MT35XU=y -CONFIG_PHYLIB=y -CONFIG_PHY_AQUANTIA=y -CONFIG_PHY_REALTEK=y -CONFIG_DM_MDIO=y -CONFIG_MII=y -CONFIG_FSL_ENETC=y -CONFIG_PCIE_ECAM_GENERIC=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_PINCTRL_IMX_SCMI=y -CONFIG_POWER_DOMAIN=y -CONFIG_SCMI_POWER_DOMAIN=y -CONFIG_DM_REGULATOR=y -CONFIG_SPL_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_SPL_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_DM_RTC=y -CONFIG_DM_SERIAL=y -CONFIG_FSL_LPUART=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_NXP_FSPI=y -CONFIG_ULP_WATCHDOG=y -CONFIG_LZO=y -CONFIG_BZIP2=y +#include <configs/imx95_evk.config> diff --git a/configs/imx95_a0_19x19_evk_defconfig b/configs/imx95_a0_19x19_evk_defconfig new file mode 100644 index 00000000000..9376f11b151 --- /dev/null +++ b/configs/imx95_a0_19x19_evk_defconfig @@ -0,0 +1,2 @@ +#include <configs/imx95_evk.config> +CONFIG_IMX95_A0=y diff --git a/configs/imx95_evk.config b/configs/imx95_evk.config new file mode 100644 index 00000000000..231b42cb377 --- /dev/null +++ b/configs/imx95_evk.config @@ -0,0 +1,150 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SOURCE_FILE="imx95_19x19_evk" +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx95-19x19-evk" +CONFIG_TARGET_IMX95_19X19_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx95-19x19-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set +CONFIG_BOARD_LATE_INIT=y +CONFIG_PCI_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x20000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_RX_ETH_BUFFER=8 +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_ADP5585_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_IMX_MU_MBOX=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_FSL_ENETC=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_ULP_WATCHDOG=y +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 36274804881..c657b0166e0 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -132,6 +132,7 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y +CONFIG_HBMC_AM654=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index d97d331fdbd..09784f300db 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -116,6 +116,7 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y +CONFIG_HBMC_AM654=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y @@ -124,6 +125,7 @@ CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_S28HX_T=y CONFIG_MULTIPLEXER=y +CONFIG_SPL_MUX_MMIO=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index ceb2e273b54..52290722686 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -124,6 +124,7 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y +CONFIG_HBMC_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SOFT_RESET=y @@ -133,6 +134,7 @@ CONFIG_SPI_FLASH_S28HX_T=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_MT35XU=y CONFIG_MULTIPLEXER=y +CONFIG_SPL_MUX_MMIO=y CONFIG_PINCTRL=y # CONFIG_PINCTRL_GENERIC is not set CONFIG_SPL_PINCTRL=y diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 13cff7b1a02..3ed07d18e10 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -27,6 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_CYCLIC=y CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_ATF=y # CONFIG_BOOTM_NETBSD is not set @@ -34,6 +35,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/k230_canmv_defconfig b/configs/k230_canmv_defconfig index a43412f0290..8781c12d3fd 100644 --- a/configs/k230_canmv_defconfig +++ b/configs/k230_canmv_defconfig @@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80400000 CONFIG_DEFAULT_DEVICE_TREE="k230-canmv" +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0xc000000 CONFIG_TARGET_K230_CANMV=y CONFIG_ARCH_RV64I=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 6937aa224a1..9f933592c9d 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -5,6 +5,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SYS_MEM_TOP_HIDE=0x400000 # CONFIG_DEBUG_UART is not set @@ -13,6 +14,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 @@ -20,6 +22,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_OF_UPSTREAM=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 70393de5736..f1f3930564b 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -5,7 +5,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000 CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_IDENT_STRING="milkv_duo" CONFIG_TARGET_MILKV_DUO=y diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig index 29c7636f827..152984d16ad 100644 --- a/configs/mvebu_ac5_rd_defconfig +++ b/configs/mvebu_ac5_rd_defconfig @@ -50,7 +50,6 @@ CONFIG_ROOTPATH="/srv/nfs/" CONFIG_USE_SERVERIP=y CONFIG_SERVERIP="0.0.0.0" CONFIG_CLK=y -CONFIG_CLK_MVEBU=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index f0e9ae9f674..52ad18e4dd9 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -47,7 +47,6 @@ CONFIG_AHCI_GENERIC=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y -CONFIG_CLK_MVEBU=y # CONFIG_MVEBU_GPIO is not set CONFIG_DM_I2C=y CONFIG_SYS_I2C_MV=y diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 94fbcf4f2d9..f3222e89b91 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -58,7 +58,6 @@ CONFIG_AHCI_GENERIC=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y -CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MV=y CONFIG_MISC=y diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig index 6e270be157b..69d6f7e34c3 100644 --- a/configs/mvebu_espressobin_ultra-88f3720_defconfig +++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig @@ -57,7 +57,6 @@ CONFIG_AHCI_GENERIC=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y -CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MV=y CONFIG_MISC=y diff --git a/configs/n1_defconfig b/configs/n1_defconfig new file mode 100644 index 00000000000..9bba6db99b5 --- /dev/null +++ b/configs/n1_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x00110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="n1" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra20-samsung-n1" +CONFIG_SPL_STACK=0xffffc +CONFIG_SPL_TEXT_BASE=0x00108000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_TEGRA20=y +CONFIG_TARGET_SAMSUNG_N1=y +CONFIG_TEGRA_ENABLE_UARTB=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2085 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra20 (N1) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x11000000 +CONFIG_FASTBOOT_BUF_SIZE=0x5000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MAX8907=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MAX8907=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y +CONFIG_SYSRESET_MAX8907=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ULPI=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Samsung" +CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 +CONFIG_USB_GADGET_PRODUCT_NUM=0x685F +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +# CONFIG_VIDEO_BPP8 is not set +CONFIG_VIDEO_LCD_SONY_L4F00430T01=y +CONFIG_BACKLIGHT_SAMSUNG_CMC623=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_SAMSUNG_CMC623=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 8e5e7e3e1e5..1653ab8b44f 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -28,6 +28,8 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set @@ -38,6 +40,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -73,4 +76,8 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/orangepi-5-ultra-rk3588_defconfig b/configs/orangepi-5-ultra-rk3588_defconfig new file mode 100644 index 00000000000..f3274325922 --- /dev/null +++ b/configs/orangepi-5-ultra-rk3588_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-orangepi-5-ultra" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-ultra.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index a002178b7fb..2ebcf8b83fc 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -18,13 +18,21 @@ CONFIG_TEGRA210=y CONFIG_TARGET_P3450_0000=y CONFIG_TEGRA_GPU=y CONFIG_PCI=y +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=753664 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=2089 CONFIG_CONSOLE_MUX=y CONFIG_SYS_STDIO_DEREGISTER=y CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set # CONFIG_CMD_IMI is not set +# CONFIG_CRC32_VERIFY is not set CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -53,7 +61,6 @@ CONFIG_RTL8169=y CONFIG_NVME_PCI=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y -CONFIG_TEGRA114_SPI=y CONFIG_TEGRA210_QSPI=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 7567a6aa739..5c81ced4956 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun8i-s3-pinecube" CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_SUNXI_DRAM_DDR3_1333=y @@ -9,13 +9,13 @@ CONFIG_DRAM_ODT_EN=y CONFIG_I2C0_ENABLE=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SPL_I2C=y -CONFIG_NO_NET=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_MTD=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP209_POWER=y CONFIG_AXP_DCDC2_VOLT=1250 CONFIG_AXP_DCDC3_VOLT=3300 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 817d4fe1d64..2070d534232 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -36,6 +36,7 @@ CONFIG_TPL_GPIO=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_CMD_VBE is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index bf39a1da723..e22585a705a 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_FIT=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 2a876aefecd..c588d01a676 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 36f8b457586..d1c43575c2a 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -6,7 +6,6 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_BSS_START_ADDR=0x84000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index a9ff831be91..cb91dfd9432 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -4,7 +4,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 8384fe78a31..2ef67d40269 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -4,7 +4,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 34e14b8f8df..04dec72ceac 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_SPL_BSS_START_ADDR=0x84000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 4ab362f0d43..3734836fa61 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN3=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x700000 diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig index 5ef81682caa..d3df0fd0baf 100644 --- a/configs/r8a77970_v3msk_defconfig +++ b/configs/r8a77970_v3msk_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN3=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x700000 diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 414bfdebab1..7405f207612 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN3=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 12d92067de5..2d487722677 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN3=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index f4f5c57451f..1b99ba1f02b 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -4,7 +4,6 @@ CONFIG_ARM=y CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN4=y CONFIG_COUNTER_FREQUENCY=16666666 -CONFIG_TEXT_BASE=0x50000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xC00000 CONFIG_ENV_SECT_SIZE=0x40000 diff --git a/configs/r8a779g3_sparrowhawk_defconfig b/configs/r8a779g3_sparrowhawk_defconfig index 9aa8dc83317..2d1abf6f26d 100644 --- a/configs/r8a779g3_sparrowhawk_defconfig +++ b/configs/r8a779g3_sparrowhawk_defconfig @@ -18,13 +18,14 @@ CONFIG_SYS_BARGSIZE=2048 CONFIG_SYS_CBSIZE=2048 CONFIG_BAUDRATE=921600 CONFIG_BINMAN=y -CONFIG_BOOTCOMMAND="tftp 0x50000000 fitImage && bootm 0x50000000" +CONFIG_BOOTCOMMAND="tftp ${loadaddr} fitImage && bootm ${loadaddr}" CONFIG_DEFAULT_FDT_FILE="r8a779g3-sparrow-hawk.dtb" CONFIG_CMD_REMOTEPROC=y CONFIG_GPIO_HOG=y CONFIG_REMOTEPROC_RENESAS_APMU=y CONFIG_BITBANGMII=y CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NVME_PCI=y CONFIG_PCI=y @@ -33,6 +34,15 @@ CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_USB=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_XHCI_GENERIC=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_RCAR is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y diff --git a/configs/radxa-cubie-a5e_defconfig b/configs/radxa-cubie-a5e_defconfig index 88019acf576..9d204ef5548 100644 --- a/configs/radxa-cubie-a5e_defconfig +++ b/configs/radxa-cubie-a5e_defconfig @@ -22,6 +22,8 @@ CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_PHY_REALTEK=y +CONFIG_SUN8I_EMAC=y CONFIG_REGULATOR_AXP=y CONFIG_AXP717_POWER=y CONFIG_AXP_DCDC2_VOLT=920 diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig index f5e097f3edf..0941d1b9be8 100644 --- a/configs/radxa-e20c-rk3528_defconfig +++ b/configs/radxa-e20c-rk3528_defconfig @@ -20,6 +20,8 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MISC=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_RNG=y CONFIG_CMD_REGULATOR=y @@ -28,6 +30,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_BUTTON=y CONFIG_BUTTON_ADC=y CONFIG_BUTTON_GPIO=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y @@ -43,6 +46,7 @@ CONFIG_DM_MDIO=y CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_PWM_ROCKCHIP=y @@ -50,6 +54,12 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y diff --git a/configs/renesas_rcar.config b/configs/renesas_rcar.config index db5846e992c..45776be62ea 100644 --- a/configs/renesas_rcar.config +++ b/configs/renesas_rcar.config @@ -18,6 +18,7 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_HUSH_PARSER=y CONFIG_MTD=y diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index c2bdc521018..401e237a816 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -3,7 +3,6 @@ CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_SYS_INIT_SP_BSS_OFFSET=1048576 CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RENESAS=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x80000 CONFIG_ENV_SIZE=0x20000 diff --git a/configs/ringneck-px30_defconfig b/configs/ringneck-px30_defconfig index ba15e386770..2240ba80e5e 100644 --- a/configs/ringneck-px30_defconfig +++ b/configs/ringneck-px30_defconfig @@ -40,6 +40,7 @@ CONFIG_SPL_ATF=y # CONFIG_CMD_VBE is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set CONFIG_CMD_BIND=y diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index 0b91337b17b..d3f7061f04d 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -3,7 +3,6 @@ CONFIG_ARM=y CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN3=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xFFFFE000 diff --git a/configs/sama7d65_curiosity_mmc1_defconfig b/configs/sama7d65_curiosity_mmc1_defconfig index e819e51b458..6b7e576a477 100644 --- a/configs/sama7d65_curiosity_mmc1_defconfig +++ b/configs/sama7d65_curiosity_mmc1_defconfig @@ -6,17 +6,21 @@ CONFIG_TARGET_SAMA7D65_CURIOSITY=y CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60014ef0 -CONFIG_SYS_MEMTEST_START=0x60000000 -CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="microchip/at91-sama7d65_curiosity" -CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x62000000 CONFIG_DEBUG_UART_BASE=0xe2020200 CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART=y +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y -CONFIG_SYS_LOAD_ADDR=0x62000000 +# CONFIG_EFI_LOADER_HII is not set CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y @@ -25,8 +29,6 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x61000000 at91-sama7d65_curiosity.dtb; fatload mmc 0:1 0x62000000 zImage; bootz 0x62000000 - 0x61000000" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_IMI=y CONFIG_CMD_MD5SUM=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_STRINGS=y @@ -38,12 +40,11 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND=y -CONFIG_CMD_SF_TEST=y CONFIG_CMD_DHCP=y -CONFIG_CMD_WGET=y +CONFIG_CMD_DNS=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DNS=y +CONFIG_CMD_WGET=y CONFIG_CMD_HASH=y CONFIG_HASH_VERIFY=y CONFIG_CMD_EXT4=y @@ -51,10 +52,8 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 -CONFIG_DM=y CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_CLK_AT91=y @@ -72,37 +71,21 @@ CONFIG_MICROCHIP_FLEXCOM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y CONFIG_DM_NAND_ATMEL=y CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_DM_SPI_FLASH=n -CONFIG_SF_DEFAULT_MODE=0x0 -CONFIG_SF_DEFAULT_SPEED=133000000 -CONFIG_SPI_FLASH_SFDP_SUPPORT=n -CONFIG_SPI_FLASH_SOFT_RESET=n -CONFIG_SPI_FLASH_MACRONIX=n -CONFIG_SPI_FLASH_MX66LM1G45G=n -CONFIG_SPI_FLASH_SST=n -CONFIG_SPI_FLASH_MTD=n -CONFIG_DM_ETH=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH_PHY=y CONFIG_MACB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y -CONFIG_DM_RESET=y CONFIG_RESET_AT91=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y -CONFIG_SPI=n -# CONFIG_ATMEL_SPI is not set -CONFIG_TIMER=y CONFIG_SYSRESET=y -CONFIG_SYSRESET_CMD_RESET=y CONFIG_SYSRESET_AT91=y +CONFIG_TIMER=y CONFIG_MCHP_PIT64B_TIMER=y -CONFIG_OF_LIBFDT_OVERLAY=y -# CONFIG_EFI_LOADER_HII is not set CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 6d2aec3a43e..23651ec764d 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -90,6 +90,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_GPT_RENAME=y CONFIG_CMD_IDE=y CONFIG_CMD_I2C=y +CONFIG_CMD_I3C=y CONFIG_CMD_LOADM=y CONFIG_CMD_LSBLK=y CONFIG_CMD_MTD=y @@ -206,9 +207,7 @@ CONFIG_ARM_FFA_TRANSPORT=y CONFIG_FPGA_ALTERA=y CONFIG_FPGA_STRATIX_II=y CONFIG_FPGA_STRATIX_V=y -CONFIG_FPGA_ACEX1K=y CONFIG_FPGA_CYCLON2=y -CONFIG_FPGA_LATTICE=y CONFIG_FPGA_XILINX=y CONFIG_FPGA_SPARTAN2=y CONFIG_FPGA_SPARTAN3=y @@ -228,6 +227,9 @@ CONFIG_I2C_CROS_EC_LDO=y CONFIG_DM_I2C_GPIO=y CONFIG_I2C_MUX=y CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I3C=y +CONFIG_I3C_SANDBOX=y +CONFIG_DW_I3C_MASTER=y CONFIG_CROS_EC_KEYB=y CONFIG_I8042_KEYB=y CONFIG_IOMMU=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 01963a4e54e..f341e3e0735 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -11,7 +11,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe70 CONFIG_SPL_BSS_START_ADDR=0x85000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index acbea7fe1bb..0a736f2ba95 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -12,7 +12,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe60 CONFIG_SPL_BSS_START_ADDR=0x85000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/configs/sige5-rk3576_defconfig b/configs/sige5-rk3576_defconfig new file mode 100644 index 00000000000..c515e145595 --- /dev/null +++ b/configs/sige5-rk3576_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-armsom-sige5" +CONFIG_ROCKCHIP_RK3576=y +CONFIG_SYS_LOAD_ADDR=0x40c00800 +CONFIG_DEBUG_UART_BASE=0x2AD40000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-armsom-sige5.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMINFO_MAP=y +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_RNG=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index acdd1ad5205..af462d2086f 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -5,7 +5,6 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN3=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3F0000 diff --git a/configs/sipeed_licheerv_nano_defconfig b/configs/sipeed_licheerv_nano_defconfig index fc7f82e878a..9aa3ede10c5 100644 --- a/configs/sipeed_licheerv_nano_defconfig +++ b/configs/sipeed_licheerv_nano_defconfig @@ -5,7 +5,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000 CONFIG_DEFAULT_DEVICE_TREE="sg2002-licheerv-nano-b" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_IDENT_STRING="licheerv_nano" CONFIG_TARGET_LICHEERV_NANO=y diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 9fcdfb4a8fe..bb9e7f7d903 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -5,6 +5,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_SF_DEFAULT_BUS=3 CONFIG_TARGET_SIPEED_MAIX=y diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig index 11d78688780..aadadbcab3f 100644 --- a/configs/sipeed_maix_smode_defconfig +++ b/configs/sipeed_maix_smode_defconfig @@ -6,6 +6,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_SF_DEFAULT_BUS=3 CONFIG_TARGET_SIPEED_MAIX=y diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index cc812c7008c..b373201dbaa 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -46,6 +46,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x9fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y CONFIG_SPL_MTD=y +CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 @@ -57,6 +58,7 @@ CONFIG_CMD_NVEDIT_SELECT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_I3C=y CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -71,8 +73,6 @@ CONFIG_ENV_IS_IN_UBI=y CONFIG_ENV_UBI_PART="root" CONFIG_ENV_UBI_VOLUME="env" CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y @@ -81,6 +81,8 @@ CONFIG_SPL_GPIO_HOG=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_I3C=y +CONFIG_DW_I3C_MASTER=y CONFIG_MISC=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_SPANSION=y @@ -90,6 +92,7 @@ CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_DWC_ETH_XGMAC=y CONFIG_RGMII=y +CONFIG_AGILEX5_PMGR_POWER_DOMAIN=y CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y @@ -103,5 +106,3 @@ CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y -CONFIG_SPL_POWER_DOMAIN=y -CONFIG_AGILEX5_PMGR_POWER_DOMAIN=y diff --git a/configs/socfpga_agilex7m_defconfig b/configs/socfpga_agilex7m_defconfig new file mode 100644 index 00000000000..0a8c58234b9 --- /dev/null +++ b/configs/socfpga_agilex7m_defconfig @@ -0,0 +1,19 @@ +#include <configs/socfpga_agilex_defconfig> + +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +# CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK is not set +# CONFIG_IDENT_STRING is not set +CONFIG_SPL_BSS_START_ADDR=0x1ff00000 +CONFIG_TARGET_SOCFPGA_AGILEX7M_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex7m" +# CONFIG_QSPI_BOOT is not set +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x1fa00000 +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX7M # " +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),-(root)" +# CONFIG_ENV_IS_IN_UBI is not set +# CONFIG_ENV_UBI_PART is not set +# CONFIG_ENV_UBI_VOLUME is not set +# CONFIG_USE_BOOTFILE is not set +# CONFIG_DESIGNWARE_SPI is not set diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig deleted file mode 100644 index a2bd40d5dbd..00000000000 --- a/configs/socfpga_agilex_atf_defconfig +++ /dev/null @@ -1,93 +0,0 @@ -CONFIG_ARM=y -CONFIG_COUNTER_FREQUENCY=400000000 -CONFIG_ARCH_SOCFPGA=y -CONFIG_TEXT_BASE=0x200000 -CONFIG_SYS_MALLOC_LEN=0x500000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 -CONFIG_SF_DEFAULT_MODE=0x2003 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x200 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" -CONFIG_DM_RESET=y -CONFIG_SPL_STACK=0xffe3f000 -CONFIG_SPL_TEXT_BASE=0xFFE00000 -CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -CONFIG_SPL_BSS_START_ADDR=0x3ff00000 -CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_SYS_LOAD_ADDR=0x02000000 -CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y -CONFIG_IDENT_STRING="socfpga_agilex" -CONFIG_SPL_FS_FAT=y -CONFIG_REMAKE_ELF=y -CONFIG_FIT=y -CONFIG_SPL_FIT_SIGNATURE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 -CONFIG_BOOTDELAY=5 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="earlycon" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" -CONFIG_SYS_PBSIZE=2082 -CONFIG_SPL_MAX_SIZE=0x40000 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set -CONFIG_SPL_HAVE_INIT_STACK=y -CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 -CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 -CONFIG_SPL_CACHE=y -CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb" -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SPL_ALTERA_SDRAM=y -CONFIG_DWAPB_GPIO=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_DW=y -CONFIG_SYS_MMC_MAX_BLK_COUNT=256 -CONFIG_MMC_DW=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_ETH_DESIGNWARE=y -CONFIG_MII=y -CONFIG_SYS_NS16550_MEM32=y -CONFIG_SPI=y -CONFIG_CADENCE_QSPI=y -CONFIG_DESIGNWARE_SPI=y -CONFIG_USB=y -CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y -CONFIG_DESIGNWARE_WATCHDOG=y -CONFIG_WDT=y -# CONFIG_SPL_USE_TINY_PRINTF is not set -CONFIG_PANIC_HANG=y -CONFIG_SPL_CRC32=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 0b6194c1f27..1c3664bc0d7 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -1,38 +1,37 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=400000000 CONFIG_ARCH_SOCFPGA=y -CONFIG_TEXT_BASE=0x1000 -CONFIG_SYS_MALLOC_LEN=0x500000 +CONFIG_TEXT_BASE=0x200000 CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x101000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 CONFIG_SF_DEFAULT_MODE=0x2003 -CONFIG_ENV_SIZE=0x1000 -CONFIG_ENV_OFFSET=0x200 +CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_DEFAULT_DEVICE_TREE="intel/socfpga_agilex_socdk" CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 CONFIG_SPL_TEXT_BASE=0xFFE00000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x3ff00000 CONFIG_SPL_BSS_MAX_SIZE=0x100000 -CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y CONFIG_IDENT_STRING="socfpga_agilex" CONFIG_SPL_FS_FAT=y -# CONFIG_PSCI_RESET is not set -CONFIG_SYS_MEMTEST_START=0x00000000 -CONFIG_SYS_MEMTEST_END=0x3fe00000 -CONFIG_REMAKE_ELF=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_FIT=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="earlycon" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run fatscript; run mmcload; run linux_qspi_enable; run mmcboot" -CONFIG_SYS_PBSIZE=2082 +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y @@ -40,38 +39,47 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_MTD=y +CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 -CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" -CONFIG_HUSH_PARSER=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x04000000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_NVEDIT_SELECT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -# CONFIG_CMD_MTDPARTS is not set -CONFIG_ENV_IS_IN_MMC=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="Image" +CONFIG_CMD_SMC=y +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_UPSTREAM=y +CONFIG_OF_LIST="" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_UBI_PART="root" +CONFIG_ENV_UBI_VOLUME="env" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y +CONFIG_DM_MTD=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y @@ -82,8 +90,9 @@ CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_USB_DWC2=y -CONFIG_USB_STORAGE=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y # CONFIG_SPL_USE_TINY_PRINTF is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_CRC32=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 8eec3d8d67a..edce692ecd1 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -11,7 +11,7 @@ CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x200 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_DEFAULT_DEVICE_TREE="intel/socfpga_agilex_socdk" CONFIG_DM_RESET=y CONFIG_SPL_STACK=0xffe3f000 CONFIG_SPL_TEXT_BASE=0xFFE00000 @@ -63,9 +63,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 5bf431b4a18..1ef20ba97a8 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -63,8 +63,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index c0dc8558153..5d51c4786c0 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -64,8 +64,6 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index ed26f2dffde..63ea467baef 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -63,8 +63,6 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_USE_BOOTFILE=y -CONFIG_BOOTFILE="kernel.itb" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_ALTERA_SDRAM=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 3e34e4a87f8..bd1aacbad6a 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_STACK=0x8180000 CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_SPL_BSS_START_ADDR=0x8040000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -86,6 +85,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y +CONFIG_DNS=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/stm32mp23_defconfig b/configs/stm32mp23_defconfig index 3f8fa6ce527..840855c23e5 100644 --- a/configs/stm32mp23_defconfig +++ b/configs/stm32mp23_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_STM32MP23X=y CONFIG_DDR_CACHEABLE_SIZE=0x10000000 CONFIG_CMD_STM32KEY=y -CONFIG_ENV_OFFSET_REDUND=0x940000 CONFIG_TARGET_ST_STM32MP23X=y CONFIG_SYS_MEMTEST_START=0x84000000 CONFIG_SYS_MEMTEST_END=0x88000000 @@ -46,11 +45,8 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" -CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" -CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_NO_NET=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 14619ffd96c..2b02cd86d61 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y +CONFIG_OF_UPSTREAM_BUILD_VENDOR=y +CONFIG_OF_UPSTREAM_VENDOR="st" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y diff --git a/configs/surface-2_defconfig b/configs/surface-2_defconfig new file mode 100644 index 00000000000..6e287539f53 --- /dev/null +++ b/configs/surface-2_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_SYS_MALLOC_LEN=0x2500000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="surface-2" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra114-microsoft-surface-2-0b" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA114=y +CONFIG_TARGET_SURFACE_2=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_PBSIZE=2086 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra114 (Surface 2) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_LIST="tegra114-microsoft-surface-2-0b tegra114-microsoft-surface-2-13" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65090=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_PALMAS=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_SAMSUNG_LTL106HL02=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 2763cbb428a..48cd8991591 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a" CONFIG_SPL_STACK=0xffe0170000 CONFIG_SPL_BSS_START_ADDR=0xffe0160000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_TARGET_TH1520_LPI4A=y diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig index 335ea4d8de3..8ba2a996ee2 100644 --- a/configs/tiger-rk3588_defconfig +++ b/configs/tiger-rk3588_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_ATF=y # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_ELF is not set +CONFIG_CMD_ERASEENV=y CONFIG_CMD_ADC=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index acfab5755ba..7ecab30b624 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -63,7 +63,6 @@ CONFIG_AHCI_PCI=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y CONFIG_CLK=y -CONFIG_CLK_MVEBU=y # CONFIG_MVEBU_GPIO is not set CONFIG_DM_I2C=y CONFIG_SYS_I2C_MV=y diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig index 2f557801d29..851d7bb2cb9 100644 --- a/configs/uDPU_defconfig +++ b/configs/uDPU_defconfig @@ -50,7 +50,6 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CLK=y -CONFIG_CLK_MVEBU=y CONFIG_DM_I2C=y CONFIG_DM_I2C_GPIO=y CONFIG_SYS_I2C_MV=y diff --git a/configs/voyager_spl_defconfig b/configs/voyager_spl_defconfig new file mode 100644 index 00000000000..f7390405dac --- /dev/null +++ b/configs/voyager_spl_defconfig @@ -0,0 +1,65 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x401800000 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x410000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="qilai-voyager" +CONFIG_SPL_BSS_START_ADDR=0x400400000 +CONFIG_SYS_LOAD_ADDR=0x400100000 +CONFIG_SPL=y +CONFIG_TARGET_ANDES_VOYAGER=y +CONFIG_NR_CPUS=4 +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +# CONFIG_AVAILABLE_HARTS is not set +CONFIG_SYS_MONITOR_BASE=0x88000000 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x410000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_CONSOLE_RECORD=y +CONFIG_CONSOLE_RECORD_OUT_SIZE_F=0x2000 +CONFIG_SYS_PBSIZE=1050 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_SPL_CYCLIC is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y +# CONFIG_BINMAN_FDT is not set diff --git a/configs/x240_defconfig b/configs/x240_defconfig index ff64916204c..c78077ba33a 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_IPV6=y CONFIG_CLK=y -CONFIG_CLK_MVEBU=y CONFIG_GPIO_HOG=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 92f7aa04ec0..e3341179a68 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -40,5 +41,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index b61ec90d096..c95b4497395 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -44,5 +45,6 @@ CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig index c4d458370b6..a3cc1a5669e 100644 --- a/configs/xilinx_mbv64_defconfig +++ b/configs/xilinx_mbv64_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -41,5 +42,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig index 2d7227c9e33..3d49670c60c 100644 --- a/configs/xilinx_mbv64_smode_defconfig +++ b/configs/xilinx_mbv64_smode_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -45,5 +46,6 @@ CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 7a7abf66eb5..4412f52bbd2 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -45,15 +45,9 @@ CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x2000000 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb" CONFIG_SPL_FPGA=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_SPI_KERNEL_OFFS=0x280000 -CONFIG_SYS_SPI_ARGS_OFFS=0x200000 -CONFIG_SYS_SPI_ARGS_SIZE=0x80000 CONFIG_SYS_MAXARGS=32 # CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_IMLS=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 3e2ac614405..332e9401187 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -51,17 +51,10 @@ CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_BINMAN_SYMBOLS is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y -CONFIG_SPL_FS_LOAD_KERNEL_NAME="" -CONFIG_SPL_FS_LOAD_ARGS_NAME="" CONFIG_SPL_FPGA=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000 CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SYS_SPI_KERNEL_OFFS=0x80000 -CONFIG_SYS_SPI_ARGS_OFFS=0xa0000 -CONFIG_SYS_SPI_ARGS_SIZE=0xa0000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_SMBIOS=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 65c8a4bbaad..b45ac8063fc 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -48,17 +48,10 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x20000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 -CONFIG_SPL_FS_LOAD_KERNEL_NAME="atf-uboot.ub" -CONFIG_SPL_FS_LOAD_ARGS_NAME="u-boot.bin" CONFIG_SPL_FPGA=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x8000000 CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 -CONFIG_SYS_SPI_KERNEL_OFFS=0x80000 -CONFIG_SYS_SPI_ARGS_OFFS=0xa0000 -CONFIG_SYS_SPI_ARGS_SIZE=0xa0000 CONFIG_SPL_ATF=y CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_CMD_SMBIOS=y diff --git a/doc/api/i3c.rst b/doc/api/i3c.rst new file mode 100644 index 00000000000..7906face080 --- /dev/null +++ b/doc/api/i3c.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2025 Altera Corporation <www.altera.com> + +I3C Subsystem +=============== + +.. kernel-doc:: include/i3c.h + :internal: diff --git a/doc/api/index.rst b/doc/api/index.rst index cf9d21e4c1c..d97630e7671 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -15,6 +15,7 @@ U-Boot API documentation fs getopt interrupt + i3c led linker_lists logging diff --git a/doc/board/andestech/index.rst b/doc/board/andestech/index.rst index cacc5791a91..5ef93308b49 100644 --- a/doc/board/andestech/index.rst +++ b/doc/board/andestech/index.rst @@ -8,3 +8,4 @@ Andes Tech adp-ag101p ae350 + voyager diff --git a/doc/board/andestech/voyager.rst b/doc/board/andestech/voyager.rst new file mode 100644 index 00000000000..63553216d60 --- /dev/null +++ b/doc/board/andestech/voyager.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Voyager +======= + +Qilai RISC-V SoC +---------------- +The QiLai SoC chip is Andes' first RISC-V SoC. It includes high performance +quad-core Andes AX45MP cluster and one NX27V vector processor. + +The Voyager development platform is based on Qilai and capable of running Linux. + +Mainline support +---------------- + +The support for following drivers are already enabled: + +1. UART driver +2. MMC driver +3. SPI driver + +Building +~~~~~~~~ + +How to build U-Boot SPL +~~~~~~~~~~~~~~~~~~~~~~~ +Before building U-Boot SPL, OpenSBI must be build first. +OpenSBI can be cloned and build for Voyager as below: + +1. Get the RISC-V toolchain. +2. Setup cross compilation environment variable. + +.. code-block:: none + + git clone https://github.com/riscv-software-src/opensbi.git + cd opensbi + make PLATFORM=generic + +Copy OpenSBI FW_DYNAMIC image (build/platform/generic/firmware/fw_dynamic.bin) +into U-Boot root directory, then + +.. code-block:: console + + export CROSS_COMPILE=riscv64-linux-gnu- + cd <U-Boot-dir> + cp fw_dynamic.bin . + make voyager_spl_defconfig + make + +Booting +~~~~~~~ + +Currently, we rely on vendor ROM code to initialize the DDR +and load the u-boot image, then boot from it. + +Sample boot log from Voyager board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: none + + U-Boot SPL 2025.10-rc1-00130-ga28bcbba4778-dirty (Aug 06 2025 - 17:46:10 +0800) + Trying to boot from RAM + + U-Boot 2025.10-rc1-00130-ga28bcbba4778-dirty (Aug 06 2025 - 17:46:10 +0800) + + CPU: riscv + Model: andestech,ax45 + DRAM: 16 GiB + Core: 25 devices, 14 uclasses, devicetree: board + MMC: mmc@30c00000: 0 + Loading Environment from SPIFlash... SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB + *** Warning - bad CRC, using default environment + + In: serial@30300000 + Out: serial@30300000 + Err: serial@30300000 + Net: No ethernet found. + Hit any key to stop autoboot: 0 + No ethernet found. + No ethernet found. + RISC-V # diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index cf2f893b723..b5948d9affc 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -179,6 +179,32 @@ Provide the U-Boot S-mode ELF image as *-kernel* parameter and do not add a qemu-system-riscv64 -accel kvm -nographic -machine virt -kernel u-boot +Running as flash binary +----------------------- + +U-Boot can be provided to QEMU as an emulated flash drive. +This can for instance be used to test capsule updates. + +Build qemu-riscv64_smode_defconfig with:: + + CONFIG_XIP=y + CONFIG_TEXT_BASE=0x20000000 + CONFIG_CMD_MTD=y + CONFIG_FLASH_CFI_MTD=y + +Pad u-boot.bin to 32 MiB size: + +.. code-block:: bash + + truncate -s 32M u-boot.bin + +Invoke QEMU with: + +.. code-block:: bash + + qemu-system-riscv64 -M virt -nographic \ + -drive if=pflash,format=raw,unit=0,file=u-boot.bin,readonly=off + Debug UART ---------- diff --git a/doc/board/index.rst b/doc/board/index.rst index e084c7fb1df..7870f1bc246 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -47,6 +47,7 @@ Board-specific doc nxp/index openpiton/index ouya/index + pegatron/index phytec/index purism/index qualcomm/index diff --git a/doc/board/microsoft/index.rst b/doc/board/microsoft/index.rst index 107f3527852..8318449a9a2 100644 --- a/doc/board/microsoft/index.rst +++ b/doc/board/microsoft/index.rst @@ -6,4 +6,5 @@ Microsoft .. toctree:: :maxdepth: 2 + surface-2 surface-rt diff --git a/doc/board/microsoft/surface-2.rst b/doc/board/microsoft/surface-2.rst new file mode 100644 index 00000000000..8185c6f5ae4 --- /dev/null +++ b/doc/board/microsoft/surface-2.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Microsoft Surface 2 tablet +========================================= + +Quick Start +----------- + +- Build U-Boot +- Boot + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make surface-2_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for loading. + +Boot +---- + +Currently, U-Boot can be preloaded into RAM via the Fusée Gelée. To enter +RCM protocol use ``power`` and ``volume up`` key combination from powered +off device. The host PC should recognize an APX device. + +Built U-Boot ``u-boot-dtb-tegra.bin`` can be loaded from fusee-tools +directory with + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/surface-2.bct + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while loading, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, poweroff and enter U-Boot console. diff --git a/doc/board/nxp/imx95_evk.rst b/doc/board/nxp/imx95_evk.rst index 27cd15eb7c9..709992e016d 100644 --- a/doc/board/nxp/imx95_evk.rst +++ b/doc/board/nxp/imx95_evk.rst @@ -25,6 +25,17 @@ Note: srctree is U-Boot source directory $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + +i.MX95 A0 silicon version + +.. code-block:: bash + + $ cp firmware-ele-imx-2.0.2-89161a8/mx95a0-ahab-container.img $(srctree) + +i.MX95 B0 silicon version + +.. code-block:: bash + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) Get DDR PHY Firmware Images @@ -53,12 +64,24 @@ branch: master $ export TOOLS=$PWD $ git clone -b master https://github.com/nxp-imx/imx-oei.git $ cd imx-oei - $ make board=mx95lp5 oei=ddr DEBUG=1 + +i.MX95 A0 silicon version + +.. code-block:: bash + + $ make board=mx95lp5 oei=ddr DEBUG=1 r=A0 DDR_CONFIG=XIMX95LPD5EVK19_6400mbps_train_timing_a1 all $ cp build/mx95lp5/ddr/oei-m33-ddr.bin $(srctree) - $ make board=mx95lp5 oei=tcm DEBUG=1 + $ make board=mx95lp5 oei=tcm DEBUG=1 r=A0 all $ cp build/mx95lp5/tcm/oei-m33-tcm.bin $(srctree) +i.MX95 B0 silicon version + +.. code-block:: bash + + $ make board=mx95lp5 oei=ddr DEBUG=1 r=B0 all + $ cp build/mx95lp5/ddr/oei-m33-ddr.bin $(srctree) + Get and Build System Manager Image -------------------------------------- @@ -82,13 +105,14 @@ Get and Build the ARM Trusted Firmware Note: srctree is U-Boot source directory Get ATF from: https://github.com/nxp-imx/imx-atf/ -branch: lf_v2.10 +branch: lf_v2.12 .. code-block:: bash $ export CROSS_COMPILE=aarch64-poky-linux- $ unset LDFLAGS - $ git clone -b lf_v2.10 https://github.com/nxp-imx/imx-atf.git + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git $ cd imx-atf $ make PLAT=imx95 bl31 $ cp build/imx95/release/bl31.bin $(srctree) @@ -96,6 +120,16 @@ branch: lf_v2.10 Build the Bootloader Image -------------------------- +i.MX95 A0 silicon version + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx95_a0_19x19_evk_defconfig + $ make + +i.MX95 B0 silicon version + .. code-block:: bash $ export CROSS_COMPILE=aarch64-poky-linux- diff --git a/doc/board/pegatron/chagall.rst b/doc/board/pegatron/chagall.rst new file mode 100644 index 00000000000..18ed425ec73 --- /dev/null +++ b/doc/board/pegatron/chagall.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Pegatron Chagall tablet +====================================== + +Quick Start +----------- + +- Build U-Boot +- Boot + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make chagall_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for loading. + +Boot +---- + +Currently, U-Boot can be preloaded into RAM via the Fusée Gelée. To enter +RCM protocol use ``power`` and ``volume up`` key combination from powered +off device. The host PC should recognize an APX device. + +Built U-Boot ``u-boot-dtb-tegra.bin`` can be loaded from fusee-tools +directory with + +.. code-block:: bash + + $ ./run_bootloader.sh -s T30 -t ./bct/chagall.bct + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while loading, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, reboot, reboot RCM and poweroff. diff --git a/doc/board/pegatron/index.rst b/doc/board/pegatron/index.rst new file mode 100644 index 00000000000..8fd8d5fa547 --- /dev/null +++ b/doc/board/pegatron/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Pegatron +======== + +.. toctree:: + :maxdepth: 2 + + chagall diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index b88299cbba2..de3aa79cb5c 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -134,7 +134,9 @@ List of mainline supported Rockchip boards: - Radxa ROCK 3B (rock-3b-rk3568) * rk3576 + - ArmSoM Sige5 (sige5-rk3576) - Firefly ROC-RK3576-PC (roc-pc-rk3576) + - Generic RK3576 (generic-rk3576) * rk3588 - ArmSoM Sige7 (sige7-rk3588) @@ -145,6 +147,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s) - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s) + - GameForce Ace (gameforce-ace-rk3588s) - Generic RK3588S/RK3588 (generic-rk3588) - Hardkernel ODROID-M2 (odroid-m2-rk3588s) - Indiedroid Nova (nova-rk3588s) @@ -161,6 +164,7 @@ List of mainline supported Rockchip boards: - Xunlong Orange Pi 5 (orangepi-5-rk3588s) - Xunlong Orange Pi 5 Max (orangepi-5-max-rk3588) - Xunlong Orange Pi 5 Plus (orangepi-5-plus-rk3588) + - Xunlong Orange Pi 5 Ultra (orangepi-5-ultra-rk3588) - Yanyi Tech CoolPi 4 Model B (coolpi-4b-rk3588s) - Yanyi Tech CoolPi CM5 EVB (coolpi-cm5-evb-rk3588) - Yanyi Tech CoolPi CM5 GenBook (coolpi-cm5-genbook-rk3588) diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst index a1c9636b050..1b92c9518a5 100644 --- a/doc/board/samsung/index.rst +++ b/doc/board/samsung/index.rst @@ -8,3 +8,4 @@ Samsung axy17lte e850-96 + n1 diff --git a/doc/board/samsung/n1.rst b/doc/board/samsung/n1.rst new file mode 100644 index 00000000000..4dbb3141774 --- /dev/null +++ b/doc/board/samsung/n1.rst @@ -0,0 +1,51 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Samsung N1 device family +======================================= + +``DISCLAMER!`` Moving your Samsung Galaxy R (GT-I9103) or Samsung Captivate Glide +(SGH-i927) to use U-Boot assumes replacement of the sboot. Vendor android firmwares +will no longer be able to run on the device. This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Boot + +Build U-Boot +------------ + +Device support is implemented by applying config fragment to a generic board +defconfig. Generic board defconfig is suitable for Samsung Galaxy R (GT-I9103) +while Samsung Captivate Glide (SGH-i927) support is provided by applying +``bose.config`` fragment. + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make n1_defconfig bose.config # For Captivate Glide + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for further processing. + +Boot +---- + +Currently, U-Boot can be preloaded into RAM via the NvFlash. To enter +RCM protocol use ``home`` and ``volume up`` for Galaxy R and ``volume down`` +and ``volume up`` Captivate Glide key combination plus plugging usb in. +The host PC should recognize an APX device. + +Built U-Boot ``u-boot-dtb-tegra.bin`` can be loaded from fusee-tools +directory with + +.. code-block:: bash + + $ ./utils/nvflash_t20 --setbct --bct ./bct/i927.bct --configfile ./utils/flash.cfg --bl u-boot-dtb-tegra.bin --sbk (in form of 0xABCDABCD 4 times) --sync # For Captivate Glide + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while loading, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, reboot, reboot RCM and poweroff. diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst index 43a1db68873..4dd998bcce9 100644 --- a/doc/board/ti/am62ax_sk.rst +++ b/doc/board/ti/am62ax_sk.rst @@ -121,12 +121,7 @@ Set the variables corresponding to this platform: Target Images -------------- In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC -variant (GP, HS-FS, HS-SE) requires a different source for these files. - - - GP - - * tiboot3-am62ax-gp-evm.bin from step 3.1 - * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2 +variant (HS-FS, HS-SE) requires a different source for these files. - HS-FS diff --git a/doc/build/clang.rst b/doc/build/clang.rst index 09bb988e923..a83ecb4fdc6 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -46,9 +46,9 @@ It can also be used to compile sandbox: FreeBSD 11 ---------- -Since llvm 3.4 is currently in the base system, the integrated assembler as -is incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils -is used instead. It needs a symlink to be picked up correctly though: +Since LLVM 3.4 is currently in the base system, the integrated assembler is +incapable of building U-Boot. Therefore gas from devel/arm-gnueabi-binutils is +used instead. It needs a symbolic link to be picked up correctly though: .. code-block:: bash @@ -64,7 +64,7 @@ The following commands compile U-Boot using the Clang xdev toolchain. gmake rpi_2_defconfig gmake CC="clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd" -j8 -Given that U-Boot will default to gcc, above commands can be +Given that U-Boot will default to gcc, the commands above can be simplified with a simple wrapper script - saved as /usr/local/bin/arm-gnueabi-freebsd-gcc - listed below: diff --git a/doc/build/gen_compile_commands.rst b/doc/build/gen_compile_commands.rst index d503764f9e3..5eb9e4ccb0a 100644 --- a/doc/build/gen_compile_commands.rst +++ b/doc/build/gen_compile_commands.rst @@ -39,7 +39,7 @@ course) to have an up-to-date database. The database will be in the root of the repository. No further modifications are needed for it to be usable by the LSP, unless you set a name for the database -other than it's default one (compile_commands.json). +other than the default one (compile_commands.json). Compatible IDEs --------------- diff --git a/doc/build/reproducible.rst b/doc/build/reproducible.rst index 8b030f469d7..1512129e374 100644 --- a/doc/build/reproducible.rst +++ b/doc/build/reproducible.rst @@ -24,4 +24,4 @@ This date is shown when we launch U-Boot: ./u-boot -T U-Boot 2023.01 (Jan 01 2023 - 00:00:00 +0000) -The same effect can be obtained with buildman using the `-r` flag. +The same effect can be obtained with Buildman using the `-r` flag. diff --git a/doc/build/tools.rst b/doc/build/tools.rst index 5bfa05b2325..1cc8eb93230 100644 --- a/doc/build/tools.rst +++ b/doc/build/tools.rst @@ -8,7 +8,7 @@ Building tools for Linux ------------------------ To allow distributions to distribute all possible tools in a generic way, -avoiding the need of specific tools building for each machine, a tools only +avoiding the need of specific building tools for each machine, a tools-only defconfig file is provided. Using this, we can build the tools by doing:: @@ -30,9 +30,8 @@ installed all required packages below in order to build these host tools:: * diffutils (3.7) * openssl-devel (1.1.1.d) -Note the version numbers in these parentheses above are the package versions -at the time being when writing this document. The MSYS2 installer tested is -http://repo.msys2.org/distrib/x86_64/msys2-x86_64-20190524.exe. +Note that the version numbers in parentheses above are the package versions at +the time of writing this document. There are 3 MSYS subsystems installed: MSYS2, MinGW32 and MinGW64. Each subsystem provides an environment to build Windows applications. The MSYS2 @@ -50,7 +49,7 @@ Launch the MSYS2 shell of the MSYS2 environment, and do the following:: Building without Python ----------------------- -The tools-only builds bytes pylibfdt by default. To disable this, use the +The tools-only builds pylibfdt by default. To disable this, use the NO_PYTHON variable:: NO_PYTHON=1 make tools-only_defconfig tools-only diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 7aa36166a5d..daf73e207d4 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -58,7 +58,7 @@ Current Status * The Merge Window for the next release (|next_ver|) is **closed** with the -rc1 release on Monday, 28 July 2025. -* The next branch is now **closed** until the -rc2 release on Monday, 11 August +* The next branch is now **open** with the -rc2 release on Monday, 11 August 2025. * Release "|next_ver|" is scheduled for Monday, 06 October 2025. @@ -73,11 +73,11 @@ For the next scheduled release, release candidates were made on:: * U-Boot |next_ver|-rc1 was released on Mon 28 July 2025. -.. * U-Boot |next_ver|-rc2 was released on Mon 11 August 2025. +* U-Boot |next_ver|-rc2 was released on Mon 11 August 2025. -.. * U-Boot |next_ver|-rc3 was released on Mon 25 August 2025. +* U-Boot |next_ver|-rc3 was released on Mon 25 August 2025. -.. * U-Boot |next_ver|-rc4 was released on Mon 08 September 2025. +* U-Boot |next_ver|-rc4 was released on Mon 08 September 2025. .. * U-Boot |next_ver|-rc5 was released on Mon 22 September 2025. diff --git a/doc/develop/spl.rst b/doc/develop/spl.rst index aa6d28fa333..7f2eac50806 100644 --- a/doc/develop/spl.rst +++ b/doc/develop/spl.rst @@ -142,7 +142,7 @@ fdtgrep is also used to remove: - the properties defined in CONFIG_OF_SPL_REMOVE_PROPS - all the pre-relocation properties ('bootph-all', 'bootph-pre-ram' (SPL), 'bootph-pre-sram' (TPL) and - 'bootph-verify' (TPL)) + 'bootph-verify' (VPL)) All the nodes remaining in the SPL devicetree are bound (see doc/driver-model/design.rst). diff --git a/doc/device-tree-bindings/power/ti,sci-pm-domain.txt b/doc/device-tree-bindings/power/ti,sci-pm-domain.txt index 72d9fbc833c..81f6314230f 100644 --- a/doc/device-tree-bindings/power/ti,sci-pm-domain.txt +++ b/doc/device-tree-bindings/power/ti,sci-pm-domain.txt @@ -30,7 +30,7 @@ Required Properties: Example (AM65x): ---------------- sysfw: sysfw { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; ... k3_pds: power-controller { compatible = "ti,sci-pm-domain"; diff --git a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt index 33dc46812ed..7de57ad4f00 100644 --- a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt +++ b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt @@ -8,7 +8,7 @@ This driver communicates with ROM for loading this firmware. Required properties: -------------------- -- compatible: Shall be: "ti,am654-system-controller" +- compatible: Shall be: "ti,am654-tisci-rproc-r5-r5" - mbox-names: "tx" for Transfer channel "rx" for Receive channel - mboxes: Corresponding phandles to mailbox channels. @@ -21,7 +21,7 @@ Example: -------- system-controller: system-controller { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5-r5"; mboxes= <&secproxy 4>, <&secproxy 5>; mbox-names = "tx", "rx"; }; diff --git a/doc/device-tree-bindings/reset/ti,sci-reset.txt b/doc/device-tree-bindings/reset/ti,sci-reset.txt index e7e2d13f9fb..740b2dfea64 100644 --- a/doc/device-tree-bindings/reset/ti,sci-reset.txt +++ b/doc/device-tree-bindings/reset/ti,sci-reset.txt @@ -23,7 +23,7 @@ Required Properties: Example (AM65x): ---------------- sysfw: sysfw { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; ... k3_reset: reset-controller { compatible = "ti,sci-reset"; diff --git a/doc/git-mailrc b/doc/git-mailrc index 747ceda3307..65626d89eac 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -23,7 +23,7 @@ alias bmeng Bin Meng <bmeng.cn@gmail.com> alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com> alias dinh Dinh Nguyen <dinguyen@kernel.org> alias ehristev Eugen Hristev <eugen.hristev@linaro.org> -alias hs Heiko Schocher <hs@denx.de> +alias hs Heiko Schocher <hs@nabladev.com> alias freenix Peng Fan <peng.fan@nxp.com> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org> alias jaehoon Jaehoon Chung <jh80.chung@samsung.com> diff --git a/doc/usage/cmd/bootefi.rst b/doc/usage/cmd/bootefi.rst index d6e4e62e383..7c5448586b7 100644 --- a/doc/usage/cmd/bootefi.rst +++ b/doc/usage/cmd/bootefi.rst @@ -12,7 +12,7 @@ Synopsis :: - bootefi <image_addr>[:<image_size>] [<fdt_addr>] + bootefi <image_addr>[:<image_size>] [<initrd_addr>:<initrd_size>] [<fdt_address>] bootefi bootmgr [<fdt_addr>] bootefi hello [<fdt_addr>] bootefi selftest [<fdt_addr>] @@ -44,6 +44,16 @@ command sequence to run a UEFI application might look like load mmc 0:1 $kernel_addr_r /EFI/grub/grubaa64.efi bootefi $kernel_addr_r $fdt_addr_r +or + +:: + + setenv bootargs root=/dev/vda1 + load mmc 0:1 $fdt_addr_r dtb + load mmc 0:1 $kernel_addr_r vmlinux + load mmc 0:1 $initrd_addr_r intird + bootefi $kernel_addr_r $initrd_addr_r:$filesize $fdt_addr_r + The last UEFI binary loaded defines the image file path in the loaded image protocol. @@ -51,21 +61,34 @@ The value of the environment variable *bootargs* is converted from UTF-8 to UTF-16 and passed as load options in the loaded image protocol to the UEFI binary. +.. note:: + + The bootefi command accepts one to three arguments. + If the second argument contains a colon ':', it is assumed to specify the + initial RAM disk. + image_addr Address of the UEFI binary. -fdt_addr - Address of the device-tree or '-'. If no address is specifiy, the - environment variable $fdt_addr is used as first fallback, the address of - U-Boot's internal device-tree $fdtcontroladdr as second fallback. - When using ACPI no device-tree shall be specified. - image_size Size of the UEFI binary file. This argument is only needed if *image_addr* does not match the address of the last loaded UEFI binary. In this case a memory device path will be used as image file path in the loaded image protocol. +initrd_addr + Address of the Linux initial RAM disk or '-'. If no address is specified, + no RAM disk is used when booting. + +initrd_size + Size of the Linux initial RAM disk. + +fdt_addr + Address of the device-tree or '-'. If no address is specified, the + environment variable $fdt_addr is used as first fallback, the address of + U-Boot's internal device-tree $fdtcontroladdr as second fallback. + When using ACPI no device-tree shall be specified. + Note UEFI binaries that are contained in FIT images are launched via the *bootm* command. diff --git a/doc/usage/cmd/i3c.rst b/doc/usage/cmd/i3c.rst new file mode 100644 index 00000000000..922fa3ea37c --- /dev/null +++ b/doc/usage/cmd/i3c.rst @@ -0,0 +1,146 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. index:: + single: i3c (command) + +i3c command +=========== + +Synopsis +-------- + +:: + + i3c <host_controller> + i3c current + i3c list + i3c device_list + i3c write <mem_addr> <length> <device_number> + i3c read <mem_addr> <length> <device_number> + +Description +----------- + +The ``i3c`` command is used to probe the i3c host controller and perform +read and write operations on the connected i3c devices. + +i3c current +------------ + +Display the currently selected i3c host controller. + +i3c list +--------- + +List all the i3c hosts defined in the device-tree. + +i3c device_list +---------------- + +List all the i3c devices' device number, static address, dynamic address, +PID, BCR, DCR, Max Write Speed, and Max Read Speed of the probed i3c host +controller. + +i3c write +---------- + +Perform a write operation from memory to the connected i3c device. The data +is read from a specified memory address and written to the selected i3c +device, which is identified by its device number. + +You need to provide the memory address (``mem_addr``), the length of data +to be written (``length``), and the device number (``device_number``). The +data in memory will be transferred to the device in the specified order. + +i3c read +--------- + +Perform a read operation from the connected i3c device to memory. The data +is read from the selected i3c device and stored at the specified memory +address. You need to provide the memory address (``mem_addr``), the length +of data to be read (``length``), and the device number (``device_number``). + +The device will send the requested data, which is then written to the memory +location you specified. This operation allows you to retrieve information +from the device and use it in your application. The data is read in the +order specified and can be multiple bytes. + +host_controller + The name of the i3c host controller defined in the device-tree. + +length + The size of the data to be read or written. + +device_number + The device number in the driver model of the device connected to the i3c + host controller. + +mem_addr + The start address in memory from which to read or write the data. + +Examples +-------- + +Probe the ``i3c0`` controller:: + + => i3c i3c0 + +Display the current i3c host controller:: + + => i3c current + +Check the device number and PID of the connected devices:: + + => i3c device_list + +Perform write operations on the connected i3c device (device 0) from memory:: + + => i3c write 0x1000 4 0 + + This command reads 4 bytes of data from memory starting at address + ``0x1000`` and writes them to device 0, which is identified by its device + number in the driver model. Example data from memory could look like this: + + ``` + Data at 0x1000: 0xAA 0xBB 0xCC 0xDD + ``` + + The bytes `0xAA`, `0xBB`, `0xCC`, and `0xDD` will be written to device 0. + +Perform a read operation from device 0 to memory (multiple bytes):: + + => i3c read 0x1000 4 0 + + This command reads 4 bytes of data from device 0 and writes them to + memory starting at address ``0x1000``. + + Example output after reading 4 bytes from device 0: + + ``` + i3c Read: + 00000000 AA BB CC DD + ``` + + The bytes `0xAA`, `0xBB`, `0xCC`, and `0xDD` are read from device 0 + and written to memory at address `0x1000`. + +Configuration +------------- + +The ``i3c`` command is only available if CONFIG_CMD_I3C=y. + +Return value +------------ + +If the command succeeds, the return value ``$?`` is set to 0. If an error +occurs, the return value ``$?`` is set to 1. + +Note +---- + +When specifying the data to be written to the i3c device (for example, with +the ``i3c write`` command), the data can be provided in either uppercase +or lowercase hexadecimal format. Both are valid and will be processed +correctly. Similarly, when reading data with ``i3c read``, the data will be +retrieved in the specified length and can include multiple bytes, all +formatted in the same way.
\ No newline at end of file diff --git a/doc/usage/cmd/sntp.rst b/doc/usage/cmd/sntp.rst index d97f83053f7..2046828130d 100644 --- a/doc/usage/cmd/sntp.rst +++ b/doc/usage/cmd/sntp.rst @@ -12,7 +12,7 @@ Synopsis :: sntp [serverip] - sntp [servername] # NET_LWIP=y && CMD_DNS=y only + sntp [servername] # NET_LWIP=y && DNS=y only Description @@ -27,8 +27,8 @@ The address of the NTP server does not need to be given if the DHCP server provides one. The legacy network stack (`CONFIG_NET=y`) can only use the first NTP server provided in the `ntp-servers` DHCP option. -When the network stack is lwIP (`CONFIG_NET_LWIP=y`) and the dns command -is enabled (`CONFIG_CMD_DNS=y`), then the sntp command accepts a server +When the network stack is lwIP (`CONFIG_NET_LWIP=y`) and DNS resolution +is enabled (`CONFIG_DNS=y`), then the sntp command accepts a server name as an argument. The network time is sent as UTC. So, if you want to set the RTC to any local @@ -61,7 +61,7 @@ Examples => date Date: 2025-06-16 (Monday) Time: 17:19:57 -With `CONFIG_NET_LWIP=y` and `CONFIG_CMD_DNS=y`: +With `CONFIG_NET_LWIP=y` and `CONFIG_DNS=y`: :: diff --git a/doc/usage/cmd/wget.rst b/doc/usage/cmd/wget.rst index 06df2842549..8feda0248b2 100644 --- a/doc/usage/cmd/wget.rst +++ b/doc/usage/cmd/wget.rst @@ -38,7 +38,7 @@ address memory address for the data downloaded host - IP address (or host name if `CONFIG_CMD_DNS` is enabled) of the HTTP + IP address (or host name if `CONFIG_DNS` is enabled) of the HTTP server, defaults to the value of environment variable *serverip*. path diff --git a/doc/usage/index.rst b/doc/usage/index.rst index b9de87a6ed9..3a48521d5d5 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -82,6 +82,7 @@ Shell commands cmd/if cmd/itest cmd/imxtract + cmd/i3c cmd/load cmd/loadb cmd/loadm diff --git a/drivers/Kconfig b/drivers/Kconfig index a073230c26d..0b0c610e629 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -56,6 +56,8 @@ source "drivers/hwspinlock/Kconfig" source "drivers/i2c/Kconfig" +source "drivers/i3c/Kconfig" + source "drivers/input/Kconfig" source "drivers/iommu/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 3c0ad17138f..7560008a842 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_$(PHASE_)DRIVERS_MISC) += misc/ obj-$(CONFIG_$(PHASE_)SYSRESET) += sysreset/ obj-$(CONFIG_$(PHASE_)FIRMWARE) +=firmware/ obj-$(CONFIG_$(PHASE_)I2C) += i2c/ +obj-$(CONFIG_$(PHASE_)I3C) += i3c/ obj-$(CONFIG_$(PHASE_)INPUT) += input/ obj-$(CONFIG_$(PHASE_)LED) += led/ obj-$(CONFIG_$(PHASE_)MMC) += mmc/ diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index 85addfe32a2..b823490d6d5 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -195,8 +195,9 @@ static int button_qcom_pmic_bind(struct udevice *parent) continue; } + label = ofnode_get_name(node); ret = device_bind_driver_to_node(parent, "qcom_pwrkey", - ofnode_get_name(node), + label, node, &dev); if (ret) { printf("Failed to bind %s! %d\n", label, ret); diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 61ffa4179a0..858f828e537 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index e1ddd02f356..242740a4b00 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include <log.h> +#include <wait_bit.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/system.h> #include <clk-uclass.h> #include <dm.h> #include <dm/lists.h> @@ -27,21 +30,33 @@ struct socfpga_clk_plat { */ static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val) { + void __iomem *base = plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); - cm_wait_for_fsm(); + + wait_for_bit_le32(base + CLKMGR_STAT, + CLKMGR_STAT_BUSY, false, 20000, false); } static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val) { + void __iomem *base = plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); - cm_wait_for_fsm(); + + wait_for_bit_le32(base + CLKMGR_STAT, + CLKMGR_STAT_BUSY, false, 20000, false); } /* function to write the ctrl register which requires a poll of the busy bit */ static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val) { + void __iomem *base = plat->regs; + CM_REG_WRITEL(plat, val, CLKMGR_CTRL); - cm_wait_for_fsm(); + + wait_for_bit_le32(base + CLKMGR_STAT, + CLKMGR_STAT_BUSY, false, 20000, false); } #define MEMBUS_MAINPLL 0 @@ -238,6 +253,7 @@ static void clk_basic_init(struct udevice *dev, { struct socfpga_clk_plat *plat = dev_get_plat(dev); u32 vcocalib; + uintptr_t base_addr = (uintptr_t)plat->regs; if (!cfg) return; @@ -302,7 +318,8 @@ static void clk_basic_init(struct udevice *dev, /* Membus programming for peripll */ membus_pll_configs(plat, MEMBUS_PERPLL); - cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + wait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT), + CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false); /* Configure ping pong counters in altera group */ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR); @@ -337,6 +354,18 @@ static void clk_basic_init(struct udevice *dev, CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST, CLKMGR_ALT_EXTCNTRST_ALLCNTRST); +#ifdef COUNTER_FREQUENCY_REAL + u32 cntfrq = COUNTER_FREQUENCY_REAL; + u32 counter_freq = 0; + + /* Update with accurate clock frequency */ + if (current_el() == 3) { + asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); + asm volatile("mrs %0, cntfrq_el0" : "=r" (counter_freq)); + debug("Counter freq = 0x%x\n", counter_freq); + } +#endif + /* Out of boot mode */ clk_write_ctrl(plat, CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h index cd68ebc4387..b3e8841a512 100644 --- a/drivers/clk/altera/clk-agilex.h +++ b/drivers/clk/altera/clk-agilex.h @@ -10,6 +10,8 @@ #include <linux/bitops.h> #endif +#define COUNTER_FREQUENCY_REAL 400000000 + #define CM_REG_READL(plat, reg) \ readl((plat)->regs + (reg)) diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index a5186f885f0..0542b066788 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -315,7 +315,8 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent) { struct clk_main *main = to_clk_main(clk); void __iomem *reg = main->reg; - unsigned int tmp, index; + unsigned int tmp; + int index; index = at91_clk_mux_val_to_index(main->clk_mux_table, main->num_parents, AT91_CLK_ID_TO_DID(parent->id)); diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index cdc5271fa83..530205b8c6b 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -335,8 +335,8 @@ struct clk *at91_clk_sama7g5_register_master(void __iomem *base, { struct clk_master *master; struct clk *clk; - u32 val, index; - int ret; + u32 val; + int ret, index; if (!base || !name || !num_parents || !parent_names || !mux_table || !clk_mux_table || id > MASTER_MAX_ID) diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 6d6f12578db..3fde8ea7138 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -74,8 +74,8 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc, int num_parents) { struct clk *clk; - int ret = -ENOMEM; - u32 val, i; + int ret = -ENOMEM, i; + u32 val; if (!sckc || !name || !parent_names || num_parents != 2) return ERR_PTR(-EINVAL); @@ -99,8 +99,10 @@ static struct clk *at91_sam9x60_clk_register_td_slck(struct sam9x60_sckc *sckc, clk = &sckc->clk; ret = clk_register(clk, UBOOT_DM_CLK_AT91_SAM9X60_TD_SLCK, name, parent_names[val]); - if (ret) + if (ret) { + i--; goto free; + } return clk; diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 3aa751bf4e4..7de4e688f03 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -192,7 +192,7 @@ static int exynos7420_clk_top0_probe(struct udevice *dev) static ulong exynos7420_peric1_get_rate(struct clk *clk) { struct clk in_clk; - unsigned int ret; + int ret; unsigned long freq = 0; switch (clk->id) { diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 7ec78dc3a80..f9fcec18f9f 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -409,6 +409,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, default: pr_err("%s: Unknown pll type for pll clk %s\n", __func__, name); + kfree(pll); return ERR_PTR(-EINVAL); }; diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index ea33bfd3239..60ab2cb379e 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -92,7 +92,8 @@ int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong ra void __iomem *reg, const u32 mask, const struct clk_div_table *table, char *name) { - u32 value = 0, div = 0; + u32 div; + int value; div = DIV_ROUND_CLOSEST(parent_rate, rate); value = rcar_clk_get_table_val(table, div); @@ -101,7 +102,7 @@ int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong ra clrsetbits_le32(reg, mask, field_prep(mask, value)); - debug("%s[%i] %s clk: parent=%i div=%u rate=%lu => val=%u\n", + debug("%s[%i] %s clk: parent=%i div=%u rate=%lu => val=%d\n", __func__, __LINE__, name, parent, div, rate, value); return 0; diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index 06f20895acc..d58557ff56d 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -1535,6 +1535,7 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) /* Might occur in cru assigned-clocks, can be ignored here */ case ACLK_BUS_VOPGL_ROOT: case BCLK_EMMC: + case CLK_REF_PCIE_INNER_PHY: case XIN_OSC0_DIV: ret = 0; break; diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index e84a0943a94..125b08ee832 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -2168,6 +2168,8 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) case CLK_CPLL_DIV10: case FCLK_DDR_CM0_CORE: case ACLK_PHP_ROOT: + case CLK_REF_PCIE0_PHY: + case CLK_REF_PCIE1_PHY: ret = 0; break; #ifndef CONFIG_SPL_BUILD diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index a0ae89d0912..858f122db1a 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -309,7 +309,7 @@ clk_stm32_register_composite(struct udevice *dev, gate_ops = &clk_stm32_gate_ops; } - clk = clk_register_composite(NULL, cfg->name, + clk = clk_register_composite(dev, cfg->name, parent_names, num_parents, mux_clk, mux_ops, div_clk, div_ops, diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4836bddd93b..950630453f9 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -201,6 +201,10 @@ static int cpu_imx_get_temp(struct cpu_imx_plat *plat) __weak u32 get_cpu_temp_grade(int *minc, int *maxc) { + if (minc && maxc) { + *minc = 0; + *maxc = 95; + } return 0; } diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index d26f87364f9..0d58e3910fe 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -10,4 +10,6 @@ source "drivers/crypto/aspeed/Kconfig" source "drivers/crypto/nuvoton/Kconfig" +source "drivers/crypto/tegra/Kconfig" + endmenu diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 2bd99fc2763..e4a4482b7f3 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -10,3 +10,4 @@ obj-y += fsl/ obj-y += hash/ obj-y += aspeed/ obj-y += nuvoton/ +obj-y += tegra/ diff --git a/drivers/crypto/tegra/Kconfig b/drivers/crypto/tegra/Kconfig new file mode 100644 index 00000000000..b027609307b --- /dev/null +++ b/drivers/crypto/tegra/Kconfig @@ -0,0 +1,7 @@ +config TEGRA_AES + bool "Support the Tegra AES" + depends on DM_AES + help + This provides a means to encrypt and decrypt data using the Tegra + Bit Stream Engine for Video/Audio. Also may provide a mean to + encrypt/decrypt/sign using already loaded device SBK. diff --git a/drivers/crypto/tegra/Makefile b/drivers/crypto/tegra/Makefile new file mode 100644 index 00000000000..a118350fd11 --- /dev/null +++ b/drivers/crypto/tegra/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_$(PHASE_)TEGRA_AES) += tegra_aes.o diff --git a/drivers/crypto/tegra/tegra_aes.c b/drivers/crypto/tegra/tegra_aes.c new file mode 100644 index 00000000000..7b374c757ba --- /dev/null +++ b/drivers/crypto/tegra/tegra_aes.c @@ -0,0 +1,591 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for NVIDIA Tegra AES hardware engine residing inside the Bit Stream Engine + * for Video (BSEV) hardware block and Bit Stream Engine for Audio (BSEA). + * + * The programming sequence for this engine is with the help of commands which travel + * via a command queue residing between the CPU and the BSEV/BSEA block. + * + * The hardware key table length is 64 bytes and each key slot divided as follows: + * 1. Key - 32 bytes + * 2. Original IV - 16 bytes + * 3. Updated IV - 16 bytes + * + * The engine has 4 slots in T20/T30 in which 0th contains SBK loaded by bootrom, + * vendor bootloaders tend to clear this slot so that anything booted after can't + * use the SBK. This is relevant for U-Boot's chainloaded from these vendor bootloaders. + * + * Copyright (c) 2010-2011, NVIDIA Corporation + * Copyright (c) 2025, Ion Agorria. + */ + +#include <dm.h> +#include <asm/io.h> +#include <malloc.h> +#include <time.h> +#include <linux/delay.h> +#include <clk.h> +#include <reset.h> +#include <uboot_aes.h> + +#include <asm/arch-tegra/crypto.h> +#include <asm/arch-tegra/fuse.h> + +/* Make sure pointers will fit register size for AES engine */ +static_assert(sizeof(void *) == sizeof(u32)); + +#define IRAM_BASE 0x40000000 + +#define TEGRA_AES_DMA_BUFFER_SIZE (0x4000 / AES_BLOCK_LENGTH) +#define TEGRA_AES_HW_MAX_KEY_LENGTH AES256_KEY_LENGTH +#define TEGRA_AES_HW_TABLE_LENGTH (TEGRA_AES_HW_MAX_KEY_LENGTH + AES_BLOCK_LENGTH * 2) +#define TEGRA_AES_IRAM_MAX_ADDR (IRAM_BASE | TEGRA_AES_KEYTABLEADDR_FIELD) + +#define TEGRA_AES_BUSY_TIMEOUT_MS 1000 + +/* Registers */ +#define TEGRA_AES_ICMDQUE_WR 0x000 +#define TEGRA_AES_CMDQUE_CONTROL 0x008 +#define TEGRA_AES_INTR_STATUS 0x018 +#define TEGRA_AES_INT_ENB 0x040 +#define TEGRA_AES_BSE_CFG 0x044 +#define TEGRA_AES_IRAM_ACCESS_CFG 0x0a0 +#define TEGRA_AES_SECURE_DEST_ADDR 0x100 +#define TEGRA_AES_SECURE_INPUT_SELECT 0x104 +#define TEGRA_AES_SECURE_CONFIG 0x108 +#define TEGRA_AES_SECURE_CONFIG_EXT 0x10c + +/* Register field macros */ +#define TEGRA_AES_ENGINE_BUSY_FIELD BIT(0) +#define TEGRA_AES_ICQ_EMPTY_FIELD BIT(3) +#define TEGRA_AES_DMA_BUSY_FIELD BIT(23) +#define TEGRA_AES_SECURE_KEY_SCH_DIS_FIELD BIT(15) +#define TEGRA_AES_KEYTABLEADDR_FIELD (BIT(17) - 1) +#define TEGRA_AES_SECURE_KEY_INDEX_SHIFT 20 +#define TEGRA_AES_SECURE_KEY_INDEX_FIELD (0x1f << TEGRA_AES_SECURE_KEY_INDEX_SHIFT) +#define TEGRA_AES_SECURE_CTR_CNT_SHIFT 16 +#define TEGRA_AES_SECURE_CTR_CNT_FIELD (0xffff << TEGRA_AES_SECURE_CTR_CNT_SHIFT) +#define TEGRA_AES_BSE_MODE_FIELD 0x1f +#define TEGRA_AES_BSE_LITTLE_ENDIAN_FIELD BIT(10) +#define TEGRA_AES_CMDQ_OPCODE_SHIFT 26 +#define TEGRA_AES_CMDQ_CTRL_ICMDQEN_FIELD BIT(1) +#define TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD BIT(4) +#define TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD BIT(5) +#define TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT 28 +#define TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT 16 +#define TEGRA_AES_SECURE_INPUT_IV_FIELD BIT(10) +#define TEGRA_AES_SECURE_INPUT_HASH_ENB_FIELD BIT(2) +#define TEGRA_AES_SECURE_CORE_SEL_SHIFT 9 +#define TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT 7 +#define TEGRA_AES_SECURE_XOR_POS_SHIFT 3 +#define TEGRA_AES_INT_ERROR_MASK 0x6ff000 + +/* Commands for BSEV/BSEA */ +#define TEGRA_AES_CMD_BLKSTARTENGINE 0x0e +#define TEGRA_AES_CMD_DMASETUP 0x10 +#define TEGRA_AES_CMD_DMACOMPLETE 0x11 +#define TEGRA_AES_CMD_SETTABLE 0x15 + +/* Flags for mode */ +#define TEGRA_AES_MODE_ENCRYPT BIT(0) +#define TEGRA_AES_MODE_CBC BIT(1) +#define TEGRA_AES_MODE_UPDATE_IV BIT(2) +#define TEGRA_AES_MODE_HASH BIT(3) + +struct tegra_aes_priv { + void *regs; + void *iram_addr; + + struct reset_ctl reset_ctl; + struct reset_ctl reset_ctl_vde; + + struct clk *clk; + struct clk *clk_parent; + + u8 current_key_size; + bool sbk_available; +}; + +static bool tegra_aes_is_busy(struct tegra_aes_priv *priv, bool dma_wait) +{ + u32 value = readl(priv->regs + TEGRA_AES_INTR_STATUS); + bool engine_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD; + bool non_empty_queue = !(value & TEGRA_AES_ICQ_EMPTY_FIELD); + bool dma_busy = dma_wait && (value & TEGRA_AES_DMA_BUSY_FIELD); + + log_debug("%s - e:%d q:%d dma:%d\n", __func__, engine_busy, non_empty_queue, dma_busy); + + return engine_busy || non_empty_queue || dma_busy; +} + +static u32 tegra_aes_check_error(struct tegra_aes_priv *priv) +{ + u32 value = readl(priv->regs + TEGRA_AES_INTR_STATUS) & TEGRA_AES_INT_ERROR_MASK; + + if (value) { + writel(TEGRA_AES_INT_ERROR_MASK, priv->regs + TEGRA_AES_INTR_STATUS); + log_debug("%s 0x%x\n", __func__, value); + } + + return value; +} + +static int tegra_aes_wait_for_idle_dma(struct tegra_aes_priv *priv, bool dma_wait) +{ + ulong start = get_timer(0); + + while (tegra_aes_is_busy(priv, dma_wait)) { + if (get_timer(start) > TEGRA_AES_BUSY_TIMEOUT_MS) { + log_err("%s: TIMEOUT!!!\n", __func__); + break; + } + mdelay(5); + } + + if (tegra_aes_check_error(priv)) + return -1; + + return 0; +} + +static int tegra_aes_wait_for_idle(struct tegra_aes_priv *priv) +{ + return tegra_aes_wait_for_idle_dma(priv, 1); +} + +static int tegra_aes_configure(struct tegra_aes_priv *priv) +{ + u32 value; + + if (tegra_aes_wait_for_idle(priv)) + return -1; + + /* IRAM config */ + writel(0, priv->regs + TEGRA_AES_IRAM_ACCESS_CFG); + + /* Reset interrupts bits, or engine will hang on next operation */ + writel(0xFFFFFFFF, priv->regs + TEGRA_AES_INTR_STATUS); + + /* Set interrupts */ + writel(0, priv->regs + TEGRA_AES_INT_ENB); + + /* Configure CMDQUE */ + value = readl(priv->regs + TEGRA_AES_CMDQUE_CONTROL); + value |= TEGRA_AES_CMDQ_CTRL_SRC_STM_SEL_FIELD | + TEGRA_AES_CMDQ_CTRL_DST_STM_SEL_FIELD | + TEGRA_AES_CMDQ_CTRL_ICMDQEN_FIELD; + writel(value, priv->regs + TEGRA_AES_CMDQUE_CONTROL); + + value = readl(priv->regs + TEGRA_AES_SECURE_CONFIG_EXT); + value &= ~TEGRA_AES_SECURE_CTR_CNT_FIELD; + writel(value, priv->regs + TEGRA_AES_SECURE_CONFIG_EXT); + + /* Configure BSE */ + value = readl(priv->regs + TEGRA_AES_BSE_CFG); + value &= ~TEGRA_AES_BSE_MODE_FIELD; + value |= TEGRA_AES_BSE_LITTLE_ENDIAN_FIELD; + writel(value, priv->regs + TEGRA_AES_BSE_CFG); + + return 0; +} + +static int tegra_aes_select_key_slot(struct tegra_aes_priv *priv, u32 key_size, u8 slot) +{ + if (tegra_aes_wait_for_idle(priv)) + return -1; + + if (key_size < (AES128_KEY_LENGTH * 8) || + key_size > (TEGRA_AES_HW_MAX_KEY_LENGTH * 8)) + return -EINVAL; + + priv->current_key_size = key_size; + + /* Select the key slot */ + u32 value = readl(priv->regs + TEGRA_AES_SECURE_CONFIG); + + value &= ~TEGRA_AES_SECURE_KEY_INDEX_FIELD; + value |= (slot << TEGRA_AES_SECURE_KEY_INDEX_SHIFT); + writel(value, priv->regs + TEGRA_AES_SECURE_CONFIG); + + return 0; +} + +static int tegra_aes_call_engine(struct tegra_aes_priv *priv, u8 *src, u8 *dst, + u32 nblocks, u32 mode) +{ + u32 value; + const u32 ICMDQ_LENGTH = 4; + u32 cmdq[ICMDQ_LENGTH]; + + log_debug("%s: 0x%p -> 0x%p blocks %d mode 0x%x\n", __func__, + src, dst, nblocks, mode); + + if (!nblocks) { + log_warning("%s: called with 0 blocks!\n", __func__); + return -1; + } + + if (tegra_aes_configure(priv)) + return -1; + + /* Configure Secure Input */ + value = 1 << TEGRA_AES_SECURE_INPUT_ALG_SEL_SHIFT | + priv->current_key_size << TEGRA_AES_SECURE_INPUT_KEY_LEN_SHIFT; + + if (mode & TEGRA_AES_MODE_UPDATE_IV) + value |= TEGRA_AES_SECURE_INPUT_IV_FIELD; + if (mode & TEGRA_AES_MODE_HASH) + value |= TEGRA_AES_SECURE_INPUT_HASH_ENB_FIELD; + if (mode & TEGRA_AES_MODE_CBC) { + value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 2 : 3) << + TEGRA_AES_SECURE_XOR_POS_SHIFT; + value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 2 : 3) << + TEGRA_AES_SECURE_VCTRAM_SEL_SHIFT; + value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 1 : 0) << + TEGRA_AES_SECURE_CORE_SEL_SHIFT; + } else { + /* ECB */ + value |= ((mode & TEGRA_AES_MODE_ENCRYPT) ? 1 : 0) << + TEGRA_AES_SECURE_CORE_SEL_SHIFT; + } + + writel(value, priv->regs + TEGRA_AES_SECURE_INPUT_SELECT); + + /* Set destination address (doing in-place at IRAM) */ + writel((u32)priv->iram_addr, priv->regs + TEGRA_AES_SECURE_DEST_ADDR); + + /* Copy src data to IRAM */ + if (src != priv->iram_addr) + memcpy(priv->iram_addr, src, nblocks * AES_BLOCK_LENGTH); + + /* Run ICMD commands */ + cmdq[0] = TEGRA_AES_CMD_DMASETUP << TEGRA_AES_CMDQ_OPCODE_SHIFT; + cmdq[1] = (u32)priv->iram_addr; + cmdq[2] = TEGRA_AES_CMD_BLKSTARTENGINE << TEGRA_AES_CMDQ_OPCODE_SHIFT | (nblocks - 1); + cmdq[3] = TEGRA_AES_CMD_DMACOMPLETE << TEGRA_AES_CMDQ_OPCODE_SHIFT; + + for (int i = 0; i < ICMDQ_LENGTH; i++) { + tegra_aes_wait_for_idle_dma(priv, (ICMDQ_LENGTH - 1) == i); + writel(cmdq[i], priv->regs + TEGRA_AES_ICMDQUE_WR); + } + + if (tegra_aes_wait_for_idle(priv)) + return -1; + + /* Put the result from IRAM to destination if not hashing */ + if (dst != priv->iram_addr && !(mode & TEGRA_AES_MODE_HASH)) + memcpy(dst, priv->iram_addr, nblocks * AES_BLOCK_LENGTH); + + return 0; +} + +static int tegra_aes_process_blocks(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks, u32 mode) +{ + struct tegra_aes_priv *priv = dev_get_priv(dev); + + log_debug("%s: 0x%p -> 0x%p blocks %d mode 0x%x\n", + __func__, src, dst, num_aes_blocks, mode); + + if (!num_aes_blocks) { + log_warning("%s: called with 0 blocks!\n", __func__); + return -1; + } + + /* Load initial IV if CBC mode */ + if (mode & TEGRA_AES_MODE_CBC) { + if (tegra_aes_call_engine(priv, iv, priv->iram_addr, 1, TEGRA_AES_MODE_CBC)) + return -1; + + /* Add update IV flag */ + mode |= TEGRA_AES_MODE_UPDATE_IV; + } + + /* Process blocks by calling engine several times per dma buffer size */ + while (num_aes_blocks > 0) { + u32 blocks = min(num_aes_blocks, (u32)TEGRA_AES_DMA_BUFFER_SIZE); + + if (tegra_aes_call_engine(priv, src, dst, blocks, mode)) + return -1; + + num_aes_blocks -= blocks; + src += blocks * AES_BLOCK_LENGTH; + dst += blocks * AES_BLOCK_LENGTH; + } + + return 0; +} + +static int tegra_aes_ops_available_key_slots(struct udevice *dev) +{ + return 4; /* 4 slots in Tegra20 and Tegra30 */ +} + +static int tegra_aes_ops_select_key_slot(struct udevice *dev, u32 key_size, u8 slot) +{ + struct tegra_aes_priv *priv = dev_get_priv(dev); + + if (slot == TEGRA_AES_SLOT_SBK && !priv->sbk_available) { + log_warning("%s: SBK not available!\n", __func__); + return -1; + } + + return tegra_aes_select_key_slot(priv, key_size, slot); +} + +static int tegra_aes_ops_set_key_for_key_slot(struct udevice *dev, u32 key_size, + u8 *key, u8 slot) +{ + struct tegra_aes_priv *priv = dev_get_priv(dev); + const u8 SUBCMD_CRYPTO_TABLE_SEL = 0x3; + const u8 SUBCMD_KEY_TABLE_SEL = 0x8; + const u8 CMDQ_KEYTABLEADDR_SHIFT = 0; + const u8 CMDQ_KEYTABLEID_SHIFT = 17; + const u8 CMDQ_TABLESEL_SHIFT = 24; + u32 value, addr; + + log_debug("%s: slot %d\n", __func__, slot); + + if (tegra_aes_configure(priv)) + return -1; + + if (key_size < (AES128_KEY_LENGTH * 8) || + key_size > (TEGRA_AES_HW_MAX_KEY_LENGTH * 8)) + return -EINVAL; + + if (slot == TEGRA_AES_SLOT_SBK) + log_debug("%s: SBK slot being set!\n", __func__); + + /* Clear and copy data to IRAM */ + memset(priv->iram_addr, 0, TEGRA_AES_HW_TABLE_LENGTH); + memcpy(priv->iram_addr, key, key_size / 8); + + /* Mask the addr */ + addr = ((u32)priv->iram_addr) & TEGRA_AES_KEYTABLEADDR_FIELD; + + /* Command for engine to load AES key from IRAM */ + value = TEGRA_AES_CMD_SETTABLE << TEGRA_AES_CMDQ_OPCODE_SHIFT | + SUBCMD_CRYPTO_TABLE_SEL << CMDQ_TABLESEL_SHIFT | + (SUBCMD_KEY_TABLE_SEL | slot) << CMDQ_KEYTABLEID_SHIFT | + addr << CMDQ_KEYTABLEADDR_SHIFT; + writel(value, priv->regs + TEGRA_AES_ICMDQUE_WR); + + return tegra_aes_wait_for_idle(priv); +} + +static int tegra_aes_ops_aes_ecb_encrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + return tegra_aes_process_blocks(dev, NULL, src, dst, num_aes_blocks, + TEGRA_AES_MODE_ENCRYPT); +} + +static int tegra_aes_ops_aes_ecb_decrypt(struct udevice *dev, u8 *src, u8 *dst, + u32 num_aes_blocks) +{ + return tegra_aes_process_blocks(dev, NULL, src, dst, num_aes_blocks, 0); +} + +static int tegra_aes_ops_aes_cbc_encrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + return tegra_aes_process_blocks(dev, iv, src, dst, num_aes_blocks, + TEGRA_AES_MODE_CBC | TEGRA_AES_MODE_ENCRYPT); +} + +static int tegra_aes_ops_aes_cbc_decrypt(struct udevice *dev, u8 *iv, u8 *src, + u8 *dst, u32 num_aes_blocks) +{ + return tegra_aes_process_blocks(dev, iv, src, dst, num_aes_blocks, + TEGRA_AES_MODE_CBC); +} + +static void tegra_aes_test_loaded_sbk(struct udevice *dev) +{ + struct tegra_aes_priv *priv = dev_get_priv(dev); + enum fuse_operating_mode opmode = tegra_fuse_get_operation_mode(); + const u8 ZERO_KEY_CIPHERTEXT[AES_BLOCK_LENGTH] = { + 0x66, 0xe9, 0x4b, 0xd4, 0xef, 0x8a, 0x2c, 0x3b, + 0x88, 0x4c, 0xfa, 0x59, 0xca, 0x34, 0x2b, 0x2e + }; + + /* Encrypt a zero block, we use ECB so that we only care about SBK and not the IV */ + memset(priv->iram_addr, 0, AES_BLOCK_LENGTH); + tegra_aes_select_key_slot(priv, 128, TEGRA_AES_SLOT_SBK); + tegra_aes_call_engine(priv, priv->iram_addr, priv->iram_addr, 1, TEGRA_AES_MODE_ENCRYPT); + + /* Evaluate the result of engine operation */ + if (!memcmp(priv->iram_addr, AES_ZERO_BLOCK, AES_BLOCK_LENGTH)) { + log_err("%s: engine is not operational! (opmode 0x%x)\n", __func__, opmode); + } else if (!memcmp(priv->iram_addr, ZERO_KEY_CIPHERTEXT, AES_BLOCK_LENGTH)) { + if (opmode == MODE_ODM_PRODUCTION_SECURE) { + log_warning("%s: SBK is zero or is cleared from engine! (opmode 0x%x)\n", + __func__, opmode); + } else { + log_debug("%s - SBK is zero and available! (opmode 0x%x)\n", + __func__, opmode); + priv->sbk_available = true; + } + } else { + if (opmode == MODE_ODM_PRODUCTION_SECURE) { + log_debug("%s: SBK is available! (opmode 0x%x)\n", __func__, opmode); + priv->sbk_available = true; + } else { + log_warning("%s: SBK is not zero and should be! (opmode 0x%x)\n", + __func__, opmode); + } + } +} + +static int tegra_aes_hw_init(struct udevice *dev) +{ + struct tegra_aes_priv *priv = dev_get_priv(dev); + u32 value; + int ret; + + if (priv->clk_parent) { + ret = reset_assert(&priv->reset_ctl_vde); + if (ret) { + log_debug("%s: VDE reset assert failed: %d\n", __func__, ret); + return ret; + } + } + + ret = reset_assert(&priv->reset_ctl); + if (ret) { + log_debug("%s: BSE reset assert failed: %d\n", __func__, ret); + return ret; + } + + if (priv->clk_parent) { + ret = clk_enable(priv->clk_parent); + if (ret) { + log_err("%s: VDE clock enable failed: %d\n", __func__, ret); + return ret; + } + + ret = clk_set_rate(priv->clk_parent, 50 * 1000000); + if (IS_ERR_VALUE(ret)) { + log_err("%s: VDE clock set rate failed: %d\n", __func__, ret); + return ret; + } + } + + ret = clk_enable(priv->clk); + if (ret) { + log_err("%s: BSE clock enable failed: %d\n", __func__, ret); + return ret; + } + + if (priv->clk_parent) { + ret = reset_deassert(&priv->reset_ctl_vde); + if (ret) { + log_err("%s: VDE reset deassert failed: %d\n", __func__, ret); + return ret; + } + } + + ret = reset_deassert(&priv->reset_ctl); + if (ret) { + log_err("%s: BSE reset deassert failed: %d\n", __func__, ret); + return ret; + } + + /* Enable key schedule generation in hardware */ + value = readl(priv->regs + TEGRA_AES_SECURE_CONFIG_EXT); + value &= ~TEGRA_AES_SECURE_KEY_SCH_DIS_FIELD; + writel(value, priv->regs + TEGRA_AES_SECURE_CONFIG_EXT); + + /* Check if SBK is loaded in SBK slot or was erased */ + priv->sbk_available = false; + tegra_aes_test_loaded_sbk(dev); + + return 0; +} + +static int tegra_aes_probe(struct udevice *dev) +{ + struct tegra_aes_priv *priv = dev_get_priv(dev); + fdt_size_t iram_size = 0; + u32 value; + int ret; + + priv->current_key_size = AES128_KEY_LENGTH; + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) { + log_err("%s: Cannot find aes reg address, binding failed\n", __func__); + return -EINVAL; + } + + priv->iram_addr = devfdt_get_addr_size_name_ptr(dev, "iram-buffer", &iram_size); + if (!priv->iram_addr) { + log_debug("%s: Cannot find iram buffer address, binding failed\n", __func__); + return -EINVAL; + } + + if (iram_size < TEGRA_AES_DMA_BUFFER_SIZE * AES_BLOCK_LENGTH) { + log_debug("%s: Unsupported iram buffer size: 0x%x required: 0x%x\n", + __func__, iram_size, TEGRA_AES_DMA_BUFFER_SIZE); + return -EINVAL; + } + + /* Make sure the IRAM address is kept block aligned and accessible for slot loading */ + value = (uint32_t)priv->iram_addr; + if ((value & 0xFFF0000F) != IRAM_BASE || value > TEGRA_AES_IRAM_MAX_ADDR) { + log_debug("%s: iram buffer must be located inside iram,", __func__); + log_debug("AES block aligned and not above 0x%08x, current addr %p\n", + (u32)TEGRA_AES_IRAM_MAX_ADDR, priv->iram_addr); + return -EINVAL; + } + + ret = reset_get_by_name(dev, NULL, &priv->reset_ctl); + if (ret) { + log_debug("%s: failed to get BSE reset: %d\n", __func__, ret); + return ret; + } + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + log_err("%s: failed to get BSE clock: %d\n", __func__, ret); + return ret; + } + + /* VDE clock and reset required by BSEV */ + ret = reset_get_by_name(dev, "vde", &priv->reset_ctl_vde); + if (ret) + log_debug("%s: failed to get VDE reset: %d\n", __func__, ret); + + priv->clk_parent = devm_clk_get(dev, "vde"); + if (IS_ERR(priv->clk_parent)) + log_debug("%s: failed to get BSE clock: %d\n", __func__, ret); + + return tegra_aes_hw_init(dev); +} + +static const struct aes_ops tegra_aes_ops = { + .available_key_slots = tegra_aes_ops_available_key_slots, + .select_key_slot = tegra_aes_ops_select_key_slot, + .set_key_for_key_slot = tegra_aes_ops_set_key_for_key_slot, + .aes_ecb_encrypt = tegra_aes_ops_aes_ecb_encrypt, + .aes_ecb_decrypt = tegra_aes_ops_aes_ecb_decrypt, + .aes_cbc_encrypt = tegra_aes_ops_aes_cbc_encrypt, + .aes_cbc_decrypt = tegra_aes_ops_aes_cbc_decrypt, +}; + +static const struct udevice_id tegra_aes_ids[] = { + { .compatible = "nvidia,tegra20-bsea" }, + { .compatible = "nvidia,tegra20-bsev" }, + { .compatible = "nvidia,tegra30-bsea" }, + { .compatible = "nvidia,tegra30-bsev" }, + { } +}; + +U_BOOT_DRIVER(tegra_aes) = { + .name = "tegra_aes", + .id = UCLASS_AES, + .of_match = tegra_aes_ids, + .probe = tegra_aes_probe, + .ops = &tegra_aes_ops, + .priv_auto = sizeof(struct tegra_aes_priv), +}; diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index c627f16711e..7ed43965be5 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -13,4 +13,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c index 7f2cccb6af2..b36a765a5de 100644 --- a/drivers/ddr/altera/sdram_agilex.c +++ b/drivers/ddr/altera/sdram_agilex.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -72,12 +73,22 @@ int sdram_mmr_init_full(struct udevice *dev) */ /* Configure DDR IO size x16, x32 and x64 mode */ u32 update_value; + u32 reg; update_value = hmc_readl(plat, NIOSRESERVED0); update_value = (update_value & 0xFF) >> 5; - /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */ - update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); + /* Read ACF from boot_scratch_cold_8 register bit[18]*/ + reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + reg = ((reg & SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK) + >> SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT); + + /* bit-2 of DDRIOCTRL: Configure DDR data rate 0-Half-rate 1-Quarter-rate */ + clrsetbits_le32(&update_value, + DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK, + reg << DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_SHIFT); + hmc_ecc_writel(plat, update_value, DDRIOCTRL); /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */ @@ -114,20 +125,6 @@ int sdram_mmr_init_full(struct udevice *dev) printf("DDR: %lld MiB\n", gd->ram_size >> 20); - /* This enables nonsecure access to DDR */ - /* mpuregion0addr_limit */ - FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, - FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); - FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); - - /* nonmpuregion0addr_limit */ - FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, - FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); - - /* Enable mpuregion0enable and nonmpuregion0enable */ - FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, - FW_MPU_DDR_SCR_EN_SET); - u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); /* Enable or disable the DDR ECC */ @@ -157,11 +154,10 @@ int sdram_mmr_init_full(struct udevice *dev) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } - /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */ - writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); - sdram_size_check(&bd); + sdram_set_firewall(&bd); + priv->info.base = bd.bi_dram[0].start; priv->info.size = gd->ram_size; diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c new file mode 100644 index 00000000000..9b3cc5c7b86 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <dm.h> +#include <hang.h> +#include <log.h> +#include <ram.h> +#include <reset.h> +#include <wait_bit.h> +#include <wdt.h> +#include <asm/arch/system_manager.h> +#include <linux/bitfield.h> +#include "iossm_mailbox.h" +#include "sdram_soc64.h" +#include "uibssm_mailbox.h" + +/* NOCPLL register */ +#define SYSMGR_HMC_CLK 0xB4 +#define SYSMGR_HMC_CLK_NOCPLL BIT(8) + +/* MPFE NOC registers */ +#define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50 +#define F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 0x58 +#define SIDEBANDMGR_FLAGOUTSET0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSET0 +#define SIDEBANDMGR_FLAGOUTSTATUS0_REG SOCFPGA_F2SDRAM_MGR_ADDRESS +\ + F2SDRAM_SIDEBAND_FLAGOUTSTATUS0 + +#define SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL BIT(4) +#define SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING BIT(5) + +/* Reset type */ +enum reset_type { + POR_RESET, + WARM_RESET, + COLD_RESET, + NCONFIG, + JTAG_CONFIG, + RSU_RECONFIG +}; + +phys_addr_t io96b_csr_reg_addr[] = { + 0xf8400000, /* IO96B_0 CSR registers address */ + 0xf8800000 /* IO96B_1 CSR registers address */ +}; + +phys_addr_t uib_csr_reg_addr[] = { + 0xf8400000, /* UIB_0 CSR registers address */ + 0xf8410000, /* UIB_1 CSR registers address */ + 0xf8420000, /* UIB_2 CSR registers address */ + 0xf8430000, /* UIB_3 CSR registers address */ + 0xf8440000, /* UIB_4 CSR registers address */ + 0xf8450000, /* UIB_5 CSR registers address */ + 0xf8460000, /* UIB_6 CSR registers address */ + 0xf8470000 /* UIB_7 CSR registers address */ +}; + +static enum reset_type get_reset_type(u32 reg) +{ + return FIELD_GET(ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK, reg); +} + +bool is_ddr_init_hang(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + debug("%s: 0x%x\n", __func__, reg); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK) + return true; + + return false; +} + +void ddr_init_inprogress(bool start) +{ + if (start) + setbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); + else + clrbits_le32(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8, + ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK); +} + +static const char *memory_type_in_use(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + return (plat->mem_type == DDR_MEMORY ? "DDR" : "HBM"); +} + +static bool is_ddr_in_use(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + + return (plat->mem_type == DDR_MEMORY ? true : false); +} + +int populate_ddr_handoff(struct udevice *dev, struct io96b_info *io96b_ctrl, + struct uib_info *uib_ctrl) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + int i; + u8 count = 0; + u32 len = SOC64_HANDOFF_DDR_LEN; + u32 handoff_table[len]; + + /* Read handoff for DDR configuration */ + socfpga_handoff_read((void *)SOC64_HANDOFF_DDR_BASE, handoff_table, len); + + /* Interleaving Mode */ + if (handoff_table[0] & SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK) + plat->multichannel_interleaving = true; + else + plat->multichannel_interleaving = false; + + debug("%s: MPFE-EMIF is in %s mode\n", __func__, + plat->multichannel_interleaving ? "interleaving" : "multichannel"); + + /* Memory type */ + if (handoff_table[2] & SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK) + plat->mem_type = HBM_MEMORY; + else + plat->mem_type = DDR_MEMORY; + + debug("%s: Memory type is %s\n", __func__ + , plat->mem_type ? "HBM" : "DDR"); + + if (plat->mem_type == HBM_MEMORY) { + /* Assign UIB CSR base address if it is valid */ + for (i = 0; i < MAX_UIB_SUPPORTED; i++) { + if (handoff_table[3] & BIT(i)) { + uib_ctrl->uib[count].uib_csr_addr = uib_csr_reg_addr[i]; + debug("%s: UIB 0x%llx CSR enabled\n", __func__ + , uib_ctrl->uib[count].uib_csr_addr); + count++; + } + } + + uib_ctrl->num_instance = count; + debug("%s: returned num_instance 0x%x\n", __func__, uib_ctrl->num_instance); + + /* + * HBM memory size + * 1 UIB channel has 2 pseudo channels + * 1 pseudo channel is 1GB, hence 1 UIB channel is 2GB + */ + uib_ctrl->overall_size = (phys_size_t)uib_ctrl->num_instance * SZ_2G; + + /* UIB ECC status */ + uib_ctrl->ecc_status = handoff_table[4]; + + debug("%s: ECC status 0x%x\n", __func__, uib_ctrl->ecc_status); + } else { + /* Assign IO96B CSR base address if it is valid */ + for (i = 0; i < MAX_IO96B_SUPPORTED; i++) { + if (handoff_table[1] & BIT(i)) { + io96b_ctrl->io96b[i].io96b_csr_addr = io96b_csr_reg_addr[i]; + + debug("%s: IO96B 0x%llx CSR enabled\n", __func__, + io96b_ctrl->io96b[i].io96b_csr_addr); + + count++; + } + } + + io96b_ctrl->num_instance = count; + debug("%s: returned num_instance 0x%x\n", __func__, io96b_ctrl->num_instance); + } + + return 0; +} + +int config_mpfe_sideband_mgr(struct udevice *dev) +{ + struct altera_sdram_plat *plat = dev_get_plat(dev); + u32 reg, mask; + int ret = 0; + + if (plat->multichannel_interleaving) { + mask = SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING; + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, mask); + } else { + mask = SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL; + setbits_le32(SIDEBANDMGR_FLAGOUTSET0_REG, mask); + } + + reg = readl(SIDEBANDMGR_FLAGOUTSTATUS0_REG); + + debug("%s: F2SDRAM_SIDEBAND_FLAGOUTSTATUS0: 0x%x\n", __func__, reg); + + if ((reg & mask) == SIDEBANDMGR_FLAGOUTSET0_REG_INTERLEAVING) + debug("%s: Interleaving bit is set\n", __func__); + else if ((reg & mask) == SIDEBANDMGR_FLAGOUTSET0_REG_MULTICHANNEL) + debug("%s: Multichannel bit is set\n", __func__); + else + ret = -EINVAL; + + return ret; +} + +bool hps_ocram_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK) + return true; + + return false; +} + +bool ddr_ecc_dbe_status(void) +{ + u32 reg = readl(socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_BOOT_SCRATCH_COLD8); + + if (reg & ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK) + return true; + + return false; +} + +int sdram_mmr_init_full(struct udevice *dev) +{ + int i, ret = 0; + struct altera_sdram_plat *plat = dev_get_plat(dev); + struct altera_sdram_priv *priv = dev_get_priv(dev); + struct io96b_info *io96b_ctrl = malloc(sizeof(*io96b_ctrl)); + struct uib_info *uib_ctrl = malloc(sizeof(*uib_ctrl)); + struct bd_info bd = {0}; + bool full_mem_init = false, is_ddr_hang_be4_rst = false; + phys_size_t hw_size; + u32 reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); + enum reset_type reset_t = get_reset_type(reg); + + /* Populating DDR handoff data */ + debug("DDR: Populating DDR handoff\n"); + + ret = populate_ddr_handoff(dev, io96b_ctrl, uib_ctrl); + if (ret) { + printf("DDR: Failed to populate DDR handoff\n"); + + goto err; + } + + debug("%s: Address MPFE 0x%llx\n", memory_type_in_use(dev), plat->mpfe_base_addr); + + /* DDR initialization progress status tracking */ + is_ddr_hang_be4_rst = is_ddr_init_hang(); + + printf("%s: SDRAM init in progress ...\n", memory_type_in_use(dev)); + + ddr_init_inprogress(true); + + /* Configuring MPFE sideband manager registers - multichannel or interleaving*/ + debug("%s: MPFE configuration in progress ...\n", memory_type_in_use(dev)); + + ret = config_mpfe_sideband_mgr(dev); + if (ret) { + printf("%s: Failed to configure multichannel/interleaving mode\n", + memory_type_in_use(dev)); + + goto err; + } + + debug("%s: MPFE configuration completed\n", memory_type_in_use(dev)); + + debug("%s: Waiting for NOCPLL locked ...\n", memory_type_in_use(dev)); + + /* Ensure NOCPLL locked */ + ret = wait_for_bit_le32((const void *)socfpga_get_sysmgr_addr() + SYSMGR_HMC_CLK + , SYSMGR_HMC_CLK_NOCPLL, true, TIMEOUT, false); + if (ret) { + printf("%s: NOCPLL is not locked\n", memory_type_in_use(dev)); + + goto err; + } + + debug("%s: NOCPLL locked\n", memory_type_in_use(dev)); + + debug("%s: Checking calibration...\n", memory_type_in_use(dev)); + + if (is_ddr_in_use(dev)) { + /* Configure if polling is needed for IO96B GEN PLL locked */ + io96b_ctrl->ckgen_lock = false; + + /* Ensure calibration status passing */ + init_mem_cal(io96b_ctrl); + + printf("DDR: Calibration success\n"); + + /* Initiate IOSSM mailbox */ + io96b_mb_init(io96b_ctrl); + + /* DDR type */ + ret = get_mem_technology(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR type\n"); + + goto err; + } + + /* DDR size */ + ret = get_mem_width_info(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR size\n"); + + goto err; + } + } else { + /* Ensure calibration status passing */ + uib_init_mem_cal(uib_ctrl); + + /* Need to trigger re-calibration for HBM DBE */ + if (ddr_ecc_dbe_status()) { + for (i = 0; i < uib_ctrl->num_instance; i++) + uib_ctrl->uib[i].cal_status = false; + + uib_ctrl->overall_cal_status = false; + } + + /* Trigger re-calibration if calibration failed */ + if (!(uib_ctrl->overall_cal_status)) { + printf("HBM: Re-calibration in progress...\n"); + + uib_trig_mem_cal(uib_ctrl); + } + + if (!(uib_ctrl->overall_cal_status)) { + printf("HBM: Retry calibration failed & not able to re-calibrate\n"); + + ret = -EINVAL; + goto err; + } + + debug("HBM: Setting Error Mask Register\n"); + + /* Responder Error Mask Register */ + for (i = 0; i < uib_ctrl->num_instance; i++) { + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET, + UIB_DRAM_SBE_MSK | UIB_INTERNAL_CORR_ERR_MSK, + UIB_DRAM_SBE(0x1) | UIB_INTERNAL_CORR_ERR(0x1)); + + debug("HBM: Error Mask Pseudo CH0 addr: 0x%llx\n", + uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET); + + debug("HBM: Error Mask Pseudo CH0 value: 0x%x\n", + readl(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH0_OFFSET)); + + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET, + UIB_DRAM_SBE_MSK | UIB_INTERNAL_CORR_ERR_MSK, + UIB_DRAM_SBE(0x1) | UIB_INTERNAL_CORR_ERR(0x1)); + + debug("HBM: Error Mask Pseudo CH1 addr: 0x%llx\n", + uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET); + + debug("HBM: Error Mask Pseudo CH1 value: 0x%x\n\n", + readl(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_ERRMSK_PSEUDO_CH1_OFFSET)); + } + + printf("HBM: Calibration success\n"); + } + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + printf("%s: Failed to decode memory node\n", memory_type_in_use(dev)); + + goto err; + } + + if (!is_ddr_in_use(dev)) { + hw_size = uib_ctrl->overall_size; + } else { + /* ECC status */ + ret = ecc_enable_status(io96b_ctrl); + if (ret) { + printf("DDR: Failed to get DDR ECC status\n"); + + goto err; + } + + hw_size = io96b_ctrl->overall_size; + + if (io96b_ctrl->inline_ecc) + hw_size = CALC_INLINE_ECC_HW_SIZE(hw_size); + } + + if (gd->ram_size != hw_size) { + printf("%s: Warning: DRAM size from device tree (%lld MiB)\n", + memory_type_in_use(dev), gd->ram_size >> 20); + printf(" mismatch with hardware (%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size > hw_size) { + printf("%s: Error: DRAM size from device tree is greater\n", + memory_type_in_use(dev)); + printf(" than hardware size.\n"); + + hang(); + } + + printf("%s: %lld MiB\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM"), + gd->ram_size >> 20); + + if (is_ddr_in_use(dev)) { + /* + * Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (io96b_ctrl->ecc_status) { + if (ecc_interrupt_status(io96b_ctrl)) { + if (CONFIG_IS_ENABLED(WDT)) { + struct udevice *wdt; + + printf("DDR: ECC error recover start now\n"); + ret = uclass_first_device_err(UCLASS_WDT, &wdt); + if (ret) { + printf("DDR: Failed to trigger watchdog reset\n"); + hang(); + } + + wdt_expire_now(wdt, 0); + } + hang(); + } + + full_mem_init = hps_ocram_dbe_status() | is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + debug("%s: Needed to fully initialize DDR memory\n", + io96b_ctrl->ddr_type); + + ret = bist_mem_init_start(io96b_ctrl); + if (ret) { + printf("%s: Failed to fully initialize DDR memory\n", + io96b_ctrl->ddr_type); + + goto err; + } + } + } + } else { + debug("HBM: ECC enable status: %d\n", uib_ctrl->ecc_status); + + /* + * Is HPS cold or warm reset? If yes, Skip full memory initialization if ECC + * enabled to preserve memory content + */ + if (uib_ctrl->ecc_status) { + full_mem_init = hps_ocram_dbe_status() | ddr_ecc_dbe_status() | + is_ddr_hang_be4_rst; + if (full_mem_init || !(reset_t == WARM_RESET || reset_t == COLD_RESET)) { + debug("HBM: Needed to fully initialize HBM memory\n"); + + ret = uib_bist_mem_init_start(uib_ctrl); + if (ret) { + printf("HBM: Failed to fully initialize HBM memory\n"); + + goto err; + } + } + } + } + + /* Ensure sanity memory test passing */ + sdram_size_check(&bd); + printf("%s: size check success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + + sdram_set_firewall(&bd); + + printf("%s: firewall init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + + /* Ending DDR driver initialization success tracking */ + ddr_init_inprogress(false); + + printf("%s init success\n", (is_ddr_in_use(dev) ? io96b_ctrl->ddr_type : "HBM")); + +err: + free(io96b_ctrl); + free(uib_ctrl); + + return ret; +} diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 27fbe80ed41..f8fc92060db 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -29,7 +29,10 @@ #define PGTABLE_OFF 0x4000 -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SINGLE_RANK_CLAMSHELL 0xc3c3 +#define DUAL_RANK_CLAMSHELL 0xa5a5 + +#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -258,8 +261,19 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); + u32 reg_ctrlcfg6_value = hmc_readl(plat, CTRLCFG6); + u32 cs_rank = CTRLCFG6_CFG_CS_CHIP(reg_ctrlcfg6_value); + u32 cs_addr_width; + + if (cs_rank == SINGLE_RANK_CLAMSHELL) + cs_addr_width = 0; + else if (cs_rank == DUAL_RANK_CLAMSHELL) + cs_addr_width = 1; + else + cs_addr_width = DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw); + phys_size_t size = (phys_size_t)1 << - (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + (cs_addr_width + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + @@ -398,7 +412,7 @@ static int altera_sdram_of_to_plat(struct udevice *dev) /* These regs info are part of DDR handoff in bitstream */ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) return 0; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; @@ -467,6 +481,7 @@ static const struct udevice_id altera_sdram_ids[] = { { .compatible = "intel,sdr-ctl-agilex" }, { .compatible = "intel,sdr-ctl-n5x" }, { .compatible = "intel,sdr-ctl-agilex5" }, + { .compatible = "intel,sdr-ctl-agilex7m" }, { /* sentinel */ } }; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 183b1a33080..6031cef560e 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -21,6 +21,17 @@ struct altera_sdram_plat { bool dualport; bool dualemif; }; +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +enum memory_type { + DDR_MEMORY = 0, + HBM_MEMORY +}; + +struct altera_sdram_plat { + fdt_addr_t mpfe_base_addr; + bool multichannel_interleaving; + enum memory_type mem_type; +}; #else struct altera_sdram_plat { void __iomem *hmc; @@ -48,6 +59,8 @@ struct altera_sdram_plat { #define RSTHANDSHAKESTAT 0x218 #define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 +#define DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_MSK BIT(2) +#define DDR_HMC_DDRIOCTRL_MPFE_HMCA_DATA_RATE_SHIFT 2 #define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) #define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) #define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) @@ -63,7 +76,7 @@ struct altera_sdram_plat { #define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) #define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) #define DDR_HMC_RSTHANDSHAKE_MASK 0x0000000f -#define DDR_HMC_CORE2SEQ_INT_REQ 0xF +#define DDR_HMC_CORE2SEQ_INT_REQ 0x0000000f #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f @@ -75,6 +88,8 @@ struct altera_sdram_plat { #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c #define CTRLCFG3 0x34 +#define CTRLCFG5 0x3c +#define CTRLCFG6 0x40 #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c #define CALTIMING1 0x80 @@ -89,90 +104,93 @@ struct altera_sdram_plat { #define NIOSRESERVED2 0x118 #define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1f) #define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ - (((x) >> 5) & 0x1F) + (((x) >> 5) & 0x1f) #define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ - (((x) >> 10) & 0xF) + (((x) >> 10) & 0xf) #define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ (((x) >> 14) & 0x3) #define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ (((x) >> 16) & 0x7) #define CTRLCFG0_CFG_MEMTYPE(x) \ - (((x) >> 0) & 0xF) + ((x) & 0xf) #define CTRLCFG0_CFG_DIMM_TYPE(x) \ (((x) >> 4) & 0x7) #define CTRLCFG0_CFG_AC_POS(x) \ (((x) >> 7) & 0x3) #define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ - (((x) >> 9) & 0x1F) + (((x) >> 9) & 0x1f) #define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ - (((x) >> 0) & 0x1F) + ((x) & 0x1f) #define CTRLCFG1_CFG_ADDR_ORDER(x) \ (((x) >> 5) & 0x3) #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ (((x) >> 7) & 0x1) +#define CTRLCFG6_CFG_CS_CHIP(x) \ + ((x) & 0xFFFF) + #define DRAMTIMING0_CFG_TCL(x) \ - (((x) >> 0) & 0x7F) + ((x) & 0x7f) #define CALTIMING0_CFG_ACT_TO_RDWR(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3f) #define CALTIMING0_CFG_ACT_TO_PCH(x) \ - (((x) >> 6) & 0x3F) + (((x) >> 6) & 0x3f) #define CALTIMING0_CFG_ACT_TO_ACT(x) \ - (((x) >> 12) & 0x3F) + (((x) >> 12) & 0x3f) #define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ - (((x) >> 18) & 0x3F) + (((x) >> 18) & 0x3f) #define CALTIMING1_CFG_RD_TO_RD(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3f) #define CALTIMING1_CFG_RD_TO_RD_DC(x) \ - (((x) >> 6) & 0x3F) + (((x) >> 6) & 0x3f) #define CALTIMING1_CFG_RD_TO_RD_DB(x) \ - (((x) >> 12) & 0x3F) + (((x) >> 12) & 0x3f) #define CALTIMING1_CFG_RD_TO_WR(x) \ (((x) >> 18) & 0x3F) #define CALTIMING1_CFG_RD_TO_WR_DC(x) \ - (((x) >> 24) & 0x3F) + (((x) >> 24) & 0x3f) #define CALTIMING2_CFG_RD_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3f) #define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ - (((x) >> 6) & 0x3F) + (((x) >> 6) & 0x3f) #define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ - (((x) >> 12) & 0x3F) + (((x) >> 12) & 0x3f) #define CALTIMING2_CFG_WR_TO_WR(x) \ - (((x) >> 18) & 0x3F) + (((x) >> 18) & 0x3f) #define CALTIMING2_CFG_WR_TO_WR_DC(x) \ - (((x) >> 24) & 0x3F) + (((x) >> 24) & 0x3f) #define CALTIMING3_CFG_WR_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3F) #define CALTIMING3_CFG_WR_TO_RD(x) \ - (((x) >> 6) & 0x3F) + (((x) >> 6) & 0x3f) #define CALTIMING3_CFG_WR_TO_RD_DC(x) \ - (((x) >> 12) & 0x3F) + (((x) >> 12) & 0x3f) #define CALTIMING3_CFG_WR_TO_RD_DB(x) \ - (((x) >> 18) & 0x3F) + (((x) >> 18) & 0x3f) #define CALTIMING3_CFG_WR_TO_PCH(x) \ - (((x) >> 24) & 0x3F) + (((x) >> 24) & 0x3f) #define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ - (((x) >> 0) & 0x3F) + ((x) & 0x3f) #define CALTIMING4_CFG_PCH_TO_VALID(x) \ - (((x) >> 6) & 0x3F) + (((x) >> 6) & 0x3f) #define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ - (((x) >> 12) & 0x3F) + (((x) >> 12) & 0x3f) #define CALTIMING4_CFG_ARF_TO_VALID(x) \ - (((x) >> 18) & 0xFF) + (((x) >> 18) & 0xff) #define CALTIMING4_CFG_PDN_TO_VALID(x) \ - (((x) >> 26) & 0x3F) + (((x) >> 26) & 0x3f) #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ - (((x) >> 0) & 0xFF) + ((x) & 0xff) /* Firewall DDR scheduler MPFE */ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 diff --git a/drivers/ddr/altera/uibssm_mailbox.c b/drivers/ddr/altera/uibssm_mailbox.c new file mode 100644 index 00000000000..deef61f1178 --- /dev/null +++ b/drivers/ddr/altera/uibssm_mailbox.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <hang.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include "uibssm_mailbox.h" + +#define MAX_RETRIES 3 + +int uib_bist_mem_init_start(struct uib_info *uib_ctrl) +{ + struct uib_mb_resp usr_resp; + bool bist_start, bist_success; + u32 start; + + for (int i = 0; i < uib_ctrl->num_instance; i++) { + bist_start = false; + bist_success = false; + + /* + * Full memory initialization BIST performed on all UIB channels + * start memory initialization BIST on full memory address + */ + uib_mb_req(uib_ctrl->uib[i].uib_csr_addr, + UIB_CMD_TRIG_CONTROLLER_OP, + UIB_BIST_MEM_INIT_START, + UIB_BIST_FULL_MEM, &usr_resp); + + bist_start = UIBSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & + UIB_BIST_INITIATE_PASS; + + if (!bist_start) { + printf("%s: Failed to initialize memory on UIB instance %d\n", + __func__, i); + + return -EINVAL; + } + + /* Polling for the initiated memory initialization BIST status */ + start = get_timer(0); + while (!bist_success) { + udelay(1); + + /* + * cmd_param_0 is not used in BIST status request, + * hence set the value to 0 + */ + uib_mb_req(uib_ctrl->uib[i].uib_csr_addr, + UIB_CMD_TRIG_CONTROLLER_OP, + UIB_BIST_MEM_INIT_STATUS, + 0, &usr_resp); + + bist_success = UIBSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & + BIT(0); + + if (!bist_success && (get_timer(start) > TIMEOUT)) { + printf("%s: Timeout initializing memory on UIB instance %d\n", + __func__, i); + + return -ETIMEDOUT; + } + } + + debug("%s: Memory initialized successfully on UIB instance %d\n", __func__, i); + } + + return 0; +} + +int uib_cal_status(phys_addr_t addr) +{ + int ret = 0; + phys_addr_t status_addr = addr + UIB_R_INITSTS_OFFSET; + + /* Ensure calibration completed */ + ret = wait_for_bit_le32((const void *)status_addr, UIB_R_INITSTS_INITSTS_PASS, true, + TIMEOUT, false); + if (ret) + printf("%s: HBM calibration UIB instance 0x%llx timeout\n", __func__, status_addr); + + return ret; +} + +void uib_init_mem_cal(struct uib_info *uib_ctrl) +{ + int i, ret; + + if (!uib_ctrl->num_instance) { + uib_ctrl->overall_cal_status = false; + } else { + uib_ctrl->overall_cal_status = true; + + /* Check initial calibration status for the assigned UIB */ + for (i = 0; i < uib_ctrl->num_instance; i++) { + ret = uib_cal_status(uib_ctrl->uib[i].uib_csr_addr); + if (ret) { + uib_ctrl->uib[i].cal_status = false; + uib_ctrl->overall_cal_status = false; + + printf("%s: Initial HBM calibration UIB_%d failed\n", __func__, i); + break; + } + + uib_ctrl->uib[i].cal_status = true; + + debug("%s: Initial HBM calibration UIB_%d succeed\n", __func__, i); + } + } +} + +/* Trying 3 times re-calibration if initial calibration failed */ +void uib_trig_mem_cal(struct uib_info *uib_ctrl) +{ + int i, j, cal_stat; + + if (!uib_ctrl->num_instance) { + uib_ctrl->overall_cal_status = false; + } else { + uib_ctrl->overall_cal_status = true; + + for (i = 0; i < uib_ctrl->num_instance; i++) { + uib_ctrl->uib[i].cal_status = false; + + /* Initiate Re-calibration */ + for (j = 0; j < MAX_RETRIES; j++) { + clrsetbits_le32(uib_ctrl->uib[i].uib_csr_addr + + UIB_R_INITCTL_OFFSET, + UIB_R_INITCTL_INITTYPE_MASK | + UIB_R_INITCTL_INITREQ_MASK, + UIB_R_INITCTL_INITTYPE(UIB_RST_REQUEST_WITH_CAL) | + UIB_R_INITCTL_INITREQ(1)); + + cal_stat = uib_cal_status(uib_ctrl->uib[i].uib_csr_addr); + if (cal_stat) + continue; + + debug("%s: HBM re-calibration UIB_%d succeed\n", __func__, i); + + uib_ctrl->uib[i].cal_status = true; + break; + } + + if (!uib_ctrl->uib[i].cal_status) { + uib_ctrl->overall_cal_status = false; + + printf("%s: HBM re-calibration UIB_%d failed\n", __func__, i); + break; + } + } + } +} + +static void uib_mailbox_write_request(u32 data, u32 target_write_addr, phys_addr_t csr_addr) +{ + int ret; + + /* + * Read from chms0020 MBWRADDR_VALID and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #1 Read MBWRADDR_VALID from UIB_R_MBWRCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBWRCTL, + UIB_R_MBWRCTL_MBWRADDR_VALID, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBWRADDR_VALID is not zero\n", __func__); + + hang(); + } + + /* Write <target write address> to chms0024 MBWRADDR */ + debug("%s: #2 Write 0x%x to UIB_R_MBWRADDR\n", __func__, target_write_addr); + writel(target_write_addr, csr_addr + UIB_R_MBWRADDR); + + /* + * Write 1 to chms0020 MBWRADDR_VALID to indicate the address is now valid + * for FW to read + */ + debug("%s: #3 Write 1 to MBWRADDR_VALID for FW to read address\n", __func__); + setbits_le32(csr_addr + UIB_R_MBWRCTL, UIB_R_MBWRCTL_MBWRADDR_VALID); + + /* + * Read from chms0020 MBWRDATA_VALID and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #4 Read MBWRDATA_VALID from UIB_R_MBWRCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBWRCTL, + UIB_R_MBWRCTL_MBWRDATA_VALID, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBWRADDR_VALID is not zero\n", __func__); + + hang(); + } + + /* + * Read from chms0020 MBWRDATA_END and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #5 Read R_MBWRCTL_MBWRDATA_END from UIB_R_MBWRCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBWRCTL, + UIB_R_MBWRCTL_MBWRDATA_END, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBWRDATA_END is not zero\n", __func__); + + hang(); + } + + /* Write <write data> to chms0028 MMR_MBWRDATA */ + debug("%s: #6 Write 0x%x to UIB_R_MBWRDATA\n", __func__, data); + writel(data, csr_addr + UIB_R_MBWRDATA); + + /* + * Write 1 to chms0020 MBWRDATA_END to indicate if the <write data> is the last burst + * for FW to read for the <target write address> + */ + debug("%s: #7 Write 1 to MBWRDATA_END to inform FW this is last burst of data to read\n", + __func__); + setbits_le32(csr_addr + UIB_R_MBWRCTL, UIB_R_MBWRCTL_MBWRDATA_END); + + /* Write 1 to chms0020 MBWRDATA_VALID to indicate the data is now valid for FW to read */ + debug("%s: #8 Write 1 to MBWRDATA_VALID for FW to read data\n", __func__); + setbits_le32(csr_addr + UIB_R_MBWRCTL, UIB_R_MBWRCTL_MBWRDATA_VALID); +} + +static u32 uib_mailbox_read_request(u32 target_read_addr, phys_addr_t csr_addr) +{ + int ret; + u32 reg, rd_data = 0; + + /* + * Read from chms0030 MBRDADDR_VALID and ensure its not set or + * wait till it get cleared by controller + */ + debug("%s: #1 Read MBRDADDR_VALID from UIB_R_MBRDCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBRDCTL, + UIB_R_MBRDCTL_MBRDADDR_VALID, false, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBRDADDR_VALID is not zero\n", __func__); + + hang(); + } + + /* Write <target read address> to chms0034 MBRDADDR */ + debug("%s: #2 Write 0x%x to UIB_R_MBRDADDR\n", __func__, target_read_addr); + writel(target_read_addr, csr_addr + UIB_R_MBRDADDR); + + /* + * Write 1 to chms0030 MBRDADDR_VALID to indicate the address is now valid + * for FW to read + */ + debug("%s: #3 Write 1 to MBRDADDR_VALID for FW to read address\n", __func__); + setbits_le32(csr_addr + UIB_R_MBRDCTL, UIB_R_MBRDCTL_MBRDADDR_VALID); + + /* + * Continuously poll the chms0030 MBRDDATA_VALID. If MBRDDATA_VALID are set, read + * chms0038 MBRDDATA and chms0030 MBRDDATA_END to retrieve the <read data> and + * <end of read burst> status accordingly + */ + debug("%s: #4 Read MBRDDATA_VALID from UIB_R_MBRDCTL\n", __func__); + ret = wait_for_bit_le32((const void *)csr_addr + UIB_R_MBRDCTL, + UIB_R_MBRDCTL_MBRDDATA_VALID, true, TIMEOUT, false); + if (ret) { + printf("%s: TIMEOUT!!! MBRDDATA_VALID is zero\n", __func__); + + hang(); + } + + reg = readl(csr_addr + UIB_R_MBRRDATA); + debug("%s: #5 Read data from UIB_R_MBRRDATA = 0x%x\n", __func__, reg); + rd_data = reg; + + reg = readl(csr_addr + UIB_R_MBRDCTL); + debug("%s: #6 Read end of read burst status from UIB_R_MBRDCTL = 0x%x\n", __func__, reg); + + /* + * Once done retrieving the data, write 1 to chms0030 MBRDDATA_VALID, + * chms0030 MBRDDATA_END to clear the register + */ + debug("%s: #7 Write 1 to MBRDDATA_VALID for FW to read address\n", __func__); + setbits_le32(csr_addr + UIB_R_MBRDCTL, UIB_R_MBRDCTL_MBRDDATA_VALID | + UIB_R_MBWRCTL_MBWRDATA_END); + + return rd_data; +} + +int uib_mb_req(phys_addr_t uib_csr_addr, u32 usr_cmd_type, u32 usr_cmd_opcode, + u32 cmd_param_0, struct uib_mb_resp *resp) +{ + u32 cmd_req; + + /* Initialized zeros for responses */ + resp->cmd_resp_status = 0; + + /* Write CMD_REQ (CMD_TYPE and CMD_OPCODE) */ + cmd_req = FIELD_PREP(CMD_TYPE_MASK, usr_cmd_type) | + FIELD_PREP(CMD_OPCODE_MASK, usr_cmd_opcode); + uib_mailbox_write_request(cmd_req, 0, uib_csr_addr); + + debug("%s: Write 0x%x to UIBSSM_CMD_REQ_OFFSET 0x%llx\n", __func__, cmd_req, uib_csr_addr); + + /* Write CMD_PARAM_* */ + if (cmd_param_0) + uib_mailbox_write_request(cmd_param_0, 0, uib_csr_addr); + else + debug("%s: cmd_param_0 is NULL\n", __func__); + + /* read CMD_RESPONSE_STATUS */ + resp->cmd_resp_status = uib_mailbox_read_request(0, uib_csr_addr); + + debug("%s: CMD_RESPONSE_STATUS 0x%llx: 0x%x\n", __func__, + uib_csr_addr, resp->cmd_resp_status); + debug("%s: STATUS_CMD_RESPONSE_ERROR: 0x%lx\n", __func__, + UIBSSM_CMD_RESPONSE_ERROR(resp->cmd_resp_status)); + debug("%s: STATUS_GENERAL_ERROR: 0x%lx\n", __func__, + UIBSSM_GENERAL_ERROR(resp->cmd_resp_status)); + + return 0; +} diff --git a/drivers/ddr/altera/uibssm_mailbox.h b/drivers/ddr/altera/uibssm_mailbox.h new file mode 100644 index 00000000000..771efab191e --- /dev/null +++ b/drivers/ddr/altera/uibssm_mailbox.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#define TIMEOUT_120000MS 120000 +#define TIMEOUT TIMEOUT_120000MS + +#define UIBSSM_CMD_RESPONSE_DATA_SHORT_MASK GENMASK(31, 16) +#define UIBSSM_CMD_RESPONSE_DATA_SHORT(x) FIELD_GET(UIBSSM_CMD_RESPONSE_DATA_SHORT_MASK, x) +#define UIBSSM_CMD_RESPONSE_ERROR_MASK GENMASK(7, 5) +#define UIBSSM_CMD_RESPONSE_ERROR(x) FIELD_GET(UIBSSM_CMD_RESPONSE_ERROR_MASK, x) +#define UIBSSM_GENERAL_ERROR_MASK GENMASK(4, 1) +#define UIBSSM_GENERAL_ERROR(x) FIELD_GET(UIBSSM_GENERAL_ERROR_MASK, x) + +/* UIB Responder Initialization Control Register */ +#define UIB_R_INITCTL_OFFSET 0x10 +#define UIB_R_INITCTL_INITREQ_MASK BIT(0) +#define UIB_R_INITCTL_INITTYPE_MASK GENMASK(11, 8) +#define UIB_R_INITCTL_INITREQ(x) FIELD_PREP(UIB_R_INITCTL_INITREQ_MASK, x) +#define UIB_R_INITCTL_INITTYPE(x) FIELD_PREP(UIB_R_INITCTL_INITTYPE_MASK, x) +#define UIB_RST_REQUEST_WITH_CAL 5 + +/* UIB Initialization control and status registers */ +#define UIB_R_INITSTS_OFFSET 0x14 +#define UIB_R_INITSTS_INITSTS_PASS BIT(1) +#define MAX_UIB_SUPPORTED 8 + +#define UIB_R_MBWRCTL 0x20 +#define UIB_R_MBWRADDR 0x24 +#define UIB_R_MBWRDATA 0x28 +#define UIB_R_MBWRCTL_MBWRADDR_VALID BIT(0) +#define UIB_R_MBWRCTL_MBWRDATA_VALID BIT(4) +#define UIB_R_MBWRCTL_MBWRDATA_END BIT(7) + +#define UIB_R_MBRDCTL 0x30 +#define UIB_R_MBRDADDR 0x34 +#define UIB_R_MBRRDATA 0x38 +#define UIB_R_MBRDCTL_MBRDADDR_VALID BIT(0) +#define UIB_R_MBRDCTL_MBRDDATA_VALID BIT(4) +#define UIB_R_MBRDCTL_MBRDDATA_END BIT(7) + +/* Responder Error Mask Register */ +#define UIB_R_ERRMSK_PSEUDO_CH0_OFFSET 0x520 +#define UIB_R_ERRMSK_PSEUDO_CH1_OFFSET 0X820 +#define UIB_DRAM_SBE_MSK BIT(25) +#define UIB_INTERNAL_CORR_ERR_MSK BIT(30) +#define UIB_DRAM_SBE(x) FIELD_PREP(UIB_DRAM_SBE_MSK, x) +#define UIB_INTERNAL_CORR_ERR(x) FIELD_PREP(UIB_INTERNAL_CORR_ERR_MSK, x) + +/* CMD_REQ Register Definition */ +#define CMD_TYPE_MASK GENMASK(23, 16) +#define CMD_OPCODE_MASK GENMASK(15, 0) + +/* supported mailbox command type */ +enum uibssm_mailbox_cmd_type { + UIB_CMD_TRIG_CONTROLLER_OP = 0x04 +}; + +/* supported mailbox command opcode */ +enum uibssm_mailbox_cmd_opcode { + UIB_BIST_MEM_INIT_START = 0x0303, + UIB_BIST_MEM_INIT_STATUS +}; + +/* CMD_PARAM_0 for opcode UIB_BIST_MEM_INIT_START */ +#define UIB_BIST_FULL_MEM BIT(6) + +/* UIBSSM_CMD_RESPONSE_DATA_SHORT for opcode UIB_BIST_MEM_INIT_START */ +#define UIB_BIST_INITIATE_PASS BIT(0) + +/* + * UIBSSM mailbox response outputs + * + * @cmd_resp_status: Command Interface status + */ +struct uib_mb_resp { + u32 cmd_resp_status; +}; + +/* + * UIB instance specific information + * + * @uib_csr_addr: UIB instance CSR address + * @cal_status: UIB instance calibration status + */ +struct uib_instance { + phys_addr_t uib_csr_addr; + bool cal_status; +}; + +/* + * Overall UIB instance(s) information + * + * @num_instance: Number of instance(s) assigned to HPS + * @overall_cal_status: Overall calibration status for all UIB instance(s) + * @ecc_status: ECC enable status (false = disabled, true = enabled) + * @overall_size: Total HBM memory size + * @uib: UIB instance specific information + */ +struct uib_info { + u8 num_instance; + bool overall_cal_status; + bool ecc_status; + phys_size_t overall_size; + struct uib_instance uib[MAX_UIB_SUPPORTED]; +}; + +/* Supported UIB function */ +int uib_mb_req(phys_addr_t uib_csr_addr, + u32 usr_cmd_type, u32 usr_cmd_opcode, + u32 cmd_param_0, struct uib_mb_resp *resp); +int uib_cal_status(phys_addr_t addr); +void uib_init_mem_cal(struct uib_info *uib_ctrl); +void uib_trig_mem_cal(struct uib_info *uib_ctrl); +int uib_bist_mem_init_start(struct uib_info *uib_ctrl); diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 723265ab2e5..01824310995 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -2327,7 +2327,7 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) { struct udma_dev *ud = dev_get_priv(dma->dev); struct cppi5_host_desc_t *desc_tx; - dma_addr_t dma_src = (dma_addr_t)src; + dma_addr_t dma_src = (uintptr_t)src; struct ti_udma_drv_packet_data packet_data = { 0 }; dma_addr_t paddr; struct udma_chan *uc; @@ -2426,7 +2426,7 @@ static int udma_receive(struct dma *dma, void **dst, void *metadata) cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); - *dst = (void *)buf_dma; + *dst = (void *)(uintptr_t)buf_dma; uc->num_rx_bufs--; return pkt_len; @@ -2518,7 +2518,7 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size) desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM; desc_rx = uc->desc_rx + (desc_num * uc->config.hdesc_size); - dma_dst = (dma_addr_t)dst; + dma_dst = (uintptr_t)dst; cppi5_hdesc_reset_hbdesc(desc_rx); diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c deleted file mode 100644 index e1514fc56d0..00000000000 --- a/drivers/fpga/ACEX1K.c +++ /dev/null @@ -1,245 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de - * - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - */ - -#define LOG_CATEGORY UCLASS_FPGA - -#include <config.h> /* core U-Boot definitions */ -#include <console.h> -#include <log.h> -#include <ACEX1K.h> /* ACEX device family */ -#include <linux/delay.h> -#include <time.h> - -/* Note: The assumption is that we cannot possibly run fast enough to - * overrun the device (the Slave Parallel mode can free run at 50MHz). - * If there is a need to operate slower, define CFG_FPGA_DELAY in - * the board config file to slow things down. - */ -#ifndef CFG_FPGA_DELAY -#define CFG_FPGA_DELAY() -#endif - -#ifndef CFG_SYS_FPGA_WAIT -#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ -#endif - -static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); -static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize); -/* static int ACEX1K_ps_info(Altera_desc *desc); */ - -/* ------------------------------------------------------------------------- */ -/* ACEX1K Generic Implementation */ -int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - log_debug("Launching Passive Serial Loader\n"); - ret_val = ACEX1K_ps_load (desc, buf, bsize); - break; - - /* Add new interface types here */ - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - -int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - log_debug("Launching Passive Serial Dump\n"); - ret_val = ACEX1K_ps_dump (desc, buf, bsize); - break; - - /* Add new interface types here */ - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - -int ACEX1K_info( Altera_desc *desc ) -{ - return FPGA_SUCCESS; -} - -/* ------------------------------------------------------------------------- */ -/* ACEX1K Passive Serial Generic Implementation */ - -static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns; - int i; - - log_debug("start with interface functions @ 0x%p\n", fn); - - if (fn) { - size_t bytecount = 0; - unsigned char *data = (unsigned char *) buf; - int cookie = desc->cookie; /* make a local copy */ - unsigned long ts; /* timestamp */ - - log_debug("Function Table:\n" - "ptr:\t0x%p\n" - "struct: 0x%p\n" - "config:\t0x%p\n" - "status:\t0x%p\n" - "clk:\t0x%p\n" - "data:\t0x%p\n" - "done:\t0x%p\n\n", - &fn, fn, fn->config, fn->status, - fn->clk, fn->data, fn->done); -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - printf ("Loading FPGA Device %d...", cookie); -#endif - - /* - * Run the pre configuration function if there is one. - */ - if (*fn->pre) { - (*fn->pre) (cookie); - } - - /* Establish the initial state */ - (*fn->config) (true, true, cookie); /* Assert nCONFIG */ - - udelay(2); /* T_cfg > 2us */ - - /* nSTATUS should be asserted now */ - (*fn->done) (cookie); - if ( !(*fn->status) (cookie) ) { - puts ("** nSTATUS is not asserted.\n"); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - - (*fn->config) (false, true, cookie); /* Deassert nCONFIG */ - udelay(2); /* T_cf2st1 < 4us */ - - /* Wait for nSTATUS to be released (i.e. deasserted) */ - ts = get_timer (0); /* get current time */ - do { - CFG_FPGA_DELAY (); - if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ - puts ("** Timeout waiting for STATUS to go high.\n"); - (*fn->abort) (cookie); - return FPGA_FAIL; - } - (*fn->done) (cookie); - } while ((*fn->status) (cookie)); - - /* Get ready for the burn */ - CFG_FPGA_DELAY (); - - /* Load the data */ - while (bytecount < bsize) { - unsigned char val=0; -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc ()) { - (*fn->abort) (cookie); - return FPGA_FAIL; - } -#endif - /* Altera detects an error if INIT goes low (active) - while DONE is low (inactive) */ -#if 0 /* not yet implemented */ - if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { - puts ("** CRC error during FPGA load.\n"); - (*fn->abort) (cookie); - return (FPGA_FAIL); - } -#endif - val = data [bytecount ++ ]; - i = 8; - do { - /* Deassert the clock */ - (*fn->clk) (false, true, cookie); - CFG_FPGA_DELAY (); - /* Write data */ - (*fn->data) ((val & 0x01), true, cookie); - CFG_FPGA_DELAY (); - /* Assert the clock */ - (*fn->clk) (true, true, cookie); - CFG_FPGA_DELAY (); - val >>= 1; - i --; - } while (i > 0); - -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % (bsize / 40) == 0) - putc ('.'); /* let them know we are alive */ -#endif - } - - CFG_FPGA_DELAY (); - -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc (' '); /* terminate the dotted line */ -#endif - - /* - * Checking FPGA's CONF_DONE signal - correctly booted ? - */ - - if ( ! (*fn->done) (cookie) ) { - puts ("** Booting failed! CONF_DONE is still deasserted.\n"); - (*fn->abort) (cookie); - return (FPGA_FAIL); - } - - /* - * "DCLK must be clocked an additional 10 times fpr ACEX 1K..." - */ - - for (i = 0; i < 12; i++) { - CFG_FPGA_DELAY (); - (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - CFG_FPGA_DELAY (); - (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - } - - ret_val = FPGA_SUCCESS; - -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (ret_val == FPGA_SUCCESS) { - puts ("Done.\n"); - } - else { - puts ("Fail.\n"); - } -#endif - (*fn->post) (cookie); - - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; -} - -static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize) -{ - /* Readback is only available through the Slave Parallel and */ - /* boundary-scan interfaces. */ - printf ("%s: Passive Serial Dumping is unavailable\n", - __FUNCTION__); - return FPGA_FAIL; -} diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 9456ca3149a..e2593057fac 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -34,12 +34,6 @@ config FPGA_STRATIX_V help Say Y here to enable the Altera Stratix V FPGA specific driver. -config FPGA_ACEX1K - bool "Enable Altera ACEX 1K driver" - depends on FPGA_ALTERA - help - Say Y here to enable the Altera ACEX 1K FPGA specific driver. - config FPGA_CYCLON2 bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA @@ -61,12 +55,6 @@ config FPGA_INTEL_SDM_MAILBOX Enable FPGA driver for writing full bitstream into Intel FPGA devices through SDM (Secure Device Manager) Mailbox. -config FPGA_LATTICE - bool "Enable Lattice FPGA driver" - help - This is used for the lattice FPGAs. Please check the source code as - there is no documentation for this at present. - config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 610c168fc35..f22d3b3d86e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -14,10 +14,8 @@ obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o obj-$(CONFIG_FPGA_XILINX) += xilinx.o -obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o ifdef CONFIG_FPGA_ALTERA obj-y += altera.o -obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 64fda3a307c..4a9aa74357e 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -28,10 +28,7 @@ static const struct altera_fpga { int (*dump)(Altera_desc *, const void *, size_t); int (*info)(Altera_desc *); } altera_fpga[] = { -#if defined(CONFIG_FPGA_ACEX1K) - { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, - { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, -#elif defined(CONFIG_FPGA_CYCLON2) +#if defined(CONFIG_FPGA_CYCLON2) { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, #endif diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 7e78d6e2d6c..1c464c1e912 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -174,10 +174,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) ret_val = FPGA_SUCCESS; #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (ret_val == FPGA_SUCCESS) - puts("Done.\n"); - else - puts("Fail.\n"); + puts("Done.\n"); #endif /* diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 2297fefd149..b4e3896d2e8 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -9,7 +9,6 @@ #include <log.h> #include <xilinx.h> /* xilinx specific definitions */ #include <altera.h> /* altera specific definitions */ -#include <lattice.h> #include <dm/device_compat.h> /* Local static data */ @@ -81,14 +80,6 @@ static int fpga_dev_info(int devnum) log_err("No support for Altera devices.\n"); #endif break; - case fpga_lattice: -#if defined(CONFIG_FPGA_LATTICE) - log_info("Lattice Device\nDescriptor @ 0x%p\n", desc); - ret_val = lattice_info(desc->devdesc); -#else - log_err("No support for Lattice devices.\n"); -#endif - break; default: log_err("Invalid or unsupported device type %d\n", desc->devtype); @@ -267,13 +258,6 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, log_err("No support for Altera devices.\n"); #endif break; - case fpga_lattice: -#if defined(CONFIG_FPGA_LATTICE) - ret_val = lattice_load(desc->devdesc, buf, bsize); -#else - log_err("No support for Lattice devices.\n"); -#endif - break; default: log_err("Invalid or unsupported device type %d\n", desc->devtype); @@ -312,13 +296,6 @@ int fpga_dump(int devnum, const void *buf, size_t bsize) log_err("No support for Altera devices.\n"); #endif break; - case fpga_lattice: -#if defined(CONFIG_FPGA_LATTICE) - ret_val = lattice_dump(desc->devdesc, buf, bsize); -#else - log_err("No support for Lattice devices.\n"); -#endif - break; default: log_err("Invalid or unsupported device type %d\n", desc->devtype); diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.c deleted file mode 100644 index 37d5c5ec9ec..00000000000 --- a/drivers/fpga/ivm_core.c +++ /dev/null @@ -1,3149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Porting to u-boot: - * - * (C) Copyright 2010 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Lattice ispVME Embedded code to load Lattice's FPGA: - * - * Copyright 2009 Lattice Semiconductor Corp. - * - * ispVME Embedded allows programming of Lattice's suite of FPGA - * devices on embedded systems through the JTAG port. The software - * is distributed in source code form and is open to re - distribution - * and modification where applicable. - * - * Revision History of ivm_core.c module: - * 4/25/06 ht Change some variables from unsigned short or int - * to long int to make the code compiler independent. - * 5/24/06 ht Support using RESET (TRST) pin as a special purpose - * control pin such as triggering the loading of known - * state exit. - * 3/6/07 ht added functions to support output to terminals - * - * 09/11/07 NN Type cast mismatch variables - * Moved the sclock() function to hardware.c - * 08/28/08 NN Added Calculate checksum support. - * 4/1/09 Nguyen replaced the recursive function call codes on - * the ispVMLCOUNT function - */ - -#include <log.h> -#include <linux/string.h> -#include <malloc.h> -#include <lattice.h> -#include <vsprintf.h> - -#define vme_out_char(c) printf("%c", c) -#define vme_out_hex(c) printf("%x", c) -#define vme_out_string(s) printf("%s", s) - -/* - * - * Global variables used to specify the flow control and data type. - * - * g_usFlowControl: flow control register. Each bit in the - * register can potentially change the - * personality of the embedded engine. - * g_usDataType: holds the data type of the current row. - * - */ - -static unsigned short g_usFlowControl; -unsigned short g_usDataType; - -/* - * - * Global variables used to specify the ENDDR and ENDIR. - * - * g_ucEndDR: the state that the device goes to after SDR. - * g_ucEndIR: the state that the device goes to after SIR. - * - */ - -unsigned char g_ucEndDR = DRPAUSE; -unsigned char g_ucEndIR = IRPAUSE; - -/* - * - * Global variables used to support header/trailer. - * - * g_usHeadDR: the number of lead devices in bypass. - * g_usHeadIR: the sum of IR length of lead devices. - * g_usTailDR: the number of tail devices in bypass. - * g_usTailIR: the sum of IR length of tail devices. - * - */ - -static unsigned short g_usHeadDR; -static unsigned short g_usHeadIR; -static unsigned short g_usTailDR; -static unsigned short g_usTailIR; - -/* - * - * Global variable to store the number of bits of data or instruction - * to be shifted into or out from the device. - * - */ - -static unsigned short g_usiDataSize; - -/* - * - * Stores the frequency. Default to 1 MHz. - * - */ - -static int g_iFrequency = 1000; - -/* - * - * Stores the maximum amount of ram needed to hold a row of data. - * - */ - -static unsigned short g_usMaxSize; - -/* - * - * Stores the LSH or RSH value. - * - */ - -static unsigned short g_usShiftValue; - -/* - * - * Stores the current repeat loop value. - * - */ - -static unsigned short g_usRepeatLoops; - -/* - * - * Stores the current vendor. - * - */ - -static signed char g_cVendor = LATTICE; - -/* - * - * Stores the VME file CRC. - * - */ - -unsigned short g_usCalculatedCRC; - -/* - * - * Stores the Device Checksum. - * - */ -/* 08/28/08 NN Added Calculate checksum support. */ -unsigned long g_usChecksum; -static unsigned int g_uiChecksumIndex; - -/* - * - * Stores the current state of the JTAG state machine. - * - */ - -static signed char g_cCurrentJTAGState; - -/* - * - * Global variables used to support looping. - * - * g_pucHeapMemory: holds the entire repeat loop. - * g_iHeapCounter: points to the current byte in the repeat loop. - * g_iHEAPSize: the current size of the repeat in bytes. - * - */ - -unsigned char *g_pucHeapMemory; -unsigned short g_iHeapCounter; -unsigned short g_iHEAPSize; -static unsigned short previous_size; - -/* - * - * Global variables used to support intelligent programming. - * - * g_usIntelDataIndex: points to the current byte of the - * intelligent buffer. - * g_usIntelBufferSize: holds the size of the intelligent - * buffer. - * - */ - -unsigned short g_usIntelDataIndex; -unsigned short g_usIntelBufferSize; - -/* - * - * Supported VME versions. - * - */ - -const char *const g_szSupportedVersions[] = { - "__VME2.0", "__VME3.0", "____12.0", "____12.1", 0}; - -/* - * - * Holds the maximum size of each respective buffer. These variables are used - * to write the HEX files when converting VME to HEX. - * -*/ - -static unsigned short g_usTDOSize; -static unsigned short g_usMASKSize; -static unsigned short g_usTDISize; -static unsigned short g_usDMASKSize; -static unsigned short g_usLCOUNTSize; -static unsigned short g_usHDRSize; -static unsigned short g_usTDRSize; -static unsigned short g_usHIRSize; -static unsigned short g_usTIRSize; -static unsigned short g_usHeapSize; - -/* - * - * Global variables used to store data. - * - * g_pucOutMaskData: local RAM to hold one row of MASK data. - * g_pucInData: local RAM to hold one row of TDI data. - * g_pucOutData: local RAM to hold one row of TDO data. - * g_pucHIRData: local RAM to hold the current SIR header. - * g_pucTIRData: local RAM to hold the current SIR trailer. - * g_pucHDRData: local RAM to hold the current SDR header. - * g_pucTDRData: local RAM to hold the current SDR trailer. - * g_pucIntelBuffer: local RAM to hold the current intelligent buffer - * g_pucOutDMaskData: local RAM to hold one row of DMASK data. - * - */ - -unsigned char *g_pucOutMaskData = NULL, - *g_pucInData = NULL, - *g_pucOutData = NULL, - *g_pucHIRData = NULL, - *g_pucTIRData = NULL, - *g_pucHDRData = NULL, - *g_pucTDRData = NULL, - *g_pucIntelBuffer = NULL, - *g_pucOutDMaskData = NULL; - -/* - * - * JTAG state machine transition table. - * - */ - -struct { - unsigned char CurState; /* From this state */ - unsigned char NextState; /* Step to this state */ - unsigned char Pattern; /* The tragetory of TMS */ - unsigned char Pulses; /* The number of steps */ -} g_JTAGTransistions[25] = { -{ RESET, RESET, 0xFC, 6 }, /* Transitions from RESET */ -{ RESET, IDLE, 0x00, 1 }, -{ RESET, DRPAUSE, 0x50, 5 }, -{ RESET, IRPAUSE, 0x68, 6 }, -{ IDLE, RESET, 0xE0, 3 }, /* Transitions from IDLE */ -{ IDLE, DRPAUSE, 0xA0, 4 }, -{ IDLE, IRPAUSE, 0xD0, 5 }, -{ DRPAUSE, RESET, 0xF8, 5 }, /* Transitions from DRPAUSE */ -{ DRPAUSE, IDLE, 0xC0, 3 }, -{ DRPAUSE, IRPAUSE, 0xF4, 7 }, -{ DRPAUSE, DRPAUSE, 0xE8, 6 },/* 06/14/06 Support POLL STATUS LOOP*/ -{ IRPAUSE, RESET, 0xF8, 5 }, /* Transitions from IRPAUSE */ -{ IRPAUSE, IDLE, 0xC0, 3 }, -{ IRPAUSE, DRPAUSE, 0xE8, 6 }, -{ DRPAUSE, SHIFTDR, 0x80, 2 }, /* Extra transitions using SHIFTDR */ -{ IRPAUSE, SHIFTDR, 0xE0, 5 }, -{ SHIFTDR, DRPAUSE, 0x80, 2 }, -{ SHIFTDR, IDLE, 0xC0, 3 }, -{ IRPAUSE, SHIFTIR, 0x80, 2 },/* Extra transitions using SHIFTIR */ -{ SHIFTIR, IRPAUSE, 0x80, 2 }, -{ SHIFTIR, IDLE, 0xC0, 3 }, -{ DRPAUSE, DRCAPTURE, 0xE0, 4 }, /* 11/15/05 Support DRCAPTURE*/ -{ DRCAPTURE, DRPAUSE, 0x80, 2 }, -{ IDLE, DRCAPTURE, 0x80, 2 }, -{ IRPAUSE, DRCAPTURE, 0xE0, 4 } -}; - -/* - * - * List to hold all LVDS pairs. - * - */ - -LVDSPair *g_pLVDSList; -unsigned short g_usLVDSPairCount; - -/* - * - * Function prototypes. - * - */ - -static signed char ispVMDataCode(void); -static long ispVMDataSize(void); -static void ispVMData(unsigned char *Data); -static signed char ispVMShift(signed char Code); -static signed char ispVMAmble(signed char Code); -static signed char ispVMLoop(unsigned short a_usLoopCount); -static signed char ispVMBitShift(signed char mode, unsigned short bits); -static void ispVMComment(unsigned short a_usCommentSize); -static void ispVMHeader(unsigned short a_usHeaderSize); -static signed char ispVMLCOUNT(unsigned short a_usCountSize); -static void ispVMClocks(unsigned short Clocks); -static void ispVMBypass(signed char ScanType, unsigned short Bits); -static void ispVMStateMachine(signed char NextState); -static signed char ispVMSend(unsigned short int); -static signed char ispVMRead(unsigned short int); -static signed char ispVMReadandSave(unsigned short int); -static signed char ispVMProcessLVDS(unsigned short a_usLVDSCount); -static void ispVMMemManager(signed char types, unsigned short size); - -/* - * - * External variables and functions in hardware.c module - * - */ -static signed char g_cCurrentJTAGState; - -#ifdef DEBUG - -/* - * - * GetState - * - * Returns the state as a string based on the opcode. Only used - * for debugging purposes. - * - */ - -const char *GetState(unsigned char a_ucState) -{ - switch (a_ucState) { - case RESET: - return "RESET"; - case IDLE: - return "IDLE"; - case IRPAUSE: - return "IRPAUSE"; - case DRPAUSE: - return "DRPAUSE"; - case SHIFTIR: - return "SHIFTIR"; - case SHIFTDR: - return "SHIFTDR"; - case DRCAPTURE:/* 11/15/05 support DRCAPTURE*/ - return "DRCAPTURE"; - default: - break; - } - - return 0; -} - -/* - * - * PrintData - * - * Prints the data. Only used for debugging purposes. - * - */ - -void PrintData(unsigned short a_iDataSize, unsigned char *a_pucData) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short usByteSize = 0; - unsigned short usBitIndex = 0; - signed short usByteIndex = 0; - unsigned char ucByte = 0; - unsigned char ucFlipByte = 0; - - if (a_iDataSize % 8) { - /* 09/11/07 NN Type cast mismatch variables */ - usByteSize = (unsigned short)(a_iDataSize / 8 + 1); - } else { - /* 09/11/07 NN Type cast mismatch variables */ - usByteSize = (unsigned short)(a_iDataSize / 8); - } - puts("("); - /* 09/11/07 NN Type cast mismatch variables */ - for (usByteIndex = (signed short)(usByteSize - 1); - usByteIndex >= 0; usByteIndex--) { - ucByte = a_pucData[usByteIndex]; - ucFlipByte = 0x00; - - /* - * - * Flip each byte. - * - */ - - for (usBitIndex = 0; usBitIndex < 8; usBitIndex++) { - ucFlipByte <<= 1; - if (ucByte & 0x1) { - ucFlipByte |= 0x1; - } - - ucByte >>= 1; - } - - /* - * - * Print the flipped byte. - * - */ - - printf("%.02X", ucFlipByte); - if ((usByteSize - usByteIndex) % 40 == 39) { - puts("\n\t\t"); - } - if (usByteIndex < 0) - break; - } - puts(")"); -} -#endif /* DEBUG */ - -void ispVMMemManager(signed char cTarget, unsigned short usSize) -{ - switch (cTarget) { - case XTDI: - case TDI: - if (g_pucInData != NULL) { - if (previous_size == usSize) {/*memory exist*/ - break; - } else { - free(g_pucInData); - g_pucInData = NULL; - } - } - g_pucInData = (unsigned char *) malloc(usSize / 8 + 2); - previous_size = usSize; - case XTDO: - case TDO: - if (g_pucOutData != NULL) { - if (previous_size == usSize) { /*already exist*/ - break; - } else { - free(g_pucOutData); - g_pucOutData = NULL; - } - } - g_pucOutData = (unsigned char *) malloc(usSize / 8 + 2); - previous_size = usSize; - break; - case MASK: - if (g_pucOutMaskData != NULL) { - if (previous_size == usSize) {/*already allocated*/ - break; - } else { - free(g_pucOutMaskData); - g_pucOutMaskData = NULL; - } - } - g_pucOutMaskData = (unsigned char *) malloc(usSize / 8 + 2); - previous_size = usSize; - break; - case HIR: - if (g_pucHIRData != NULL) { - free(g_pucHIRData); - g_pucHIRData = NULL; - } - g_pucHIRData = (unsigned char *) malloc(usSize / 8 + 2); - break; - case TIR: - if (g_pucTIRData != NULL) { - free(g_pucTIRData); - g_pucTIRData = NULL; - } - g_pucTIRData = (unsigned char *) malloc(usSize / 8 + 2); - break; - case HDR: - if (g_pucHDRData != NULL) { - free(g_pucHDRData); - g_pucHDRData = NULL; - } - g_pucHDRData = (unsigned char *) malloc(usSize / 8 + 2); - break; - case TDR: - if (g_pucTDRData != NULL) { - free(g_pucTDRData); - g_pucTDRData = NULL; - } - g_pucTDRData = (unsigned char *) malloc(usSize / 8 + 2); - break; - case HEAP: - if (g_pucHeapMemory != NULL) { - free(g_pucHeapMemory); - g_pucHeapMemory = NULL; - } - g_pucHeapMemory = (unsigned char *) malloc(usSize + 2); - break; - case DMASK: - if (g_pucOutDMaskData != NULL) { - if (previous_size == usSize) { /*already allocated*/ - break; - } else { - free(g_pucOutDMaskData); - g_pucOutDMaskData = NULL; - } - } - g_pucOutDMaskData = (unsigned char *) malloc(usSize / 8 + 2); - previous_size = usSize; - break; - case LHEAP: - if (g_pucIntelBuffer != NULL) { - free(g_pucIntelBuffer); - g_pucIntelBuffer = NULL; - } - g_pucIntelBuffer = (unsigned char *) malloc(usSize + 2); - break; - case LVDS: - if (g_pLVDSList != NULL) { - free(g_pLVDSList); - g_pLVDSList = NULL; - } - g_pLVDSList = (LVDSPair *) malloc(usSize * sizeof(LVDSPair)); - if (g_pLVDSList) - memset(g_pLVDSList, 0, usSize * sizeof(LVDSPair)); - break; - default: - return; - } -} - -void ispVMFreeMem(void) -{ - if (g_pucHeapMemory != NULL) { - free(g_pucHeapMemory); - g_pucHeapMemory = NULL; - } - - if (g_pucOutMaskData != NULL) { - free(g_pucOutMaskData); - g_pucOutMaskData = NULL; - } - - if (g_pucInData != NULL) { - free(g_pucInData); - g_pucInData = NULL; - } - - if (g_pucOutData != NULL) { - free(g_pucOutData); - g_pucOutData = NULL; - } - - if (g_pucHIRData != NULL) { - free(g_pucHIRData); - g_pucHIRData = NULL; - } - - if (g_pucTIRData != NULL) { - free(g_pucTIRData); - g_pucTIRData = NULL; - } - - if (g_pucHDRData != NULL) { - free(g_pucHDRData); - g_pucHDRData = NULL; - } - - if (g_pucTDRData != NULL) { - free(g_pucTDRData); - g_pucTDRData = NULL; - } - - if (g_pucOutDMaskData != NULL) { - free(g_pucOutDMaskData); - g_pucOutDMaskData = NULL; - } - - if (g_pucIntelBuffer != NULL) { - free(g_pucIntelBuffer); - g_pucIntelBuffer = NULL; - } - - if (g_pLVDSList != NULL) { - free(g_pLVDSList); - g_pLVDSList = NULL; - } -} - -/* - * - * ispVMDataSize - * - * Returns a VME-encoded number, usually used to indicate the - * bit length of an SIR/SDR command. - * - */ - -long ispVMDataSize(void) -{ - /* 09/11/07 NN added local variables initialization */ - long int iSize = 0; - signed char cCurrentByte = 0; - signed char cIndex = 0; - cIndex = 0; - while ((cCurrentByte = GetByte()) & 0x80) { - iSize |= ((long int) (cCurrentByte & 0x7F)) << cIndex; - cIndex += 7; - } - iSize |= ((long int) (cCurrentByte & 0x7F)) << cIndex; - return iSize; -} - -/* - * - * ispVMCode - * - * This is the heart of the embedded engine. All the high-level opcodes - * are extracted here. Once they have been identified, then it - * will call other functions to handle the processing. - * - */ - -signed char ispVMCode(void) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short iRepeatSize = 0; - signed char cOpcode = 0; - signed char cRetCode = 0; - unsigned char ucState = 0; - unsigned short usDelay = 0; - unsigned short usToggle = 0; - unsigned char usByte = 0; - - /* - * - * Check the compression flag only if this is the first time - * this function is entered. Do not check the compression flag if - * it is being called recursively from other functions within - * the embedded engine. - * - */ - - if (!(g_usDataType & LHEAP_IN) && !(g_usDataType & HEAP_IN)) { - usByte = GetByte(); - if (usByte == 0xf1) { - g_usDataType |= COMPRESS; - } else if (usByte == 0xf2) { - g_usDataType &= ~COMPRESS; - } else { - return VME_INVALID_FILE; - } - } - - /* - * - * Begin looping through all the VME opcodes. - * - */ - - while ((cOpcode = GetByte()) >= 0) { - - switch (cOpcode) { - case STATE: - - /* - * Step the JTAG state machine. - */ - - ucState = GetByte(); - - /* - * Step the JTAG state machine to DRCAPTURE - * to support Looping. - */ - - if ((g_usDataType & LHEAP_IN) && - (ucState == DRPAUSE) && - (g_cCurrentJTAGState == ucState)) { - ispVMStateMachine(DRCAPTURE); - } - - ispVMStateMachine(ucState); - -#ifdef DEBUG - if (g_usDataType & LHEAP_IN) { - debug("LDELAY %s ", GetState(ucState)); - } else { - debug("STATE %s;\n", GetState(ucState)); - } -#endif /* DEBUG */ - break; - case SIR: - case SDR: - case XSDR: - -#ifdef DEBUG - switch (cOpcode) { - case SIR: - puts("SIR "); - break; - case SDR: - case XSDR: - if (g_usDataType & LHEAP_IN) { - puts("LSDR "); - } else { - puts("SDR "); - } - break; - } -#endif /* DEBUG */ - /* - * - * Shift in data into the device. - * - */ - - cRetCode = ispVMShift(cOpcode); - if (cRetCode != 0) { - return cRetCode; - } - break; - case WAIT: - - /* - * - * Observe delay. - * - */ - - /* 09/11/07 NN Type cast mismatch variables */ - usDelay = (unsigned short) ispVMDataSize(); - ispVMDelay(usDelay); - -#ifdef DEBUG - if (usDelay & 0x8000) { - - /* - * Since MSB is set, the delay time must be - * decoded to millisecond. The SVF2VME encodes - * the MSB to represent millisecond. - */ - - usDelay &= ~0x8000; - if (g_usDataType & LHEAP_IN) { - printf("%.2E SEC;\n", - (float) usDelay / 1000); - } else { - printf("RUNTEST %.2E SEC;\n", - (float) usDelay / 1000); - } - } else { - /* - * Since MSB is not set, the delay time - * is given as microseconds. - */ - - if (g_usDataType & LHEAP_IN) { - printf("%.2E SEC;\n", - (float) usDelay / 1000000); - } else { - printf("RUNTEST %.2E SEC;\n", - (float) usDelay / 1000000); - } - } -#endif /* DEBUG */ - break; - case TCK: - - /* - * Issue clock toggles. - */ - - /* 09/11/07 NN Type cast mismatch variables */ - usToggle = (unsigned short) ispVMDataSize(); - ispVMClocks(usToggle); - -#ifdef DEBUG - printf("RUNTEST %d TCK;\n", usToggle); -#endif /* DEBUG */ - break; - case ENDDR: - - /* - * - * Set the ENDDR. - * - */ - - g_ucEndDR = GetByte(); - -#ifdef DEBUG - printf("ENDDR %s;\n", GetState(g_ucEndDR)); -#endif /* DEBUG */ - break; - case ENDIR: - - /* - * - * Set the ENDIR. - * - */ - - g_ucEndIR = GetByte(); - -#ifdef DEBUG - printf("ENDIR %s;\n", GetState(g_ucEndIR)); -#endif /* DEBUG */ - break; - case HIR: - case TIR: - case HDR: - case TDR: - -#ifdef DEBUG - switch (cOpcode) { - case HIR: - puts("HIR "); - break; - case TIR: - puts("TIR "); - break; - case HDR: - puts("HDR "); - break; - case TDR: - puts("TDR "); - break; - } -#endif /* DEBUG */ - /* - * Set the header/trailer of the device in order - * to bypass - * successfully. - */ - - cRetCode = ispVMAmble(cOpcode); - if (cRetCode != 0) { - return cRetCode; - } - -#ifdef DEBUG - puts(";\n"); -#endif /* DEBUG */ - break; - case MEM: - - /* - * The maximum RAM required to support - * processing one row of the VME file. - */ - - /* 09/11/07 NN Type cast mismatch variables */ - g_usMaxSize = (unsigned short) ispVMDataSize(); - -#ifdef DEBUG - printf("// MEMSIZE %d\n", g_usMaxSize); -#endif /* DEBUG */ - break; - case VENDOR: - - /* - * - * Set the VENDOR type. - * - */ - - cOpcode = GetByte(); - switch (cOpcode) { - case LATTICE: -#ifdef DEBUG - puts("// VENDOR LATTICE\n"); -#endif /* DEBUG */ - g_cVendor = LATTICE; - break; - case ALTERA: -#ifdef DEBUG - puts("// VENDOR ALTERA\n"); -#endif /* DEBUG */ - g_cVendor = ALTERA; - break; - case XILINX: -#ifdef DEBUG - puts("// VENDOR XILINX\n"); -#endif /* DEBUG */ - g_cVendor = XILINX; - break; - default: - break; - } - break; - case SETFLOW: - - /* - * Set the flow control. Flow control determines - * the personality of the embedded engine. - */ - - /* 09/11/07 NN Type cast mismatch variables */ - g_usFlowControl |= (unsigned short) ispVMDataSize(); - break; - case RESETFLOW: - - /* - * - * Unset the flow control. - * - */ - - /* 09/11/07 NN Type cast mismatch variables */ - g_usFlowControl &= (unsigned short) ~(ispVMDataSize()); - break; - case HEAP: - - /* - * - * Allocate heap size to store loops. - * - */ - - cRetCode = GetByte(); - if (cRetCode != SECUREHEAP) { - return VME_INVALID_FILE; - } - /* 09/11/07 NN Type cast mismatch variables */ - g_iHEAPSize = (unsigned short) ispVMDataSize(); - - /* - * Store the maximum size of the HEAP buffer. - * Used to convert VME to HEX. - */ - - if (g_iHEAPSize > g_usHeapSize) { - g_usHeapSize = g_iHEAPSize; - } - - ispVMMemManager(HEAP, (unsigned short) g_iHEAPSize); - break; - case REPEAT: - - /* - * - * Execute loops. - * - */ - - g_usRepeatLoops = 0; - - /* 09/11/07 NN Type cast mismatch variables */ - iRepeatSize = (unsigned short) ispVMDataSize(); - - cRetCode = ispVMLoop((unsigned short) iRepeatSize); - if (cRetCode != 0) { - return cRetCode; - } - break; - case ENDLOOP: - - /* - * - * Exit point from processing loops. - * - */ - - return cRetCode; - case ENDVME: - - /* - * The only valid exit point that indicates - * end of programming. - */ - - return cRetCode; - case SHR: - - /* - * - * Right-shift address. - * - */ - - g_usFlowControl |= SHIFTRIGHT; - - /* 09/11/07 NN Type cast mismatch variables */ - g_usShiftValue = (unsigned short) (g_usRepeatLoops * - (unsigned short)GetByte()); - break; - case SHL: - - /* - * Left-shift address. - */ - - g_usFlowControl |= SHIFTLEFT; - - /* 09/11/07 NN Type cast mismatch variables */ - g_usShiftValue = (unsigned short) (g_usRepeatLoops * - (unsigned short)GetByte()); - break; - case FREQUENCY: - - /* - * - * Set the frequency. - * - */ - - /* 09/11/07 NN Type cast mismatch variables */ - g_iFrequency = (int) (ispVMDataSize() / 1000); - if (g_iFrequency == 1) - g_iFrequency = 1000; - -#ifdef DEBUG - printf("FREQUENCY %.2E HZ;\n", - (float) g_iFrequency * 1000); -#endif /* DEBUG */ - break; - case LCOUNT: - - /* - * - * Process LCOUNT command. - * - */ - - cRetCode = ispVMLCOUNT((unsigned short)ispVMDataSize()); - if (cRetCode != 0) { - return cRetCode; - } - break; - case VUES: - - /* - * - * Set the flow control to verify USERCODE. - * - */ - - g_usFlowControl |= VERIFYUES; - break; - case COMMENT: - - /* - * - * Display comment. - * - */ - - ispVMComment((unsigned short) ispVMDataSize()); - break; - case LVDS: - - /* - * - * Process LVDS command. - * - */ - - ispVMProcessLVDS((unsigned short) ispVMDataSize()); - break; - case HEADER: - - /* - * - * Discard header. - * - */ - - ispVMHeader((unsigned short) ispVMDataSize()); - break; - /* 03/14/06 Support Toggle ispENABLE signal*/ - case ispEN: - ucState = GetByte(); - if ((ucState == ON) || (ucState == 0x01)) - writePort(g_ucPinENABLE, 0x01); - else - writePort(g_ucPinENABLE, 0x00); - ispVMDelay(1); - break; - /* 05/24/06 support Toggle TRST pin*/ - case TRST: - ucState = GetByte(); - if (ucState == 0x01) - writePort(g_ucPinTRST, 0x01); - else - writePort(g_ucPinTRST, 0x00); - ispVMDelay(1); - break; - default: - - /* - * - * Invalid opcode encountered. - * - */ - -#ifdef DEBUG - printf("\nINVALID OPCODE: 0x%.2X\n", cOpcode); -#endif /* DEBUG */ - - return VME_INVALID_FILE; - } - } - - /* - * - * Invalid exit point. Processing the token 'ENDVME' is the only - * valid way to exit the embedded engine. - * - */ - - return VME_INVALID_FILE; -} - -/* - * - * ispVMDataCode - * - * Processes the TDI/TDO/MASK/DMASK etc of an SIR/SDR command. - * - */ - -signed char ispVMDataCode(void) -{ - /* 09/11/07 NN added local variables initialization */ - signed char cDataByte = 0; - signed char siDataSource = 0; /*source of data from file by default*/ - - if (g_usDataType & HEAP_IN) { - siDataSource = 1; /*the source of data from memory*/ - } - - /* - * - * Clear the data type register. - * - **/ - - g_usDataType &= ~(MASK_DATA + TDI_DATA + - TDO_DATA + DMASK_DATA + CMASK_DATA); - - /* - * Iterate through SIR/SDR command and look for TDI, - * TDO, MASK, etc. - */ - - while ((cDataByte = GetByte()) >= 0) { - ispVMMemManager(cDataByte, g_usMaxSize); - switch (cDataByte) { - case TDI: - - /* - * Store the maximum size of the TDI buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usTDISize) { - g_usTDISize = g_usiDataSize; - } - /* - * Updated data type register to indicate that - * TDI data is currently being used. Process the - * data in the VME file into the TDI buffer. - */ - - g_usDataType |= TDI_DATA; - ispVMData(g_pucInData); - break; - case XTDO: - - /* - * Store the maximum size of the TDO buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usTDOSize) { - g_usTDOSize = g_usiDataSize; - } - - /* - * Updated data type register to indicate that - * TDO data is currently being used. - */ - - g_usDataType |= TDO_DATA; - break; - case TDO: - - /* - * Store the maximum size of the TDO buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usTDOSize) { - g_usTDOSize = g_usiDataSize; - } - - /* - * Updated data type register to indicate - * that TDO data is currently being used. - * Process the data in the VME file into the - * TDO buffer. - */ - - g_usDataType |= TDO_DATA; - ispVMData(g_pucOutData); - break; - case MASK: - - /* - * Store the maximum size of the MASK buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usMASKSize) { - g_usMASKSize = g_usiDataSize; - } - - /* - * Updated data type register to indicate that - * MASK data is currently being used. Process - * the data in the VME file into the MASK buffer - */ - - g_usDataType |= MASK_DATA; - ispVMData(g_pucOutMaskData); - break; - case DMASK: - - /* - * Store the maximum size of the DMASK buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usDMASKSize) { - g_usDMASKSize = g_usiDataSize; - } - - /* - * Updated data type register to indicate that - * DMASK data is currently being used. Process - * the data in the VME file into the DMASK - * buffer. - */ - - g_usDataType |= DMASK_DATA; - ispVMData(g_pucOutDMaskData); - break; - case CMASK: - - /* - * Updated data type register to indicate that - * MASK data is currently being used. Process - * the data in the VME file into the MASK buffer - */ - - g_usDataType |= CMASK_DATA; - ispVMData(g_pucOutMaskData); - break; - case CONTINUE: - return 0; - default: - /* - * Encountered invalid opcode. - */ - return VME_INVALID_FILE; - } - - switch (cDataByte) { - case TDI: - - /* - * Left bit shift. Used when performing - * algorithm looping. - */ - - if (g_usFlowControl & SHIFTLEFT) { - ispVMBitShift(SHL, g_usShiftValue); - g_usFlowControl &= ~SHIFTLEFT; - } - - /* - * Right bit shift. Used when performing - * algorithm looping. - */ - - if (g_usFlowControl & SHIFTRIGHT) { - ispVMBitShift(SHR, g_usShiftValue); - g_usFlowControl &= ~SHIFTRIGHT; - } - default: - break; - } - - if (siDataSource) { - g_usDataType |= HEAP_IN; /*restore from memory*/ - } - } - - if (siDataSource) { /*fetch data from heap memory upon return*/ - g_usDataType |= HEAP_IN; - } - - if (cDataByte < 0) { - - /* - * Encountered invalid opcode. - */ - - return VME_INVALID_FILE; - } else { - return 0; - } -} - -/* - * - * ispVMData - * Extract one row of data operand from the current data type opcode. Perform - * the decompression if necessary. Extra RAM is not required for the - * decompression process. The decompression scheme employed in this module - * is on row by row basis. The format of the data stream: - * [compression code][compressed data stream] - * 0x00 --No compression - * 0x01 --Compress by 0x00. - * Example: - * Original stream: 0x000000000000000000000001 - * Compressed stream: 0x01000901 - * Detail: 0x01 is the code, 0x00 is the key, - * 0x09 is the count of 0x00 bytes, - * 0x01 is the uncompressed byte. - * 0x02 --Compress by 0xFF. - * Example: - * Original stream: 0xFFFFFFFFFFFFFFFFFFFFFF01 - * Compressed stream: 0x02FF0901 - * Detail: 0x02 is the code, 0xFF is the key, - * 0x09 is the count of 0xFF bytes, - * 0x01 is the uncompressed byte. - * 0x03 - * : : - * 0xFE -- Compress by nibble blocks. - * Example: - * Original stream: 0x84210842108421084210 - * Compressed stream: 0x0584210 - * Detail: 0x05 is the code, means 5 nibbles block. - * 0x84210 is the 5 nibble blocks. - * The whole row is 80 bits given by g_usiDataSize. - * The number of times the block repeat itself - * is found by g_usiDataSize/(4*0x05) which is 4. - * 0xFF -- Compress by the most frequently happen byte. - * Example: - * Original stream: 0x04020401030904040404 - * Compressed stream: 0xFF04(0,1,0x02,0,1,0x01,1,0x03,1,0x09,0,0,0) - * or: 0xFF044090181C240 - * Detail: 0xFF is the code, 0x04 is the key. - * a bit of 0 represent the key shall be put into - * the current bit position and a bit of 1 - * represent copying the next of 8 bits of data - * in. - * - */ - -void ispVMData(unsigned char *ByteData) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short size = 0; - unsigned short i, j, m, getData = 0; - unsigned char cDataByte = 0; - unsigned char compress = 0; - unsigned short FFcount = 0; - unsigned char compr_char = 0xFF; - unsigned short index = 0; - signed char compression = 0; - - /*convert number in bits to bytes*/ - if (g_usiDataSize % 8 > 0) { - /* 09/11/07 NN Type cast mismatch variables */ - size = (unsigned short)(g_usiDataSize / 8 + 1); - } else { - /* 09/11/07 NN Type cast mismatch variables */ - size = (unsigned short)(g_usiDataSize / 8); - } - - /* - * If there is compression, then check if compress by key - * of 0x00 or 0xFF or by other keys or by nibble blocks - */ - - if (g_usDataType & COMPRESS) { - compression = 1; - compress = GetByte(); - if ((compress == VAR) && (g_usDataType & HEAP_IN)) { - getData = 1; - g_usDataType &= ~(HEAP_IN); - compress = GetByte(); - } - - switch (compress) { - case 0x00: - /* No compression */ - compression = 0; - break; - case 0x01: - /* Compress by byte 0x00 */ - compr_char = 0x00; - break; - case 0x02: - /* Compress by byte 0xFF */ - compr_char = 0xFF; - break; - case 0xFF: - /* Huffman encoding */ - compr_char = GetByte(); - i = 8; - for (index = 0; index < size; index++) { - ByteData[index] = 0x00; - if (i > 7) { - cDataByte = GetByte(); - i = 0; - } - if ((cDataByte << i++) & 0x80) - m = 8; - else { - ByteData[index] = compr_char; - m = 0; - } - - for (j = 0; j < m; j++) { - if (i > 7) { - cDataByte = GetByte(); - i = 0; - } - ByteData[index] |= - ((cDataByte << i++) & 0x80) >> j; - } - } - size = 0; - break; - default: - for (index = 0; index < size; index++) - ByteData[index] = 0x00; - for (index = 0; index < compress; index++) { - if (index % 2 == 0) - cDataByte = GetByte(); - for (i = 0; i < size * 2 / compress; i++) { - j = (unsigned short)(index + - (i * (unsigned short)compress)); - /*clear the nibble to zero first*/ - if (j%2) { - if (index % 2) - ByteData[j/2] |= - cDataByte & 0xF; - else - ByteData[j/2] |= - cDataByte >> 4; - } else { - if (index % 2) - ByteData[j/2] |= - cDataByte << 4; - else - ByteData[j/2] |= - cDataByte & 0xF0; - } - } - } - size = 0; - break; - } - } - - FFcount = 0; - - /* Decompress by byte 0x00 or 0xFF */ - for (index = 0; index < size; index++) { - if (FFcount <= 0) { - cDataByte = GetByte(); - if ((cDataByte == VAR) && (g_usDataType&HEAP_IN) && - !getData && !(g_usDataType&COMPRESS)) { - getData = 1; - g_usDataType &= ~(HEAP_IN); - cDataByte = GetByte(); - } - ByteData[index] = cDataByte; - if ((compression) && (cDataByte == compr_char)) - /* 09/11/07 NN Type cast mismatch variables */ - FFcount = (unsigned short) ispVMDataSize(); - /*The number of 0xFF or 0x00 bytes*/ - } else { - FFcount--; /*Use up the 0xFF chain first*/ - ByteData[index] = compr_char; - } - } - - if (getData) { - g_usDataType |= HEAP_IN; - getData = 0; - } -} - -/* - * - * ispVMShift - * - * Processes the SDR/XSDR/SIR commands. - * - */ - -signed char ispVMShift(signed char a_cCode) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short iDataIndex = 0; - unsigned short iReadLoop = 0; - signed char cRetCode = 0; - - cRetCode = 0; - /* 09/11/07 NN Type cast mismatch variables */ - g_usiDataSize = (unsigned short) ispVMDataSize(); - - /*clear the flags first*/ - g_usDataType &= ~(SIR_DATA + EXPRESS + SDR_DATA); - switch (a_cCode) { - case SIR: - g_usDataType |= SIR_DATA; - /* - * 1/15/04 If performing cascading, then go directly to SHIFTIR. - * Else, go to IRPAUSE before going to SHIFTIR - */ - if (g_usFlowControl & CASCADE) { - ispVMStateMachine(SHIFTIR); - } else { - ispVMStateMachine(IRPAUSE); - ispVMStateMachine(SHIFTIR); - if (g_usHeadIR > 0) { - ispVMBypass(HIR, g_usHeadIR); - sclock(); - } - } - break; - case XSDR: - g_usDataType |= EXPRESS; /*mark simultaneous in and out*/ - case SDR: - g_usDataType |= SDR_DATA; - /* - * 1/15/04 If already in SHIFTDR, then do not move state or - * shift in header. This would imply that the previously - * shifted frame was a cascaded frame. - */ - if (g_cCurrentJTAGState != SHIFTDR) { - /* - * 1/15/04 If performing cascading, then go directly - * to SHIFTDR. Else, go to DRPAUSE before going - * to SHIFTDR - */ - if (g_usFlowControl & CASCADE) { - if (g_cCurrentJTAGState == DRPAUSE) { - ispVMStateMachine(SHIFTDR); - /* - * 1/15/04 If cascade flag has been seat - * and the current state is DRPAUSE, - * this implies that the first cascaded - * frame is about to be shifted in. The - * header must be shifted prior to - * shifting the first cascaded frame. - */ - if (g_usHeadDR > 0) { - ispVMBypass(HDR, g_usHeadDR); - sclock(); - } - } else { - ispVMStateMachine(SHIFTDR); - } - } else { - ispVMStateMachine(DRPAUSE); - ispVMStateMachine(SHIFTDR); - if (g_usHeadDR > 0) { - ispVMBypass(HDR, g_usHeadDR); - sclock(); - } - } - } - break; - default: - return VME_INVALID_FILE; - } - - cRetCode = ispVMDataCode(); - - if (cRetCode != 0) { - return VME_INVALID_FILE; - } - -#ifdef DEBUG - printf("%d ", g_usiDataSize); - - if (g_usDataType & TDI_DATA) { - puts("TDI "); - PrintData(g_usiDataSize, g_pucInData); - } - - if (g_usDataType & TDO_DATA) { - puts("\n\t\tTDO "); - PrintData(g_usiDataSize, g_pucOutData); - } - - if (g_usDataType & MASK_DATA) { - puts("\n\t\tMASK "); - PrintData(g_usiDataSize, g_pucOutMaskData); - } - - if (g_usDataType & DMASK_DATA) { - puts("\n\t\tDMASK "); - PrintData(g_usiDataSize, g_pucOutDMaskData); - } - - puts(";\n"); -#endif /* DEBUG */ - - if (g_usDataType & TDO_DATA || g_usDataType & DMASK_DATA) { - if (g_usDataType & DMASK_DATA) { - cRetCode = ispVMReadandSave(g_usiDataSize); - if (!cRetCode) { - if (g_usTailDR > 0) { - sclock(); - ispVMBypass(TDR, g_usTailDR); - } - ispVMStateMachine(DRPAUSE); - ispVMStateMachine(SHIFTDR); - if (g_usHeadDR > 0) { - ispVMBypass(HDR, g_usHeadDR); - sclock(); - } - for (iDataIndex = 0; - iDataIndex < g_usiDataSize / 8 + 1; - iDataIndex++) - g_pucInData[iDataIndex] = - g_pucOutData[iDataIndex]; - g_usDataType &= ~(TDO_DATA + DMASK_DATA); - cRetCode = ispVMSend(g_usiDataSize); - } - } else { - cRetCode = ispVMRead(g_usiDataSize); - if (cRetCode == -1 && g_cVendor == XILINX) { - for (iReadLoop = 0; iReadLoop < 30; - iReadLoop++) { - cRetCode = ispVMRead(g_usiDataSize); - if (!cRetCode) { - break; - } else { - /* Always DRPAUSE */ - ispVMStateMachine(DRPAUSE); - /* - * Bypass other devices - * when appropriate - */ - ispVMBypass(TDR, g_usTailDR); - ispVMStateMachine(g_ucEndDR); - ispVMStateMachine(IDLE); - ispVMDelay(1000); - } - } - } - } - } else { /*TDI only*/ - cRetCode = ispVMSend(g_usiDataSize); - } - - /*transfer the input data to the output buffer for the next verify*/ - if ((g_usDataType & EXPRESS) || (a_cCode == SDR)) { - if (g_pucOutData) { - for (iDataIndex = 0; iDataIndex < g_usiDataSize / 8 + 1; - iDataIndex++) - g_pucOutData[iDataIndex] = - g_pucInData[iDataIndex]; - } - } - - switch (a_cCode) { - case SIR: - /* 1/15/04 If not performing cascading, then shift ENDIR */ - if (!(g_usFlowControl & CASCADE)) { - if (g_usTailIR > 0) { - sclock(); - ispVMBypass(TIR, g_usTailIR); - } - ispVMStateMachine(g_ucEndIR); - } - break; - case XSDR: - case SDR: - /* 1/15/04 If not performing cascading, then shift ENDDR */ - if (!(g_usFlowControl & CASCADE)) { - if (g_usTailDR > 0) { - sclock(); - ispVMBypass(TDR, g_usTailDR); - } - ispVMStateMachine(g_ucEndDR); - } - break; - default: - break; - } - - return cRetCode; -} - -/* - * - * ispVMAmble - * - * This routine is to extract Header and Trailer parameter for SIR and - * SDR operations. - * - * The Header and Trailer parameter are the pre-amble and post-amble bit - * stream need to be shifted into TDI or out of TDO of the devices. Mostly - * is for the purpose of bypassing the leading or trailing devices. ispVM - * supports only shifting data into TDI to bypass the devices. - * - * For a single device, the header and trailer parameters are all set to 0 - * as default by ispVM. If it is for multiple devices, the header and trailer - * value will change as specified by the VME file. - * - */ - -signed char ispVMAmble(signed char Code) -{ - signed char compress = 0; - /* 09/11/07 NN Type cast mismatch variables */ - g_usiDataSize = (unsigned short)ispVMDataSize(); - -#ifdef DEBUG - printf("%d", g_usiDataSize); -#endif /* DEBUG */ - - if (g_usiDataSize) { - - /* - * Discard the TDI byte and set the compression bit in the data - * type register to false if compression is set because TDI data - * after HIR/HDR/TIR/TDR is not compressed. - */ - - GetByte(); - if (g_usDataType & COMPRESS) { - g_usDataType &= ~(COMPRESS); - compress = 1; - } - } - - switch (Code) { - case HIR: - - /* - * Store the maximum size of the HIR buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usHIRSize) { - g_usHIRSize = g_usiDataSize; - } - - /* - * Assign the HIR value and allocate memory. - */ - - g_usHeadIR = g_usiDataSize; - if (g_usHeadIR) { - ispVMMemManager(HIR, g_usHeadIR); - ispVMData(g_pucHIRData); - -#ifdef DEBUG - puts(" TDI "); - PrintData(g_usHeadIR, g_pucHIRData); -#endif /* DEBUG */ - } - break; - case TIR: - - /* - * Store the maximum size of the TIR buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usTIRSize) { - g_usTIRSize = g_usiDataSize; - } - - /* - * Assign the TIR value and allocate memory. - */ - - g_usTailIR = g_usiDataSize; - if (g_usTailIR) { - ispVMMemManager(TIR, g_usTailIR); - ispVMData(g_pucTIRData); - -#ifdef DEBUG - puts(" TDI "); - PrintData(g_usTailIR, g_pucTIRData); -#endif /* DEBUG */ - } - break; - case HDR: - - /* - * Store the maximum size of the HDR buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usHDRSize) { - g_usHDRSize = g_usiDataSize; - } - - /* - * Assign the HDR value and allocate memory. - * - */ - - g_usHeadDR = g_usiDataSize; - if (g_usHeadDR) { - ispVMMemManager(HDR, g_usHeadDR); - ispVMData(g_pucHDRData); - -#ifdef DEBUG - puts(" TDI "); - PrintData(g_usHeadDR, g_pucHDRData); -#endif /* DEBUG */ - } - break; - case TDR: - - /* - * Store the maximum size of the TDR buffer. - * Used to convert VME to HEX. - */ - - if (g_usiDataSize > g_usTDRSize) { - g_usTDRSize = g_usiDataSize; - } - - /* - * Assign the TDR value and allocate memory. - * - */ - - g_usTailDR = g_usiDataSize; - if (g_usTailDR) { - ispVMMemManager(TDR, g_usTailDR); - ispVMData(g_pucTDRData); - -#ifdef DEBUG - puts(" TDI "); - PrintData(g_usTailDR, g_pucTDRData); -#endif /* DEBUG */ - } - break; - default: - break; - } - - /* - * - * Re-enable compression if it was previously set. - * - **/ - - if (compress) { - g_usDataType |= COMPRESS; - } - - if (g_usiDataSize) { - Code = GetByte(); - if (Code == CONTINUE) { - return 0; - } else { - - /* - * Encountered invalid opcode. - */ - - return VME_INVALID_FILE; - } - } - - return 0; -} - -/* - * - * ispVMLoop - * - * Perform the function call upon by the REPEAT opcode. - * Memory is to be allocated to store the entire loop from REPEAT to ENDLOOP. - * After the loop is stored then execution begin. The REPEATLOOP flag is set - * on the g_usFlowControl register to indicate the repeat loop is in session - * and therefore fetch opcode from the memory instead of from the file. - * - */ - -signed char ispVMLoop(unsigned short a_usLoopCount) -{ - /* 09/11/07 NN added local variables initialization */ - signed char cRetCode = 0; - unsigned short iHeapIndex = 0; - unsigned short iLoopIndex = 0; - - g_usShiftValue = 0; - for (iHeapIndex = 0; iHeapIndex < g_iHEAPSize; iHeapIndex++) { - g_pucHeapMemory[iHeapIndex] = GetByte(); - } - - if (g_pucHeapMemory[iHeapIndex - 1] != ENDLOOP) { - return VME_INVALID_FILE; - } - - g_usFlowControl |= REPEATLOOP; - g_usDataType |= HEAP_IN; - - for (iLoopIndex = 0; iLoopIndex < a_usLoopCount; iLoopIndex++) { - g_iHeapCounter = 0; - cRetCode = ispVMCode(); - g_usRepeatLoops++; - if (cRetCode < 0) { - break; - } - } - - g_usDataType &= ~(HEAP_IN); - g_usFlowControl &= ~(REPEATLOOP); - return cRetCode; -} - -/* - * - * ispVMBitShift - * - * Shift the TDI stream left or right by the number of bits. The data in - * *g_pucInData is of the VME format, so the actual shifting is the reverse of - * IEEE 1532 or SVF format. - * - */ - -signed char ispVMBitShift(signed char mode, unsigned short bits) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short i = 0; - unsigned short size = 0; - unsigned short tmpbits = 0; - - if (g_usiDataSize % 8 > 0) { - /* 09/11/07 NN Type cast mismatch variables */ - size = (unsigned short)(g_usiDataSize / 8 + 1); - } else { - /* 09/11/07 NN Type cast mismatch variables */ - size = (unsigned short)(g_usiDataSize / 8); - } - - switch (mode) { - case SHR: - for (i = 0; i < size; i++) { - if (g_pucInData[i] != 0) { - tmpbits = bits; - while (tmpbits > 0) { - g_pucInData[i] <<= 1; - if (g_pucInData[i] == 0) { - i--; - g_pucInData[i] = 1; - } - tmpbits--; - } - } - } - break; - case SHL: - for (i = 0; i < size; i++) { - if (g_pucInData[i] != 0) { - tmpbits = bits; - while (tmpbits > 0) { - g_pucInData[i] >>= 1; - if (g_pucInData[i] == 0) { - i--; - g_pucInData[i] = 8; - } - tmpbits--; - } - } - } - break; - default: - return VME_INVALID_FILE; - } - - return 0; -} - -/* - * - * ispVMComment - * - * Displays the SVF comments. - * - */ - -void ispVMComment(unsigned short a_usCommentSize) -{ - char cCurByte = 0; - for (; a_usCommentSize > 0; a_usCommentSize--) { - /* - * - * Print character to the terminal. - * - **/ - cCurByte = GetByte(); - vme_out_char(cCurByte); - } - cCurByte = '\n'; - vme_out_char(cCurByte); -} - -/* - * - * ispVMHeader - * - * Iterate the length of the header and discard it. - * - */ - -void ispVMHeader(unsigned short a_usHeaderSize) -{ - for (; a_usHeaderSize > 0; a_usHeaderSize--) { - GetByte(); - } -} - -/* - * - * ispVMCalculateCRC32 - * - * Calculate the 32-bit CRC. - * - */ - -void ispVMCalculateCRC32(unsigned char a_ucData) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned char ucIndex = 0; - unsigned char ucFlipData = 0; - unsigned short usCRCTableEntry = 0; - unsigned int crc_table[16] = { - 0x0000, 0xCC01, 0xD801, - 0x1400, 0xF001, 0x3C00, - 0x2800, 0xE401, 0xA001, - 0x6C00, 0x7800, 0xB401, - 0x5000, 0x9C01, 0x8801, - 0x4400 - }; - - for (ucIndex = 0; ucIndex < 8; ucIndex++) { - ucFlipData <<= 1; - if (a_ucData & 0x01) { - ucFlipData |= 0x01; - } - a_ucData >>= 1; - } - - /* 09/11/07 NN Type cast mismatch variables */ - usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]); - g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF); - g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^ - usCRCTableEntry ^ crc_table[ucFlipData & 0xF]); - usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]); - g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF); - g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^ - usCRCTableEntry ^ crc_table[(ucFlipData >> 4) & 0xF]); -} - -/* - * - * ispVMLCOUNT - * - * Process the intelligent programming loops. - * - */ - -signed char ispVMLCOUNT(unsigned short a_usCountSize) -{ - unsigned short usContinue = 1; - unsigned short usIntelBufferIndex = 0; - unsigned short usCountIndex = 0; - signed char cRetCode = 0; - signed char cRepeatHeap = 0; - signed char cOpcode = 0; - unsigned char ucState = 0; - unsigned short usDelay = 0; - unsigned short usToggle = 0; - - g_usIntelBufferSize = (unsigned short)ispVMDataSize(); - - /* - * Allocate memory for intel buffer. - * - */ - - ispVMMemManager(LHEAP, g_usIntelBufferSize); - - /* - * Store the maximum size of the intelligent buffer. - * Used to convert VME to HEX. - */ - - if (g_usIntelBufferSize > g_usLCOUNTSize) { - g_usLCOUNTSize = g_usIntelBufferSize; - } - - /* - * Copy intel data to the buffer. - */ - - for (usIntelBufferIndex = 0; usIntelBufferIndex < g_usIntelBufferSize; - usIntelBufferIndex++) { - g_pucIntelBuffer[usIntelBufferIndex] = GetByte(); - } - - /* - * Set the data type register to get data from the intelligent - * data buffer. - */ - - g_usDataType |= LHEAP_IN; - - /* - * - * If the HEAP_IN flag is set, temporarily unset the flag so data will be - * retrieved from the status buffer. - * - **/ - - if (g_usDataType & HEAP_IN) { - g_usDataType &= ~HEAP_IN; - cRepeatHeap = 1; - } - -#ifdef DEBUG - printf("LCOUNT %d;\n", a_usCountSize); -#endif /* DEBUG */ - - /* - * Iterate through the intelligent programming command. - */ - - for (usCountIndex = 0; usCountIndex < a_usCountSize; usCountIndex++) { - - /* - * - * Initialize the intel data index to 0 before each iteration. - * - **/ - - g_usIntelDataIndex = 0; - cOpcode = 0; - ucState = 0; - usDelay = 0; - usToggle = 0; - usContinue = 1; - - /* - * - * Begin looping through all the VME opcodes. - * - */ - /* - * 4/1/09 Nguyen replaced the recursive function call codes on - * the ispVMLCOUNT function - * - */ - while (usContinue) { - cOpcode = GetByte(); - switch (cOpcode) { - case HIR: - case TIR: - case HDR: - case TDR: - /* - * Set the header/trailer of the device in order - * to bypass successfully. - */ - - ispVMAmble(cOpcode); - break; - case STATE: - - /* - * Step the JTAG state machine. - */ - - ucState = GetByte(); - /* - * Step the JTAG state machine to DRCAPTURE - * to support Looping. - */ - - if ((g_usDataType & LHEAP_IN) && - (ucState == DRPAUSE) && - (g_cCurrentJTAGState == ucState)) { - ispVMStateMachine(DRCAPTURE); - } - ispVMStateMachine(ucState); -#ifdef DEBUG - printf("LDELAY %s ", GetState(ucState)); -#endif /* DEBUG */ - break; - case SIR: -#ifdef DEBUG - printf("SIR "); -#endif /* DEBUG */ - /* - * Shift in data into the device. - */ - - cRetCode = ispVMShift(cOpcode); - break; - case SDR: - -#ifdef DEBUG - printf("LSDR "); -#endif /* DEBUG */ - /* - * Shift in data into the device. - */ - - cRetCode = ispVMShift(cOpcode); - break; - case WAIT: - - /* - * - * Observe delay. - * - */ - - usDelay = (unsigned short)ispVMDataSize(); - ispVMDelay(usDelay); - -#ifdef DEBUG - if (usDelay & 0x8000) { - - /* - * Since MSB is set, the delay time must - * be decoded to millisecond. The - * SVF2VME encodes the MSB to represent - * millisecond. - */ - - usDelay &= ~0x8000; - printf("%.2E SEC;\n", - (float) usDelay / 1000); - } else { - /* - * Since MSB is not set, the delay time - * is given as microseconds. - */ - - printf("%.2E SEC;\n", - (float) usDelay / 1000000); - } -#endif /* DEBUG */ - break; - case TCK: - - /* - * Issue clock toggles. - */ - - usToggle = (unsigned short)ispVMDataSize(); - ispVMClocks(usToggle); - -#ifdef DEBUG - printf("RUNTEST %d TCK;\n", usToggle); -#endif /* DEBUG */ - break; - case ENDLOOP: - - /* - * Exit point from processing loops. - */ - usContinue = 0; - break; - - case COMMENT: - - /* - * Display comment. - */ - - ispVMComment((unsigned short) ispVMDataSize()); - break; - case ispEN: - ucState = GetByte(); - if ((ucState == ON) || (ucState == 0x01)) - writePort(g_ucPinENABLE, 0x01); - else - writePort(g_ucPinENABLE, 0x00); - ispVMDelay(1); - break; - case TRST: - if (GetByte() == 0x01) - writePort(g_ucPinTRST, 0x01); - else - writePort(g_ucPinTRST, 0x00); - ispVMDelay(1); - break; - default: - - /* - * Invalid opcode encountered. - */ - - debug("\nINVALID OPCODE: 0x%.2X\n", cOpcode); - - return VME_INVALID_FILE; - } - } - if (cRetCode >= 0) { - /* - * Break if intelligent programming is successful. - */ - - break; - } - - } - /* - * If HEAP_IN flag was temporarily disabled, - * re-enable it before exiting - */ - - if (cRepeatHeap) { - g_usDataType |= HEAP_IN; - } - - /* - * Set the data type register to not get data from the - * intelligent data buffer. - */ - - g_usDataType &= ~LHEAP_IN; - return cRetCode; -} -/* - * - * ispVMClocks - * - * Applies the specified number of pulses to TCK. - * - */ - -void ispVMClocks(unsigned short Clocks) -{ - unsigned short iClockIndex = 0; - for (iClockIndex = 0; iClockIndex < Clocks; iClockIndex++) { - sclock(); - } -} - -/* - * - * ispVMBypass - * - * This procedure takes care of the HIR, HDR, TIR, TDR for the - * purpose of putting the other devices into Bypass mode. The - * current state is checked to find out if it is at DRPAUSE or - * IRPAUSE. If it is at DRPAUSE, perform bypass register scan. - * If it is at IRPAUSE, scan into instruction registers the bypass - * instruction. - * - */ - -void ispVMBypass(signed char ScanType, unsigned short Bits) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short iIndex = 0; - unsigned short iSourceIndex = 0; - unsigned char cBitState = 0; - unsigned char cCurByte = 0; - unsigned char *pcSource = NULL; - - if (Bits <= 0) { - return; - } - - switch (ScanType) { - case HIR: - pcSource = g_pucHIRData; - break; - case TIR: - pcSource = g_pucTIRData; - break; - case HDR: - pcSource = g_pucHDRData; - break; - case TDR: - pcSource = g_pucTDRData; - break; - default: - break; - } - - iSourceIndex = 0; - cBitState = 0; - for (iIndex = 0; iIndex < Bits - 1; iIndex++) { - /* Scan instruction or bypass register */ - if (iIndex % 8 == 0) { - cCurByte = pcSource[iSourceIndex++]; - } - cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80) - ? 0x01 : 0x00); - writePort(g_ucPinTDI, cBitState); - sclock(); - } - - if (iIndex % 8 == 0) { - cCurByte = pcSource[iSourceIndex++]; - } - - cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80) - ? 0x01 : 0x00); - writePort(g_ucPinTDI, cBitState); -} - -/* - * - * ispVMStateMachine - * - * This procedure steps all devices in the daisy chain from a given - * JTAG state to the next desirable state. If the next state is TLR, - * the JTAG state machine is brute forced into TLR by driving TMS - * high and pulse TCK 6 times. - * - */ - -void ispVMStateMachine(signed char cNextJTAGState) -{ - /* 09/11/07 NN added local variables initialization */ - signed char cPathIndex = 0; - signed char cStateIndex = 0; - - if ((g_cCurrentJTAGState == cNextJTAGState) && - (cNextJTAGState != RESET)) { - return; - } - - for (cStateIndex = 0; cStateIndex < 25; cStateIndex++) { - if ((g_cCurrentJTAGState == - g_JTAGTransistions[cStateIndex].CurState) && - (cNextJTAGState == - g_JTAGTransistions[cStateIndex].NextState)) { - break; - } - } - - g_cCurrentJTAGState = cNextJTAGState; - for (cPathIndex = 0; - cPathIndex < g_JTAGTransistions[cStateIndex].Pulses; - cPathIndex++) { - if ((g_JTAGTransistions[cStateIndex].Pattern << cPathIndex) - & 0x80) { - writePort(g_ucPinTMS, (unsigned char) 0x01); - } else { - writePort(g_ucPinTMS, (unsigned char) 0x00); - } - sclock(); - } - - writePort(g_ucPinTDI, 0x00); - writePort(g_ucPinTMS, 0x00); -} - -/* - * - * ispVMStart - * - * Enable the port to the device and set the state to RESET (TLR). - * - */ - -void ispVMStart(void) -{ -#ifdef DEBUG - printf("// ISPVM EMBEDDED ADDED\n"); - printf("STATE RESET;\n"); -#endif - g_usFlowControl = 0; - g_usDataType = g_uiChecksumIndex = g_cCurrentJTAGState = 0; - g_usHeadDR = g_usHeadIR = g_usTailDR = g_usTailIR = 0; - g_usMaxSize = g_usShiftValue = g_usRepeatLoops = 0; - g_usTDOSize = g_usMASKSize = g_usTDISize = 0; - g_usDMASKSize = g_usLCOUNTSize = g_usHDRSize = 0; - g_usTDRSize = g_usHIRSize = g_usTIRSize = g_usHeapSize = 0; - g_pLVDSList = NULL; - g_usLVDSPairCount = 0; - previous_size = 0; - - ispVMStateMachine(RESET); /*step devices to RESET state*/ -} - -/* - * - * ispVMEnd - * - * Set the state of devices to RESET to enable the devices and disable - * the port. - * - */ - -void ispVMEnd(void) -{ -#ifdef DEBUG - printf("// ISPVM EMBEDDED ADDED\n"); - printf("STATE RESET;\n"); - printf("RUNTEST 1.00E-001 SEC;\n"); -#endif - - ispVMStateMachine(RESET); /*step devices to RESET state */ - ispVMDelay(1000); /*wake up devices*/ -} - -/* - * - * ispVMSend - * - * Send the TDI data stream to devices. The data stream can be - * instructions or data. - * - */ - -signed char ispVMSend(unsigned short a_usiDataSize) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short iIndex = 0; - unsigned short iInDataIndex = 0; - unsigned char cCurByte = 0; - unsigned char cBitState = 0; - - for (iIndex = 0; iIndex < a_usiDataSize - 1; iIndex++) { - if (iIndex % 8 == 0) { - cCurByte = g_pucInData[iInDataIndex++]; - } - cBitState = (unsigned char)(((cCurByte << iIndex % 8) & 0x80) - ? 0x01 : 0x00); - writePort(g_ucPinTDI, cBitState); - sclock(); - } - - if (iIndex % 8 == 0) { - /* Take care of the last bit */ - cCurByte = g_pucInData[iInDataIndex]; - } - - cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80) - ? 0x01 : 0x00); - - writePort(g_ucPinTDI, cBitState); - if (g_usFlowControl & CASCADE) { - /*1/15/04 Clock in last bit for the first n-1 cascaded frames */ - sclock(); - } - - return 0; -} - -/* - * - * ispVMRead - * - * Read the data stream from devices and verify. - * - */ - -signed char ispVMRead(unsigned short a_usiDataSize) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short usDataSizeIndex = 0; - unsigned short usErrorCount = 0; - unsigned short usLastBitIndex = 0; - unsigned char cDataByte = 0; - unsigned char cMaskByte = 0; - unsigned char cInDataByte = 0; - unsigned char cCurBit = 0; - unsigned char cByteIndex = 0; - unsigned short usBufferIndex = 0; - unsigned char ucDisplayByte = 0x00; - unsigned char ucDisplayFlag = 0x01; - char StrChecksum[256] = {0}; - unsigned char g_usCalculateChecksum = 0x00; - - /* 09/11/07 NN Type cast mismatch variables */ - usLastBitIndex = (unsigned short)(a_usiDataSize - 1); - -#ifndef DEBUG - /* - * If mask is not all zeros, then set the display flag to 0x00, - * otherwise it shall be set to 0x01 to indicate that data read - * from the device shall be displayed. If DEBUG is defined, - * always display data. - */ - - for (usDataSizeIndex = 0; usDataSizeIndex < (a_usiDataSize + 7) / 8; - usDataSizeIndex++) { - if (g_usDataType & MASK_DATA) { - if (g_pucOutMaskData[usDataSizeIndex] != 0x00) { - ucDisplayFlag = 0x00; - break; - } - } else if (g_usDataType & CMASK_DATA) { - g_usCalculateChecksum = 0x01; - ucDisplayFlag = 0x00; - break; - } else { - ucDisplayFlag = 0x00; - break; - } - } -#endif /* DEBUG */ - - /* - * - * Begin shifting data in and out of the device. - * - **/ - - for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize; - usDataSizeIndex++) { - if (cByteIndex == 0) { - - /* - * Grab byte from TDO buffer. - */ - - if (g_usDataType & TDO_DATA) { - cDataByte = g_pucOutData[usBufferIndex]; - } - - /* - * Grab byte from MASK buffer. - */ - - if (g_usDataType & MASK_DATA) { - cMaskByte = g_pucOutMaskData[usBufferIndex]; - } else { - cMaskByte = 0xFF; - } - - /* - * Grab byte from CMASK buffer. - */ - - if (g_usDataType & CMASK_DATA) { - cMaskByte = 0x00; - g_usCalculateChecksum = 0x01; - } - - /* - * Grab byte from TDI buffer. - */ - - if (g_usDataType & TDI_DATA) { - cInDataByte = g_pucInData[usBufferIndex]; - } - - usBufferIndex++; - } - - cCurBit = readPort(); - - if (ucDisplayFlag) { - ucDisplayByte <<= 1; - ucDisplayByte |= cCurBit; - } - - /* - * Check if data read from port matches with expected TDO. - */ - - if (g_usDataType & TDO_DATA) { - /* 08/28/08 NN Added Calculate checksum support. */ - if (g_usCalculateChecksum) { - if (cCurBit == 0x01) - g_usChecksum += - (1 << (g_uiChecksumIndex % 8)); - g_uiChecksumIndex++; - } else { - if ((((cMaskByte << cByteIndex) & 0x80) - ? 0x01 : 0x00)) { - if (cCurBit != (unsigned char) - (((cDataByte << cByteIndex) & 0x80) - ? 0x01 : 0x00)) { - usErrorCount++; - } - } - } - } - - /* - * Write TDI data to the port. - */ - - writePort(g_ucPinTDI, - (unsigned char)(((cInDataByte << cByteIndex) & 0x80) - ? 0x01 : 0x00)); - - if (usDataSizeIndex < usLastBitIndex) { - - /* - * Clock data out from the data shift register. - */ - - sclock(); - } else if (g_usFlowControl & CASCADE) { - - /* - * Clock in last bit for the first N - 1 cascaded frames - */ - - sclock(); - } - - /* - * Increment the byte index. If it exceeds 7, then reset it back - * to zero. - */ - - cByteIndex++; - if (cByteIndex >= 8) { - if (ucDisplayFlag) { - - /* - * Store displayed data in the TDO buffer. By reusing - * the TDO buffer to store displayed data, there is no - * need to allocate a buffer simply to hold display - * data. This will not cause any false verification - * errors because the true TDO byte has already - * been consumed. - */ - - g_pucOutData[usBufferIndex - 1] = ucDisplayByte; - ucDisplayByte = 0; - } - - cByteIndex = 0; - } - /* 09/12/07 Nguyen changed to display the 1 bit expected data */ - else if (a_usiDataSize == 1) { - if (ucDisplayFlag) { - - /* - * Store displayed data in the TDO buffer. - * By reusing the TDO buffer to store displayed - * data, there is no need to allocate - * a buffer simply to hold display data. This - * will not cause any false verification errors - * because the true TDO byte has already - * been consumed. - */ - - /* - * Flip ucDisplayByte and store it in cDataByte. - */ - cDataByte = 0x00; - for (usBufferIndex = 0; usBufferIndex < 8; - usBufferIndex++) { - cDataByte <<= 1; - if (ucDisplayByte & 0x01) { - cDataByte |= 0x01; - } - ucDisplayByte >>= 1; - } - g_pucOutData[0] = cDataByte; - ucDisplayByte = 0; - } - - cByteIndex = 0; - } - } - - if (ucDisplayFlag) { - -#ifdef DEBUG - debug("RECEIVED TDO ("); -#else - vme_out_string("Display Data: 0x"); -#endif /* DEBUG */ - - /* 09/11/07 NN Type cast mismatch variables */ - for (usDataSizeIndex = (unsigned short) - ((a_usiDataSize + 7) / 8); - usDataSizeIndex > 0 ; usDataSizeIndex--) { - cMaskByte = g_pucOutData[usDataSizeIndex - 1]; - cDataByte = 0x00; - - /* - * Flip cMaskByte and store it in cDataByte. - */ - - for (usBufferIndex = 0; usBufferIndex < 8; - usBufferIndex++) { - cDataByte <<= 1; - if (cMaskByte & 0x01) { - cDataByte |= 0x01; - } - cMaskByte >>= 1; - } -#ifdef DEBUG - printf("%.2X", cDataByte); - if ((((a_usiDataSize + 7) / 8) - usDataSizeIndex) - % 40 == 39) { - printf("\n\t\t"); - } -#else - vme_out_hex(cDataByte); -#endif /* DEBUG */ - } - -#ifdef DEBUG - printf(")\n\n"); -#else - vme_out_string("\n\n"); -#endif /* DEBUG */ - /* 09/02/08 Nguyen changed to display the data Checksum */ - if (g_usChecksum != 0) { - g_usChecksum &= 0xFFFF; - sprintf(StrChecksum, "Data Checksum: %.4lX\n\n", - g_usChecksum); - vme_out_string(StrChecksum); - g_usChecksum = 0; - } - } - - if (usErrorCount > 0) { - if (g_usFlowControl & VERIFYUES) { - vme_out_string( - "USERCODE verification failed. " - "Continue programming......\n\n"); - g_usFlowControl &= ~(VERIFYUES); - return 0; - } else { - -#ifdef DEBUG - printf("TOTAL ERRORS: %d\n", usErrorCount); -#endif /* DEBUG */ - - return VME_VERIFICATION_FAILURE; - } - } else { - if (g_usFlowControl & VERIFYUES) { - vme_out_string("USERCODE verification passed. " - "Programming aborted.\n\n"); - g_usFlowControl &= ~(VERIFYUES); - return 1; - } else { - return 0; - } - } -} - -/* - * - * ispVMReadandSave - * - * Support dynamic I/O. - * - */ - -signed char ispVMReadandSave(unsigned short int a_usiDataSize) -{ - /* 09/11/07 NN added local variables initialization */ - unsigned short int usDataSizeIndex = 0; - unsigned short int usLastBitIndex = 0; - unsigned short int usBufferIndex = 0; - unsigned short int usOutBitIndex = 0; - unsigned short int usLVDSIndex = 0; - unsigned char cDataByte = 0; - unsigned char cDMASKByte = 0; - unsigned char cInDataByte = 0; - unsigned char cCurBit = 0; - unsigned char cByteIndex = 0; - signed char cLVDSByteIndex = 0; - - /* 09/11/07 NN Type cast mismatch variables */ - usLastBitIndex = (unsigned short) (a_usiDataSize - 1); - - /* - * - * Iterate through the data bits. - * - */ - - for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize; - usDataSizeIndex++) { - if (cByteIndex == 0) { - - /* - * Grab byte from DMASK buffer. - */ - - if (g_usDataType & DMASK_DATA) { - cDMASKByte = g_pucOutDMaskData[usBufferIndex]; - } else { - cDMASKByte = 0x00; - } - - /* - * Grab byte from TDI buffer. - */ - - if (g_usDataType & TDI_DATA) { - cInDataByte = g_pucInData[usBufferIndex]; - } - - usBufferIndex++; - } - - cCurBit = readPort(); - cDataByte = (unsigned char)(((cInDataByte << cByteIndex) & 0x80) - ? 0x01 : 0x00); - - /* - * Initialize the byte to be zero. - */ - - if (usOutBitIndex % 8 == 0) { - g_pucOutData[usOutBitIndex / 8] = 0x00; - } - - /* - * Use TDI, DMASK, and device TDO to create new TDI (actually - * stored in g_pucOutData). - */ - - if ((((cDMASKByte << cByteIndex) & 0x80) ? 0x01 : 0x00)) { - - if (g_pLVDSList) { - for (usLVDSIndex = 0; - usLVDSIndex < g_usLVDSPairCount; - usLVDSIndex++) { - if (g_pLVDSList[usLVDSIndex]. - usNegativeIndex == - usDataSizeIndex) { - g_pLVDSList[usLVDSIndex]. - ucUpdate = 0x01; - break; - } - } - } - - /* - * DMASK bit is 1, use TDI. - */ - - g_pucOutData[usOutBitIndex / 8] |= (unsigned char) - (((cDataByte & 0x1) ? 0x01 : 0x00) << - (7 - usOutBitIndex % 8)); - } else { - - /* - * DMASK bit is 0, use device TDO. - */ - - g_pucOutData[usOutBitIndex / 8] |= (unsigned char) - (((cCurBit & 0x1) ? 0x01 : 0x00) << - (7 - usOutBitIndex % 8)); - } - - /* - * Shift in TDI in order to get TDO out. - */ - - usOutBitIndex++; - writePort(g_ucPinTDI, cDataByte); - if (usDataSizeIndex < usLastBitIndex) { - sclock(); - } - - /* - * Increment the byte index. If it exceeds 7, then reset it back - * to zero. - */ - - cByteIndex++; - if (cByteIndex >= 8) { - cByteIndex = 0; - } - } - - /* - * If g_pLVDSList exists and pairs need updating, then update - * the negative-pair to receive the flipped positive-pair value. - */ - - if (g_pLVDSList) { - for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount; - usLVDSIndex++) { - if (g_pLVDSList[usLVDSIndex].ucUpdate) { - - /* - * Read the positive value and flip it. - */ - - cDataByte = (unsigned char) - (((g_pucOutData[g_pLVDSList[usLVDSIndex]. - usPositiveIndex / 8] - << (g_pLVDSList[usLVDSIndex]. - usPositiveIndex % 8)) & 0x80) ? - 0x01 : 0x00); - /* 09/11/07 NN Type cast mismatch variables */ - cDataByte = (unsigned char) (!cDataByte); - - /* - * Get the byte that needs modification. - */ - - cInDataByte = - g_pucOutData[g_pLVDSList[usLVDSIndex]. - usNegativeIndex / 8]; - - if (cDataByte) { - - /* - * Copy over the current byte and - * set the negative bit to 1. - */ - - cDataByte = 0x00; - for (cLVDSByteIndex = 7; - cLVDSByteIndex >= 0; - cLVDSByteIndex--) { - cDataByte <<= 1; - if (7 - - (g_pLVDSList[usLVDSIndex]. - usNegativeIndex % 8) == - cLVDSByteIndex) { - - /* - * Set negative bit to 1 - */ - - cDataByte |= 0x01; - } else if (cInDataByte & 0x80) { - cDataByte |= 0x01; - } - - cInDataByte <<= 1; - } - - /* - * Store the modified byte. - */ - - g_pucOutData[g_pLVDSList[usLVDSIndex]. - usNegativeIndex / 8] = cDataByte; - } else { - - /* - * Copy over the current byte and set - * the negative bit to 0. - */ - - cDataByte = 0x00; - for (cLVDSByteIndex = 7; - cLVDSByteIndex >= 0; - cLVDSByteIndex--) { - cDataByte <<= 1; - if (7 - - (g_pLVDSList[usLVDSIndex]. - usNegativeIndex % 8) == - cLVDSByteIndex) { - - /* - * Set negative bit to 0 - */ - - cDataByte |= 0x00; - } else if (cInDataByte & 0x80) { - cDataByte |= 0x01; - } - - cInDataByte <<= 1; - } - - /* - * Store the modified byte. - */ - - g_pucOutData[g_pLVDSList[usLVDSIndex]. - usNegativeIndex / 8] = cDataByte; - } - - break; - } - } - } - - return 0; -} - -signed char ispVMProcessLVDS(unsigned short a_usLVDSCount) -{ - unsigned short usLVDSIndex = 0; - - /* - * Allocate memory to hold LVDS pairs. - */ - - ispVMMemManager(LVDS, a_usLVDSCount); - g_usLVDSPairCount = a_usLVDSCount; - -#ifdef DEBUG - printf("LVDS %d (", a_usLVDSCount); -#endif /* DEBUG */ - - /* - * Iterate through each given LVDS pair. - */ - - for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount; usLVDSIndex++) { - - /* - * Assign the positive and negative indices of the LVDS pair. - */ - - /* 09/11/07 NN Type cast mismatch variables */ - g_pLVDSList[usLVDSIndex].usPositiveIndex = - (unsigned short) ispVMDataSize(); - /* 09/11/07 NN Type cast mismatch variables */ - g_pLVDSList[usLVDSIndex].usNegativeIndex = - (unsigned short)ispVMDataSize(); - -#ifdef DEBUG - if (usLVDSIndex < g_usLVDSPairCount - 1) { - printf("%d:%d, ", - g_pLVDSList[usLVDSIndex].usPositiveIndex, - g_pLVDSList[usLVDSIndex].usNegativeIndex); - } else { - printf("%d:%d", - g_pLVDSList[usLVDSIndex].usPositiveIndex, - g_pLVDSList[usLVDSIndex].usNegativeIndex); - } -#endif /* DEBUG */ - - } - -#ifdef DEBUG - printf(");\n"); -#endif /* DEBUG */ - - return 0; -} diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c deleted file mode 100644 index 29cf2f60974..00000000000 --- a/drivers/fpga/lattice.c +++ /dev/null @@ -1,379 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * - * ispVM functions adapted from Lattice's ispmVMEmbedded code: - * Copyright 2009 Lattice Semiconductor Corp. - */ - -#include <log.h> -#include <malloc.h> -#include <fpga.h> -#include <lattice.h> -#include <linux/delay.h> - -static lattice_board_specific_func *pfns; -static const char *fpga_image; -static unsigned long read_bytes; -static unsigned long bufsize; -static unsigned short expectedCRC; - -/* - * External variables and functions declared in ivm_core.c module. - */ -extern unsigned short g_usCalculatedCRC; -extern unsigned short g_usDataType; -extern unsigned char *g_pucIntelBuffer; -extern unsigned char *g_pucHeapMemory; -extern unsigned short g_iHeapCounter; -extern unsigned short g_iHEAPSize; -extern unsigned short g_usIntelDataIndex; -extern unsigned short g_usIntelBufferSize; -extern char *const g_szSupportedVersions[]; - -/* - * ispVMDelay - * - * Users must implement a delay to observe a_usTimeDelay, where - * bit 15 of the a_usTimeDelay defines the unit. - * 1 = milliseconds - * 0 = microseconds - * Example: - * a_usTimeDelay = 0x0001 = 1 microsecond delay. - * a_usTimeDelay = 0x8001 = 1 millisecond delay. - * - * This subroutine is called upon to provide a delay from 1 millisecond to a few - * hundreds milliseconds each time. - * It is understood that due to a_usTimeDelay is defined as unsigned short, a 16 - * bits integer, this function is restricted to produce a delay to 64000 - * micro-seconds or 32000 milli-second maximum. The VME file will never pass on - * to this function a delay time > those maximum number. If it needs more than - * those maximum, the VME file will launch the delay function several times to - * realize a larger delay time cummulatively. - * It is perfectly alright to provide a longer delay than required. It is not - * acceptable if the delay is shorter. - */ -void ispVMDelay(unsigned short delay) -{ - if (delay & 0x8000) - delay = (delay & ~0x8000) * 1000; - udelay(delay); -} - -void writePort(unsigned char a_ucPins, unsigned char a_ucValue) -{ - a_ucValue = a_ucValue ? 1 : 0; - - switch (a_ucPins) { - case g_ucPinTDI: - pfns->jtag_set_tdi(a_ucValue); - break; - case g_ucPinTCK: - pfns->jtag_set_tck(a_ucValue); - break; - case g_ucPinTMS: - pfns->jtag_set_tms(a_ucValue); - break; - default: - printf("%s: requested unknown pin\n", __func__); - } -} - -unsigned char readPort(void) -{ - return pfns->jtag_get_tdo(); -} - -void sclock(void) -{ - writePort(g_ucPinTCK, 0x01); - writePort(g_ucPinTCK, 0x00); -} - -void calibration(void) -{ - /* Apply 2 pulses to TCK. */ - writePort(g_ucPinTCK, 0x00); - writePort(g_ucPinTCK, 0x01); - writePort(g_ucPinTCK, 0x00); - writePort(g_ucPinTCK, 0x01); - writePort(g_ucPinTCK, 0x00); - - ispVMDelay(0x8001); - - /* Apply 2 pulses to TCK. */ - writePort(g_ucPinTCK, 0x01); - writePort(g_ucPinTCK, 0x00); - writePort(g_ucPinTCK, 0x01); - writePort(g_ucPinTCK, 0x00); -} - -/* - * GetByte - * - * Returns a byte to the caller. The returned byte depends on the - * g_usDataType register. If the HEAP_IN bit is set, then the byte - * is returned from the HEAP. If the LHEAP_IN bit is set, then - * the byte is returned from the intelligent buffer. Otherwise, - * the byte is returned directly from the VME file. - */ -unsigned char GetByte(void) -{ - unsigned char ucData; - unsigned int block_size = 4 * 1024; - - if (g_usDataType & HEAP_IN) { - - /* - * Get data from repeat buffer. - */ - - if (g_iHeapCounter > g_iHEAPSize) { - - /* - * Data over-run. - */ - - return 0xFF; - } - - ucData = g_pucHeapMemory[g_iHeapCounter++]; - } else if (g_usDataType & LHEAP_IN) { - - /* - * Get data from intel buffer. - */ - - if (g_usIntelDataIndex >= g_usIntelBufferSize) { - return 0xFF; - } - - ucData = g_pucIntelBuffer[g_usIntelDataIndex++]; - } else { - if (read_bytes == bufsize) { - return 0xFF; - } - ucData = *fpga_image++; - read_bytes++; - - if (!(read_bytes % block_size)) { - printf("Downloading FPGA %ld/%ld completed\r", - read_bytes, - bufsize); - } - - if (expectedCRC != 0) { - ispVMCalculateCRC32(ucData); - } - } - - return ucData; -} - -signed char ispVM(void) -{ - char szFileVersion[9] = { 0 }; - signed char cRetCode = 0; - signed char cIndex = 0; - signed char cVersionIndex = 0; - unsigned char ucReadByte = 0; - unsigned short crc; - - g_pucHeapMemory = NULL; - g_iHeapCounter = 0; - g_iHEAPSize = 0; - g_usIntelDataIndex = 0; - g_usIntelBufferSize = 0; - g_usCalculatedCRC = 0; - expectedCRC = 0; - ucReadByte = GetByte(); - switch (ucReadByte) { - case FILE_CRC: - crc = (unsigned char)GetByte(); - crc <<= 8; - crc |= GetByte(); - expectedCRC = crc; - - for (cIndex = 0; cIndex < 8; cIndex++) - szFileVersion[cIndex] = GetByte(); - - break; - default: - szFileVersion[0] = (signed char) ucReadByte; - for (cIndex = 1; cIndex < 8; cIndex++) - szFileVersion[cIndex] = GetByte(); - - break; - } - - /* - * - * Compare the VME file version against the supported version. - * - */ - - for (cVersionIndex = 0; g_szSupportedVersions[cVersionIndex] != 0; - cVersionIndex++) { - for (cIndex = 0; cIndex < 8; cIndex++) { - if (szFileVersion[cIndex] != - g_szSupportedVersions[cVersionIndex][cIndex]) { - cRetCode = VME_VERSION_FAILURE; - break; - } - cRetCode = 0; - } - - if (cRetCode == 0) { - break; - } - } - - if (cRetCode < 0) { - return VME_VERSION_FAILURE; - } - - printf("VME file checked: starting downloading to FPGA\n"); - - ispVMStart(); - - cRetCode = ispVMCode(); - - ispVMEnd(); - ispVMFreeMem(); - puts("\n"); - - if (cRetCode == 0 && expectedCRC != 0 && - (expectedCRC != g_usCalculatedCRC)) { - printf("Expected CRC: 0x%.4X\n", expectedCRC); - printf("Calculated CRC: 0x%.4X\n", g_usCalculatedCRC); - return VME_CRC_FAILURE; - } - return cRetCode; -} - -static int lattice_validate(Lattice_desc *desc, const char *fn) -{ - int ret_val = false; - - if (desc) { - if ((desc->family > min_lattice_type) && - (desc->family < max_lattice_type)) { - if ((desc->iface > min_lattice_iface_type) && - (desc->iface < max_lattice_iface_type)) { - if (desc->size) { - ret_val = true; - } else { - printf("%s: NULL part size\n", fn); - } - } else { - printf("%s: Invalid Interface type, %d\n", - fn, desc->iface); - } - } else { - printf("%s: Invalid family type, %d\n", - fn, desc->family); - } - } else { - printf("%s: NULL descriptor!\n", fn); - } - - return ret_val; -} - -int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - if (!lattice_validate(desc, (char *)__func__)) { - printf("%s: Invalid device descriptor\n", __func__); - } else { - pfns = desc->iface_fns; - - switch (desc->family) { - case Lattice_XP2: - fpga_image = buf; - read_bytes = 0; - bufsize = bsize; - debug("%s: Launching the Lattice ISPVME Loader:" - " addr %p size 0x%lx...\n", - __func__, fpga_image, bufsize); - ret_val = ispVM(); - if (ret_val) - printf("%s: error %d downloading FPGA image\n", - __func__, ret_val); - else - puts("FPGA downloaded successfully\n"); - break; - default: - printf("%s: Unsupported family type, %d\n", - __func__, desc->family); - } - } - - return ret_val; -} - -int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize) -{ - puts("Dump not supported for Lattice FPGA\n"); - - return FPGA_FAIL; - -} - -int lattice_info(Lattice_desc *desc) -{ - int ret_val = FPGA_FAIL; - - if (lattice_validate(desc, (char *)__func__)) { - printf("Family: \t"); - switch (desc->family) { - case Lattice_XP2: - puts("XP2\n"); - break; - /* Add new family types here */ - default: - printf("Unknown family type, %d\n", desc->family); - } - - puts("Interface type:\t"); - switch (desc->iface) { - case lattice_jtag_mode: - puts("JTAG Mode\n"); - break; - /* Add new interface types here */ - default: - printf("Unsupported interface type, %d\n", desc->iface); - } - - printf("Device Size: \t%zu bytes\n", - desc->size); - - if (desc->iface_fns) { - printf("Device Function Table @ 0x%p\n", - desc->iface_fns); - switch (desc->family) { - case Lattice_XP2: - break; - /* Add new family types here */ - default: - break; - } - } else { - puts("No Device Function Table.\n"); - } - - if (desc->desc) - printf("Model: \t%s\n", desc->desc); - - ret_val = FPGA_SUCCESS; - } else { - printf("%s: Invalid device descriptor\n", __func__); - } - - return ret_val; -} diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 28c68faba55..25b348648ef 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -50,6 +50,9 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ desc = fpga_validate(devnum, dataptr, 0); + if (!desc) + return FPGA_FAIL; + /* Assign xilinx device description */ xdesc = desc->devdesc; diff --git a/drivers/i2c/rcar_iic.c b/drivers/i2c/rcar_iic.c index e019d06be41..42d575e29ba 100644 --- a/drivers/i2c/rcar_iic.c +++ b/drivers/i2c/rcar_iic.c @@ -191,7 +191,7 @@ static int rcar_iic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) return -EREMOTEIO; } - return ret; + return 0; } static int rcar_iic_set_speed(struct udevice *dev, uint speed) diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig new file mode 100644 index 00000000000..d877a744353 --- /dev/null +++ b/drivers/i3c/Kconfig @@ -0,0 +1,27 @@ +menuconfig I3C + tristate "I3C support" + select I2C + help + I3C is a serial protocol standardized by the MIPI alliance. + + It's supposed to be backward compatible with I2C while providing + support for high speed transfers and native interrupt support + without the need for extra pins. + + The I3C protocol also standardizes the slave device types and is + mainly designed to communicate with sensors. + + If you want I3C support, you should say Y here and also to the + specific driver for your bus adapter(s) below. + +config I3C_SANDBOX + bool "Enable support for the sandbox I3C" + help + This is a sandbox I3C used for testing. It provides 2 interfaces and + records the settings passed into it. + +if I3C + +source "drivers/i3c/master/Kconfig" + +endif # I3C diff --git a/drivers/i3c/Makefile b/drivers/i3c/Makefile new file mode 100644 index 00000000000..d38d2350c9a --- /dev/null +++ b/drivers/i3c/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y := i3c-uclass.o device.o master.o +obj-y += master/ +obj-$(CONFIG_I3C_SANDBOX) += sandbox_i3c.o diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c new file mode 100644 index 00000000000..32c57bccc42 --- /dev/null +++ b/drivers/i3c/device.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Cadence Design Systems Inc. + * + * Author: Boris Brezillon <boris.brezillon@bootlin.com> + */ + +#include <linux/bug.h> +#include <linux/completion.h> +#include <dm/device.h> + +#include "internals.h" + +/* i3c */ + +#define I3C_MATCH_DCR 0x1 +#define I3C_MATCH_MANUF 0x2 +#define I3C_MATCH_PART 0x4 +#define I3C_MATCH_EXTRA_INFO 0x8 + +struct i3c_device_id { + __u8 match_flags; + __u8 dcr; + __u16 manuf_id; + __u16 part_id; + __u16 extra_info; + + const void *data; +}; + +/** + * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a + * specific device + * + * @dev: device with which the transfers should be done + * @xfers: array of transfers + * @nxfers: number of transfers + * + * Initiate one or several private SDR transfers with @dev. + * + * This function can sleep and thus cannot be called in atomic context. + * + * Return: 0 in case of success, a negative error core otherwise. + */ +int i3c_device_do_priv_xfers(struct i3c_device *dev, + struct i3c_priv_xfer *xfers, + int nxfers) +{ + int ret, i; + + if (nxfers < 1) + return 0; + + for (i = 0; i < nxfers; i++) { + if (!xfers[i].len || !xfers[i].data.in) + return -EINVAL; + } + + i3c_bus_normaluse_lock(dev->bus); + ret = i3c_dev_do_priv_xfers_locked(dev->desc, xfers, nxfers); + i3c_bus_normaluse_unlock(dev->bus); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers); + +/** + * i3c_device_get_info() - get I3C device information + * + * @dev: device we want information on + * @info: the information object to fill in + * + * Retrieve I3C dev info. + */ +void i3c_device_get_info(struct i3c_device *dev, + struct i3c_device_info *info) +{ + if (!info) + return; + + i3c_bus_normaluse_lock(dev->bus); + if (dev->desc) + *info = dev->desc->info; + i3c_bus_normaluse_unlock(dev->bus); +} +EXPORT_SYMBOL_GPL(i3c_device_get_info); + +/** + * i3c_device_disable_ibi() - Disable IBIs coming from a specific device + * @dev: device on which IBIs should be disabled + * + * This function disable IBIs coming from a specific device and wait for + * all pending IBIs to be processed. + * + * Return: 0 in case of success, a negative error core otherwise. + */ +int i3c_device_disable_ibi(struct i3c_device *dev) +{ + int ret = -ENOENT; + + i3c_bus_normaluse_lock(dev->bus); + if (dev->desc) { + mutex_lock(&dev->desc->ibi_lock); + ret = i3c_dev_disable_ibi_locked(dev->desc); + mutex_unlock(&dev->desc->ibi_lock); + } + i3c_bus_normaluse_unlock(dev->bus); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_device_disable_ibi); + +/** + * i3c_device_enable_ibi() - Enable IBIs coming from a specific device + * @dev: device on which IBIs should be enabled + * + * This function enable IBIs coming from a specific device and wait for + * all pending IBIs to be processed. This should be called on a device + * where i3c_device_request_ibi() has succeeded. + * + * Note that IBIs from this device might be received before this function + * returns to its caller. + * + * Return: 0 in case of success, a negative error core otherwise. + */ +int i3c_device_enable_ibi(struct i3c_device *dev) +{ + int ret = -ENOENT; + + i3c_bus_normaluse_lock(dev->bus); + if (dev->desc) { + mutex_lock(&dev->desc->ibi_lock); + ret = i3c_dev_enable_ibi_locked(dev->desc); + mutex_unlock(&dev->desc->ibi_lock); + } + i3c_bus_normaluse_unlock(dev->bus); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_device_enable_ibi); + +/** + * i3c_device_request_ibi() - Request an IBI + * @dev: device for which we should enable IBIs + * @req: setup requested for this IBI + * + * This function is responsible for pre-allocating all resources needed to + * process IBIs coming from @dev. When this function returns, the IBI is not + * enabled until i3c_device_enable_ibi() is called. + * + * Return: 0 in case of success, a negative error core otherwise. + */ +int i3c_device_request_ibi(struct i3c_device *dev, + const struct i3c_ibi_setup *req) +{ + int ret = -ENOENT; + + if (!req->handler || !req->num_slots) + return -EINVAL; + + i3c_bus_normaluse_lock(dev->bus); + if (dev->desc) { + mutex_lock(&dev->desc->ibi_lock); + ret = i3c_dev_request_ibi_locked(dev->desc, req); + mutex_unlock(&dev->desc->ibi_lock); + } + i3c_bus_normaluse_unlock(dev->bus); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_device_request_ibi); + +/** + * i3c_device_free_ibi() - Free all resources needed for IBI handling + * @dev: device on which you want to release IBI resources + * + * This function is responsible for de-allocating resources previously + * allocated by i3c_device_request_ibi(). It should be called after disabling + * IBIs with i3c_device_disable_ibi(). + */ +void i3c_device_free_ibi(struct i3c_device *dev) +{ + i3c_bus_normaluse_lock(dev->bus); + if (dev->desc) { + mutex_lock(&dev->desc->ibi_lock); + i3c_dev_free_ibi_locked(dev->desc); + mutex_unlock(&dev->desc->ibi_lock); + } + i3c_bus_normaluse_unlock(dev->bus); +} +EXPORT_SYMBOL_GPL(i3c_device_free_ibi); + +/** + * i3cdev_to_dev() - Returns the device embedded in @i3cdev + * @i3cdev: I3C device + * + * Return: a pointer to a device object. + */ +struct udevice *i3cdev_to_dev(struct i3c_device *i3cdev) +{ + return &i3cdev->dev; +} +EXPORT_SYMBOL_GPL(i3cdev_to_dev); + +/** + * dev_to_i3cdev() - Returns the I3C device containing @dev + * @dev: device object + * + * Return: a pointer to an I3C device object. + */ +struct i3c_device *dev_to_i3cdev(struct udevice *dev) +{ + return container_of(dev, struct i3c_device, dev); +} +EXPORT_SYMBOL_GPL(dev_to_i3cdev); + +/** + * i3c_device_match_id() - Returns the i3c_device_id entry matching @i3cdev + * @i3cdev: I3C device + * @id_table: I3C device match table + * + * Return: a pointer to an i3c_device_id object or NULL if there's no match. + */ +const struct i3c_device_id * +i3c_device_match_id(struct i3c_device *i3cdev, + const struct i3c_device_id *id_table) +{ + struct i3c_device_info devinfo; + const struct i3c_device_id *id; + u16 manuf, part, ext_info; + bool rndpid; + + i3c_device_get_info(i3cdev, &devinfo); + + manuf = I3C_PID_MANUF_ID(devinfo.pid); + part = I3C_PID_PART_ID(devinfo.pid); + ext_info = I3C_PID_EXTRA_INFO(devinfo.pid); + rndpid = I3C_PID_RND_LOWER_32BITS(devinfo.pid); + + for (id = id_table; id->match_flags != 0; id++) { + if ((id->match_flags & I3C_MATCH_DCR) && + id->dcr != devinfo.dcr) + continue; + + if ((id->match_flags & I3C_MATCH_MANUF) && + id->manuf_id != manuf) + continue; + + if ((id->match_flags & I3C_MATCH_PART) && + (rndpid || id->part_id != part)) + continue; + + if ((id->match_flags & I3C_MATCH_EXTRA_INFO) && + (rndpid || id->extra_info != ext_info)) + continue; + + return id; + } + + return NULL; +} +EXPORT_SYMBOL_GPL(i3c_device_match_id); diff --git a/drivers/i3c/i3c-uclass.c b/drivers/i3c/i3c-uclass.c new file mode 100644 index 00000000000..72944424c1d --- /dev/null +++ b/drivers/i3c/i3c-uclass.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <dm.h> +#include <i3c.h> +#include <errno.h> +#include <log.h> +#include <dm/device-internal.h> +#include <linux/ctype.h> + +int dm_i3c_read(struct udevice *dev, u32 dev_number, + u8 *buf, u32 num_bytes) +{ + struct dm_i3c_ops *ops = i3c_get_ops(dev); + + if (!ops->read) + return -ENOSYS; + + return ops->read(dev, dev_number, buf, num_bytes); +} + +int dm_i3c_write(struct udevice *dev, u32 dev_number, + u8 *buf, u32 num_bytes) +{ + struct dm_i3c_ops *ops = i3c_get_ops(dev); + + if (!ops->write) + return -ENOSYS; + + return ops->write(dev, dev_number, buf, num_bytes); +} + +UCLASS_DRIVER(i3c) = { + .id = UCLASS_I3C, + .name = "i3c", +}; diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h new file mode 100644 index 00000000000..86b7b44cfca --- /dev/null +++ b/drivers/i3c/internals.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Cadence Design Systems Inc. + * + * Author: Boris Brezillon <boris.brezillon@bootlin.com> + */ + +#ifndef I3C_INTERNALS_H +#define I3C_INTERNALS_H + +#include <linux/i3c/master.h> + +extern struct bus_type i3c_bus_type; + +void i3c_bus_normaluse_lock(struct i3c_bus *bus); +void i3c_bus_normaluse_unlock(struct i3c_bus *bus); + +int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev, + struct i3c_priv_xfer *xfers, + int nxfers); +int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev); +int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev); +int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev, + const struct i3c_ibi_setup *req); +void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev); +#endif /* I3C_INTERNAL_H */ diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c new file mode 100644 index 00000000000..019167a2dc5 --- /dev/null +++ b/drivers/i3c/master.c @@ -0,0 +1,2066 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Cadence Design Systems Inc. + * + * Author: Boris Brezillon <boris.brezillon@bootlin.com> + */ + +#include <dm.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/of.h> +#include <dm/of_access.h> +#include <linux/bitmap.h> +#include <linux/bug.h> +#include <linux/compat.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/list.h> + +#include "internals.h" + +#define MAX_IDR_ID 64 + +struct idr_layer { + int used; + void *ptr; +}; + +struct idr { + struct idr_layer id[MAX_IDR_ID]; + bool updated; +}; + +static int idr_alloc(struct idr *idp, void *ptr, int start, int end, gfp_t gfp_mask) +{ + struct idr_layer *idl; + int i = 0; + + while (i < MAX_IDR_ID) { + idl = &idp->id[i]; + if (idl->used == 0) { + idl->used = 1; + idl->ptr = ptr; + idp->updated = true; + return i; + } + i++; + } + return -ENOSPC; +} + +/** + * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation + * @bus: I3C bus to take the lock on + * + * This function takes the bus lock so that no other operations can occur on + * the bus. This is needed for all kind of bus maintenance operation, like + * - enabling/disabling slave events + * - re-triggering DAA + * - changing the dynamic address of a device + * - relinquishing mastership + * - ... + * + * The reason for this kind of locking is that we don't want drivers and core + * logic to rely on I3C device information that could be changed behind their + * back. + */ +static void i3c_bus_maintenance_lock(struct i3c_bus *bus) +{ + down_write(&bus->lock); +} + +/** + * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance + * operation + * @bus: I3C bus to release the lock on + * + * Should be called when the bus maintenance operation is done. See + * i3c_bus_maintenance_lock() for more details on what these maintenance + * operations are. + */ +static void i3c_bus_maintenance_unlock(struct i3c_bus *bus) +{ + up_write(&bus->lock); +} + +/** + * i3c_bus_normaluse_lock - Lock the bus for a normal operation + * @bus: I3C bus to take the lock on + * + * This function takes the bus lock for any operation that is not a maintenance + * operation (see i3c_bus_maintenance_lock() for a non-exhaustive list of + * maintenance operations). Basically all communications with I3C devices are + * normal operations (HDR, SDR transfers or CCC commands that do not change bus + * state or I3C dynamic address). + * + * Note that this lock is not guaranteeing serialization of normal operations. + * In other words, transfer requests passed to the I3C master can be submitted + * in parallel and I3C master drivers have to use their own locking to make + * sure two different communications are not inter-mixed, or access to the + * output/input queue is not done while the engine is busy. + */ +void i3c_bus_normaluse_lock(struct i3c_bus *bus) +{ + down_read(&bus->lock); +} + +/** + * i3c_bus_normaluse_unlock - Release the bus lock after a normal operation + * @bus: I3C bus to release the lock on + * + * Should be called when a normal operation is done. See + * i3c_bus_normaluse_lock() for more details on what these normal operations + * are. + */ +void i3c_bus_normaluse_unlock(struct i3c_bus *bus) +{ + up_read(&bus->lock); +} + +static struct i3c_master_controller * +i3c_bus_to_i3c_master(struct i3c_bus *i3cbus) +{ + return container_of(i3cbus, struct i3c_master_controller, bus); +} + +static int i3c_device_match(struct udevice *dev, struct driver *drv) +{ + struct i3c_device *i3cdev; + struct i3c_driver *i3cdrv; + + i3cdev = dev_to_i3cdev(dev); + i3cdrv = drv_to_i3cdrv(drv); + if (i3c_device_match_id(i3cdev, i3cdrv->id_table)) + return 1; + + return 0; +} + +static int i3c_device_probe(struct udevice *dev) +{ + struct i3c_device *i3cdev = dev_to_i3cdev(dev); + struct i3c_driver *driver = drv_to_i3cdrv(dev->driver); + + return driver->probe(i3cdev); +} + +static void i3c_device_remove(struct udevice *dev) +{ + struct i3c_device *i3cdev = dev_to_i3cdev(dev); + struct i3c_driver *driver = drv_to_i3cdrv(dev->driver); + + if (driver->remove) + driver->remove(i3cdev); +} + +struct bus_type { + const char *name; + int (*match)(struct udevice *dev, struct driver *drv); + int (*probe)(struct udevice *dev); + void (*remove)(struct udevice *dev); +}; + +struct bus_type i3c_bus_type = { + .name = "i3c", + .match = i3c_device_match, + .probe = i3c_device_probe, + .remove = i3c_device_remove, +}; + +static enum i3c_addr_slot_status +i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr) +{ + int status, bitpos = addr * 2; + + if (addr > I2C_MAX_ADDR) + return I3C_ADDR_SLOT_RSVD; + + status = bus->addrslots[bitpos / BITS_PER_LONG]; + status >>= bitpos % BITS_PER_LONG; + + return status & I3C_ADDR_SLOT_STATUS_MASK; +} + +static void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr, + enum i3c_addr_slot_status status) +{ + int bitpos = addr * 2; + unsigned long *ptr; + + if (addr > I2C_MAX_ADDR) + return; + + ptr = bus->addrslots + (bitpos / BITS_PER_LONG); + *ptr &= ~((unsigned long)I3C_ADDR_SLOT_STATUS_MASK << + (bitpos % BITS_PER_LONG)); + *ptr |= (unsigned long)status << (bitpos % BITS_PER_LONG); +} + +static bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr) +{ + enum i3c_addr_slot_status status; + + status = i3c_bus_get_addr_slot_status(bus, addr); + + return status == I3C_ADDR_SLOT_FREE; +} + +static int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr) +{ + enum i3c_addr_slot_status status; + u8 addr; + + for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) { + status = i3c_bus_get_addr_slot_status(bus, addr); + if (status == I3C_ADDR_SLOT_FREE) + return addr; + } + + return -ENOMEM; +} + +static void i3c_bus_init_addrslots(struct i3c_bus *bus) +{ + int i; + + /* Addresses 0 to 7 are reserved. */ + for (i = 0; i < 8; i++) + i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD); + + /* + * Reserve broadcast address and all addresses that might collide + * with the broadcast address when facing a single bit error. + */ + i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR, + I3C_ADDR_SLOT_RSVD); + for (i = 0; i < 7; i++) + i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i), + I3C_ADDR_SLOT_RSVD); +} + +static int i3c_bus_init(struct i3c_bus *i3cbus) +{ + int ret; + struct idr i3c_bus_idr = {}; + + init_rwsem(&i3cbus->lock); + INIT_LIST_HEAD(&i3cbus->devs.i2c); + INIT_LIST_HEAD(&i3cbus->devs.i3c); + i3c_bus_init_addrslots(i3cbus); + i3cbus->mode = I3C_BUS_MODE_PURE; + + mutex_lock(&i3c_core_lock); + ret = idr_alloc(&i3c_bus_idr, i3cbus, 0, 0, GFP_KERNEL); + mutex_unlock(&i3c_core_lock); + + if (ret < 0) + return ret; + + i3cbus->id = ret; + + return 0; +} + +static int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode, + unsigned long max_i2c_scl_rate) +{ + struct i3c_master_controller *master = i3c_bus_to_i3c_master(i3cbus); + + i3cbus->mode = mode; + + switch (i3cbus->mode) { + case I3C_BUS_MODE_PURE: + if (!i3cbus->scl_rate.i3c) + i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE; + break; + case I3C_BUS_MODE_MIXED_FAST: + case I3C_BUS_MODE_MIXED_LIMITED: + if (!i3cbus->scl_rate.i3c) + i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE; + if (!i3cbus->scl_rate.i2c) + i3cbus->scl_rate.i2c = max_i2c_scl_rate; + break; + case I3C_BUS_MODE_MIXED_SLOW: + if (!i3cbus->scl_rate.i2c) + i3cbus->scl_rate.i2c = max_i2c_scl_rate; + if (!i3cbus->scl_rate.i3c || + i3cbus->scl_rate.i3c > i3cbus->scl_rate.i2c) + i3cbus->scl_rate.i3c = i3cbus->scl_rate.i2c; + break; + default: + return -EINVAL; + } + + dev_dbg(master->dev, "i2c-scl = %ld Hz i3c-scl = %ld Hz\n", + i3cbus->scl_rate.i2c, i3cbus->scl_rate.i3c); + + /* + * I3C/I2C frequency may have been overridden, check that user-provided + * values are not exceeding max possible frequency. + */ + if (i3cbus->scl_rate.i3c > I3C_BUS_MAX_I3C_SCL_RATE || + i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_RATE) + return -EINVAL; + + return 0; +} + +static void i3c_master_free_i2c_dev(struct i2c_dev_desc *dev) +{ + kfree(dev); +} + +static struct i2c_dev_desc * +i3c_master_alloc_i2c_dev(struct i3c_master_controller *master, + const struct i2c_dev_boardinfo *boardinfo) +{ + struct i2c_dev_desc *dev; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return ERR_PTR(-ENOMEM); + + dev->common.master = master; + dev->boardinfo = boardinfo; + dev->addr = boardinfo->base.addr; + dev->lvr = boardinfo->lvr; + + return dev; +} + +static void *i3c_ccc_cmd_dest_init(struct i3c_ccc_cmd_dest *dest, u8 addr, + u16 payloadlen) +{ + dest->addr = addr; + dest->payload.len = payloadlen; + if (payloadlen) + dest->payload.data = kzalloc(payloadlen, GFP_KERNEL); + else + dest->payload.data = NULL; + + return dest->payload.data; +} + +static void i3c_ccc_cmd_dest_cleanup(struct i3c_ccc_cmd_dest *dest) +{ + kfree(dest->payload.data); +} + +static void i3c_ccc_cmd_init(struct i3c_ccc_cmd *cmd, bool rnw, u8 id, + struct i3c_ccc_cmd_dest *dests, + unsigned int ndests) +{ + cmd->rnw = rnw ? 1 : 0; + cmd->id = id; + cmd->dests = dests; + cmd->ndests = ndests; + cmd->err = I3C_ERROR_UNKNOWN; +} + +static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master, + struct i3c_ccc_cmd *cmd) +{ + int ret; + + if (!cmd || !master) + return -EINVAL; + + if (WARN_ON(master->init_done)) + return -EINVAL; + + if (!master->ops->send_ccc_cmd) + return -EOPNOTSUPP; + + if ((cmd->id & I3C_CCC_DIRECT) && (!cmd->dests || !cmd->ndests)) + return -EINVAL; + + if (master->ops->supports_ccc_cmd && + !master->ops->supports_ccc_cmd(master, cmd)) + return -EOPNOTSUPP; + + ret = master->ops->send_ccc_cmd(master, cmd); + if (ret) { + if (cmd->err != I3C_ERROR_UNKNOWN) + return cmd->err; + + return ret; + } + + return 0; +} + +/** + * i3c_master_get_free_addr() - get a free address on the bus + * @master: I3C master object + * @start_addr: where to start searching + * + * This function must be called with the bus lock held in write mode. + * + * Return: the first free address starting at @start_addr (included) or -ENOMEM + * if there's no more address available. + */ +int i3c_master_get_free_addr(struct i3c_master_controller *master, + u8 start_addr) +{ + return i3c_bus_get_free_addr(&master->bus, start_addr); +} +EXPORT_SYMBOL_GPL(i3c_master_get_free_addr); + +static void i3c_master_free_i3c_dev(struct i3c_dev_desc *dev) +{ + kfree(dev); +} + +static struct i3c_dev_desc * +i3c_master_alloc_i3c_dev(struct i3c_master_controller *master, + const struct i3c_device_info *info) +{ + struct i3c_dev_desc *dev; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) + return ERR_PTR(-ENOMEM); + + dev->common.master = master; + dev->info = *info; + + return dev; +} + +static int i3c_master_rstdaa_locked(struct i3c_master_controller *master, + u8 addr) +{ + enum i3c_addr_slot_status addrstat; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + if (!master) + return -EINVAL; + + addrstat = i3c_bus_get_addr_slot_status(&master->bus, addr); + if (addr != I3C_BROADCAST_ADDR && addrstat != I3C_ADDR_SLOT_I3C_DEV) + return -EINVAL; + + i3c_ccc_cmd_dest_init(&dest, addr, 0); + i3c_ccc_cmd_init(&cmd, false, + I3C_CCC_RSTDAA(addr == I3C_BROADCAST_ADDR), + &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + + i3c_ccc_cmd_dest_cleanup(&dest); + + if (ret) + ret = cmd.err; + + return ret; +} + +/** + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment) + * procedure + * @master: master used to send frames on the bus + * + * Send a ENTDAA CCC command to start a DAA procedure. + * + * Note that this function only sends the ENTDAA CCC command, all the logic + * behind dynamic address assignment has to be handled in the I3C master + * driver. + * + * This function must be called with the bus lock held in write mode. + * + * Return: 0 in case of success, a positive I3C error code if the error is + * one of the official Mx error codes, and a negative error code otherwise. + */ +int i3c_master_entdaa_locked(struct i3c_master_controller *master) +{ + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); + i3c_ccc_cmd_init(&cmd, false, I3C_CCC_ENTDAA, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked); + +static int i3c_master_enec_disec_locked(struct i3c_master_controller *master, + u8 addr, bool enable, u8 evts) +{ + struct i3c_ccc_events *events; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + events = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*events)); + if (!events) + return -ENOMEM; + + events->events = evts; + i3c_ccc_cmd_init(&cmd, false, + enable ? + I3C_CCC_ENEC(addr == I3C_BROADCAST_ADDR) : + I3C_CCC_DISEC(addr == I3C_BROADCAST_ADDR), + &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + + if (ret) + ret = cmd.err; + + return ret; +} + +/** + * i3c_master_disec_locked() - send a DISEC CCC command + * @master: master used to send frames on the bus + * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR + * @evts: events to disable + * + * Send a DISEC CCC command to disable some or all events coming from a + * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR. + * + * This function must be called with the bus lock held in write mode. + * + * Return: 0 in case of success, a positive I3C error code if the error is + * one of the official Mx error codes, and a negative error code otherwise. + */ +int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr, + u8 evts) +{ + return i3c_master_enec_disec_locked(master, addr, false, evts); +} +EXPORT_SYMBOL_GPL(i3c_master_disec_locked); + +/** + * i3c_master_enec_locked() - send an ENEC CCC command + * @master: master used to send frames on the bus + * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR + * @evts: events to disable + * + * Sends an ENEC CCC command to enable some or all events coming from a + * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR. + * + * This function must be called with the bus lock held in write mode. + * + * Return: 0 in case of success, a positive I3C error code if the error is + * one of the official Mx error codes, and a negative error code otherwise. + */ +int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr, + u8 evts) +{ + return i3c_master_enec_disec_locked(master, addr, true, evts); +} +EXPORT_SYMBOL_GPL(i3c_master_enec_locked); + +static int i3c_master_setda_locked(struct i3c_master_controller *master, + u8 oldaddr, u8 newaddr, bool setdasa) +{ + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_setda *setda; + struct i3c_ccc_cmd cmd; + int ret; + + if (!oldaddr || !newaddr) + return -EINVAL; + + setda = i3c_ccc_cmd_dest_init(&dest, oldaddr, sizeof(*setda)); + if (!setda) + return -ENOMEM; + + setda->addr = newaddr << 1; + i3c_ccc_cmd_init(&cmd, false, + setdasa ? I3C_CCC_SETDASA : I3C_CCC_SETNEWDA, + &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_setdasa_locked(struct i3c_master_controller *master, + u8 static_addr, u8 dyn_addr) +{ + return i3c_master_setda_locked(master, static_addr, dyn_addr, true); +} + +static int i3c_master_setnewda_locked(struct i3c_master_controller *master, + u8 oldaddr, u8 newaddr) +{ + return i3c_master_setda_locked(master, oldaddr, newaddr, false); +} + +static int i3c_master_getmrl_locked(struct i3c_master_controller *master, + struct i3c_device_info *info) +{ + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_mrl *mrl; + struct i3c_ccc_cmd cmd; + int ret; + + mrl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mrl)); + if (!mrl) + return -ENOMEM; + + /* + * When the device does not have IBI payload GETMRL only returns 2 + * bytes of data. + */ + if (!(info->bcr & I3C_BCR_IBI_PAYLOAD)) + dest.payload.len -= 1; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMRL, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + switch (dest.payload.len) { + case 3: + info->max_ibi_len = mrl->ibi_len; + fallthrough; + case 2: + info->max_read_len = be16_to_cpu(mrl->read_len); + break; + default: + ret = -EIO; + goto out; + } + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_getmwl_locked(struct i3c_master_controller *master, + struct i3c_device_info *info) +{ + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_mwl *mwl; + struct i3c_ccc_cmd cmd; + int ret; + + mwl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mwl)); + if (!mwl) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMWL, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + if (dest.payload.len != sizeof(*mwl)) { + ret = -EIO; + goto out; + } + + info->max_write_len = be16_to_cpu(mwl->len); + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_getmxds_locked(struct i3c_master_controller *master, + struct i3c_device_info *info) +{ + struct i3c_ccc_getmxds *getmaxds; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + getmaxds = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, + sizeof(*getmaxds)); + if (!getmaxds) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMXDS, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + if (dest.payload.len != 2 && dest.payload.len != 5) { + ret = -EIO; + goto out; + } + + info->max_read_ds = getmaxds->maxrd; + info->max_write_ds = getmaxds->maxwr; + if (dest.payload.len == 5) + info->max_read_turnaround = getmaxds->maxrdturn[0] | + ((u32)getmaxds->maxrdturn[1] << 8) | + ((u32)getmaxds->maxrdturn[2] << 16); + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_gethdrcap_locked(struct i3c_master_controller *master, + struct i3c_device_info *info) +{ + struct i3c_ccc_gethdrcap *gethdrcap; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + gethdrcap = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, + sizeof(*gethdrcap)); + if (!gethdrcap) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETHDRCAP, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + if (dest.payload.len != 1) { + ret = -EIO; + goto out; + } + + info->hdr_cap = gethdrcap->modes; + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_getpid_locked(struct i3c_master_controller *master, + struct i3c_device_info *info) +{ + struct i3c_ccc_getpid *getpid; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret, i; + + getpid = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getpid)); + if (!getpid) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETPID, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + info->pid = 0; + for (i = 0; i < sizeof(getpid->pid); i++) { + int sft = (sizeof(getpid->pid) - i - 1) * 8; + + info->pid |= (u64)getpid->pid[i] << sft; + } + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_getbcr_locked(struct i3c_master_controller *master, + struct i3c_device_info *info) +{ + struct i3c_ccc_getbcr *getbcr; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + getbcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getbcr)); + if (!getbcr) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETBCR, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + info->bcr = getbcr->bcr; + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_getdcr_locked(struct i3c_master_controller *master, + struct i3c_device_info *info) +{ + struct i3c_ccc_getdcr *getdcr; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + getdcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getdcr)); + if (!getdcr) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETDCR, &dest, 1); + ret = i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + info->dcr = getdcr->dcr; + +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +static int i3c_master_retrieve_dev_info(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + enum i3c_addr_slot_status slot_status; + int ret; + + if (!dev->info.dyn_addr) + return -EINVAL; + + slot_status = i3c_bus_get_addr_slot_status(&master->bus, + dev->info.dyn_addr); + if (slot_status == I3C_ADDR_SLOT_RSVD || + slot_status == I3C_ADDR_SLOT_I2C_DEV) + return -EINVAL; + + ret = i3c_master_getpid_locked(master, &dev->info); + if (ret) + return ret; + + ret = i3c_master_getbcr_locked(master, &dev->info); + if (ret) + return ret; + + ret = i3c_master_getdcr_locked(master, &dev->info); + if (ret) + return ret; + + if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) { + ret = i3c_master_getmxds_locked(master, &dev->info); + if (ret) + return ret; + } + + if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) + dev->info.max_ibi_len = 1; + + i3c_master_getmrl_locked(master, &dev->info); + i3c_master_getmwl_locked(master, &dev->info); + + if (dev->info.bcr & I3C_BCR_HDR_CAP) { + ret = i3c_master_gethdrcap_locked(master, &dev->info); + if (ret) + return ret; + } + + return 0; +} + +static void i3c_master_put_i3c_addrs(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + + if (dev->info.static_addr) + i3c_bus_set_addr_slot_status(&master->bus, + dev->info.static_addr, + I3C_ADDR_SLOT_FREE); + + if (dev->info.dyn_addr) + i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr, + I3C_ADDR_SLOT_FREE); + + if (dev->boardinfo && dev->boardinfo->init_dyn_addr) + i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr, + I3C_ADDR_SLOT_FREE); +} + +static int i3c_master_get_i3c_addrs(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + enum i3c_addr_slot_status status; + + if (!dev->info.static_addr && !dev->info.dyn_addr) + return 0; + + if (dev->info.static_addr) { + status = i3c_bus_get_addr_slot_status(&master->bus, + dev->info.static_addr); + if (status != I3C_ADDR_SLOT_FREE) + return -EBUSY; + + i3c_bus_set_addr_slot_status(&master->bus, + dev->info.static_addr, + I3C_ADDR_SLOT_I3C_DEV); + } + + /* + * ->init_dyn_addr should have been reserved before that, so, if we're + * trying to apply a pre-reserved dynamic address, we should not try + * to reserve the address slot a second time. + */ + if (dev->info.dyn_addr && + (!dev->boardinfo || + dev->boardinfo->init_dyn_addr != dev->info.dyn_addr)) { + status = i3c_bus_get_addr_slot_status(&master->bus, + dev->info.dyn_addr); + if (status != I3C_ADDR_SLOT_FREE) + goto err_release_static_addr; + + i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr, + I3C_ADDR_SLOT_I3C_DEV); + } + + return 0; + +err_release_static_addr: + if (dev->info.static_addr) + i3c_bus_set_addr_slot_status(&master->bus, + dev->info.static_addr, + I3C_ADDR_SLOT_FREE); + + return -EBUSY; +} + +static int i3c_master_attach_i3c_dev(struct i3c_master_controller *master, + struct i3c_dev_desc *dev) +{ + int ret; + + /* + * We don't attach devices to the controller until they are + * addressable on the bus. + */ + if (!dev->info.static_addr && !dev->info.dyn_addr) + return 0; + + ret = i3c_master_get_i3c_addrs(dev); + if (ret) + return ret; + + /* Do not attach the master device itself. */ + if (master->this != dev && master->ops->attach_i3c_dev) { + ret = master->ops->attach_i3c_dev(dev); + if (ret) { + i3c_master_put_i3c_addrs(dev); + return ret; + } + } + + list_add_tail(&dev->common.node, &master->bus.devs.i3c); + + return 0; +} + +static int i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, + u8 old_dyn_addr) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + enum i3c_addr_slot_status status; + int ret; + + if (dev->info.dyn_addr != old_dyn_addr && + (!dev->boardinfo || + dev->info.dyn_addr != dev->boardinfo->init_dyn_addr)) { + status = i3c_bus_get_addr_slot_status(&master->bus, + dev->info.dyn_addr); + if (status != I3C_ADDR_SLOT_FREE) + return -EBUSY; + i3c_bus_set_addr_slot_status(&master->bus, + dev->info.dyn_addr, + I3C_ADDR_SLOT_I3C_DEV); + } + + if (master->ops->reattach_i3c_dev) { + ret = master->ops->reattach_i3c_dev(dev, old_dyn_addr); + if (ret) { + i3c_master_put_i3c_addrs(dev); + return ret; + } + } + + return 0; +} + +static void i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + + /* Do not detach the master device itself. */ + if (master->this != dev && master->ops->detach_i3c_dev) + master->ops->detach_i3c_dev(dev); + + i3c_master_put_i3c_addrs(dev); + list_del(&dev->common.node); +} + +static int i3c_master_attach_i2c_dev(struct i3c_master_controller *master, + struct i2c_dev_desc *dev) +{ + int ret; + + if (master->ops->attach_i2c_dev) { + ret = master->ops->attach_i2c_dev(dev); + if (ret) + return ret; + } + + list_add_tail(&dev->common.node, &master->bus.devs.i2c); + + return 0; +} + +static void i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) +{ + struct i3c_master_controller *master = i2c_dev_get_master(dev); + + list_del(&dev->common.node); + + if (master->ops->detach_i2c_dev) + master->ops->detach_i2c_dev(dev); +} + +static int i3c_master_early_i3c_dev_add(struct i3c_master_controller *master, + struct i3c_dev_boardinfo *boardinfo) +{ + struct i3c_device_info info = { + .static_addr = boardinfo->static_addr, + }; + struct i3c_dev_desc *i3cdev; + int ret; + + i3cdev = i3c_master_alloc_i3c_dev(master, &info); + if (IS_ERR(i3cdev)) + return -ENOMEM; + + i3cdev->boardinfo = boardinfo; + + ret = i3c_master_attach_i3c_dev(master, i3cdev); + if (ret) + goto err_free_dev; + + ret = i3c_master_setdasa_locked(master, i3cdev->info.static_addr, + i3cdev->boardinfo->init_dyn_addr); + if (ret) + goto err_detach_dev; + + i3cdev->info.dyn_addr = i3cdev->boardinfo->init_dyn_addr; + ret = i3c_master_reattach_i3c_dev(i3cdev, 0); + if (ret) + goto err_rstdaa; + + ret = i3c_master_retrieve_dev_info(i3cdev); + if (ret) + goto err_rstdaa; + + return 0; + +err_rstdaa: + i3c_master_rstdaa_locked(master, i3cdev->boardinfo->init_dyn_addr); +err_detach_dev: + i3c_master_detach_i3c_dev(i3cdev); +err_free_dev: + i3c_master_free_i3c_dev(i3cdev); + + return ret; +} + +static void +i3c_master_register_new_i3c_devs(struct i3c_master_controller *master) +{ + struct i3c_dev_desc *desc; + int ret; + + if (!master->init_done) + return; + + i3c_bus_for_each_i3cdev(&master->bus, desc) { + if (desc->dev || !desc->info.dyn_addr || desc == master->this) + continue; + + desc->dev = kzalloc(sizeof(*desc->dev), GFP_KERNEL); + if (!desc->dev) + continue; + + desc->dev->bus = &master->bus; + desc->dev->desc = desc; + desc->dev->dev.parent = master->dev; + dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id, + desc->info.pid); + + ret = device_register(&desc->dev->dev); + if (ret) + dev_err(master->dev, + "Failed to add I3C device (err = %d)\n", ret); + } +} + +/** + * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment) + * @master: master doing the DAA + * + * This function is instantiating an I3C device object and adding it to the + * I3C device list. All device information are automatically retrieved using + * standard CCC commands. + * + * The I3C device object is returned in case the master wants to attach + * private data to it using i3c_dev_set_master_data(). + * + * This function must be called with the bus lock held in write mode. + * + * Return: a 0 in case of success, an negative error code otherwise. + */ +int i3c_master_do_daa(struct i3c_master_controller *master) +{ + int ret; + + i3c_bus_maintenance_lock(&master->bus); + ret = master->ops->do_daa(master); + i3c_bus_maintenance_unlock(&master->bus); + + if (ret) + return ret; + + i3c_bus_normaluse_lock(&master->bus); + i3c_master_register_new_i3c_devs(master); + i3c_bus_normaluse_unlock(&master->bus); + + return 0; +} +EXPORT_SYMBOL_GPL(i3c_master_do_daa); + +/** + * i3c_master_set_info() - set master device information + * @master: master used to send frames on the bus + * @info: I3C device information + * + * Set master device info. This should be called from + * &i3c_master_controller_ops->bus_init(). + * + * Not all &i3c_device_info fields are meaningful for a master device. + * Here is a list of fields that should be properly filled: + * + * - &i3c_device_info->dyn_addr + * - &i3c_device_info->bcr + * - &i3c_device_info->dcr + * - &i3c_device_info->pid + * - &i3c_device_info->hdr_cap if %I3C_BCR_HDR_CAP bit is set in + * &i3c_device_info->bcr + * + * This function must be called with the bus lock held in maintenance mode. + * + * Return: 0 if @info contains valid information (not every piece of + * information can be checked, but we can at least make sure @info->dyn_addr + * and @info->bcr are correct), -EINVAL otherwise. + */ +int i3c_master_set_info(struct i3c_master_controller *master, + const struct i3c_device_info *info) +{ + struct i3c_dev_desc *i3cdev; + int ret; + + if (!i3c_bus_dev_addr_is_avail(&master->bus, info->dyn_addr)) + return -EINVAL; + + if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER && + master->secondary) + return -EINVAL; + + if (master->this) + return -EINVAL; + + i3cdev = i3c_master_alloc_i3c_dev(master, info); + if (IS_ERR(i3cdev)) + return PTR_ERR(i3cdev); + + master->this = i3cdev; + master->bus.cur_master = master->this; + + ret = i3c_master_attach_i3c_dev(master, i3cdev); + if (ret) + goto err_free_dev; + + return 0; + +err_free_dev: + i3c_master_free_i3c_dev(i3cdev); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_master_set_info); + +static void i3c_master_detach_free_devs(struct i3c_master_controller *master) +{ + struct i3c_dev_desc *i3cdev, *i3ctmp; + struct i2c_dev_desc *i2cdev, *i2ctmp; + + list_for_each_entry_safe(i3cdev, i3ctmp, &master->bus.devs.i3c, + common.node) { + i3c_master_detach_i3c_dev(i3cdev); + + if (i3cdev->boardinfo && i3cdev->boardinfo->init_dyn_addr) + i3c_bus_set_addr_slot_status(&master->bus, + i3cdev->boardinfo->init_dyn_addr, + I3C_ADDR_SLOT_FREE); + + i3c_master_free_i3c_dev(i3cdev); + } + + list_for_each_entry_safe(i2cdev, i2ctmp, &master->bus.devs.i2c, + common.node) { + i3c_master_detach_i2c_dev(i2cdev); + i3c_bus_set_addr_slot_status(&master->bus, + i2cdev->addr, + I3C_ADDR_SLOT_FREE); + i3c_master_free_i2c_dev(i2cdev); + } +} + +/** + * i3c_master_bus_init() - initialize an I3C bus + * @master: main master initializing the bus + * + * This function is following all initialisation steps described in the I3C + * specification: + * + * 1. Attach I2C devs to the master so that the master can fill its internal + * device table appropriately + * + * 2. Call &i3c_master_controller_ops->bus_init() method to initialize + * the master controller. That's usually where the bus mode is selected + * (pure bus or mixed fast/slow bus) + * + * 3. Instruct all devices on the bus to drop their dynamic address. This is + * particularly important when the bus was previously configured by someone + * else (for example the bootloader) + * + * 4. Disable all slave events. + * + * 5. Reserve address slots for I3C devices with init_dyn_addr. And if devices + * also have static_addr, try to pre-assign dynamic addresses requested by + * the FW with SETDASA and attach corresponding statically defined I3C + * devices to the master. + * + * 6. Do a DAA (Dynamic Address Assignment) to assign dynamic addresses to all + * remaining I3C devices + * + * Once this is done, all I3C and I2C devices should be usable. + * + * Return: a 0 in case of success, an negative error code otherwise. + */ +static int i3c_master_bus_init(struct i3c_master_controller *master) +{ + enum i3c_addr_slot_status status; + struct i2c_dev_boardinfo *i2cboardinfo; + struct i3c_dev_boardinfo *i3cboardinfo; + struct i2c_dev_desc *i2cdev; + int ret; + + /* + * First attach all devices with static definitions provided by the + * FW. + */ + list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) { + status = i3c_bus_get_addr_slot_status(&master->bus, + i2cboardinfo->base.addr); + if (status != I3C_ADDR_SLOT_FREE) { + ret = -EBUSY; + goto err_detach_devs; + } + + i3c_bus_set_addr_slot_status(&master->bus, + i2cboardinfo->base.addr, + I3C_ADDR_SLOT_I2C_DEV); + + i2cdev = i3c_master_alloc_i2c_dev(master, i2cboardinfo); + if (IS_ERR(i2cdev)) { + ret = PTR_ERR(i2cdev); + goto err_detach_devs; + } + + ret = i3c_master_attach_i2c_dev(master, i2cdev); + if (ret) { + i3c_master_free_i2c_dev(i2cdev); + goto err_detach_devs; + } + } + + /* + * Now execute the controller specific ->bus_init() routine, which + * might configure its internal logic to match the bus limitations. + */ + ret = master->ops->bus_init(master); + if (ret) + goto err_detach_devs; + + /* + * The master device should have been instantiated in ->bus_init(), + * complain if this was not the case. + */ + if (!master->this) { + dev_err(master->dev, + "master_set_info() was not called in ->bus_init()\n"); + ret = -EINVAL; + goto err_bus_cleanup; + } + + /* + * Reset all dynamic address that may have been assigned before + * (assigned by the bootloader for example). + */ + ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); + if (ret && ret != I3C_ERROR_M2) + goto err_bus_cleanup; + + /* Disable all slave events before starting DAA. */ + ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR, + I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR | + I3C_CCC_EVENT_HJ); + if (ret && ret != I3C_ERROR_M2) + goto err_bus_cleanup; + + /* + * Reserve init_dyn_addr first, and then try to pre-assign dynamic + * address and retrieve device information if needed. + * In case pre-assign dynamic address fails, setting dynamic address to + * the requested init_dyn_addr is retried after DAA is done in + * i3c_master_add_i3c_dev_locked(). + */ + list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { + /* + * We don't reserve a dynamic address for devices that + * don't explicitly request one. + */ + if (!i3cboardinfo->init_dyn_addr) + continue; + + ret = i3c_bus_get_addr_slot_status(&master->bus, + i3cboardinfo->init_dyn_addr); + if (ret != I3C_ADDR_SLOT_FREE) { + ret = -EBUSY; + goto err_rstdaa; + } + + i3c_bus_set_addr_slot_status(&master->bus, + i3cboardinfo->init_dyn_addr, + I3C_ADDR_SLOT_I3C_DEV); + + /* + * Only try to create/attach devices that have a static + * address. Other devices will be created/attached when + * DAA happens, and the requested dynamic address will + * be set using SETNEWDA once those devices become + * addressable. + */ + + if (i3cboardinfo->static_addr) + i3c_master_early_i3c_dev_add(master, i3cboardinfo); + } + + ret = i3c_master_do_daa(master); + if (ret) + goto err_rstdaa; + + return 0; + +err_rstdaa: + i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); + +err_bus_cleanup: + if (master->ops->bus_cleanup) + master->ops->bus_cleanup(master); + +err_detach_devs: + i3c_master_detach_free_devs(master); + + return ret; +} + +static void i3c_master_attach_boardinfo(struct i3c_dev_desc *i3cdev) +{ + struct i3c_master_controller *master = i3cdev->common.master; + struct i3c_dev_boardinfo *i3cboardinfo; + + list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { + if (i3cdev->info.pid != i3cboardinfo->pid) + continue; + + i3cdev->boardinfo = i3cboardinfo; + i3cdev->info.static_addr = i3cboardinfo->static_addr; + return; + } +} + +static struct i3c_dev_desc * +i3c_master_search_i3c_dev_duplicate(struct i3c_dev_desc *refdev) +{ + struct i3c_master_controller *master = i3c_dev_get_master(refdev); + struct i3c_dev_desc *i3cdev; + + i3c_bus_for_each_i3cdev(&master->bus, i3cdev) { + if (i3cdev != refdev && i3cdev->info.pid == refdev->info.pid) + return i3cdev; + } + + return NULL; +} + +/** + * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus + * @master: master used to send frames on the bus + * @addr: I3C slave dynamic address assigned to the device + * + * This function is instantiating an I3C device object and adding it to the + * I3C device list. All device information are automatically retrieved using + * standard CCC commands. + * + * The I3C device object is returned in case the master wants to attach + * private data to it using i3c_dev_set_master_data(). + * + * This function must be called with the bus lock held in write mode. + * + * Return: a 0 in case of success, an negative error code otherwise. + */ +int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, + u8 addr) +{ + struct i3c_device_info info = { .dyn_addr = addr }; + struct i3c_dev_desc *newdev, *olddev; + u8 old_dyn_addr = addr, expected_dyn_addr; + struct i3c_ibi_setup ibireq = { }; + bool enable_ibi = false; + int ret; + + if (!master) + return -EINVAL; + + newdev = i3c_master_alloc_i3c_dev(master, &info); + if (IS_ERR(newdev)) + return PTR_ERR(newdev); + + master->this = newdev; + ret = i3c_master_attach_i3c_dev(master, newdev); + if (ret) + goto err_free_dev; + + ret = i3c_master_retrieve_dev_info(newdev); + if (ret) + goto err_detach_dev; + + i3c_master_attach_boardinfo(newdev); + + olddev = i3c_master_search_i3c_dev_duplicate(newdev); + if (olddev) { + newdev->dev = olddev->dev; + if (newdev->dev) + newdev->dev->desc = newdev; + + /* + * We need to restore the IBI state too, so let's save the + * IBI information and try to restore them after olddev has + * been detached+released and its IBI has been stopped and + * the associated resources have been freed. + */ + mutex_lock(&olddev->ibi_lock); + if (olddev->ibi) { + ibireq.handler = olddev->ibi->handler; + ibireq.max_payload_len = olddev->ibi->max_payload_len; + ibireq.num_slots = olddev->ibi->num_slots; + + if (olddev->ibi->enabled) { + enable_ibi = true; + i3c_dev_disable_ibi_locked(olddev); + } + + i3c_dev_free_ibi_locked(olddev); + } + mutex_unlock(&olddev->ibi_lock); + + old_dyn_addr = olddev->info.dyn_addr; + + i3c_master_detach_i3c_dev(olddev); + i3c_master_free_i3c_dev(olddev); + } + + ret = i3c_master_reattach_i3c_dev(newdev, old_dyn_addr); + if (ret) + goto err_detach_dev; + + /* + * Depending on our previous state, the expected dynamic address might + * differ: + * - if the device already had a dynamic address assigned, let's try to + * re-apply this one + * - if the device did not have a dynamic address and the firmware + * requested a specific address, pick this one + * - in any other case, keep the address automatically assigned by the + * master + */ + if (old_dyn_addr && old_dyn_addr != newdev->info.dyn_addr) + expected_dyn_addr = old_dyn_addr; + else if (newdev->boardinfo && newdev->boardinfo->init_dyn_addr) + expected_dyn_addr = newdev->boardinfo->init_dyn_addr; + else + expected_dyn_addr = newdev->info.dyn_addr; + + if (newdev->info.dyn_addr != expected_dyn_addr) { + /* + * Try to apply the expected dynamic address. If it fails, keep + * the address assigned by the master. + */ + ret = i3c_master_setnewda_locked(master, + newdev->info.dyn_addr, + expected_dyn_addr); + if (!ret) { + old_dyn_addr = newdev->info.dyn_addr; + newdev->info.dyn_addr = expected_dyn_addr; + i3c_master_reattach_i3c_dev(newdev, old_dyn_addr); + } else { + dev_err(master->dev, + "Failed to assign reserved/old address to device %d%llx", + master->bus.id, newdev->info.pid); + } + } + + /* + * Now is time to try to restore the IBI setup. If we're lucky, + * everything works as before, otherwise, all we can do is complain. + * FIXME: maybe we should add callback to inform the driver that it + * should request the IBI again instead of trying to hide that from + * him. + */ + if (ibireq.handler) { + mutex_lock(&newdev->ibi_lock); + ret = i3c_dev_request_ibi_locked(newdev, &ibireq); + if (ret) { + dev_err(master->dev, + "Failed to request IBI on device %d-%llx", + master->bus.id, newdev->info.pid); + } else if (enable_ibi) { + ret = i3c_dev_enable_ibi_locked(newdev); + if (ret) + dev_err(master->dev, + "Failed to re-enable IBI on device %d-%llx", + master->bus.id, newdev->info.pid); + } + mutex_unlock(&newdev->ibi_lock); + } + + return 0; + +err_detach_dev: + if (newdev->dev && newdev->dev->desc) + newdev->dev->desc = NULL; + + i3c_master_detach_i3c_dev(newdev); + +err_free_dev: + i3c_master_free_i3c_dev(newdev); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); + +#define OF_I3C_REG1_IS_I2C_DEV BIT(31) + +static int +of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master, + struct device_node *node, u32 *reg) +{ + struct i3c_dev_boardinfo *boardinfo; + struct udevice *dev = master->dev; + enum i3c_addr_slot_status addrstatus; + u32 init_dyn_addr = 0; + + boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL); + if (!boardinfo) + return -ENOMEM; + + if (reg[0]) { + if (reg[0] > I3C_MAX_ADDR) + return -EINVAL; + + addrstatus = i3c_bus_get_addr_slot_status(&master->bus, + reg[0]); + if (addrstatus != I3C_ADDR_SLOT_FREE) + return -EINVAL; + } + + boardinfo->static_addr = reg[0]; + + if (!dev_read_u32(dev, "assigned-address", &init_dyn_addr)) { + if (init_dyn_addr > I3C_MAX_ADDR) + return -EINVAL; + + addrstatus = i3c_bus_get_addr_slot_status(&master->bus, + init_dyn_addr); + if (addrstatus != I3C_ADDR_SLOT_FREE) + return -EINVAL; + } + + boardinfo->pid = ((u64)reg[1] << 32) | reg[2]; + + if ((boardinfo->pid & GENMASK_ULL(63, 48)) || + I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) + return -EINVAL; + + boardinfo->init_dyn_addr = init_dyn_addr; + boardinfo->of_node = node; + list_add_tail(&boardinfo->node, &master->boardinfo.i3c); + + return 0; +} + +static int of_i3c_master_add_dev(struct i3c_master_controller *master, + struct device_node *node) +{ + u32 reg[3]; + int ret; + + if (!master || !node) + return -EINVAL; + + ret = dev_read_u32_array(master->dev, "reg", reg, ARRAY_SIZE(reg)); + if (ret) + return ret; + + ret = of_i3c_master_add_i3c_boardinfo(master, node, reg); + + return ret; +} + +static int of_populate_i3c_bus(struct i3c_master_controller *master) +{ + struct udevice *dev = master->dev; + struct device_node *node = NULL; + ofnode child; + int ret; + u32 val; + + if (ofnode_valid(dev_ofnode(dev))) + return 0; + + ofnode_for_each_subnode(child, dev_ofnode(dev)) { + ret = of_i3c_master_add_dev(master, node); + if (ret) { + of_node_put(node); + return ret; + } + } + + /* + * The user might want to limit I2C and I3C speed in case some devices + * on the bus are not supporting typical rates, or if the bus topology + * prevents it from using max possible rate. + */ + if (!dev_read_u32(dev, "i2c-scl-hz", &val)) + master->bus.scl_rate.i2c = val; + + if (!dev_read_u32(dev, "i3c-scl-hz", &val)) + master->bus.scl_rate.i3c = val; + + return 0; +} + +static void i3c_master_handle_ibi(struct work_struct *work) +{ + struct i3c_ibi_slot *slot = container_of(work, struct i3c_ibi_slot, + work); + struct i3c_dev_desc *dev = slot->dev; + struct i3c_master_controller *master = i3c_dev_get_master(dev); + struct i3c_ibi_payload payload; + + payload.data = slot->data; + payload.len = slot->len; + + if (dev->dev) + dev->ibi->handler(dev->dev, &payload); + + master->ops->recycle_ibi_slot(dev, slot); +} + +static void i3c_master_init_ibi_slot(struct i3c_dev_desc *dev, + struct i3c_ibi_slot *slot) +{ + slot->dev = dev; + i3c_master_handle_ibi(&slot->work); +} + +struct i3c_generic_ibi_slot { + struct list_head node; + struct i3c_ibi_slot base; +}; + +struct i3c_generic_ibi_pool { + spinlock_t lock; /* spinlock for ibi pool */ + unsigned int num_slots; + struct i3c_generic_ibi_slot *slots; + void *payload_buf; + struct list_head free_slots; + struct list_head pending; +}; + +/** + * i3c_generic_ibi_free_pool() - Free a generic IBI pool + * @pool: the IBI pool to free + * + * Free all IBI slots allated by a generic IBI pool. + */ +void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool) +{ + struct i3c_generic_ibi_slot *slot; + unsigned int nslots = 0; + + while (!list_empty(&pool->free_slots)) { + slot = list_first_entry(&pool->free_slots, + struct i3c_generic_ibi_slot, node); + list_del(&slot->node); + nslots++; + } + + /* + * If the number of freed slots is not equal to the number of allocated + * slots we have a leak somewhere. + */ + WARN_ON(nslots != pool->num_slots); + + kfree(pool->payload_buf); + kfree(pool->slots); + kfree(pool); +} +EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool); + +/** + * i3c_generic_ibi_alloc_pool() - Create a generic IBI pool + * @dev: the device this pool will be used for + * @req: IBI setup request describing what the device driver expects + * + * Create a generic IBI pool based on the information provided in @req. + * + * Return: a valid IBI pool in case of success, an ERR_PTR() otherwise. + */ +struct i3c_generic_ibi_pool * +i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev, + const struct i3c_ibi_setup *req) +{ + struct i3c_generic_ibi_pool *pool; + struct i3c_generic_ibi_slot *slot; + unsigned int i; + int ret; + + pool = kzalloc(sizeof(*pool), GFP_KERNEL); + if (!pool) + return ERR_PTR(-ENOMEM); + + spin_lock_init(&pool->lock); + INIT_LIST_HEAD(&pool->free_slots); + INIT_LIST_HEAD(&pool->pending); + + pool->slots = kcalloc(req->num_slots, sizeof(*slot), GFP_KERNEL); + if (!pool->slots) { + ret = -ENOMEM; + goto err_free_pool; + } + + if (req->max_payload_len) { + pool->payload_buf = kcalloc(req->num_slots, + req->max_payload_len, GFP_KERNEL); + if (!pool->payload_buf) { + ret = -ENOMEM; + goto err_free_pool; + } + } + + for (i = 0; i < req->num_slots; i++) { + slot = &pool->slots[i]; + i3c_master_init_ibi_slot(dev, &slot->base); + + if (req->max_payload_len) + slot->base.data = pool->payload_buf + + (i * req->max_payload_len); + + list_add_tail(&slot->node, &pool->free_slots); + pool->num_slots++; + } + + return pool; + +err_free_pool: + i3c_generic_ibi_free_pool(pool); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(i3c_generic_ibi_alloc_pool); + +/** + * i3c_generic_ibi_get_free_slot() - Get a free slot from a generic IBI pool + * @pool: the pool to query an IBI slot on + * + * Search for a free slot in a generic IBI pool. + * The slot should be returned to the pool using i3c_generic_ibi_recycle_slot() + * when it's no longer needed. + * + * Return: a pointer to a free slot, or NULL if there's no free slot available. + */ +struct i3c_ibi_slot * +i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool) +{ + struct i3c_generic_ibi_slot *slot; + unsigned long flags; + + spin_lock_irqsave(&pool->lock, flags); + slot = list_first_entry_or_null(&pool->free_slots, + struct i3c_generic_ibi_slot, node); + + if (slot) + list_del(&slot->node); + spin_unlock_irqrestore(&pool->lock, flags); + + return slot ? &slot->base : NULL; +} +EXPORT_SYMBOL_GPL(i3c_generic_ibi_get_free_slot); + +/** + * i3c_generic_ibi_recycle_slot() - Return a slot to a generic IBI pool + * @pool: the pool to return the IBI slot to + * @s: IBI slot to recycle + * + * Add an IBI slot back to its generic IBI pool. Should be called from the + * master driver struct_master_controller_ops->recycle_ibi() method. + */ +void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool, + struct i3c_ibi_slot *s) +{ + struct i3c_generic_ibi_slot *slot; + unsigned long flags; + + if (!s) + return; + + slot = container_of(s, struct i3c_generic_ibi_slot, base); + spin_lock_irqsave(&pool->lock, flags); + list_add_tail(&slot->node, &pool->free_slots); + spin_unlock_irqrestore(&pool->lock, flags); +} +EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot); + +static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops) +{ + if (!ops || !ops->bus_init || !ops->priv_xfers || + !ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers) + return -EINVAL; + + if (ops->request_ibi && + (!ops->enable_ibi || !ops->disable_ibi || !ops->free_ibi || + !ops->recycle_ibi_slot)) + return -EINVAL; + + return 0; +} + +/** + * i3c_master_register() - register an I3C master + * @master: master used to send frames on the bus + * @parent: the parent device (the one that provides this I3C master + * controller) + * @ops: the master controller operations + * @secondary: true if you are registering a secondary master. Will return + * -ENOTSUPP if set to true since secondary masters are not yet + * supported + * + * This function takes care of everything for you: + * + * - creates and initializes the I3C bus + * - populates the bus with static I2C devs if @parent->of_node is not + * NULL + * - registers all I3C devices added by the controller during bus + * initialization + * - registers the I2C adapter and all I2C devices + * + * Return: 0 in case of success, a negative error code otherwise. + */ +int i3c_master_register(struct i3c_master_controller *master, + struct udevice *dev, + const struct i3c_master_controller_ops *ops, + bool secondary) +{ + unsigned long i2c_scl_rate = I3C_BUS_I2C_FM_PLUS_SCL_RATE; + struct i3c_bus *i3cbus = i3c_master_get_bus(master); + enum i3c_bus_mode mode = I3C_BUS_MODE_PURE; + struct i2c_dev_boardinfo *i2cbi; + int ret; + + /* We do not support secondary masters yet. */ + if (secondary) + return -EOPNOTSUPP; + + ret = i3c_master_check_ops(ops); + if (ret) + return ret; + + master->dev = dev; + + master->ops = ops; + master->secondary = secondary; + INIT_LIST_HEAD(&master->boardinfo.i2c); + INIT_LIST_HEAD(&master->boardinfo.i3c); + + ret = i3c_bus_init(i3cbus); + if (ret) + return ret; + + dev_set_name(master->dev, "i3c-%d", i3cbus->id); + + ret = of_populate_i3c_bus(master); + if (ret) + return ret; + + list_for_each_entry(i2cbi, &master->boardinfo.i2c, node) { + switch (i2cbi->lvr & I3C_LVR_I2C_INDEX_MASK) { + case I3C_LVR_I2C_INDEX(0): + if (mode < I3C_BUS_MODE_MIXED_FAST) + mode = I3C_BUS_MODE_MIXED_FAST; + break; + case I3C_LVR_I2C_INDEX(1): + if (mode < I3C_BUS_MODE_MIXED_LIMITED) + mode = I3C_BUS_MODE_MIXED_LIMITED; + break; + case I3C_LVR_I2C_INDEX(2): + if (mode < I3C_BUS_MODE_MIXED_SLOW) + mode = I3C_BUS_MODE_MIXED_SLOW; + break; + default: + ret = -EINVAL; + return ret; + } + + if (i2cbi->lvr & I3C_LVR_I2C_FM_MODE) + i2c_scl_rate = I3C_BUS_I2C_FM_SCL_RATE; + } + + ret = i3c_bus_set_mode(i3cbus, mode, i2c_scl_rate); + if (ret) + return ret; + + ret = i3c_master_bus_init(master); + if (ret) + return ret; + + /* + * We're done initializing the bus and the controller, we can now + * register I3C devices discovered during the initial DAA. + */ + master->init_done = true; + i3c_bus_normaluse_lock(&master->bus); + i3c_master_register_new_i3c_devs(master); + i3c_bus_normaluse_unlock(&master->bus); + + return ret; +} +EXPORT_SYMBOL_GPL(i3c_master_register); + +int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev, + struct i3c_priv_xfer *xfers, + int nxfers) +{ + struct i3c_master_controller *master; + + if (!dev) + return -ENOENT; + + master = i3c_dev_get_master(dev); + if (!master || !xfers) + return -EINVAL; + + if (!master->ops->priv_xfers) + return -EOPNOTSUPP; + + return master->ops->priv_xfers(dev, xfers, nxfers); +} + +int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *master; + int ret; + + if (!dev->ibi) + return -EINVAL; + + master = i3c_dev_get_master(dev); + ret = master->ops->disable_ibi(dev); + if (ret) + return ret; + + dev->ibi->enabled = false; + + return 0; +} + +int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + int ret; + + if (!dev->ibi) + return -EINVAL; + + ret = master->ops->enable_ibi(dev); + if (!ret) + dev->ibi->enabled = true; + + return ret; +} + +int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev, + const struct i3c_ibi_setup *req) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + struct i3c_device_ibi_info *ibi; + int ret; + + if (!master->ops->request_ibi) + return -EOPNOTSUPP; + + if (dev->ibi) + return -EBUSY; + + ibi = kzalloc(sizeof(*ibi), GFP_KERNEL); + if (!ibi) + return -ENOMEM; + + ibi->handler = req->handler; + ibi->max_payload_len = req->max_payload_len; + ibi->num_slots = req->num_slots; + + dev->ibi = ibi; + ret = master->ops->request_ibi(dev, req); + if (ret) { + kfree(ibi); + dev->ibi = NULL; + } + + return ret; +} + +void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *master = i3c_dev_get_master(dev); + + if (!dev->ibi) + return; + + if (WARN_ON(dev->ibi->enabled)) + WARN_ON(i3c_dev_disable_ibi_locked(dev)); + + master->ops->free_ibi(dev); + kfree(dev->ibi); + dev->ibi = NULL; +} + +MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>"); +MODULE_DESCRIPTION("I3C core"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig new file mode 100644 index 00000000000..79776f60ae4 --- /dev/null +++ b/drivers/i3c/master/Kconfig @@ -0,0 +1,11 @@ +config DW_I3C_MASTER + tristate "Synopsys DesignWare I3C master driver" + depends on I3C + help + Support for Synopsys DesignWare MIPI I3C Controller. + + For details please see + https://www.synopsys.com/dw/ipdir.php?ds=mipi_i3c + + This driver can also be built as a module. If so, the module + will be called dw-i3c-master. diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile new file mode 100644 index 00000000000..c7562f1aa33 --- /dev/null +++ b/drivers/i3c/master/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c-master.c new file mode 100644 index 00000000000..d96eb9b134e --- /dev/null +++ b/drivers/i3c/master/dw-i3c-master.c @@ -0,0 +1,1062 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. + * + * Author: Vitor Soares <vitor.soares@synopsys.com> + */ + +#include <asm/io.h> +#include <dm.h> +#include <dw-i3c.h> +#include <i2c.h> +#include <log.h> +#include <malloc.h> +#include <pci.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <linux/compat.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/iopoll.h> +#include <linux/i3c/master.h> + +#ifdef CONFIG_SANDBOX +#define cpu_relax() do {} while (0) +#endif + +static u8 even_parity(u8 p) +{ + p ^= p >> 4; + p &= 0xf; + + return (0x9669 >> p) & 1; +} + +ulong msecs_to_jiffies(ulong msec) +{ + ulong hz = CONFIG_SYS_HZ; + + return (msec + (1000 / hz) - 1) / (1000 / hz); +} + +static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, + const struct i3c_ccc_cmd *cmd) +{ + if (cmd->ndests > 1) + return false; + + switch (cmd->id) { + case I3C_CCC_ENEC(true): + case I3C_CCC_ENEC(false): + case I3C_CCC_DISEC(true): + case I3C_CCC_DISEC(false): + case I3C_CCC_ENTAS(0, true): + case I3C_CCC_ENTAS(0, false): + case I3C_CCC_RSTDAA(true): + case I3C_CCC_RSTDAA(false): + case I3C_CCC_ENTDAA: + case I3C_CCC_SETMWL(true): + case I3C_CCC_SETMWL(false): + case I3C_CCC_SETMRL(true): + case I3C_CCC_SETMRL(false): + case I3C_CCC_ENTHDR(0): + case I3C_CCC_SETDASA: + case I3C_CCC_SETNEWDA: + case I3C_CCC_GETMWL: + case I3C_CCC_GETMRL: + case I3C_CCC_GETPID: + case I3C_CCC_GETBCR: + case I3C_CCC_GETDCR: + case I3C_CCC_GETSTATUS: + case I3C_CCC_GETMXDS: + case I3C_CCC_GETHDRCAP: + return true; + default: + return false; + } +} + +static inline struct dw_i3c_master * +to_dw_i3c_master(struct i3c_master_controller *master) +{ + return container_of(master, struct dw_i3c_master, base); +} + +static void dw_i3c_master_disable(struct dw_i3c_master *master) +{ + writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE, + master->regs + DEVICE_CTRL); +} + +static void dw_i3c_master_enable(struct dw_i3c_master *master) +{ + writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE, + master->regs + DEVICE_CTRL); +} + +static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) +{ + int pos; + + for (pos = 0; pos < master->maxdevs; pos++) { + if (addr == master->addrs[pos]) + return pos; + } + + return -EINVAL; +} + +static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) +{ + if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0))) + return -ENOSPC; + + return ffs(master->free_pos) - 1; +} + +static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, + const u8 *bytes, int nbytes) +{ + writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4); + if (nbytes & 3) { + u32 tmp = 0; + + memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3); + writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1); + } +} + +static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, + u8 *bytes, int nbytes) +{ + readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4); + if (nbytes & 3) { + u32 tmp; + + readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1); + memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3); + } +} + +static struct dw_i3c_xfer * +dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) +{ + struct dw_i3c_xfer *xfer; + + xfer = kzalloc(STRUCT_SZ(struct dw_i3c_xfer, ncmds), GFP_KERNEL); + if (!xfer) + return NULL; + + INIT_LIST_HEAD(&xfer->node); + xfer->ncmds = ncmds; + xfer->ret = -ETIMEDOUT; + + return xfer; +} + +static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer) +{ + kfree(xfer); +} + +static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) +{ + struct dw_i3c_xfer *xfer = master->xferqueue.cur; + unsigned int i; + u32 thld_ctrl; + + if (!xfer) + return; + + for (i = 0; i < xfer->ncmds; i++) { + struct dw_i3c_cmd *cmd = &xfer->cmds[i]; + + dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len); + } + + thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); + thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; + thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds); + writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); + + for (i = 0; i < xfer->ncmds; i++) { + struct dw_i3c_cmd *cmd = &xfer->cmds[i]; + + writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT); + writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT); + } +} + +static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, + struct dw_i3c_xfer *xfer) +{ + unsigned long flags; + + spin_lock_irqsave(&master->xferqueue.lock, flags); + + if (master->xferqueue.cur) { + list_add_tail(&xfer->node, &master->xferqueue.list); + } else { + master->xferqueue.cur = xfer; + dw_i3c_master_start_xfer_locked(master); + } + + spin_unlock_irqrestore(&master->xferqueue.lock, flags); +} + +static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, + struct dw_i3c_xfer *xfer) +{ + if (master->xferqueue.cur == xfer) { + u32 status; + + master->xferqueue.cur = NULL; + + writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | + RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE, + master->regs + RESET_CTRL); + + readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, + !status, 10, 1000000); + } else { + list_del_init(&xfer->node); + } +} + +static int dw_i3c_status_poll_timeout(struct dw_i3c_master *master) +{ + u32 status; + unsigned long base, limit; + + base = get_timer(0); + limit = CONFIG_SYS_HZ * 5000 / 1000; + do { + status = readl(master->regs + INTR_STATUS); + if (status) + return 0; + + cpu_relax(); + } while (get_timer(base) < limit); + + return -ETIMEDOUT; +} + +static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, + struct dw_i3c_xfer *xfer) +{ + unsigned long flags; + + spin_lock_irqsave(&master->xferqueue.lock, flags); + dw_i3c_master_dequeue_xfer_locked(master, xfer); + spin_unlock_irqrestore(&master->xferqueue.lock, flags); +} + +static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) +{ + struct dw_i3c_xfer *xfer = master->xferqueue.cur; + int i, ret = 0; + u32 nresp; + + if (!xfer) + return; + + nresp = readl(master->regs + QUEUE_STATUS_LEVEL); + nresp = QUEUE_STATUS_LEVEL_RESP(nresp); + + for (i = 0; i < nresp; i++) { + struct dw_i3c_cmd *cmd; + u32 resp; + + resp = readl(master->regs + RESPONSE_QUEUE_PORT); + + cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)]; + cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp); + cmd->error = RESPONSE_PORT_ERR_STATUS(resp); + if (cmd->rx_len && !cmd->error) + dw_i3c_master_read_rx_fifo(master, cmd->rx_buf, + cmd->rx_len); + } + + for (i = 0; i < nresp; i++) { + switch (xfer->cmds[i].error) { + case RESPONSE_NO_ERROR: + break; + case RESPONSE_ERROR_PARITY: + case RESPONSE_ERROR_IBA_NACK: + case RESPONSE_ERROR_TRANSF_ABORT: + case RESPONSE_ERROR_CRC: + case RESPONSE_ERROR_FRAME: + ret = -EIO; + break; + case RESPONSE_ERROR_OVER_UNDER_FLOW: + ret = -ENOSPC; + break; + case RESPONSE_ERROR_I2C_W_NACK_ERR: + case RESPONSE_ERROR_ADDRESS_NACK: + default: + ret = -EINVAL; + break; + } + } + + xfer->ret = ret; + + if (ret < 0) { + dw_i3c_master_dequeue_xfer_locked(master, xfer); + writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME, + master->regs + DEVICE_CTRL); + } + + xfer = list_first_entry_or_null(&master->xferqueue.list, + struct dw_i3c_xfer, + node); + if (xfer) + list_del_init(&xfer->node); + + master->xferqueue.cur = xfer; + dw_i3c_master_start_xfer_locked(master); +} + +static int dw_i3c_clk_cfg(struct dw_i3c_master *master) +{ + unsigned long core_rate, core_period; + u32 scl_timing; + u8 hcnt, lcnt; + + core_rate = clk_get_rate(&master->core_clk); + if (!core_rate) + return -EINVAL; + + core_period = DIV_ROUND_UP(1000000000, core_rate); + + hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1; + if (hcnt < SCL_I3C_TIMING_CNT_MIN) + hcnt = SCL_I3C_TIMING_CNT_MIN; + + /* set back to THIGH_MAX_NS, after disable spike filter */ + if (!master->first_broadcast) { + lcnt = SCL_I3C_TIMING_LCNT(readl(master->regs + SCL_I3C_OD_TIMING)); + scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | lcnt; + writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); + return 0; + } + + lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt; + if (lcnt < SCL_I3C_TIMING_CNT_MIN) + lcnt = SCL_I3C_TIMING_CNT_MIN; + + scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); + writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); + + /* + * In pure i3c mode, MST_FREE represents tCAS. In shared mode, this + * will be set up by dw_i2c_clk_cfg as tLOW. + */ + if (master->base.bus.mode == I3C_BUS_MODE_PURE) + writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); + + lcnt = max_t(u8, + DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt); + + /* first broadcast thigh to 200ns, to disable spike filter */ + hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_INIT_OD_MIN_NS, core_period); + + scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); + writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); + + lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt; + scl_timing = SCL_EXT_LCNT_1(lcnt); + lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt; + scl_timing |= SCL_EXT_LCNT_2(lcnt); + lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt; + scl_timing |= SCL_EXT_LCNT_3(lcnt); + lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt; + scl_timing |= SCL_EXT_LCNT_4(lcnt); + writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); + + return 0; +} + +static int dw_i2c_clk_cfg(struct dw_i3c_master *master) +{ + unsigned long core_rate, core_period; + u16 hcnt, lcnt; + u32 scl_timing; + + core_rate = clk_get_rate(&master->core_clk); + if (!core_rate) + return -EINVAL; + + core_period = DIV_ROUND_UP(1000000000, core_rate); + + lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period); + hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt; + scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) | + SCL_I2C_FMP_TIMING_LCNT(lcnt); + writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); + + lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period); + hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt; + scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) | + SCL_I2C_FM_TIMING_LCNT(lcnt); + writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); + + writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); + writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, + master->regs + DEVICE_CTRL); + + return 0; +} + +static int dw_i3c_master_bus_init(struct i3c_master_controller *m) +{ + struct dw_i3c_master *master = to_dw_i3c_master(m); + struct i3c_bus *bus = i3c_master_get_bus(m); + struct i3c_device_info info = { }; + u32 thld_ctrl; + int ret; + + /* first broadcast to disable spike filter */ + master->first_broadcast = true; + + switch (bus->mode) { + case I3C_BUS_MODE_MIXED_FAST: + case I3C_BUS_MODE_MIXED_LIMITED: + ret = dw_i2c_clk_cfg(master); + if (ret) + return ret; + fallthrough; + case I3C_BUS_MODE_PURE: + ret = dw_i3c_clk_cfg(master); + if (ret) + return ret; + break; + default: + return -EINVAL; + } + + thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); + thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; + writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); + + thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL); + thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF; + writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); + + writel(INTR_ALL, master->regs + INTR_STATUS); + writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); + writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); + + ret = i3c_master_get_free_addr(m, 0); + if (ret < 0) + return ret; + + writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret), + master->regs + DEVICE_ADDR); + + memset(&info, 0, sizeof(info)); + info.dyn_addr = ret; + + ret = i3c_master_set_info(&master->base, &info); + if (ret) + return ret; + + writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT); + writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); + + /* For now don't support Hot-Join */ + writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, + master->regs + DEVICE_CTRL); + + dw_i3c_master_enable(master); + + return 0; +} + +static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m) +{ + struct dw_i3c_master *master = to_dw_i3c_master(m); + + dw_i3c_master_disable(master); +} + +static void dw_i3c_master_irq_handler(struct dw_i3c_master *master) +{ + u32 status, en; + + status = readl(master->regs + INTR_STATUS); + en = readl(master->regs + INTR_STATUS_EN); + + if (!(status & readl(master->regs + INTR_STATUS_EN))) { + pr_err("Failed to get completion status, status=%d, status_en=%d\n", status, en); + writel(INTR_ALL, master->regs + INTR_STATUS); + } + + spin_lock(&master->xferqueue.lock); + dw_i3c_master_end_xfer_locked(master, status); + + if (status & INTR_TRANSFER_ERR_STAT) + writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); + + /* set back to THIGH_MAX_NS, after disable spike filter */ + if (master->first_broadcast) { + master->first_broadcast = false; + int ret = dw_i3c_clk_cfg(master); + + if (ret) + pr_err("Failed to set clk cfg\n"); + } + + spin_unlock(&master->xferqueue.lock); +} + +static int dw_i3c_ccc_set(struct dw_i3c_master *master, + struct i3c_ccc_cmd *ccc) +{ + struct dw_i3c_xfer *xfer; + struct dw_i3c_cmd *cmd; + int ret, pos = 0; + + if (ccc->id & I3C_CCC_DIRECT) { + pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); + if (pos < 0) + return pos; + } + + xfer = dw_i3c_master_alloc_xfer(master, 1); + if (!xfer) + return -ENOMEM; + + cmd = xfer->cmds; + cmd->tx_buf = ccc->dests[0].payload.data; + cmd->tx_len = ccc->dests[0].payload.len; + + cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | + COMMAND_PORT_TRANSFER_ARG; + + cmd->cmd_lo = COMMAND_PORT_CP | + COMMAND_PORT_DEV_INDEX(pos) | + COMMAND_PORT_CMD(ccc->id) | + COMMAND_PORT_TOC | + COMMAND_PORT_ROC; + + dw_i3c_master_enqueue_xfer(master, xfer); + + if (dw_i3c_status_poll_timeout(master) > POLL_SUCCESS) + dw_i3c_master_dequeue_xfer(master, xfer); + else + dw_i3c_master_irq_handler(master); + + ret = xfer->ret; + + if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) + ccc->err = I3C_ERROR_M2; + + dw_i3c_master_free_xfer(xfer); + + return ret; +} + +static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) +{ + struct dw_i3c_xfer *xfer; + struct dw_i3c_cmd *cmd; + int ret, pos; + + pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); + if (pos < 0) + return pos; + + xfer = dw_i3c_master_alloc_xfer(master, 1); + if (!xfer) + return -ENOMEM; + + cmd = xfer->cmds; + cmd->rx_buf = ccc->dests[0].payload.data; + cmd->rx_len = ccc->dests[0].payload.len; + + cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | + COMMAND_PORT_TRANSFER_ARG; + + cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | + COMMAND_PORT_CP | + COMMAND_PORT_DEV_INDEX(pos) | + COMMAND_PORT_CMD(ccc->id) | + COMMAND_PORT_TOC | + COMMAND_PORT_ROC; + + dw_i3c_master_enqueue_xfer(master, xfer); + + if (dw_i3c_status_poll_timeout(master) > POLL_SUCCESS) + dw_i3c_master_dequeue_xfer(master, xfer); + else + dw_i3c_master_irq_handler(master); + + ret = xfer->ret; + + if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) + ccc->err = I3C_ERROR_M2; + dw_i3c_master_free_xfer(xfer); + + return ret; +} + +static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, + struct i3c_ccc_cmd *ccc) +{ + struct dw_i3c_master *master = to_dw_i3c_master(m); + int ret = 0; + + if (ccc->id == I3C_CCC_ENTDAA) + return -EINVAL; + + if (ccc->rnw) + ret = dw_i3c_ccc_get(master, ccc); + else + ret = dw_i3c_ccc_set(master, ccc); + + return ret; +} + +static int dw_i3c_master_daa(struct i3c_master_controller *m) +{ + struct dw_i3c_master *master = to_dw_i3c_master(m); + struct dw_i3c_xfer *xfer; + struct dw_i3c_cmd *cmd; + u32 olddevs, newdevs; + u8 p, last_addr = 0; + int ret, pos; + + olddevs = ~(master->free_pos); + + /* Prepare DAT before launching DAA. */ + for (pos = 0; pos < master->maxdevs; pos++) { + if (olddevs & BIT(pos)) + continue; + + ret = i3c_master_get_free_addr(m, last_addr + 1); + if (ret < 0) + return -ENOSPC; + + master->addrs[pos] = ret; + p = even_parity(ret); + last_addr = ret; + ret |= (p << 7); + + writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret), + master->regs + + DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); + } + + xfer = dw_i3c_master_alloc_xfer(master, 1); + if (!xfer) + return -ENOMEM; + + pos = dw_i3c_master_get_free_pos(master); + cmd = &xfer->cmds[0]; + cmd->cmd_hi = 0x1; + cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) | + COMMAND_PORT_DEV_INDEX(pos) | + COMMAND_PORT_CMD(I3C_CCC_ENTDAA) | + COMMAND_PORT_ADDR_ASSGN_CMD | + COMMAND_PORT_TOC | + COMMAND_PORT_ROC; + + dw_i3c_master_enqueue_xfer(master, xfer); + + if (dw_i3c_status_poll_timeout(master) > POLL_SUCCESS) + dw_i3c_master_dequeue_xfer(master, xfer); + else + dw_i3c_master_irq_handler(master); + + newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0); + newdevs &= ~olddevs; + + for (pos = 0; pos < master->maxdevs; pos++) { + if (newdevs & BIT(pos)) { + i3c_master_add_i3c_dev_locked(m, master->addrs[pos]); + master->i3cdev[pos] = m->this; + master->num_i3cdevs++; + } + } + + dw_i3c_master_free_xfer(xfer); + + return 0; +} + +static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev, + struct i3c_priv_xfer *i3c_xfers, + u32 i3c_nxfers) +{ + struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct dw_i3c_master *master = to_dw_i3c_master(m); + unsigned int nrxwords = 0, ntxwords = 0; + struct dw_i3c_xfer *xfer; + int i, ret = 0; + + if (!i3c_nxfers) + return 0; + + if (i3c_nxfers > master->caps.cmdfifodepth) + return -EOPNOTSUPP; + + for (i = 0; i < i3c_nxfers; i++) { + if (i3c_xfers[i].rnw) + nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); + else + ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); + } + + if (ntxwords > master->caps.datafifodepth || + nrxwords > master->caps.datafifodepth) + return -EOPNOTSUPP; + + xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers); + if (!xfer) + return -ENOMEM; + + for (i = 0; i < i3c_nxfers; i++) { + struct dw_i3c_cmd *cmd = &xfer->cmds[i]; + + cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) | + COMMAND_PORT_TRANSFER_ARG; + + if (i3c_xfers[i].rnw) { + cmd->rx_buf = i3c_xfers[i].data.in; + cmd->rx_len = i3c_xfers[i].len; + cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | + COMMAND_PORT_SPEED(dev->info.max_read_ds); + + } else { + cmd->tx_buf = i3c_xfers[i].data.out; + cmd->tx_len = i3c_xfers[i].len; + cmd->cmd_lo = + COMMAND_PORT_SPEED(dev->info.max_write_ds); + } + + cmd->cmd_lo |= COMMAND_PORT_TID(i) | + COMMAND_PORT_DEV_INDEX(data->index) | + COMMAND_PORT_ROC; + + if (i == (i3c_nxfers - 1)) + cmd->cmd_lo |= COMMAND_PORT_TOC; + } + + dw_i3c_master_enqueue_xfer(master, xfer); + + if (dw_i3c_status_poll_timeout(master) > POLL_SUCCESS) + dw_i3c_master_dequeue_xfer(master, xfer); + else + dw_i3c_master_irq_handler(master); + + ret = xfer->ret; + + dw_i3c_master_free_xfer(xfer); + + return ret; +} + +static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, + u8 old_dyn_addr) +{ + struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct dw_i3c_master *master = to_dw_i3c_master(m); + int pos; + + pos = dw_i3c_master_get_free_pos(master); + + if (data->index > pos && pos > 0) { + writel(0, + master->regs + + DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); + + master->addrs[data->index] = 0; + master->free_pos |= BIT(data->index); + + data->index = pos; + master->addrs[pos] = dev->info.dyn_addr; + master->free_pos &= ~BIT(pos); + } + + writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr), + master->regs + + DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); + + master->addrs[data->index] = dev->info.dyn_addr; + + return 0; +} + +static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) +{ + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct dw_i3c_master *master = to_dw_i3c_master(m); + struct dw_i3c_i2c_dev_data *data; + int pos; + + pos = dw_i3c_master_get_free_pos(master); + if (pos < 0) + return pos; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->index = pos; + master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr; + master->free_pos &= ~BIT(pos); + i3c_dev_set_master_data(dev, data); + + writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]), + master->regs + + DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); + + return 0; +} + +static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) +{ + struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); + struct i3c_master_controller *m = i3c_dev_get_master(dev); + struct dw_i3c_master *master = to_dw_i3c_master(m); + + writel(0, + master->regs + + DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); + + i3c_dev_set_master_data(dev, NULL); + master->addrs[data->index] = 0; + master->free_pos |= BIT(data->index); + kfree(data); +} + +static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, + const struct i2c_msg *i2c_xfers, + int i2c_nxfers) +{ + struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); + struct i3c_master_controller *m = i2c_dev_get_master(dev); + struct dw_i3c_master *master = to_dw_i3c_master(m); + unsigned int nrxwords = 0, ntxwords = 0; + struct dw_i3c_xfer *xfer; + int i, ret = 0; + + if (!i2c_nxfers) + return 0; + + if (i2c_nxfers > master->caps.cmdfifodepth) + return -EOPNOTSUPP; + + for (i = 0; i < i2c_nxfers; i++) { + if (i2c_xfers[i].flags & I2C_M_RD) + nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); + else + ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); + } + + if (ntxwords > master->caps.datafifodepth || + nrxwords > master->caps.datafifodepth) + return -EOPNOTSUPP; + + xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers); + if (!xfer) + return -ENOMEM; + + for (i = 0; i < i2c_nxfers; i++) { + struct dw_i3c_cmd *cmd = &xfer->cmds[i]; + + cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) | + COMMAND_PORT_TRANSFER_ARG; + + cmd->cmd_lo = COMMAND_PORT_TID(i) | + COMMAND_PORT_DEV_INDEX(data->index) | + COMMAND_PORT_ROC; + + if (i2c_xfers[i].flags & I2C_M_RD) { + cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER; + cmd->rx_buf = i2c_xfers[i].buf; + cmd->rx_len = i2c_xfers[i].len; + } else { + cmd->tx_buf = i2c_xfers[i].buf; + cmd->tx_len = i2c_xfers[i].len; + } + + if (i == (i2c_nxfers - 1)) + cmd->cmd_lo |= COMMAND_PORT_TOC; + } + + dw_i3c_master_enqueue_xfer(master, xfer); + + if (dw_i3c_status_poll_timeout(master) > POLL_SUCCESS) + dw_i3c_master_dequeue_xfer(master, xfer); + else + dw_i3c_master_irq_handler(master); + + ret = xfer->ret; + dw_i3c_master_free_xfer(xfer); + + return ret; +} + +static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) +{ + struct i3c_master_controller *m = i2c_dev_get_master(dev); + struct dw_i3c_master *master = to_dw_i3c_master(m); + struct dw_i3c_i2c_dev_data *data; + int pos; + + pos = dw_i3c_master_get_free_pos(master); + if (pos < 0) + return pos; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->index = pos; + master->addrs[pos] = dev->addr; + master->free_pos &= ~BIT(pos); + i2c_dev_set_master_data(dev, data); + + writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV | + DEV_ADDR_TABLE_STATIC_ADDR(dev->addr), + master->regs + + DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); + + return 0; +} + +static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) +{ + struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); + struct i3c_master_controller *m = i2c_dev_get_master(dev); + struct dw_i3c_master *master = to_dw_i3c_master(m); + + writel(0, + master->regs + + DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); + + i2c_dev_set_master_data(dev, NULL); + master->addrs[data->index] = 0; + master->free_pos |= BIT(data->index); + kfree(data); +} + +static const struct i3c_master_controller_ops dw_mipi_i3c_ops = { + .bus_init = dw_i3c_master_bus_init, + .bus_cleanup = dw_i3c_master_bus_cleanup, + .attach_i3c_dev = dw_i3c_master_attach_i3c_dev, + .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev, + .detach_i3c_dev = dw_i3c_master_detach_i3c_dev, + .do_daa = dw_i3c_master_daa, + .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd, + .send_ccc_cmd = dw_i3c_master_send_ccc_cmd, + .priv_xfers = dw_i3c_master_priv_xfers, + .attach_i2c_dev = dw_i3c_master_attach_i2c_dev, + .detach_i2c_dev = dw_i3c_master_detach_i2c_dev, + .i2c_xfers = dw_i3c_master_i2c_xfers, +}; + +static int dw_i3c_probe(struct udevice *dev) +{ + struct dw_i3c_master *master = dev_get_priv(dev); + int ret; + + if (!master->regs) + master->regs = dev_read_addr_ptr(dev); + + ret = clk_get_by_index(dev, 0, &master->core_clk); + if (ret) { + dev_err(dev, "Can't get clock: %d\n", ret); + return ret; + } + + ret = reset_get_bulk(dev, &master->resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return ret; + } + + reset_deassert_bulk(&master->resets); + + spin_lock_init(&master->xferqueue.lock); + INIT_LIST_HEAD(&master->xferqueue.list); + + writel(INTR_ALL, master->regs + INTR_STATUS); + + /* Information regarding the FIFOs/QUEUEs depth */ + ret = readl(master->regs + QUEUE_STATUS_LEVEL); + master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret); + + ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL); + master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret); + + ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER); + master->datstartaddr = ret; + master->maxdevs = ret >> 16; + master->free_pos = GENMASK(master->maxdevs - 1, 0); + + ret = i3c_master_register(&master->base, dev, + &dw_mipi_i3c_ops, false); + if (ret) + goto err_assert_rst; + + return 0; + +err_assert_rst: + reset_assert_bulk(&master->resets); + + return ret; +} + +static int dw_i3c_master_priv_read(struct udevice *dev, u32 dev_number, + u8 *buf, u32 buf_size) +{ + struct dw_i3c_master *master = dev_get_priv(dev); + struct i3c_dev_desc *i3cdev = master->i3cdev[dev_number]; + struct i3c_priv_xfer i3c_xfers; + + i3c_xfers.data.in = buf; + i3c_xfers.len = buf_size; + i3c_xfers.rnw = I3C_MSG_READ; + + return dw_i3c_master_priv_xfers(i3cdev, &i3c_xfers, 1); +} + +static int dw_i3c_master_priv_write(struct udevice *dev, u32 dev_number, + u8 *buf, u32 buf_size) +{ + struct dw_i3c_master *master = dev_get_priv(dev); + struct i3c_dev_desc *i3cdev = master->i3cdev[dev_number]; + struct i3c_priv_xfer i3c_xfers; + + i3c_xfers.data.out = buf; + i3c_xfers.len = buf_size; + i3c_xfers.rnw = I3C_MSG_WRITE; + + return dw_i3c_master_priv_xfers(i3cdev, &i3c_xfers, 1); +} + +static const struct dm_i3c_ops dw_i3c_ops = { + .i3c_xfers = dw_i3c_master_priv_xfers, + .read = dw_i3c_master_priv_read, + .write = dw_i3c_master_priv_write, +}; + +static const struct udevice_id dw_i3c_ids[] = { + { .compatible = "snps,dw-i3c-master-1.00a" }, + { } +}; + +U_BOOT_DRIVER(dw_i3c_driver) = { + .name = "dw-i3c-master", + .id = UCLASS_I3C, + .of_match = dw_i3c_ids, + .probe = dw_i3c_probe, + .priv_auto = sizeof(struct dw_i3c_master), + .ops = &dw_i3c_ops, +}; diff --git a/drivers/i3c/sandbox_i3c.c b/drivers/i3c/sandbox_i3c.c new file mode 100644 index 00000000000..e452e982566 --- /dev/null +++ b/drivers/i3c/sandbox_i3c.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <dm.h> +#include <errno.h> +#include <i3c.h> +#include <linux/i3c/master.h> + +struct sandbox_i3c_priv { + struct i3c_priv_xfer i3c_xfers; +}; + +static int sandbox_i3c_priv_read(struct udevice *dev, u32 dev_number, + u8 *buf, u32 buf_size) +{ + struct sandbox_i3c_priv *priv = dev_get_priv(dev); + struct i3c_priv_xfer i3c_xfers; + + i3c_xfers = priv->i3c_xfers; + i3c_xfers.data.in = buf; + i3c_xfers.len = buf_size; + + return 0; +} + +static int sandbox_i3c_priv_write(struct udevice *dev, u32 dev_number, + u8 *buf, u32 buf_size) +{ + struct sandbox_i3c_priv *priv = dev_get_priv(dev); + struct i3c_priv_xfer i3c_xfers; + + i3c_xfers = priv->i3c_xfers; + i3c_xfers.data.out = buf; + i3c_xfers.len = buf_size; + + return 0; +} + +static const struct dm_i3c_ops sandbox_i3c_ops = { + .read = sandbox_i3c_priv_read, + .write = sandbox_i3c_priv_write, +}; + +static const struct udevice_id sandbox_i3c_ids[] = { + { .compatible = "sandbox,i3c" }, + { } +}; + +U_BOOT_DRIVER(i3c_sandbox) = { + .name = "i3c_sandbox", + .id = UCLASS_I3C, + .of_match = sandbox_i3c_ids, + .ops = &sandbox_i3c_ops, +}; diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 4d9f004ebad..f9531c1627c 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -28,6 +28,13 @@ config IMX_MU_MBOX Enable support for i.MX Messaging Unit for communication with other processors on the SoC using mailbox interface +config MPFS_MBOX + bool "Enable MPFS system controller support" + depends on DM_MAILBOX && ARCH_RV64I + help + Enable support for the mailboxes that provide a communication + channel with the system controller integrated on PolarFire SoC. + config SANDBOX_MBOX bool "Enable the sandbox mailbox test driver" depends on DM_MAILBOX && SANDBOX diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index e8c745f7d79..b54fbdfff15 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_$(PHASE_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o +obj-$(CONFIG_MPFS_MBOX) += mpfs-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o diff --git a/drivers/mailbox/mpfs-mbox.c b/drivers/mailbox/mpfs-mbox.c new file mode 100644 index 00000000000..55238847ecd --- /dev/null +++ b/drivers/mailbox/mpfs-mbox.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip's PolarFire SoC (MPFS) Mailbox Driver + * + * Copyright (C) 2024 Microchip Technology Inc. All rights reserved. + * + * Author: Jamie Gibbons <jamie.gibbons@microchip.com> + * + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/ofnode.h> +#include <linux/bitops.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <log.h> +#include <mailbox-uclass.h> +#include <malloc.h> +#include <mpfs-mailbox.h> + +#define SERVICES_CR_OFFSET 0x50u +#define SERVICES_SR_OFFSET 0x54u + +#define SERVICE_CR_REQ_MASK 0x1u +#define SERVICE_SR_BUSY_MASK 0x2u +#define SERVICE_SR_STATUS_SHIFT 16 +#define SERVICE_CR_COMMAND_SHIFT 16 +#define MASK_8BIT 0xFF + +struct mpfs_mbox { + struct udevice *dev; + void __iomem *ctrl_base; + void __iomem *mbox_base; + struct mbox_chan *chan; +}; + +static bool mpfs_mbox_busy(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = dev_get_priv(chan->dev); + uint16_t status; + + status = readl(mbox->ctrl_base + SERVICES_SR_OFFSET); + + return status & SERVICE_SR_BUSY_MASK; +} + +static int mpfs_mbox_send(struct mbox_chan *chan, const void *data) +{ + struct mpfs_mbox *mbox = dev_get_priv(chan->dev); + struct mpfs_mss_msg *msg = (struct mpfs_mss_msg *)data; + u32 mailbox_val, cmd_shifted, value; + u8 *byte_buf; + u8 idx, byte_idx, byte_offset; + + u32 *word_buf = (u32 *)msg->cmd_data; + + if (mpfs_mbox_busy(chan)) + return -EBUSY; + + for (idx = 0; idx < (msg->cmd_data_size / BYTES_4); idx++) + writel(word_buf[idx], mbox->mbox_base + msg->mbox_offset + idx * BYTES_4); + + if ((msg->cmd_data_size % BYTES_4) > 0) { + byte_offset = (msg->cmd_data_size / BYTES_4) * BYTES_4; + byte_buf = (u8 *)(msg->cmd_data + byte_offset); + mailbox_val = readl(mbox->mbox_base + msg->mbox_offset + idx * BYTES_4); + + for (byte_idx = 0; byte_idx < (msg->cmd_data_size % BYTES_4); byte_idx++) { + mailbox_val &= ~(MASK_8BIT << (byte_idx * 0x8u)); + mailbox_val |= (u32)byte_buf[byte_idx] << (byte_idx * 0x8u); + } + writel(mailbox_val, mbox->mbox_base + msg->mbox_offset + idx * BYTES_4); + } + + cmd_shifted = msg->cmd_opcode << SERVICE_CR_COMMAND_SHIFT; + cmd_shifted |= SERVICE_CR_REQ_MASK; + writel(cmd_shifted, mbox->ctrl_base + SERVICES_CR_OFFSET); + + do { + value = readl(mbox->ctrl_base + SERVICES_CR_OFFSET); + } while (SERVICE_CR_REQ_MASK == (value & SERVICE_CR_REQ_MASK)); + + do { + value = readl(mbox->ctrl_base + SERVICES_SR_OFFSET); + } while (SERVICE_SR_BUSY_MASK == (value & SERVICE_SR_BUSY_MASK)); + + msg->response->resp_status = (value >> SERVICE_SR_STATUS_SHIFT); + if (msg->response->resp_status) + return -EBADMSG; + + return 0; +} + +static int mpfs_mbox_recv(struct mbox_chan *chan, void *data) +{ + struct mpfs_mbox *mbox = dev_get_priv(chan->dev); + struct mpfs_mss_msg *msg = data; + struct mpfs_mss_response *response = msg->response; + u8 idx; + + if (!response->resp_msg) { + dev_err(chan->dev, "failed to assign memory for response %d\n", -ENOMEM); + return -EINVAL; + } + + if (mpfs_mbox_busy(chan)) { + dev_err(chan->dev, "mailbox is busy\n"); + response->resp_status = 0xDEAD; + return -EINVAL; + } + + for (idx = 0; idx < response->resp_size; idx++) + *((u8 *)(response->resp_msg) + idx) = readb(mbox->mbox_base + msg->resp_offset + idx); + + return 0; +} + +static const struct mbox_ops mpfs_mbox_ops = { + .send = mpfs_mbox_send, + .recv = mpfs_mbox_recv, +}; + +static int mpfs_mbox_probe(struct udevice *dev) +{ + struct mpfs_mbox *mbox; + struct resource regs; + ofnode node; + int ret; + + node = dev_ofnode(dev); + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + ret = ofnode_read_resource(node, 0, ®s); + if (ret) { + dev_err(dev, "No reg property for controller base\n"); + return ret; + }; + + mbox->ctrl_base = devm_ioremap(dev, regs.start, regs.start - regs.end); + + ret = ofnode_read_resource(node, 2, ®s); + if (ret) { + dev_err(dev, "No reg property for mailbox base\n"); + return ret; + }; + + mbox->mbox_base = devm_ioremap(dev, regs.start, regs.start - regs.end); + + mbox->dev = dev; + dev_set_priv(dev, mbox); + mbox->chan->con_priv = mbox; + + return 0; +} + +static const struct udevice_id mpfs_mbox_ids[] = { + {.compatible = "microchip,mpfs-mailbox"}, + { } +}; + +U_BOOT_DRIVER(mpfs_mbox) = { + .name = "mpfs-mbox", + .id = UCLASS_MAILBOX, + .of_match = mpfs_mbox_ids, + .probe = mpfs_mbox_probe, + .priv_auto = sizeof(struct mpfs_mbox), + .ops = &mpfs_mbox_ops, +}; diff --git a/drivers/mailbox/zynqmp-ipi.c b/drivers/mailbox/zynqmp-ipi.c index 851aa737c03..f62277385fb 100644 --- a/drivers/mailbox/zynqmp-ipi.c +++ b/drivers/mailbox/zynqmp-ipi.c @@ -188,7 +188,7 @@ static int zynqmp_ipi_dest_probe(struct udevice *dev) return -EINVAL; }; zynqmp->local_req_regs = devm_ioremap(dev, res.start, - (res.start - res.end)); + resource_size(&res)); if (!zynqmp->local_req_regs) return -EINVAL; @@ -197,7 +197,7 @@ static int zynqmp_ipi_dest_probe(struct udevice *dev) return -EINVAL; }; zynqmp->local_res_regs = devm_ioremap(dev, res.start, - (res.start - res.end)); + resource_size(&res)); if (!zynqmp->local_res_regs) return -EINVAL; @@ -206,7 +206,7 @@ static int zynqmp_ipi_dest_probe(struct udevice *dev) return -EINVAL; }; zynqmp->remote_req_regs = devm_ioremap(dev, res.start, - (res.start - res.end)); + resource_size(&res)); if (!zynqmp->remote_req_regs) return -EINVAL; @@ -215,7 +215,7 @@ static int zynqmp_ipi_dest_probe(struct udevice *dev) return -EINVAL; }; zynqmp->remote_res_regs = devm_ioremap(dev, res.start, - (res.start - res.end)); + resource_size(&res)); if (!zynqmp->remote_res_regs) return -EINVAL; diff --git a/drivers/mfd/atmel-smc.c b/drivers/mfd/atmel-smc.c index 15296f71a16..94e5e7b67a0 100644 --- a/drivers/mfd/atmel-smc.c +++ b/drivers/mfd/atmel-smc.c @@ -347,7 +347,7 @@ const struct atmel_hsmc_reg_layout * atmel_hsmc_get_reg_layout(ofnode np) { int i; - const struct udevice_id *match; + const struct udevice_id *match = NULL; const char *name; int len; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0f753b9dbb9..29b84430ff5 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -658,6 +658,15 @@ config MICROCHIP_FLEXCOM Only one function can be used at a time and is chosen at boot time according to the device tree. +config MPFS_SYSCONTROLLER + bool "Enable Microchip PolarFire SoC (MPFS) System Services support" + depends on MISC + depends on MPFS_MBOX + help + This driver adds support for the PolarFire SoC (MPFS) system controller. + + If unsure, say N. + config K3_AVS0 depends on ARCH_K3 && SPL_DM_REGULATOR bool "AVS class 0 support for K3 devices" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f7422c8e95a..dc5eb3af19c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o +obj-$(CONFIG_MPFS_SYSCONTROLLER) += mpfs_syscontroller.o obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_K3_BIST) += k3_bist.o diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index a40c8badf9a..8985ab6584d 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -1282,8 +1282,7 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data) printf("%s, id:0x%x, access:%x, res:%d\n", __func__, id, access, RPC_R8(&msg)); - if (data) - *data = RPC_U32(&msg, 0U); + *data = RPC_U32(&msg, 0U); return ret; } diff --git a/drivers/misc/mpfs_syscontroller.c b/drivers/misc/mpfs_syscontroller.c new file mode 100644 index 00000000000..41e80815ab5 --- /dev/null +++ b/drivers/misc/mpfs_syscontroller.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Microchip's PolarFire SoC (MPFS) System Controller Driver + * + * Copyright (C) 2024 Microchip Technology Inc. All rights reserved. + * + * Author: Jamie Gibbons <jamie.gibbons@microchip.com> + * + */ + +#include <asm/system.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <env.h> +#include <errno.h> +#include <linux/compat.h> +#include <linux/completion.h> +#include <linux/err.h> +#include <linux/mtd/mtd.h> +#include <log.h> +#include <mailbox.h> +#include <misc.h> +#include <mpfs-mailbox.h> + +/* Descriptor table */ +#define CMD_OPCODE 0x0u +#define CMD_DATA_SIZE 0U +#define CMD_DATA NULL +#define MBOX_OFFSET 0x0 +#define RESP_OFFSET 0x0 +#define RESP_BYTES 16U + +/** + * struct mpfs_syscontroller_priv - Structure representing System Controller data. + * @chan: Mailbox channel + * @c: Completion signal + */ +struct mpfs_syscontroller_priv { + struct mbox_chan chan; + struct completion c; +}; + +/** + * mpfs_syscontroller_run_service() - Run the MPFS system service + * @sys_controller: corresponding MPFS system service device + * @msg: Message to send + * + * Return: 0 if all goes good, else appropriate error message. + */ +int mpfs_syscontroller_run_service(struct mpfs_syscontroller_priv *sys_controller, struct mpfs_mss_msg *msg) +{ + int ret; + + reinit_completion(&sys_controller->c); + + /* Run the System Service Request */ + ret = mbox_send(&sys_controller->chan, msg); + if (ret < 0) + dev_warn(sys_controller->chan.dev, "MPFS sys controller service timeout\n"); + + debug("%s: Service successful %s\n", + __func__, sys_controller->chan.dev->name); + + return ret; +} +EXPORT_SYMBOL_GPL(mpfs_syscontroller_run_service); + +/** + * mpfs_syscontroller_read_sernum() - Use system service to read the device serial number + * @sys_serv_priv: system service private data + * @device_serial_number: device serial number + * + * Return: 0 if all went ok, else return appropriate error + */ +int mpfs_syscontroller_read_sernum(struct mpfs_sys_serv *sys_serv_priv, u8 *device_serial_number) +{ + unsigned long timeoutsecs = 300; + int ret; + + struct mpfs_mss_response response = { + .resp_status = 0U, + .resp_msg = (u32 *)device_serial_number, + .resp_size = RESP_BYTES}; + struct mpfs_mss_msg msg = { + .cmd_opcode = CMD_OPCODE, + .cmd_data_size = CMD_DATA_SIZE, + .response = &response, + .cmd_data = CMD_DATA, + .mbox_offset = MBOX_OFFSET, + .resp_offset = RESP_OFFSET}; + + ret = mpfs_syscontroller_run_service(sys_serv_priv->sys_controller, &msg); + if (ret) { + dev_err(sys_serv_priv->sys_controller->chan.dev, "Service failed: %d, abort\n", ret); + return ret; + } + + /* Receive the response */ + ret = mbox_recv(&sys_serv_priv->sys_controller->chan, &msg, timeoutsecs); + if (ret) { + dev_err(sys_serv_priv->sys_controller->chan.dev, "Service failed: %d, abort. Failure: %u\n", ret, msg.response->resp_status); + return ret; + } + + debug("%s: Read successful %s\n", + __func__, sys_serv_priv->sys_controller->chan.dev->name); + + return 0; +} +EXPORT_SYMBOL(mpfs_syscontroller_read_sernum); + +static int mpfs_syscontroller_probe(struct udevice *dev) +{ + struct mpfs_syscontroller_priv *sys_controller = dev_get_priv(dev); + int ret; + + ret = mbox_get_by_index(dev, 0, &sys_controller->chan); + if (ret) { + dev_err(dev, "%s: Acquiring mailbox channel failed. ret = %d\n", + __func__, ret); + return ret; + } + + init_completion(&sys_controller->c); + dev_info(dev, "Registered MPFS system controller\n"); + + return 0; +} + +static const struct udevice_id mpfs_syscontroller_ids[] = { + { .compatible = "microchip,mpfs-sys-controller" }, + { } +}; + +struct mpfs_syscontroller_priv *mpfs_syscontroller_get(struct udevice *dev) +{ + struct mpfs_syscontroller_priv *sys_controller; + + sys_controller = dev_get_priv(dev); + if (!sys_controller) { + debug("%s: MPFS system controller found but could not register as a sub device %p\n", + __func__, sys_controller); + return ERR_PTR(-EPROBE_DEFER); + } + + return sys_controller; +} +EXPORT_SYMBOL(mpfs_syscontroller_get); + +U_BOOT_DRIVER(mpfs_syscontroller) = { + .name = "mpfs_syscontroller", + .id = UCLASS_MISC, + .of_match = mpfs_syscontroller_ids, + .probe = mpfs_syscontroller_probe, + .priv_auto = sizeof(struct mpfs_syscontroller_priv), +}; diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 6a531fa0961..838b4f4a65a 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -206,10 +206,9 @@ static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags) goto io_fail; } while (!(status & MMCI_BIT(RXRDY))); - if (status & MMCI_BIT(RXRDY)) { - *data = readl(&mci->rdr); - status = 0; - } + *data = readl(&mci->rdr); + status = 0; + io_fail: return status; } @@ -225,10 +224,9 @@ static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags) goto io_fail; } while (!(status & MMCI_BIT(TXRDY))); - if (status & MMCI_BIT(TXRDY)) { - writel(*data, &mci->tdr); - status = 0; - } + writel(*data, &mci->tdr); + status = 0; + io_fail: return status; } @@ -265,13 +263,15 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) /* Figure out the transfer arguments */ cmdr = mci_encode_cmd(cmd, data, &error_flags); - mci_set_blklen(mci, data->blocksize); + if (data) { + mci_set_blklen(mci, data->blocksize); - /* For multi blocks read/write, set the block register */ - if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) - || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) - writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize), - &mci->blkr); + /* For multi blocks read/write, set the block register */ + if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK || + cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK) + writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize), + &mci->blkr); + } /* Send the command */ writel(cmd->cmdarg, &mci->argr); diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index 761e3619329..5e025d76a82 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -500,7 +500,7 @@ static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) { struct rockchip_sdhc *priv = dev_get_priv(mmc->dev); struct sdhci_host *host = &priv->host; - char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + s8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; struct mmc_cmd cmd; u32 ctrl, blk_size; int ret; diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 9483fb57daf..122690aef3e 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -385,15 +385,29 @@ static int stm32_sdmmc2_end_data(struct udevice *dev, u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT | SDMMC_STA_IDMATE | SDMMC_STA_DATAEND; u32 status; + unsigned long timeout_msecs = ctx->data_length >> 8; + unsigned long start_timeout; + + /* At least, a timeout of 2 seconds is set */ + if (timeout_msecs < 2000) + timeout_msecs = 2000; if (data->flags & MMC_DATA_READ) mask |= SDMMC_STA_RXOVERR; else mask |= SDMMC_STA_TXUNDERR; + start_timeout = get_timer(0); status = readl(plat->base + SDMMC_STA); - while (!(status & mask)) + while (!(status & mask)) { + if (get_timer(start_timeout) > timeout_msecs) { + ctx->dpsm_abort = true; + return -ETIMEDOUT; + } + + schedule(); status = readl(plat->base + SDMMC_STA); + } /* * Need invalidate the dcache again to avoid any diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 2b7f5e5ed7b..e76601a5545 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -202,7 +202,7 @@ config RENESAS_RPC_HF config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" - depends on MULTIPLEXER && MUX_MMIO + depends on MULTIPLEXER && (MUX_MMIO || SPL_MUX_MMIO) help This is the driver for HyperBus controller on TI's AM65x and other SoCs diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c index 472ad0bdefb..01ff6e3befa 100644 --- a/drivers/mtd/nand/core.c +++ b/drivers/mtd/nand/core.c @@ -201,8 +201,8 @@ EXPORT_SYMBOL_GPL(nanddev_mtd_erase); int nanddev_init(struct nand_device *nand, const struct nand_ops *ops, struct module *owner) { - struct mtd_info *mtd = nanddev_to_mtd(nand); - struct nand_memory_organization *memorg = nanddev_get_memorg(nand); + struct mtd_info *mtd; + struct nand_memory_organization *memorg; if (!nand || !ops) return -EINVAL; @@ -210,6 +210,9 @@ int nanddev_init(struct nand_device *nand, const struct nand_ops *ops, if (!ops->erase || !ops->markbad || !ops->isbad) return -EINVAL; + mtd = nanddev_to_mtd(nand); + memorg = nanddev_get_memorg(nand); + if (!memorg->bits_per_cell || !memorg->pagesize || !memorg->pages_per_eraseblock || !memorg->eraseblocks_per_lun || !memorg->planes_per_lun || !memorg->luns_per_target || diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index adb271dfb8f..9c8a32bb0a8 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -261,11 +261,6 @@ config NAND_LPC32XX_MLC help Enable the LPC32XX MLC NAND controller. -config NAND_LPC32XX_SLC - bool "Support LPC32XX_SLC controller" - help - Enable the LPC32XX SLC NAND controller. - config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 @@ -556,12 +551,6 @@ config NAND_MXS_USE_MINIMUM_ECC endif -config NAND_MXIC - bool "Macronix raw NAND controller" - select SYS_NAND_SELF_INIT - help - This selects the Macronix raw NAND controller driver. - config NAND_ZYNQ bool "Support for Zynq Nand controller" select SPL_SYS_NAND_SELF_INIT @@ -579,22 +568,6 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS This flag prevent U-Boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. -config NAND_OCTEONTX - bool "Support for OcteonTX NAND controller" - select SYS_NAND_SELF_INIT - imply CMD_NAND - help - This enables Nand flash controller hardware found on the OcteonTX - processors. - -config NAND_OCTEONTX_HW_ECC - bool "Support Hardware ECC for OcteonTX NAND controller" - depends on NAND_OCTEONTX - default y - help - This enables Hardware BCH engine found on the OcteonTX processors to - support ECC for NAND flash controller. - config NAND_STM32_FMC2 bool "Support for NAND controller on STM32MP SoCs" depends on ARCH_STM32MP @@ -684,7 +657,7 @@ config SYS_NAND_ONFI_DETECTION config SYS_NAND_PAGE_SIZE hex "NAND chip page size" - depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ + depends on ARCH_SUNXI || NAND_OMAP_GPMC || \ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ MVEBU_SPL_BOOT_DEVICE_NAND || \ (NAND_ATMEL && SPL_NAND_SUPPORT) || \ @@ -696,7 +669,7 @@ config SYS_NAND_PAGE_SIZE config SYS_NAND_OOBSIZE hex "NAND chip OOB size" - depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ + depends on ARCH_SUNXI || NAND_OMAP_GPMC || \ SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \ (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 34cba77046a..76546a6287b 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -61,21 +61,17 @@ obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o -obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MESON) += meson_nand.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o obj-$(CONFIG_NAND_MXS) += mxs_nand.o obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o -obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o -obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_SANDBOX) += sand_nand.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o -obj-$(CONFIG_NAND_MXIC) += mxic_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o diff --git a/drivers/mtd/nand/raw/cadence_nand.c b/drivers/mtd/nand/raw/cadence_nand.c index 27aa7f97a45..4771440d1de 100644 --- a/drivers/mtd/nand/raw/cadence_nand.c +++ b/drivers/mtd/nand/raw/cadence_nand.c @@ -2196,7 +2196,7 @@ static int cadence_nand_chip_init(struct cadence_nand_info *cadence, ofnode node chip->controller = &cadence->controller; nand_set_flash_node(chip, node); mtd = nand_to_mtd(chip); - mtd->dev->parent = cadence->dev; + mtd->dev = cadence->dev; chip->options |= NAND_BUSWIDTH_AUTO; chip->select_chip = cadence_nand_select_chip; diff --git a/drivers/mtd/nand/raw/cortina_nand.c b/drivers/mtd/nand/raw/cortina_nand.c index 06918a46e93..a27a6994f56 100644 --- a/drivers/mtd/nand/raw/cortina_nand.c +++ b/drivers/mtd/nand/raw/cortina_nand.c @@ -186,14 +186,13 @@ int init_nand_dma(struct nand_chip *nand) info->tx_desc = malloc_cache_aligned((sizeof(struct tx_descriptor_t) * CA_DMA_DESC_NUM)); - info->rx_desc = malloc_cache_aligned((sizeof(struct rx_descriptor_t) * - CA_DMA_DESC_NUM)); - - if (!info->rx_desc && info->tx_desc) { + if (!info->tx_desc) { printf("Fail to alloc DMA descript!\n"); - kfree(info->tx_desc); return -ENOMEM; - } else if (info->rx_desc && !info->tx_desc) { + } + info->rx_desc = malloc_cache_aligned((sizeof(struct rx_descriptor_t) * + CA_DMA_DESC_NUM)); + if (!info->rx_desc) { printf("Fail to alloc DMA descript!\n"); kfree(info->tx_desc); return -ENOMEM; diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index b2401116689..39cb641e0b3 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -173,13 +173,9 @@ static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, time_left--; } - if (!time_left) { - dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", - irq_mask); - return 0; - } - - return denali->irq_status; + dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", + irq_mask); + return 0; } static uint32_t denali_check_irq(struct denali_nand_info *denali) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c deleted file mode 100644 index 109c31fb4d1..00000000000 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ /dev/null @@ -1,587 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * LPC32xx SLC NAND flash controller driver - * - * (C) Copyright 2015-2018 Vladimir Zapolskiy <vz@mleia.com> - * Copyright (c) 2015 Tyco Fire Protection Products. - * - * Hardware ECC support original source code - * Copyright (C) 2008 by NXP Semiconductors - * Author: Kevin Wells - */ - -#include <config.h> -#include <log.h> -#include <nand.h> -#include <linux/bug.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/rawnand.h> -#include <linux/errno.h> -#include <asm/io.h> -#include <asm/arch/config.h> -#include <asm/arch/clk.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/dma.h> -#include <asm/arch/cpu.h> -#include <linux/printk.h> - -struct lpc32xx_nand_slc_regs { - u32 data; - u32 addr; - u32 cmd; - u32 stop; - u32 ctrl; - u32 cfg; - u32 stat; - u32 int_stat; - u32 ien; - u32 isr; - u32 icr; - u32 tac; - u32 tc; - u32 ecc; - u32 dma_data; -}; - -/* CFG register */ -#define CFG_CE_LOW (1 << 5) -#define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */ -#define CFG_ECC_EN (1 << 3) /* ECC enable bit */ -#define CFG_DMA_BURST (1 << 2) /* DMA burst bit */ -#define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */ - -/* CTRL register */ -#define CTRL_SW_RESET (1 << 2) -#define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */ -#define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */ - -/* STAT register */ -#define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */ -#define STAT_NAND_READY (1 << 0) - -/* INT_STAT register */ -#define INT_STAT_TC (1 << 1) -#define INT_STAT_RDY (1 << 0) - -/* TAC register bits, be aware of overflows */ -#define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28) -#define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24) -#define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20) -#define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16) -#define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12) -#define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8) -#define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4) -#define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0) - -/* NAND ECC Layout for small page NAND devices - * Note: For large page devices, the default layouts are used. */ -static struct nand_ecclayout lpc32xx_nand_oob_16 = { - .eccbytes = 6, - .eccpos = { 10, 11, 12, 13, 14, 15, }, - .oobfree = { - { .offset = 0, .length = 4, }, - { .offset = 6, .length = 4, }, - } -}; - -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) -#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE) - -/* - * DMA Descriptors - * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area) - * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area) - */ -static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1]; -static u32 ecc_buffer[8]; /* MAX ECC size */ -static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */ - -/* - * Helper macro for the DMA client (i.e. NAND SLC): - * - to write the next DMA linked list item address - * (see arch/include/asm/arch-lpc32xx/dma.h). - * - to assign the DMA data register to DMA source or destination address. - * - to assign the ECC register to DMA source or destination address. - */ -#define lpc32xx_dmac_next_lli(x) ((u32)x) -#define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data) -#define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc) -#endif - -static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs - = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE; - -static void lpc32xx_nand_init(void) -{ - uint32_t hclk = get_hclk_clk_rate(); - - /* Reset SLC NAND controller */ - writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl); - - /* 8-bit bus, no DMA, no ECC, ordinary CE signal */ - writel(0, &lpc32xx_nand_slc_regs->cfg); - - /* Interrupts disabled and cleared */ - writel(0, &lpc32xx_nand_slc_regs->ien); - writel(INT_STAT_TC | INT_STAT_RDY, - &lpc32xx_nand_slc_regs->icr); - - /* Configure NAND flash timings */ - writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | - TAC_W_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_WWIDTH) | - TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | - TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) | - TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | - TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | - TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | - TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP), - &lpc32xx_nand_slc_regs->tac); -} - -static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, - int cmd, unsigned int ctrl) -{ - debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd); - - if (ctrl & NAND_NCE) - setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW); - else - clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW); - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd); - else if (ctrl & NAND_ALE) - writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr); -} - -static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) -{ - return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY; -} - -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) -/* - * Prepares DMA descriptors for NAND RD/WR operations - * If the size is < 256 Bytes then it is assumed to be - * an OOB transfer - */ -static void lpc32xx_nand_dma_configure(struct nand_chip *chip, - const u8 *buffer, int size, - int read) -{ - u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst; - struct lpc32xx_dmac_ll *dmalist_cur; - struct lpc32xx_dmac_ll *dmalist_cur_ecc; - - /* - * CTRL descriptor entry for reading ECC - * Copy Multiple times to sync DMA with Flash Controller - */ - ecc_ctrl = 0x5 | - DMAC_CHAN_SRC_BURST_1 | - DMAC_CHAN_DEST_BURST_1 | - DMAC_CHAN_SRC_WIDTH_32 | - DMAC_CHAN_DEST_WIDTH_32 | - DMAC_CHAN_DEST_AHB1; - - /* CTRL descriptor entry for reading/writing Data */ - ctrl = (CFG_SYS_NAND_ECCSIZE / 4) | - DMAC_CHAN_SRC_BURST_4 | - DMAC_CHAN_DEST_BURST_4 | - DMAC_CHAN_SRC_WIDTH_32 | - DMAC_CHAN_DEST_WIDTH_32 | - DMAC_CHAN_DEST_AHB1; - - /* CTRL descriptor entry for reading/writing Spare Area */ - oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) | - DMAC_CHAN_SRC_BURST_4 | - DMAC_CHAN_DEST_BURST_4 | - DMAC_CHAN_SRC_WIDTH_32 | - DMAC_CHAN_DEST_WIDTH_32 | - DMAC_CHAN_DEST_AHB1; - - if (read) { - dmasrc = lpc32xx_dmac_set_dma_data(); - dmadst = (u32)buffer; - ctrl |= DMAC_CHAN_DEST_AUTOINC; - } else { - dmadst = lpc32xx_dmac_set_dma_data(); - dmasrc = (u32)buffer; - ctrl |= DMAC_CHAN_SRC_AUTOINC; - } - - /* - * Write Operation Sequence for Small Block NAND - * ---------------------------------------------------------- - * 1. X'fer 256 bytes of data from Memory to Flash. - * 2. Copy generated ECC data from Register to Spare Area - * 3. X'fer next 256 bytes of data from Memory to Flash. - * 4. Copy generated ECC data from Register to Spare Area. - * 5. X'fer 16 byets of Spare area from Memory to Flash. - * Read Operation Sequence for Small Block NAND - * ---------------------------------------------------------- - * 1. X'fer 256 bytes of data from Flash to Memory. - * 2. Copy generated ECC data from Register to ECC calc Buffer. - * 3. X'fer next 256 bytes of data from Flash to Memory. - * 4. Copy generated ECC data from Register to ECC calc Buffer. - * 5. X'fer 16 bytes of Spare area from Flash to Memory. - * Write Operation Sequence for Large Block NAND - * ---------------------------------------------------------- - * 1. Steps(1-4) of Write Operations repeate for four times - * which generates 16 DMA descriptors to X'fer 2048 bytes of - * data & 32 bytes of ECC data. - * 2. X'fer 64 bytes of Spare area from Memory to Flash. - * Read Operation Sequence for Large Block NAND - * ---------------------------------------------------------- - * 1. Steps(1-4) of Read Operations repeate for four times - * which generates 16 DMA descriptors to X'fer 2048 bytes of - * data & 32 bytes of ECC data. - * 2. X'fer 64 bytes of Spare area from Flash to Memory. - */ - - for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) { - dmalist_cur = &dmalist[i * 2]; - dmalist_cur_ecc = &dmalist[(i * 2) + 1]; - - dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256))); - dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst); - dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc); - dmalist_cur->next_ctrl = ctrl; - - dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc(); - dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i]; - dmalist_cur_ecc->next_lli = - lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]); - dmalist_cur_ecc->next_ctrl = ecc_ctrl; - } - - if (i) { /* Data only transfer */ - dmalist_cur_ecc = &dmalist[(i * 2) - 1]; - dmalist_cur_ecc->next_lli = 0; - dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN; - return; - } - - /* OOB only transfer */ - if (read) { - dmasrc = lpc32xx_dmac_set_dma_data(); - dmadst = (u32)buffer; - oob_ctrl |= DMAC_CHAN_DEST_AUTOINC; - } else { - dmadst = lpc32xx_dmac_set_dma_data(); - dmasrc = (u32)buffer; - oob_ctrl |= DMAC_CHAN_SRC_AUTOINC; - } - - /* Read/ Write Spare Area Data To/From Flash */ - dmalist_cur = &dmalist[i * 2]; - dmalist_cur->dma_src = dmasrc; - dmalist_cur->dma_dest = dmadst; - dmalist_cur->next_lli = 0; - dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN); -} - -static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf, - int len, int read) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - u32 config; - int ret; - - /* DMA Channel Configuration */ - config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) | - (read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) | - (read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) | - DMAC_CHAN_ENABLE; - - /* Prepare DMA descriptors */ - lpc32xx_nand_dma_configure(chip, buf, len, read); - - /* Setup SLC controller and start transfer */ - if (read) - setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR); - else /* NAND_ECC_WRITE */ - clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR); - setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST); - - /* Write length for new transfers */ - if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) | - readl(&lpc32xx_nand_slc_regs->tc))) { - int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0; - writel(len + tmp, &lpc32xx_nand_slc_regs->tc); - } - - setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START); - - /* Start DMA transfers */ - ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config); - if (unlikely(ret < 0)) - BUG(); - - /* Wait for NAND to be ready */ - while (!lpc32xx_nand_dev_ready(mtd)) - ; - - /* Wait till DMA transfer is DONE */ - if (lpc32xx_dma_wait_status(dmachan)) - pr_err("NAND DMA transfer error!\r\n"); - - /* Stop DMA & HW ECC */ - clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START); - clrbits_le32(&lpc32xx_nand_slc_regs->cfg, - CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC); -} - -static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count) -{ - int i; - for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES); - i += CFG_SYS_NAND_ECCBYTES) { - u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES]; - ce = ~(ce << 2) & 0xFFFFFF; - spare[i+2] = (u8)(ce & 0xFF); ce >>= 8; - spare[i+1] = (u8)(ce & 0xFF); ce >>= 8; - spare[i] = (u8)(ce & 0xFF); - } - return 0; -} - -static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) -{ - return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS); -} - -/* - * Enables and prepares SLC NAND controller - * for doing data transfers with H/W ECC enabled. - */ -static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode) -{ - /* Clear ECC */ - writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl); - - /* Setup SLC controller for H/W ECC operations */ - setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC); -} - -/* - * lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s) - * mtd: MTD block structure - * dat: raw data read from the chip - * read_ecc: ECC from the chip - * calc_ecc: the ECC calculated from raw data - * - * Detect and correct a 1 bit error for 256 byte block - */ -int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - unsigned int i; - int ret1, ret2 = 0; - u_char *r = read_ecc; - u_char *c = calc_ecc; - u16 data_offset = 0; - - for (i = 0 ; i < ECCSTEPS ; i++) { - r += CFG_SYS_NAND_ECCBYTES; - c += CFG_SYS_NAND_ECCBYTES; - data_offset += CFG_SYS_NAND_ECCSIZE; - - ret1 = nand_correct_data(mtd, dat + data_offset, r, c); - if (ret1 < 0) - return -EBADMSG; - else - ret2 += ret1; - } - - return ret2; -} - -static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - lpc32xx_nand_xfer(mtd, buf, len, 1); -} - -static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, - int len) -{ - lpc32xx_nand_xfer(mtd, buf, len, 0); -} - -/* Reuse the logic from "nand_read_page_hwecc()" */ -static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf, int oob_required, int page) -{ - int i; - int stat; - uint8_t *p = buf; - uint8_t *ecc_calc = chip->buffers->ecccalc; - uint8_t *ecc_code = chip->buffers->ecccode; - uint32_t *eccpos = chip->ecc.layout->eccpos; - unsigned int max_bitflips = 0; - - /* - * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes - * and section 9.7, the NAND SLC & DMA allowed single DMA transaction - * of a page size using DMA controller scatter/gather mode through - * linked list; the ECC read is done without any software intervention. - */ - - lpc32xx_hwecc_enable(mtd, NAND_ECC_READ); - lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps); - lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]); - lpc32xx_dma_read_buf(mtd, chip->oob_poi, mtd->oobsize); - - for (i = 0; i < chip->ecc.total; i++) - ecc_code[i] = chip->oob_poi[eccpos[i]]; - - stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]); - if (stat < 0) - mtd->ecc_stats.failed++; - else { - mtd->ecc_stats.corrected += stat; - max_bitflips = max_t(unsigned int, max_bitflips, stat); - } - - return max_bitflips; -} - -/* Reuse the logic from "nand_write_page_hwecc()" */ -static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, - struct nand_chip *chip, - const uint8_t *buf, int oob_required, - int page) -{ - int i; - uint8_t *ecc_calc = chip->buffers->ecccalc; - const uint8_t *p = buf; - uint32_t *eccpos = chip->ecc.layout->eccpos; - - /* - * As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes - * and section 9.7, the NAND SLC & DMA allowed single DMA transaction - * of a page size using DMA controller scatter/gather mode through - * linked list; the ECC read is done without any software intervention. - */ - - lpc32xx_hwecc_enable(mtd, NAND_ECC_WRITE); - lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps); - lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]); - - for (i = 0; i < chip->ecc.total; i++) - chip->oob_poi[eccpos[i]] = ecc_calc[i]; - - lpc32xx_dma_write_buf(mtd, chip->oob_poi, mtd->oobsize); - - return 0; -} -#else -static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -{ - while (len-- > 0) - *buf++ = readl(&lpc32xx_nand_slc_regs->data); -} - -static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -{ - while (len-- > 0) - writel(*buf++, &lpc32xx_nand_slc_regs->data); -} -#endif - -static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) -{ - return readl(&lpc32xx_nand_slc_regs->data); -} - -static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) -{ - writel(byte, &lpc32xx_nand_slc_regs->data); -} - -/* - * LPC32xx has only one SLC NAND controller, don't utilize - * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function - * both in SPL NAND and U-Boot images. - */ -int board_nand_init(struct nand_chip *lpc32xx_chip) -{ -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) - int ret; - - /* Acquire a channel for our use */ - ret = lpc32xx_dma_get_channel(); - if (unlikely(ret < 0)) { - pr_info("Unable to get free DMA channel for NAND transfers\n"); - return -1; - } - dmachan = (unsigned int)ret; -#endif - - lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; - lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready; - - /* - * The implementation of these functions is quite common, but - * they MUST be defined, because access to data register - * is strictly 32-bit aligned. - */ - lpc32xx_chip->read_byte = lpc32xx_read_byte; - lpc32xx_chip->write_byte = lpc32xx_write_byte; - -#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD) - /* Hardware ECC calculation is supported when DMA driver is selected */ - lpc32xx_chip->ecc.mode = NAND_ECC_HW; - - lpc32xx_chip->read_buf = lpc32xx_dma_read_buf; - lpc32xx_chip->write_buf = lpc32xx_dma_write_buf; - - lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate; - lpc32xx_chip->ecc.correct = lpc32xx_correct_data; - lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable; - lpc32xx_chip->chip_delay = 2000; - - lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc; - lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc; - lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE; -#else - /* - * Hardware ECC calculation is not supported by the driver, - * because it requires DMA support, see LPC32x0 User Manual, - * note after SLC_ECC register description (UM10326, p.198) - */ - lpc32xx_chip->ecc.mode = NAND_ECC_SOFT; - - /* - * The implementation of these functions is quite common, but - * they MUST be defined, because access to data register - * is strictly 32-bit aligned. - */ - lpc32xx_chip->read_buf = lpc32xx_read_buf; - lpc32xx_chip->write_buf = lpc32xx_write_buf; -#endif - - /* - * These values are predefined - * for both small and large page NAND flash devices. - */ - lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE; - lpc32xx_chip->ecc.bytes = CFG_SYS_NAND_ECCBYTES; - lpc32xx_chip->ecc.strength = 1; - - if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE) - lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16; - -#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT) - lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH; -#endif - - /* Initialize NAND interface */ - lpc32xx_nand_init(); - - return 0; -} diff --git a/drivers/mtd/nand/raw/mxic_nand.c b/drivers/mtd/nand/raw/mxic_nand.c deleted file mode 100644 index 0e54b5f6938..00000000000 --- a/drivers/mtd/nand/raw/mxic_nand.c +++ /dev/null @@ -1,602 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Macronix International Co., Ltd. - * - * Author: - * Zhengxun Li <zhengxunli@mxic.com.tw> - */ - -#include <clk.h> -#include <dm.h> -#include <malloc.h> -#include <nand.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <dm/device_compat.h> -#include <linux/bug.h> -#include <linux/errno.h> -#include <linux/iopoll.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/delay.h> - -#define HC_CFG 0x0 -#define HC_CFG_IF_CFG(x) ((x) << 27) -#define HC_CFG_DUAL_SLAVE BIT(31) -#define HC_CFG_INDIVIDUAL BIT(30) -#define HC_CFG_NIO(x) (((x) / 4) << 27) -#define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2))) -#define HC_CFG_TYPE_SPI_NOR 0 -#define HC_CFG_TYPE_SPI_NAND 1 -#define HC_CFG_TYPE_SPI_RAM 2 -#define HC_CFG_TYPE_RAW_NAND 3 -#define HC_CFG_SLV_ACT(x) ((x) << 21) -#define HC_CFG_CLK_PH_EN BIT(20) -#define HC_CFG_CLK_POL_INV BIT(19) -#define HC_CFG_BIG_ENDIAN BIT(18) -#define HC_CFG_DATA_PASS BIT(17) -#define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16) -#define HC_CFG_MAN_START_EN BIT(3) -#define HC_CFG_MAN_START BIT(2) -#define HC_CFG_MAN_CS_EN BIT(1) -#define HC_CFG_MAN_CS_ASSERT BIT(0) - -#define INT_STS 0x4 -#define INT_STS_EN 0x8 -#define INT_SIG_EN 0xc -#define INT_STS_ALL GENMASK(31, 0) -#define INT_RDY_PIN BIT(26) -#define INT_RDY_SR BIT(25) -#define INT_LNR_SUSP BIT(24) -#define INT_ECC_ERR BIT(17) -#define INT_CRC_ERR BIT(16) -#define INT_LWR_DIS BIT(12) -#define INT_LRD_DIS BIT(11) -#define INT_SDMA_INT BIT(10) -#define INT_DMA_FINISH BIT(9) -#define INT_RX_NOT_FULL BIT(3) -#define INT_RX_NOT_EMPTY BIT(2) -#define INT_TX_NOT_FULL BIT(1) -#define INT_TX_EMPTY BIT(0) - -#define HC_EN 0x10 -#define HC_EN_BIT BIT(0) - -#define TXD(x) (0x14 + ((x) * 4)) -#define RXD 0x24 - -#define SS_CTRL(s) (0x30 + ((s) * 4)) -#define LRD_CFG 0x44 -#define LWR_CFG 0x80 -#define RWW_CFG 0x70 -#define OP_READ BIT(23) -#define OP_DUMMY_CYC(x) ((x) << 17) -#define OP_ADDR_BYTES(x) ((x) << 14) -#define OP_CMD_BYTES(x) (((x) - 1) << 13) -#define OP_OCTA_CRC_EN BIT(12) -#define OP_DQS_EN BIT(11) -#define OP_ENHC_EN BIT(10) -#define OP_PREAMBLE_EN BIT(9) -#define OP_DATA_DDR BIT(8) -#define OP_DATA_BUSW(x) ((x) << 6) -#define OP_ADDR_DDR BIT(5) -#define OP_ADDR_BUSW(x) ((x) << 3) -#define OP_CMD_DDR BIT(2) -#define OP_CMD_BUSW(x) (x) -#define OP_BUSW_1 0 -#define OP_BUSW_2 1 -#define OP_BUSW_4 2 -#define OP_BUSW_8 3 - -#define OCTA_CRC 0x38 -#define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16)) -#define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16))) -#define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16)) - -#define ONFI_DIN_CNT(s) (0x3c + (s)) - -#define LRD_CTRL 0x48 -#define RWW_CTRL 0x74 -#define LWR_CTRL 0x84 -#define LMODE_EN BIT(31) -#define LMODE_SLV_ACT(x) ((x) << 21) -#define LMODE_CMD1(x) ((x) << 8) -#define LMODE_CMD0(x) (x) - -#define LRD_ADDR 0x4c -#define LWR_ADDR 0x88 -#define LRD_RANGE 0x50 -#define LWR_RANGE 0x8c - -#define AXI_SLV_ADDR 0x54 - -#define DMAC_RD_CFG 0x58 -#define DMAC_WR_CFG 0x94 -#define DMAC_CFG_PERIPH_EN BIT(31) -#define DMAC_CFG_ALLFLUSH_EN BIT(30) -#define DMAC_CFG_LASTFLUSH_EN BIT(29) -#define DMAC_CFG_QE(x) (((x) + 1) << 16) -#define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12) -#define DMAC_CFG_BURST_SZ(x) ((x) << 8) -#define DMAC_CFG_DIR_READ BIT(1) -#define DMAC_CFG_START BIT(0) - -#define DMAC_RD_CNT 0x5c -#define DMAC_WR_CNT 0x98 - -#define SDMA_ADDR 0x60 - -#define DMAM_CFG 0x64 -#define DMAM_CFG_START BIT(31) -#define DMAM_CFG_CONT BIT(30) -#define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2) -#define DMAM_CFG_DIR_READ BIT(1) -#define DMAM_CFG_EN BIT(0) - -#define DMAM_CNT 0x68 - -#define LNR_TIMER_TH 0x6c - -#define RDM_CFG0 0x78 -#define RDM_CFG0_POLY(x) (x) - -#define RDM_CFG1 0x7c -#define RDM_CFG1_RDM_EN BIT(31) -#define RDM_CFG1_SEED(x) (x) - -#define LWR_SUSP_CTRL 0x90 -#define LWR_SUSP_CTRL_EN BIT(31) - -#define DMAS_CTRL 0x9c -#define DMAS_CTRL_EN BIT(31) -#define DMAS_CTRL_DIR_READ BIT(30) - -#define DATA_STROB 0xa0 -#define DATA_STROB_EDO_EN BIT(2) -#define DATA_STROB_INV_POL BIT(1) -#define DATA_STROB_DELAY_2CYC BIT(0) - -#define IDLY_CODE(x) (0xa4 + ((x) * 4)) -#define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8)) - -#define GPIO 0xc4 -#define GPIO_PT(x) BIT(3 + ((x) * 16)) -#define GPIO_RESET(x) BIT(2 + ((x) * 16)) -#define GPIO_HOLDB(x) BIT(1 + ((x) * 16)) -#define GPIO_WPB(x) BIT((x) * 16) - -#define HC_VER 0xd0 - -#define HW_TEST(x) (0xe0 + ((x) * 4)) - -#define MXIC_NFC_MAX_CLK_HZ 50000000 -#define IRQ_TIMEOUT 1000 - -struct mxic_nand_ctrl { - struct clk *send_clk; - struct clk *send_dly_clk; - void __iomem *regs; - struct nand_chip nand_chip; -}; - -/* - * struct mxic_nfc_command_format - Defines NAND flash command format - * @start_cmd: First cycle command (Start command) - * @end_cmd: Second cycle command (Last command) - * @addr_len: Number of address cycles required to send the address - * @read: Direction of command - */ - -struct mxic_nfc_command_format { - int start_cmd; - int end_cmd; - u8 addr_len; - bool read; -}; - -/* The NAND flash operations command format */ -static const struct mxic_nfc_command_format mxic_nand_commands[] = { - {NAND_CMD_READ0, NAND_CMD_READSTART, 5, 1 }, - {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, 1 }, - {NAND_CMD_READID, NAND_CMD_NONE, 1, 1 }, - {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 1 }, - {NAND_CMD_SEQIN, NAND_CMD_NONE, 5, 0 }, - {NAND_CMD_PAGEPROG, NAND_CMD_NONE, 0, 0 }, - {NAND_CMD_CACHEDPROG, NAND_CMD_NONE, 0, 0 }, - {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0 }, - {NAND_CMD_ERASE1, NAND_CMD_NONE, 3, 0 }, - {NAND_CMD_ERASE2, NAND_CMD_NONE, 0, 0 }, - {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0 }, - {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 1 }, - {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 1 }, - {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0 }, - {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0 }, -}; - -static int mxic_nfc_clk_enable(struct mxic_nand_ctrl *nfc) -{ - int ret; - - ret = clk_prepare_enable(nfc->send_clk); - if (ret) - return ret; - - ret = clk_prepare_enable(nfc->send_dly_clk); - if (ret) - goto err_send_dly_clk; - - return ret; - -err_send_dly_clk: - clk_disable_unprepare(nfc->send_clk); - - return ret; -} - -static void mxic_nfc_clk_disable(struct mxic_nand_ctrl *nfc) -{ - clk_disable_unprepare(nfc->send_clk); - clk_disable_unprepare(nfc->send_dly_clk); -} - -static void mxic_nfc_set_input_delay(struct mxic_nand_ctrl *nfc, u8 idly_code) -{ - writel(IDLY_CODE_VAL(0, idly_code) | - IDLY_CODE_VAL(1, idly_code) | - IDLY_CODE_VAL(2, idly_code) | - IDLY_CODE_VAL(3, idly_code), - nfc->regs + IDLY_CODE(0)); - writel(IDLY_CODE_VAL(4, idly_code) | - IDLY_CODE_VAL(5, idly_code) | - IDLY_CODE_VAL(6, idly_code) | - IDLY_CODE_VAL(7, idly_code), - nfc->regs + IDLY_CODE(1)); -} - -static int mxic_nfc_clk_setup(struct mxic_nand_ctrl *nfc, unsigned long freq) -{ - int ret; - - ret = clk_set_rate(nfc->send_clk, freq); - if (ret) - return ret; - - ret = clk_set_rate(nfc->send_dly_clk, freq); - if (ret) - return ret; - - /* - * A constant delay range from 0x0 ~ 0x1F for input delay, - * the unit is 78 ps, the max input delay is 2.418 ns. - */ - mxic_nfc_set_input_delay(nfc, 0xf); - - return 0; -} - -static int mxic_nfc_set_freq(struct mxic_nand_ctrl *nfc, unsigned long freq) -{ - int ret; - - if (freq > MXIC_NFC_MAX_CLK_HZ) - freq = MXIC_NFC_MAX_CLK_HZ; - - mxic_nfc_clk_disable(nfc); - ret = mxic_nfc_clk_setup(nfc, freq); - if (ret) - return ret; - - ret = mxic_nfc_clk_enable(nfc); - if (ret) - return ret; - - return 0; -} - -static void mxic_nfc_hw_init(struct mxic_nand_ctrl *nfc) -{ - writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) | - HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | - HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG); - writel(INT_STS_ALL, nfc->regs + INT_STS_EN); - writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN); - writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); - writel(0, nfc->regs + LRD_CFG); - writel(0, nfc->regs + LRD_CTRL); - writel(0x0, nfc->regs + HC_EN); -} - -static void mxic_nfc_cs_enable(struct mxic_nand_ctrl *nfc) -{ - writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN, - nfc->regs + HC_CFG); - writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG), - nfc->regs + HC_CFG); -} - -static void mxic_nfc_cs_disable(struct mxic_nand_ctrl *nfc) -{ - writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG), - nfc->regs + HC_CFG); -} - -static int mxic_nfc_data_xfer(struct mxic_nand_ctrl *nfc, const void *txbuf, - void *rxbuf, unsigned int len) -{ - unsigned int pos = 0; - - while (pos < len) { - unsigned int nbytes = len - pos; - u32 data = 0xffffffff; - u32 sts; - int ret; - - if (nbytes > 4) - nbytes = 4; - - if (txbuf) - memcpy(&data, txbuf + pos, nbytes); - - ret = readl_poll_timeout(nfc->regs + INT_STS, sts, - sts & INT_TX_EMPTY, 1000000); - if (ret) - return ret; - - writel(data, nfc->regs + TXD(nbytes % 4)); - - ret = readl_poll_timeout(nfc->regs + INT_STS, sts, - sts & INT_TX_EMPTY, 1000000); - if (ret) - return ret; - - ret = readl_poll_timeout(nfc->regs + INT_STS, sts, - sts & INT_RX_NOT_EMPTY, 1000000); - if (ret) - return ret; - - data = readl(nfc->regs + RXD); - if (rxbuf) { - data >>= (8 * (4 - nbytes)); - memcpy(rxbuf + pos, &data, nbytes); - } - - WARN_ON(readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY); - - pos += nbytes; - } - - return 0; -} - -static uint8_t mxic_nfc_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); - u8 data; - - writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); - writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | - OP_READ, nfc->regs + SS_CTRL(0)); - - mxic_nfc_data_xfer(nfc, NULL, &data, 1); - - return data; -} - -static void mxic_nfc_read_buf(struct mtd_info *mtd, uint8_t *rxbuf, int rlen) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); - - writel(0x0, nfc->regs + ONFI_DIN_CNT(0)); - writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | - OP_READ, nfc->regs + SS_CTRL(0)); - - mxic_nfc_data_xfer(nfc, NULL, rxbuf, rlen); -} - -static void mxic_nfc_write_buf(struct mtd_info *mtd, const uint8_t *txbuf, - int wlen) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); - - writel(wlen, nfc->regs + ONFI_DIN_CNT(0)); - writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F), - nfc->regs + SS_CTRL(0)); - - mxic_nfc_data_xfer(nfc, txbuf, NULL, wlen); -} - -static void mxic_nfc_cmd_function(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); - const struct mxic_nfc_command_format *cmd = NULL; - u32 sts; - u8 index, addr[5]; - - /* Emulate NAND_CMD_READOOB */ - if (command == NAND_CMD_READOOB) { - column += mtd->writesize; - command = NAND_CMD_READ0; - } - - /* Get the command format */ - for (index = 0; index < ARRAY_SIZE(mxic_nand_commands); index++) - if (command == mxic_nand_commands[index].start_cmd) - break; - - cmd = &mxic_nand_commands[index]; - - if (!(command == NAND_CMD_PAGEPROG || - command == NAND_CMD_CACHEDPROG || - command == NAND_CMD_ERASE2)) - mxic_nfc_cs_disable(nfc); - - mxic_nfc_cs_enable(nfc); - - if (column != -1) { - addr[0] = column; - addr[1] = column >> 8; - - if (page_addr != -1) { - addr[2] = page_addr; - addr[3] = page_addr >> 8; - addr[4] = page_addr >> 16; - } - } else if (page_addr != -1) { - addr[0] = page_addr; - addr[1] = page_addr >> 8; - addr[2] = page_addr >> 16; - } - - writel(0, nfc->regs + HC_EN); - writel(HC_EN_BIT, nfc->regs + HC_EN); - writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | OP_CMD_BYTES(0), - nfc->regs + SS_CTRL(0)); - - mxic_nfc_data_xfer(nfc, &cmd->start_cmd, NULL, 1); - - if (cmd->addr_len) { - writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | - OP_ADDR_BYTES(cmd->addr_len), nfc->regs + SS_CTRL(0)); - - mxic_nfc_data_xfer(nfc, &addr, NULL, cmd->addr_len); - } - - if (cmd->end_cmd != NAND_CMD_NONE) { - writel(0, nfc->regs + HC_EN); - writel(HC_EN_BIT, nfc->regs + HC_EN); - writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) | - OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0)); - - mxic_nfc_data_xfer(nfc, &cmd->end_cmd, NULL, 1); - } - - readl_poll_timeout(nfc->regs + INT_STS, sts, sts & INT_RDY_PIN, - 1000000); - - if (command == NAND_CMD_PAGEPROG || - command == NAND_CMD_CACHEDPROG || - command == NAND_CMD_ERASE2 || - command == NAND_CMD_RESET) { - mxic_nfc_cs_disable(nfc); - } -} - -static int mxic_nfc_setup_data_interface(struct mtd_info *mtd, int chipnr, - const struct nand_data_interface *conf) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct mxic_nand_ctrl *nfc = nand_get_controller_data(chip); - const struct nand_sdr_timings *sdr; - unsigned long freq; - int ret; - - sdr = nand_get_sdr_timings(conf); - if (IS_ERR(sdr)) - return PTR_ERR(sdr); - - if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) - return 0; - - freq = 1000000000 / (sdr->tRC_min / 1000); - - ret = mxic_nfc_set_freq(nfc, freq); - if (ret) - WARN_ON("Set freq failed\n"); - - if (sdr->tRC_min < 30000) - writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB); - - return 0; -} - -/* Dummy implementation: we don't support multiple chips */ -static void mxic_nfc_select_chip(struct mtd_info *mtd, int chipnr) -{ - switch (chipnr) { - case -1: - case 0: - break; - - default: - BUG(); - } -} - -static int mxic_nfc_probe(struct udevice *dev) -{ - struct mxic_nand_ctrl *nfc = dev_get_priv(dev); - struct nand_chip *nand_chip = &nfc->nand_chip; - struct mtd_info *mtd; - ofnode child; - int err; - - nfc->regs = dev_read_addr_ptr(dev); - - nfc->send_clk = devm_clk_get(dev, "send"); - if (IS_ERR(nfc->send_clk)) - return PTR_ERR(nfc->send_clk); - - nfc->send_dly_clk = devm_clk_get(dev, "send_dly"); - if (IS_ERR(nfc->send_dly_clk)) - return PTR_ERR(nfc->send_dly_clk); - - mtd = nand_to_mtd(nand_chip); - - ofnode_for_each_subnode(child, dev_ofnode(dev)) - nand_set_flash_node(nand_chip, child); - - nand_set_controller_data(nand_chip, nfc); - - nand_chip->select_chip = mxic_nfc_select_chip; - nand_chip->setup_data_interface = mxic_nfc_setup_data_interface; - nand_chip->cmdfunc = mxic_nfc_cmd_function; - nand_chip->read_byte = mxic_nfc_read_byte; - nand_chip->read_buf = mxic_nfc_read_buf; - nand_chip->write_buf = mxic_nfc_write_buf; - - mxic_nfc_hw_init(nfc); - - err = nand_scan(mtd, 1); - if (err) - return err; - - err = nand_register(0, mtd); - if (err) { - dev_err(dev, "Failed to register MTD: %d\n", err); - return err; - } - - return 0; -} - -static const struct udevice_id mxic_nfc_of_ids[] = { - { .compatible = "mxic,multi-itfc-v009-nand-controller" }, - { /* Sentinel */ } -}; - -U_BOOT_DRIVER(mxic_nfc) = { - .name = "mxic_nfc", - .id = UCLASS_MTD, - .of_match = mxic_nfc_of_ids, - .probe = mxic_nfc_probe, - .priv_auto = sizeof(struct mxic_nand_ctrl), -}; - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(mxic_nfc), &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize %s. (error %d)\n", dev->name, - ret); -} diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index ba67466069b..fecf1f5ba91 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1640,10 +1640,12 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) nand->setup_data_interface = mxs_nand_setup_interface; /* first scan to find the device and get the page size */ - if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) + err = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL); + if (err) goto err_free_buffers; - if (mxs_nand_setup_ecc(mtd)) + err = mxs_nand_setup_ecc(mtd); + if (err) goto err_free_buffers; nand->ecc.read_page = mxs_nand_ecc_read_page; diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c deleted file mode 100644 index 056a6857822..00000000000 --- a/drivers/mtd/nand/raw/octeontx_bch.c +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 Marvell International Ltd. - */ - -#include <dm.h> -#include <dm/of_access.h> -#include <malloc.h> -#include <memalign.h> -#include <nand.h> -#include <pci.h> -#include <pci_ids.h> -#include <time.h> -#include <linux/bitfield.h> -#include <linux/ctype.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/ioport.h> -#include <linux/libfdt.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand_bch.h> -#include <linux/mtd/nand_ecc.h> -#include <asm/io.h> -#include <asm/types.h> -#include <asm/dma-mapping.h> -#include <asm/arch/clock.h> -#include "octeontx_bch.h" - -static LIST_HEAD(octeontx_bch_devices); -static unsigned int num_vfs = BCH_NR_VF; -static void *bch_pf; -static void *bch_vf; -static void *token; -static bool bch_pf_initialized; -static bool bch_vf_initialized; - -static int pci_enable_sriov(struct udevice *dev, int nr_virtfn) -{ - int ret; - - ret = pci_sriov_init(dev, nr_virtfn); - if (ret) - printf("%s(%s): pci_sriov_init returned %d\n", __func__, - dev->name, ret); - return ret; -} - -void *octeontx_bch_getv(void) -{ - if (!bch_vf) - return NULL; - if (bch_vf_initialized && bch_pf_initialized) - return bch_vf; - else - return NULL; -} - -void octeontx_bch_putv(void *token) -{ - bch_vf_initialized = !!token; - bch_vf = token; -} - -void *octeontx_bch_getp(void) -{ - return token; -} - -void octeontx_bch_putp(void *token) -{ - bch_pf = token; - bch_pf_initialized = !!token; -} - -static int do_bch_init(struct bch_device *bch) -{ - return 0; -} - -static void bch_reset(struct bch_device *bch) -{ - writeq(1, bch->reg_base + BCH_CTL); - mdelay(2); -} - -static void bch_disable(struct bch_device *bch) -{ - writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C); - writeq(~0ull, bch->reg_base + BCH_ERR_INT); - bch_reset(bch); -} - -static u32 bch_check_bist_status(struct bch_device *bch) -{ - return readq(bch->reg_base + BCH_BIST_RESULT); -} - -static int bch_device_init(struct bch_device *bch) -{ - u64 bist; - int rc; - - debug("%s: Resetting...\n", __func__); - /* Reset the PF when probed first */ - bch_reset(bch); - - debug("%s: Checking BIST...\n", __func__); - /* Check BIST status */ - bist = (u64)bch_check_bist_status(bch); - if (bist) { - dev_err(dev, "BCH BIST failed with code 0x%llx\n", bist); - return -ENODEV; - } - - /* Get max VQs/VFs supported by the device */ - - bch->max_vfs = pci_sriov_get_totalvfs(bch->dev); - debug("%s: %d vfs\n", __func__, bch->max_vfs); - if (num_vfs > bch->max_vfs) { - dev_warn(dev, "Num of VFs to enable %d is greater than max available. Enabling %d VFs.\n", - num_vfs, bch->max_vfs); - num_vfs = bch->max_vfs; - } - bch->vfs_enabled = bch->max_vfs; - /* Get number of VQs/VFs to be enabled */ - /* TODO: Get CLK frequency */ - /* Reset device parameters */ - - debug("%s: Doing initialization\n", __func__); - rc = do_bch_init(bch); - - return rc; -} - -static int bch_sriov_configure(struct udevice *dev, int numvfs) -{ - struct bch_device *bch = dev_get_priv(dev); - int ret = -EBUSY; - - debug("%s(%s, %d), bch: %p, vfs_in_use: %d, enabled: %d\n", __func__, - dev->name, numvfs, bch, bch->vfs_in_use, bch->vfs_enabled); - if (bch->vfs_in_use) - goto exit; - - ret = 0; - - if (numvfs > 0) { - debug("%s: Enabling sriov\n", __func__); - ret = pci_enable_sriov(dev, numvfs); - if (ret == 0) { - bch->flags |= BCH_FLAG_SRIOV_ENABLED; - ret = numvfs; - bch->vfs_enabled = numvfs; - } - } - - debug("VFs enabled: %d\n", ret); -exit: - debug("%s: Returning %d\n", __func__, ret); - return ret; -} - -static int octeontx_pci_bchpf_probe(struct udevice *dev) -{ - struct bch_device *bch; - int ret; - - debug("%s(%s)\n", __func__, dev->name); - bch = dev_get_priv(dev); - if (!bch) - return -ENOMEM; - - bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, - PCI_REGION_TYPE, PCI_REGION_MEM); - bch->dev = dev; - - debug("%s: base address: %p\n", __func__, bch->reg_base); - ret = bch_device_init(bch); - if (ret) { - printf("%s(%s): init returned %d\n", __func__, dev->name, ret); - return ret; - } - INIT_LIST_HEAD(&bch->list); - list_add(&bch->list, &octeontx_bch_devices); - token = (void *)dev; - - debug("%s: Configuring SRIOV\n", __func__); - bch_sriov_configure(dev, num_vfs); - debug("%s: Done.\n", __func__); - octeontx_bch_putp(bch); - - return 0; -} - -static const struct pci_device_id octeontx_bchpf_pci_id_table[] = { - { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_BCH) }, - {}, -}; - -static const struct pci_device_id octeontx_bchvf_pci_id_table[] = { - { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_BCHVF)}, - {}, -}; - -/** - * Given a data block calculate the ecc data and fill in the response - * - * @param[in] block 8-byte aligned pointer to data block to calculate ECC - * @param block_size Size of block in bytes, must be a multiple of two. - * @param bch_level Number of errors that must be corrected. The number of - * parity bytes is equal to ((15 * bch_level) + 7) / 8. - * Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64. - * @param[out] ecc 8-byte aligned pointer to where ecc data should go - * @param[in] resp pointer to where responses will be written. - * - * Return: Zero on success, negative on failure. - */ -int octeontx_bch_encode(struct bch_vf *vf, dma_addr_t block, u16 block_size, - u8 bch_level, dma_addr_t ecc, dma_addr_t resp) -{ - union bch_cmd cmd; - int rc; - - memset(&cmd, 0, sizeof(cmd)); - cmd.s.cword.ecc_gen = eg_gen; - cmd.s.cword.ecc_level = bch_level; - cmd.s.cword.size = block_size; - - cmd.s.oword.ptr = ecc; - cmd.s.iword.ptr = block; - cmd.s.rword.ptr = resp; - rc = octeontx_cmd_queue_write(QID_BCH, 1, - sizeof(cmd) / sizeof(uint64_t), cmd.u); - if (rc) - return -1; - - octeontx_bch_write_doorbell(1, vf); - - return 0; -} - -/** - * Given a data block and ecc data correct the data block - * - * @param[in] block_ecc_in 8-byte aligned pointer to data block with ECC - * data concatenated to the end to correct - * @param block_size Size of block in bytes, must be a multiple of - * two. - * @param bch_level Number of errors that must be corrected. The - * number of parity bytes is equal to - * ((15 * bch_level) + 7) / 8. - * Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64. - * @param[out] block_out 8-byte aligned pointer to corrected data buffer. - * This should not be the same as block_ecc_in. - * @param[in] resp pointer to where responses will be written. - * - * Return: Zero on success, negative on failure. - */ - -int octeontx_bch_decode(struct bch_vf *vf, dma_addr_t block_ecc_in, - u16 block_size, u8 bch_level, - dma_addr_t block_out, dma_addr_t resp) -{ - union bch_cmd cmd; - int rc; - - memset(&cmd, 0, sizeof(cmd)); - cmd.s.cword.ecc_gen = eg_correct; - cmd.s.cword.ecc_level = bch_level; - cmd.s.cword.size = block_size; - - cmd.s.oword.ptr = block_out; - cmd.s.iword.ptr = block_ecc_in; - cmd.s.rword.ptr = resp; - rc = octeontx_cmd_queue_write(QID_BCH, 1, - sizeof(cmd) / sizeof(uint64_t), cmd.u); - if (rc) - return -1; - - octeontx_bch_write_doorbell(1, vf); - return 0; -} -EXPORT_SYMBOL(octeontx_bch_decode); - -int octeontx_bch_wait(struct bch_vf *vf, union bch_resp *resp, - dma_addr_t handle) -{ - ulong start = get_timer(0); - - __iormb(); /* HW is updating *resp */ - while (!resp->s.done && get_timer(start) < 10) - __iormb(); /* HW is updating *resp */ - - if (resp->s.done) - return 0; - - return -ETIMEDOUT; -} - -struct bch_q octeontx_bch_q[QID_MAX]; - -static int octeontx_cmd_queue_initialize(struct udevice *dev, int queue_id, - int max_depth, int fpa_pool, - int pool_size) -{ - /* some params are for later merge with CPT or cn83xx */ - struct bch_q *q = &octeontx_bch_q[queue_id]; - unsigned long paddr; - u64 *chunk_buffer; - int chunk = max_depth + 1; - int i, size; - - if ((unsigned int)queue_id >= QID_MAX) - return -EINVAL; - if (max_depth & chunk) /* must be 2^N - 1 */ - return -EINVAL; - - size = NQS * chunk * sizeof(u64); - chunk_buffer = dma_alloc_coherent(size, &paddr); - if (!chunk_buffer) - return -ENOMEM; - - q->base_paddr = paddr; - q->dev = dev; - q->index = 0; - q->max_depth = max_depth; - q->pool_size_m1 = pool_size; - q->base_vaddr = chunk_buffer; - - for (i = 0; i < NQS; i++) { - u64 *ixp; - int inext = (i + 1) * chunk - 1; - int j = (i + 1) % NQS; - int jnext = j * chunk; - dma_addr_t jbase = q->base_paddr + jnext * sizeof(u64); - - ixp = &chunk_buffer[inext]; - *ixp = jbase; - } - - return 0; -} - -static int octeontx_pci_bchvf_probe(struct udevice *dev) -{ - struct bch_vf *vf; - union bch_vqx_ctl ctl; - union bch_vqx_cmd_buf cbuf; - int err; - - debug("%s(%s)\n", __func__, dev->name); - vf = dev_get_priv(dev); - if (!vf) - return -ENOMEM; - - vf->dev = dev; - - /* Map PF's configuration registers */ - vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, - PCI_REGION_TYPE, PCI_REGION_MEM); - debug("%s: reg base: %p\n", __func__, vf->reg_base); - - err = octeontx_cmd_queue_initialize(dev, QID_BCH, QDEPTH - 1, 0, - sizeof(union bch_cmd) * QDEPTH); - if (err) { - dev_err(dev, "octeontx_cmd_queue_initialize() failed\n"); - goto release; - } - - ctl.u = readq(vf->reg_base + BCH_VQX_CTL(0)); - - cbuf.u = 0; - cbuf.s.ldwb = 1; - cbuf.s.dfb = 1; - cbuf.s.size = QDEPTH; - writeq(cbuf.u, vf->reg_base + BCH_VQX_CMD_BUF(0)); - - writeq(ctl.u, vf->reg_base + BCH_VQX_CTL(0)); - - writeq(octeontx_bch_q[QID_BCH].base_paddr, - vf->reg_base + BCH_VQX_CMD_PTR(0)); - - octeontx_bch_putv(vf); - - debug("%s: bch vf initialization complete\n", __func__); - - if (octeontx_bch_getv()) - return octeontx_pci_nand_deferred_probe(); - - return -1; - -release: - return err; -} - -static int octeontx_pci_bchpf_remove(struct udevice *dev) -{ - struct bch_device *bch = dev_get_priv(dev); - - bch_disable(bch); - return 0; -} - -U_BOOT_DRIVER(octeontx_pci_bchpf) = { - .name = BCHPF_DRIVER_NAME, - .id = UCLASS_MISC, - .probe = octeontx_pci_bchpf_probe, - .remove = octeontx_pci_bchpf_remove, - .priv_auto = sizeof(struct bch_device), - .flags = DM_FLAG_OS_PREPARE, -}; - -U_BOOT_DRIVER(octeontx_pci_bchvf) = { - .name = BCHVF_DRIVER_NAME, - .id = UCLASS_MISC, - .probe = octeontx_pci_bchvf_probe, - .priv_auto = sizeof(struct bch_vf), -}; - -U_BOOT_PCI_DEVICE(octeontx_pci_bchpf, octeontx_bchpf_pci_id_table); -U_BOOT_PCI_DEVICE(octeontx_pci_bchvf, octeontx_bchvf_pci_id_table); diff --git a/drivers/mtd/nand/raw/octeontx_bch.h b/drivers/mtd/nand/raw/octeontx_bch.h deleted file mode 100644 index 95a9b7126fb..00000000000 --- a/drivers/mtd/nand/raw/octeontx_bch.h +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Marvell International Ltd. - */ - -#ifndef __OCTEONTX_BCH_H__ -#define __OCTEONTX_BCH_H__ - -#include "octeontx_bch_regs.h" - -/* flags to indicate the features supported */ -#define BCH_FLAG_SRIOV_ENABLED BIT(1) - -/* - * BCH Registers map for 81xx - */ - -/* PF registers */ -#define BCH_CTL 0x0ull -#define BCH_ERR_CFG 0x10ull -#define BCH_BIST_RESULT 0x80ull -#define BCH_ERR_INT 0x88ull -#define BCH_ERR_INT_W1S 0x90ull -#define BCH_ERR_INT_ENA_W1C 0xA0ull -#define BCH_ERR_INT_ENA_W1S 0xA8ull - -/* VF registers */ -#define BCH_VQX_CTL(z) 0x0ull -#define BCH_VQX_CMD_BUF(z) 0x8ull -#define BCH_VQX_CMD_PTR(z) 0x20ull -#define BCH_VQX_DOORBELL(z) 0x800ull - -#define BCHPF_DRIVER_NAME "octeontx-bchpf" -#define BCHVF_DRIVER_NAME "octeontx-bchvf" - -struct bch_device { - struct list_head list; - u8 max_vfs; - u8 vfs_enabled; - u8 vfs_in_use; - u32 flags; - void __iomem *reg_base; - struct udevice *dev; -}; - -struct bch_vf { - u16 flags; - u8 vfid; - u8 node; - u8 priority; - struct udevice *dev; - void __iomem *reg_base; -}; - -struct buf_ptr { - u8 *vptr; - dma_addr_t dma_addr; - u16 size; -}; - -void *octeontx_bch_getv(void); -void octeontx_bch_putv(void *token); -void *octeontx_bch_getp(void); -void octeontx_bch_putp(void *token); -int octeontx_bch_wait(struct bch_vf *vf, union bch_resp *resp, - dma_addr_t handle); -/** - * Given a data block calculate the ecc data and fill in the response - * - * @param[in] block 8-byte aligned pointer to data block to calculate ECC - * @param block_size Size of block in bytes, must be a multiple of two. - * @param bch_level Number of errors that must be corrected. The number of - * parity bytes is equal to ((15 * bch_level) + 7) / 8. - * Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64. - * @param[out] ecc 8-byte aligned pointer to where ecc data should go - * @param[in] resp pointer to where responses will be written. - * - * Return: Zero on success, negative on failure. - */ -int octeontx_bch_encode(struct bch_vf *vf, dma_addr_t block, u16 block_size, - u8 bch_level, dma_addr_t ecc, dma_addr_t resp); - -/** - * Given a data block and ecc data correct the data block - * - * @param[in] block_ecc_in 8-byte aligned pointer to data block with ECC - * data concatenated to the end to correct - * @param block_size Size of block in bytes, must be a multiple of - * two. - * @param bch_level Number of errors that must be corrected. The - * number of parity bytes is equal to - * ((15 * bch_level) + 7) / 8. - * Must be 4, 8, 16, 24, 32, 40, 48, 56, 60 or 64. - * @param[out] block_out 8-byte aligned pointer to corrected data buffer. - * This should not be the same as block_ecc_in. - * @param[in] resp pointer to where responses will be written. - * - * Return: Zero on success, negative on failure. - */ - -int octeontx_bch_decode(struct bch_vf *vf, dma_addr_t block_ecc_in, - u16 block_size, u8 bch_level, - dma_addr_t block_out, dma_addr_t resp); - -/** - * Ring the BCH doorbell telling it that new commands are - * available. - * - * @param num_commands Number of new commands - * @param vf virtual function handle - */ -static inline void octeontx_bch_write_doorbell(u64 num_commands, - struct bch_vf *vf) -{ - u64 num_words = num_commands * sizeof(union bch_cmd) / sizeof(uint64_t); - - writeq(num_words, vf->reg_base + BCH_VQX_DOORBELL(0)); -} - -/** - * Since it's possible (and even likely) that the NAND device will be probed - * before the BCH device has been probed, we may need to defer the probing. - * - * In this case, the initial probe returns success but the actual probing - * is deferred until the BCH VF has been probed. - * - * Return: 0 for success, otherwise error - */ -int octeontx_pci_nand_deferred_probe(void); - -#endif /* __OCTEONTX_BCH_H__ */ diff --git a/drivers/mtd/nand/raw/octeontx_bch_regs.h b/drivers/mtd/nand/raw/octeontx_bch_regs.h deleted file mode 100644 index 7d34438fec0..00000000000 --- a/drivers/mtd/nand/raw/octeontx_bch_regs.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2018 Marvell International Ltd. - */ - -#ifndef __OCTEONTX_BCH_REGS_H__ -#define __OCTEONTX_BCH_REGS_H__ - -#define BCH_NR_VF 1 - -union bch_cmd { - u64 u[4]; - struct fields { - struct { - u64 size:12; - u64 reserved_12_31:20; - u64 ecc_level:4; - u64 reserved_36_61:26; - u64 ecc_gen:2; - } cword; - struct { - u64 ptr:49; - u64 reserved_49_55:7; - u64 nc:1; - u64 fw:1; - u64 reserved_58_63:6; - } oword; - struct { - u64 ptr:49; - u64 reserved_49_55:7; - u64 nc:1; - u64 reserved_57_63:7; - } iword; - struct { - u64 ptr:49; - u64 reserved_49_63:15; - } rword; - } s; -}; - -enum ecc_gen { - eg_correct, - eg_copy, - eg_gen, - eg_copy3, -}; - -/** Response from BCH instruction */ -union bch_resp { - u16 u16; - struct { - u16 num_errors:7; /** Number of errors in block */ - u16 zero:6; /** Always zero, ignore */ - u16 erased:1; /** Block is erased */ - u16 uncorrectable:1;/** too many bits flipped */ - u16 done:1; /** Block is done */ - } s; -}; - -union bch_vqx_ctl { - u64 u; - struct { - u64 reserved_0:1; - u64 cmd_be:1; - u64 max_read:4; - u64 reserved_6_15:10; - u64 erase_disable:1; - u64 one_cmd:1; - u64 early_term:4; - u64 reserved_22_63:42; - } s; -}; - -union bch_vqx_cmd_buf { - u64 u; - struct { - u64 reserved_0_32:33; - u64 size:13; - u64 dfb:1; - u64 ldwb:1; - u64 reserved_48_63:16; - } s; -}; - -/* keep queue state indexed, even though just one supported here, - * for later generalization to similarly-shaped queues on other Cavium devices - */ -enum { - QID_BCH, - QID_MAX -}; - -struct bch_q { - struct udevice *dev; - int index; - u16 max_depth; - u16 pool_size_m1; - u64 *base_vaddr; - dma_addr_t base_paddr; -}; - -extern struct bch_q octeontx_bch_q[QID_MAX]; - -/* with one dma-mapped area, virt<->phys conversions by +/- (vaddr-paddr) */ -static inline dma_addr_t qphys(int qid, void *v) -{ - struct bch_q *q = &octeontx_bch_q[qid]; - int off = (u8 *)v - (u8 *)q->base_vaddr; - - return q->base_paddr + off; -} - -#define octeontx_ptr_to_phys(v) qphys(QID_BCH, (v)) - -static inline void *qvirt(int qid, dma_addr_t p) -{ - struct bch_q *q = &octeontx_bch_q[qid]; - int off = p - q->base_paddr; - - return q->base_vaddr + off; -} - -#define octeontx_phys_to_ptr(p) qvirt(QID_BCH, (p)) - -/* plenty for interleaved r/w on two planes with 16k page, ecc_size 1k */ -/* QDEPTH >= 16, as successive chunks must align on 128-byte boundaries */ -#define QDEPTH 256 /* u64s in a command queue chunk, incl next-pointer */ -#define NQS 1 /* linked chunks in the chain */ - -/** - * Write an arbitrary number of command words to a command queue. - * This is a generic function; the fixed number of command word - * functions yield higher performance. - * - * Could merge with crypto version for FPA use on cn83xx - */ -static inline int octeontx_cmd_queue_write(int queue_id, bool use_locking, - int cmd_count, const u64 *cmds) -{ - int ret = 0; - u64 *cmd_ptr; - struct bch_q *qptr = &octeontx_bch_q[queue_id]; - - if (unlikely(cmd_count < 1 || cmd_count > 32)) - return -EINVAL; - if (unlikely(!cmds)) - return -EINVAL; - - cmd_ptr = qptr->base_vaddr; - - while (cmd_count > 0) { - int slot = qptr->index % (QDEPTH * NQS); - - if (slot % QDEPTH != QDEPTH - 1) { - cmd_ptr[slot] = *cmds++; - cmd_count--; - } - - qptr->index++; - } - - __iowmb(); /* flush commands before ringing bell */ - - return ret; -} - -#endif /* __OCTEONTX_BCH_REGS_H__ */ diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c deleted file mode 100644 index 3b20685fac0..00000000000 --- a/drivers/mtd/nand/raw/octeontx_nand.c +++ /dev/null @@ -1,2254 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 Marvell International Ltd. - */ - -#include <dm.h> -#include <dm/device-internal.h> -#include <dm/devres.h> -#include <dm/of_access.h> -#include <malloc.h> -#include <memalign.h> -#include <nand.h> -#include <pci.h> -#include <time.h> -#include <linux/bitfield.h> -#include <linux/ctype.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/ioport.h> -#include <linux/libfdt.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand_bch.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/rawnand.h> -#include <linux/time.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/types.h> -#include <asm/dma-mapping.h> -#include <asm/arch/clock.h> -#include "octeontx_bch.h" - -/* - * The NDF_CMD queue takes commands between 16 - 128 bit. - * All commands must be 16 bit aligned and are little endian. - * WAIT_STATUS commands must be 64 bit aligned. - * Commands are selected by the 4 bit opcode. - * - * Available Commands: - * - * 16 Bit: - * NOP - * WAIT - * BUS_ACQ, BUS_REL - * CHIP_EN, CHIP_DIS - * - * 32 Bit: - * CLE_CMD - * RD_CMD, RD_EDO_CMD - * WR_CMD - * - * 64 Bit: - * SET_TM_PAR - * - * 96 Bit: - * ALE_CMD - * - * 128 Bit: - * WAIT_STATUS, WAIT_STATUS_ALE - */ - -/* NDF Register offsets */ -#define NDF_CMD 0x0 -#define NDF_MISC 0x8 -#define NDF_ECC_CNT 0x10 -#define NDF_DRBELL 0x30 -#define NDF_ST_REG 0x38 /* status */ -#define NDF_INT 0x40 -#define NDF_INT_W1S 0x48 -#define NDF_DMA_CFG 0x50 -#define NDF_DMA_ADR 0x58 -#define NDF_INT_ENA_W1C 0x60 -#define NDF_INT_ENA_W1S 0x68 - -/* NDF command opcodes */ -#define NDF_OP_NOP 0x0 -#define NDF_OP_SET_TM_PAR 0x1 -#define NDF_OP_WAIT 0x2 -#define NDF_OP_CHIP_EN_DIS 0x3 -#define NDF_OP_CLE_CMD 0x4 -#define NDF_OP_ALE_CMD 0x5 -#define NDF_OP_WR_CMD 0x8 -#define NDF_OP_RD_CMD 0x9 -#define NDF_OP_RD_EDO_CMD 0xa -#define NDF_OP_WAIT_STATUS 0xb /* same opcode for WAIT_STATUS_ALE */ -#define NDF_OP_BUS_ACQ_REL 0xf - -#define NDF_BUS_ACQUIRE 1 -#define NDF_BUS_RELEASE 0 - -#define DBGX_EDSCR(X) (0x87A008000088 + (X) * 0x80000) - -struct ndf_nop_cmd { - u16 opcode: 4; - u16 nop: 12; -}; - -struct ndf_wait_cmd { - u16 opcode:4; - u16 r_b:1; /* wait for one cycle or PBUS_WAIT deassert */ - u16:3; - u16 wlen:3; /* timing parameter select */ - u16:5; -}; - -struct ndf_bus_cmd { - u16 opcode:4; - u16 direction:4; /* 1 = acquire, 0 = release */ - u16:8; -}; - -struct ndf_chip_cmd { - u16 opcode:4; - u16 chip:3; /* select chip, 0 = disable */ - u16 enable:1; /* 1 = enable, 0 = disable */ - u16 bus_width:2; /* 10 = 16 bit, 01 = 8 bit */ - u16:6; -}; - -struct ndf_cle_cmd { - u32 opcode:4; - u32:4; - u32 cmd_data:8; /* command sent to the PBUS AD pins */ - u32 clen1:3; /* time between PBUS CLE and WE asserts */ - u32 clen2:3; /* time WE remains asserted */ - u32 clen3:3; /* time between WE deassert and CLE */ - u32:7; -}; - -/* RD_EDO_CMD uses the same layout as RD_CMD */ -struct ndf_rd_cmd { - u32 opcode:4; - u32 data:16; /* data bytes */ - u32 rlen1:3; - u32 rlen2:3; - u32 rlen3:3; - u32 rlen4:3; -}; - -struct ndf_wr_cmd { - u32 opcode:4; - u32 data:16; /* data bytes */ - u32:4; - u32 wlen1:3; - u32 wlen2:3; - u32:3; -}; - -struct ndf_set_tm_par_cmd { - u64 opcode:4; - u64 tim_mult:4; /* multiplier for the seven parameters */ - u64 tm_par1:8; /* --> Following are the 7 timing parameters that */ - u64 tm_par2:8; /* specify the number of coprocessor cycles. */ - u64 tm_par3:8; /* A value of zero means one cycle. */ - u64 tm_par4:8; /* All values are scaled by tim_mult */ - u64 tm_par5:8; /* using tim_par * (2 ^ tim_mult). */ - u64 tm_par6:8; - u64 tm_par7:8; -}; - -struct ndf_ale_cmd { - u32 opcode:4; - u32:4; - u32 adr_byte_num:4; /* number of address bytes to be sent */ - u32:4; - u32 alen1:3; - u32 alen2:3; - u32 alen3:3; - u32 alen4:3; - u32:4; - u8 adr_byt1; - u8 adr_byt2; - u8 adr_byt3; - u8 adr_byt4; - u8 adr_byt5; - u8 adr_byt6; - u8 adr_byt7; - u8 adr_byt8; -}; - -struct ndf_wait_status_cmd { - u32 opcode:4; - u32:4; - u32 data:8; /** data */ - u32 clen1:3; - u32 clen2:3; - u32 clen3:3; - u32:8; - /** set to 5 to select WAIT_STATUS_ALE command */ - u32 ale_ind:8; - /** ALE only: number of address bytes to be sent */ - u32 adr_byte_num:4; - u32:4; - u32 alen1:3; /* ALE only */ - u32 alen2:3; /* ALE only */ - u32 alen3:3; /* ALE only */ - u32 alen4:3; /* ALE only */ - u32:4; - u8 adr_byt[4]; /* ALE only */ - u32 nine:4; /* set to 9 */ - u32 and_mask:8; - u32 comp_byte:8; - u32 rlen1:3; - u32 rlen2:3; - u32 rlen3:3; - u32 rlen4:3; -}; - -union ndf_cmd { - u64 val[2]; - union { - struct ndf_nop_cmd nop; - struct ndf_wait_cmd wait; - struct ndf_bus_cmd bus_acq_rel; - struct ndf_chip_cmd chip_en_dis; - struct ndf_cle_cmd cle_cmd; - struct ndf_rd_cmd rd_cmd; - struct ndf_wr_cmd wr_cmd; - struct ndf_set_tm_par_cmd set_tm_par; - struct ndf_ale_cmd ale_cmd; - struct ndf_wait_status_cmd wait_status; - } u; -}; - -/** Disable multi-bit error hangs */ -#define NDF_MISC_MB_DIS BIT_ULL(27) -/** High watermark for NBR FIFO or load/store operations */ -#define NDF_MISC_NBR_HWM GENMASK_ULL(26, 24) -/** Wait input filter count */ -#define NDF_MISC_WAIT_CNT GENMASK_ULL(23, 18) -/** Unfilled NFD_CMD queue bytes */ -#define NDF_MISC_FR_BYTE GENMASK_ULL(17, 7) -/** Set by HW when it reads the last 8 bytes of NDF_CMD */ -#define NDF_MISC_RD_DONE BIT_ULL(6) -/** Set by HW when it reads. SW read of NDF_CMD clears it */ -#define NDF_MISC_RD_VAL BIT_ULL(5) -/** Let HW read NDF_CMD queue. Cleared on SW NDF_CMD write */ -#define NDF_MISC_RD_CMD BIT_ULL(4) -/** Boot disable */ -#define NDF_MISC_BT_DIS BIT_ULL(2) -/** Stop command execution after completing command queue */ -#define NDF_MISC_EX_DIS BIT_ULL(1) -/** Reset fifo */ -#define NDF_MISC_RST_FF BIT_ULL(0) - -/** DMA engine enable */ -#define NDF_DMA_CFG_EN BIT_ULL(63) -/** Read or write */ -#define NDF_DMA_CFG_RW BIT_ULL(62) -/** Terminates DMA and clears enable bit */ -#define NDF_DMA_CFG_CLR BIT_ULL(61) -/** 32-bit swap enable */ -#define NDF_DMA_CFG_SWAP32 BIT_ULL(59) -/** 16-bit swap enable */ -#define NDF_DMA_CFG_SWAP16 BIT_ULL(58) -/** 8-bit swap enable */ -#define NDF_DMA_CFG_SWAP8 BIT_ULL(57) -/** Endian mode */ -#define NDF_DMA_CFG_CMD_BE BIT_ULL(56) -/** Number of 64 bit transfers */ -#define NDF_DMA_CFG_SIZE GENMASK_ULL(55, 36) - -/** Command execution status idle */ -#define NDF_ST_REG_EXE_IDLE BIT_ULL(15) -/** Command execution SM states */ -#define NDF_ST_REG_EXE_SM GENMASK_ULL(14, 11) -/** DMA and load SM states */ -#define NDF_ST_REG_BT_SM GENMASK_ULL(10, 7) -/** Queue read-back SM bad state */ -#define NDF_ST_REG_RD_FF_BAD BIT_ULL(6) -/** Queue read-back SM states */ -#define NDF_ST_REG_RD_FF GENMASK_ULL(5, 4) -/** Main SM is in a bad state */ -#define NDF_ST_REG_MAIN_BAD BIT_ULL(3) -/** Main SM states */ -#define NDF_ST_REG_MAIN_SM GENMASK_ULL(2, 0) - -#define MAX_NAND_NAME_LEN 64 -#if (defined(NAND_MAX_PAGESIZE) && (NAND_MAX_PAGESIZE > 4096)) || \ - !defined(NAND_MAX_PAGESIZE) -# undef NAND_MAX_PAGESIZE -# define NAND_MAX_PAGESIZE 4096 -#endif -#if (defined(NAND_MAX_OOBSIZE) && (NAND_MAX_OOBSIZE > 256)) || \ - !defined(NAND_MAX_OOBSIZE) -# undef NAND_MAX_OOBSIZE -# define NAND_MAX_OOBSIZE 256 -#endif - -#define OCTEONTX_NAND_DRIVER_NAME "octeontx_nand" - -#define NDF_TIMEOUT 1000 /** Timeout in ms */ -#ifndef NAND_MAX_CHIPS -# define NAND_MAX_CHIPS 8 /** Linux compatibility */ -#endif - -struct octeontx_nand_chip { - struct list_head node; - struct nand_chip nand; - struct ndf_set_tm_par_cmd timings; - int cs; - int selected_page; - int iface_mode; - int row_bytes; - int col_bytes; - bool oob_only; - bool iface_set; -}; - -struct octeontx_nand_buf { - u8 *dmabuf; - dma_addr_t dmaaddr; - int dmabuflen; - int data_len; - int data_index; -}; - -/** NAND flash controller (NDF) related information */ -struct octeontx_nfc { - struct nand_hw_control controller; - struct udevice *dev; - void __iomem *base; - struct list_head chips; - int selected_chip; /* Currently selected NAND chip number */ - - /* - * Status is separate from octeontx_nand_buf because - * it can be used in parallel and during init. - */ - u8 *stat; - dma_addr_t stat_addr; - bool use_status; - - struct octeontx_nand_buf buf; - union bch_resp *bch_resp; - dma_addr_t bch_rhandle; - - /* BCH of all-0xff, so erased pages read as error-free */ - unsigned char *eccmask; -}; - -/* settable timings - 0..7 select timing of alen1..4/clen1..3/etc */ -enum tm_idx { - t0, /* fixed at 4<<mult cycles */ - t1, t2, t3, t4, t5, t6, t7, /* settable per ONFI-timing mode */ -}; - -struct octeontx_probe_device { - struct list_head list; - struct udevice *dev; -}; - -static struct bch_vf *bch_vf; -/** Deferred devices due to BCH not being ready */ -static LIST_HEAD(octeontx_pci_nand_deferred_devices); - -/** default parameters used for probing chips */ -#define MAX_ONFI_MODE 5 - -static int default_onfi_timing; -static int slew_ns = 2; /* default timing padding */ -static int def_ecc_size = 512; /* 1024 best for sw_bch, <= 4095 for hw_bch */ -static int default_width = 1; /* 8 bit */ -static int default_page_size = 2048; -static struct ndf_set_tm_par_cmd default_timing_parms; - -/** Port from Linux */ -#define readq_poll_timeout(addr, val, cond, delay_us, timeout_us) \ -({ \ - ulong __start = get_timer(0); \ - void *__addr = (addr); \ - const ulong __timeout_ms = timeout_us / 1000; \ - do { \ - (val) = readq(__addr); \ - if (cond) \ - break; \ - if (timeout_us && get_timer(__start) > __timeout_ms) { \ - (val) = readq(__addr); \ - break; \ - } \ - if (delay_us) \ - udelay(delay_us); \ - } while (1); \ - (cond) ? 0 : -ETIMEDOUT; \ -}) - -/** Ported from Linux 4.9.0 include/linux/of.h for compatibility */ -static inline int of_get_child_count(const ofnode node) -{ - return fdtdec_get_child_count(gd->fdt_blob, ofnode_to_offset(node)); -} - -/** - * Linux compatibility from Linux 4.9.0 drivers/mtd/nand/nand_base.c - */ -static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - - if (section || !ecc->total) - return -ERANGE; - - oobregion->length = ecc->total; - oobregion->offset = mtd->oobsize - oobregion->length; - - return 0; -} - -/** - * Linux compatibility from Linux 4.9.0 drivers/mtd/nand/nand_base.c - */ -static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, - struct mtd_oob_region *oobregion) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct nand_ecc_ctrl *ecc = &chip->ecc; - - if (section) - return -ERANGE; - - oobregion->length = mtd->oobsize - ecc->total - 2; - oobregion->offset = 2; - - return 0; -} - -static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { - .ecc = nand_ooblayout_ecc_lp, - .rfree = nand_ooblayout_free_lp, -}; - -static inline struct octeontx_nand_chip *to_otx_nand(struct nand_chip *nand) -{ - return container_of(nand, struct octeontx_nand_chip, nand); -} - -static inline struct octeontx_nfc *to_otx_nfc(struct nand_hw_control *ctrl) -{ - return container_of(ctrl, struct octeontx_nfc, controller); -} - -static int octeontx_nand_calc_ecc_layout(struct nand_chip *nand) -{ - struct nand_ecclayout *layout = nand->ecc.layout; - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - struct mtd_info *mtd = &nand->mtd; - int oobsize = mtd->oobsize; - int i; - bool layout_alloc = false; - - if (!layout) { - layout = devm_kzalloc(tn->dev, sizeof(*layout), GFP_KERNEL); - if (!layout) - return -ENOMEM; - nand->ecc.layout = layout; - layout_alloc = true; - } - layout->eccbytes = nand->ecc.steps * nand->ecc.bytes; - /* Reserve 2 bytes for bad block marker */ - if (layout->eccbytes + 2 > oobsize) { - pr_err("No suitable oob scheme available for oobsize %d eccbytes %u\n", - oobsize, layout->eccbytes); - goto fail; - } - /* put ecc bytes at oob tail */ - for (i = 0; i < layout->eccbytes; i++) - layout->eccpos[i] = oobsize - layout->eccbytes + i; - layout->oobfree[0].offset = 2; - layout->oobfree[0].length = oobsize - 2 - layout->eccbytes; - nand->ecc.layout = layout; - return 0; - -fail: - if (layout_alloc) - kfree(layout); - return -1; -} - -/* - * Read a single byte from the temporary buffer. Used after READID - * to get the NAND information and for STATUS. - */ -static u8 octeontx_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - - if (tn->use_status) { - tn->use_status = false; - return *tn->stat; - } - - if (tn->buf.data_index < tn->buf.data_len) - return tn->buf.dmabuf[tn->buf.data_index++]; - - dev_err(tn->dev, "No data to read, idx: 0x%x, len: 0x%x\n", - tn->buf.data_index, tn->buf.data_len); - - return 0xff; -} - -/* - * Read a number of pending bytes from the temporary buffer. Used - * to get page and OOB data. - */ -static void octeontx_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - - if (len > tn->buf.data_len - tn->buf.data_index) { - dev_err(tn->dev, "Not enough data for read of %d bytes\n", len); - return; - } - - memcpy(buf, tn->buf.dmabuf + tn->buf.data_index, len); - tn->buf.data_index += len; -} - -static void octeontx_nand_write_buf(struct mtd_info *mtd, - const u8 *buf, int len) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - - memcpy(tn->buf.dmabuf + tn->buf.data_len, buf, len); - tn->buf.data_len += len; -} - -/* Overwrite default function to avoid sync abort on chip = -1. */ -static void octeontx_nand_select_chip(struct mtd_info *mtd, int chip) -{ -} - -static inline int timing_to_cycle(u32 psec, unsigned long clock) -{ - unsigned int ns; - int ticks; - - ns = DIV_ROUND_UP(psec, 1000); - ns += slew_ns; - - /* no rounding needed since clock is multiple of 1MHz */ - clock /= 1000000; - ns *= clock; - - ticks = DIV_ROUND_UP(ns, 1000); - - /* actual delay is (tm_parX+1)<<tim_mult */ - if (ticks) - ticks--; - - return ticks; -} - -static void set_timings(struct octeontx_nand_chip *chip, - struct ndf_set_tm_par_cmd *tp, - const struct nand_sdr_timings *timings, - unsigned long sclk) -{ - /* scaled coprocessor-cycle values */ - u32 s_wh, s_cls, s_clh, s_rp, s_wb, s_wc; - - tp->tim_mult = 0; - s_wh = timing_to_cycle(timings->tWH_min, sclk); - s_cls = timing_to_cycle(timings->tCLS_min, sclk); - s_clh = timing_to_cycle(timings->tCLH_min, sclk); - s_rp = timing_to_cycle(timings->tRP_min, sclk); - s_wb = timing_to_cycle(timings->tWB_max, sclk); - s_wc = timing_to_cycle(timings->tWC_min, sclk); - - tp->tm_par1 = s_wh; - tp->tm_par2 = s_clh; - tp->tm_par3 = s_rp + 1; - tp->tm_par4 = s_cls - s_wh; - tp->tm_par5 = s_wc - s_wh + 1; - tp->tm_par6 = s_wb; - tp->tm_par7 = 0; - tp->tim_mult++; /* overcompensate for bad math */ - - /* TODO: comment parameter re-use */ - - pr_debug("%s: tim_par: mult: %d p1: %d p2: %d p3: %d\n", - __func__, tp->tim_mult, tp->tm_par1, tp->tm_par2, tp->tm_par3); - pr_debug(" p4: %d p5: %d p6: %d p7: %d\n", - tp->tm_par4, tp->tm_par5, tp->tm_par6, tp->tm_par7); -} - -static int set_default_timings(struct octeontx_nfc *tn, - const struct nand_sdr_timings *timings) -{ - unsigned long sclk = octeontx_get_io_clock(); - - set_timings(NULL, &default_timing_parms, timings, sclk); - return 0; -} - -static int octeontx_nfc_chip_set_timings(struct octeontx_nand_chip *chip, - const struct nand_sdr_timings *timings) -{ - /*struct octeontx_nfc *tn = to_otx_nfc(chip->nand.controller);*/ - unsigned long sclk = octeontx_get_io_clock(); - - set_timings(chip, &chip->timings, timings, sclk); - return 0; -} - -/* How many bytes are free in the NFD_CMD queue? */ -static int ndf_cmd_queue_free(struct octeontx_nfc *tn) -{ - u64 ndf_misc; - - ndf_misc = readq(tn->base + NDF_MISC); - return FIELD_GET(NDF_MISC_FR_BYTE, ndf_misc); -} - -/* Submit a command to the NAND command queue. */ -static int ndf_submit(struct octeontx_nfc *tn, union ndf_cmd *cmd) -{ - int opcode = cmd->val[0] & 0xf; - - switch (opcode) { - /* All these commands fit in one 64bit word */ - case NDF_OP_NOP: - case NDF_OP_SET_TM_PAR: - case NDF_OP_WAIT: - case NDF_OP_CHIP_EN_DIS: - case NDF_OP_CLE_CMD: - case NDF_OP_WR_CMD: - case NDF_OP_RD_CMD: - case NDF_OP_RD_EDO_CMD: - case NDF_OP_BUS_ACQ_REL: - if (ndf_cmd_queue_free(tn) < 8) - goto full; - writeq(cmd->val[0], tn->base + NDF_CMD); - break; - case NDF_OP_ALE_CMD: - /* ALE commands take either one or two 64bit words */ - if (cmd->u.ale_cmd.adr_byte_num < 5) { - if (ndf_cmd_queue_free(tn) < 8) - goto full; - writeq(cmd->val[0], tn->base + NDF_CMD); - } else { - if (ndf_cmd_queue_free(tn) < 16) - goto full; - writeq(cmd->val[0], tn->base + NDF_CMD); - writeq(cmd->val[1], tn->base + NDF_CMD); - } - break; - case NDF_OP_WAIT_STATUS: /* Wait status commands take two 64bit words */ - if (ndf_cmd_queue_free(tn) < 16) - goto full; - writeq(cmd->val[0], tn->base + NDF_CMD); - writeq(cmd->val[1], tn->base + NDF_CMD); - break; - default: - dev_err(tn->dev, "%s: unknown command: %u\n", __func__, opcode); - return -EINVAL; - } - return 0; - -full: - dev_err(tn->dev, "%s: no space left in command queue\n", __func__); - return -ENOMEM; -} - -/** - * Wait for the ready/busy signal. First wait for busy to be valid, - * then wait for busy to de-assert. - */ -static int ndf_build_wait_busy(struct octeontx_nfc *tn) -{ - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.wait.opcode = NDF_OP_WAIT; - cmd.u.wait.r_b = 1; - cmd.u.wait.wlen = t6; - - if (ndf_submit(tn, &cmd)) - return -ENOMEM; - return 0; -} - -static bool ndf_dma_done(struct octeontx_nfc *tn) -{ - u64 dma_cfg; - - /* Enable bit should be clear after a transfer */ - dma_cfg = readq(tn->base + NDF_DMA_CFG); - if (!(dma_cfg & NDF_DMA_CFG_EN)) - return true; - - return false; -} - -static int ndf_wait(struct octeontx_nfc *tn) -{ - ulong start = get_timer(0); - bool done; - - while (!(done = ndf_dma_done(tn)) && get_timer(start) < NDF_TIMEOUT) - ; - - if (!done) { - dev_err(tn->dev, "%s: timeout error\n", __func__); - return -ETIMEDOUT; - } - return 0; -} - -static int ndf_wait_idle(struct octeontx_nfc *tn) -{ - u64 val; - u64 dval = 0; - int rc; - int pause = 100; - u64 tot_us = USEC_PER_SEC / 10; - - rc = readq_poll_timeout(tn->base + NDF_ST_REG, - val, val & NDF_ST_REG_EXE_IDLE, pause, tot_us); - if (!rc) - rc = readq_poll_timeout(tn->base + NDF_DMA_CFG, - dval, !(dval & NDF_DMA_CFG_EN), - pause, tot_us); - - return rc; -} - -/** Issue set timing parameters */ -static int ndf_queue_cmd_timing(struct octeontx_nfc *tn, - struct ndf_set_tm_par_cmd *timings) -{ - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.set_tm_par.opcode = NDF_OP_SET_TM_PAR; - cmd.u.set_tm_par.tim_mult = timings->tim_mult; - cmd.u.set_tm_par.tm_par1 = timings->tm_par1; - cmd.u.set_tm_par.tm_par2 = timings->tm_par2; - cmd.u.set_tm_par.tm_par3 = timings->tm_par3; - cmd.u.set_tm_par.tm_par4 = timings->tm_par4; - cmd.u.set_tm_par.tm_par5 = timings->tm_par5; - cmd.u.set_tm_par.tm_par6 = timings->tm_par6; - cmd.u.set_tm_par.tm_par7 = timings->tm_par7; - return ndf_submit(tn, &cmd); -} - -/** Issue bus acquire or release */ -static int ndf_queue_cmd_bus(struct octeontx_nfc *tn, int direction) -{ - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.bus_acq_rel.opcode = NDF_OP_BUS_ACQ_REL; - cmd.u.bus_acq_rel.direction = direction; - return ndf_submit(tn, &cmd); -} - -/* Issue chip select or deselect */ -static int ndf_queue_cmd_chip(struct octeontx_nfc *tn, int enable, int chip, - int width) -{ - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.chip_en_dis.opcode = NDF_OP_CHIP_EN_DIS; - cmd.u.chip_en_dis.chip = chip; - cmd.u.chip_en_dis.enable = enable; - cmd.u.chip_en_dis.bus_width = width; - return ndf_submit(tn, &cmd); -} - -static int ndf_queue_cmd_wait(struct octeontx_nfc *tn, int t_delay) -{ - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.wait.opcode = NDF_OP_WAIT; - cmd.u.wait.wlen = t_delay; - return ndf_submit(tn, &cmd); -} - -static int ndf_queue_cmd_cle(struct octeontx_nfc *tn, int command) -{ - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.cle_cmd.opcode = NDF_OP_CLE_CMD; - cmd.u.cle_cmd.cmd_data = command; - cmd.u.cle_cmd.clen1 = t4; - cmd.u.cle_cmd.clen2 = t1; - cmd.u.cle_cmd.clen3 = t2; - return ndf_submit(tn, &cmd); -} - -static int ndf_queue_cmd_ale(struct octeontx_nfc *tn, int addr_bytes, - struct nand_chip *nand, u64 page, - u32 col, int page_size) -{ - struct octeontx_nand_chip *octeontx_nand = (nand) ? - to_otx_nand(nand) : NULL; - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.ale_cmd.opcode = NDF_OP_ALE_CMD; - cmd.u.ale_cmd.adr_byte_num = addr_bytes; - - /* set column bit for OOB area, assume OOB follows page */ - if (octeontx_nand && octeontx_nand->oob_only) - col += page_size; - - /* page is u64 for this generality, even if cmdfunc() passes int */ - switch (addr_bytes) { - /* 4-8 bytes: page, then 2-byte col */ - case 8: - cmd.u.ale_cmd.adr_byt8 = (page >> 40) & 0xff; - fallthrough; - case 7: - cmd.u.ale_cmd.adr_byt7 = (page >> 32) & 0xff; - fallthrough; - case 6: - cmd.u.ale_cmd.adr_byt6 = (page >> 24) & 0xff; - fallthrough; - case 5: - cmd.u.ale_cmd.adr_byt5 = (page >> 16) & 0xff; - fallthrough; - case 4: - cmd.u.ale_cmd.adr_byt4 = (page >> 8) & 0xff; - cmd.u.ale_cmd.adr_byt3 = page & 0xff; - cmd.u.ale_cmd.adr_byt2 = (col >> 8) & 0xff; - cmd.u.ale_cmd.adr_byt1 = col & 0xff; - break; - /* 1-3 bytes: just the page address */ - case 3: - cmd.u.ale_cmd.adr_byt3 = (page >> 16) & 0xff; - fallthrough; - case 2: - cmd.u.ale_cmd.adr_byt2 = (page >> 8) & 0xff; - fallthrough; - case 1: - cmd.u.ale_cmd.adr_byt1 = page & 0xff; - break; - default: - break; - } - - cmd.u.ale_cmd.alen1 = t3; - cmd.u.ale_cmd.alen2 = t1; - cmd.u.ale_cmd.alen3 = t5; - cmd.u.ale_cmd.alen4 = t2; - return ndf_submit(tn, &cmd); -} - -static int ndf_queue_cmd_write(struct octeontx_nfc *tn, int len) -{ - union ndf_cmd cmd; - - memset(&cmd, 0, sizeof(cmd)); - cmd.u.wr_cmd.opcode = NDF_OP_WR_CMD; - cmd.u.wr_cmd.data = len; - cmd.u.wr_cmd.wlen1 = t3; - cmd.u.wr_cmd.wlen2 = t1; - return ndf_submit(tn, &cmd); -} - -static int ndf_build_pre_cmd(struct octeontx_nfc *tn, int cmd1, - int addr_bytes, u64 page, u32 col, int cmd2) -{ - struct nand_chip *nand = tn->controller.active; - struct octeontx_nand_chip *octeontx_nand; - struct ndf_set_tm_par_cmd *timings; - int width, page_size, rc; - - /* Also called before chip probing is finished */ - if (!nand) { - timings = &default_timing_parms; - page_size = default_page_size; - width = default_width; - } else { - octeontx_nand = to_otx_nand(nand); - timings = &octeontx_nand->timings; - page_size = nand->mtd.writesize; - if (nand->options & NAND_BUSWIDTH_16) - width = 2; - else - width = 1; - } - rc = ndf_queue_cmd_timing(tn, timings); - if (rc) - return rc; - - rc = ndf_queue_cmd_bus(tn, NDF_BUS_ACQUIRE); - if (rc) - return rc; - - rc = ndf_queue_cmd_chip(tn, 1, tn->selected_chip, width); - if (rc) - return rc; - - rc = ndf_queue_cmd_wait(tn, t1); - if (rc) - return rc; - - rc = ndf_queue_cmd_cle(tn, cmd1); - if (rc) - return rc; - - if (addr_bytes) { - rc = ndf_build_wait_busy(tn); - if (rc) - return rc; - - rc = ndf_queue_cmd_ale(tn, addr_bytes, nand, - page, col, page_size); - if (rc) - return rc; - } - - /* CLE 2 */ - if (cmd2) { - rc = ndf_build_wait_busy(tn); - if (rc) - return rc; - - rc = ndf_queue_cmd_cle(tn, cmd2); - if (rc) - return rc; - } - return 0; -} - -static int ndf_build_post_cmd(struct octeontx_nfc *tn, int hold_time) -{ - int rc; - - /* Deselect chip */ - rc = ndf_queue_cmd_chip(tn, 0, 0, 0); - if (rc) - return rc; - - rc = ndf_queue_cmd_wait(tn, t2); - if (rc) - return rc; - - /* Release bus */ - rc = ndf_queue_cmd_bus(tn, 0); - if (rc) - return rc; - - rc = ndf_queue_cmd_wait(tn, hold_time); - if (rc) - return rc; - - /* - * Last action is ringing the doorbell with number of bus - * acquire-releases cycles (currently 1). - */ - writeq(1, tn->base + NDF_DRBELL); - return 0; -} - -/* Setup the NAND DMA engine for a transfer. */ -static void ndf_setup_dma(struct octeontx_nfc *tn, int is_write, - dma_addr_t bus_addr, int len) -{ - u64 dma_cfg; - - dma_cfg = FIELD_PREP(NDF_DMA_CFG_RW, is_write) | - FIELD_PREP(NDF_DMA_CFG_SIZE, (len >> 3) - 1); - dma_cfg |= NDF_DMA_CFG_EN; - writeq(bus_addr, tn->base + NDF_DMA_ADR); - writeq(dma_cfg, tn->base + NDF_DMA_CFG); -} - -static int octeontx_nand_reset(struct octeontx_nfc *tn) -{ - int rc; - - rc = ndf_build_pre_cmd(tn, NAND_CMD_RESET, 0, 0, 0, 0); - if (rc) - return rc; - - rc = ndf_build_wait_busy(tn); - if (rc) - return rc; - - rc = ndf_build_post_cmd(tn, t2); - if (rc) - return rc; - - return 0; -} - -static int ndf_read(struct octeontx_nfc *tn, int cmd1, int addr_bytes, - u64 page, u32 col, int cmd2, int len) -{ - dma_addr_t bus_addr = tn->use_status ? tn->stat_addr : tn->buf.dmaaddr; - struct nand_chip *nand = tn->controller.active; - int timing_mode, bytes, rc; - union ndf_cmd cmd; - u64 start, end; - - pr_debug("%s(%p, 0x%x, 0x%x, 0x%llx, 0x%x, 0x%x, 0x%x)\n", __func__, - tn, cmd1, addr_bytes, page, col, cmd2, len); - if (!nand) - timing_mode = default_onfi_timing; - else - timing_mode = nand->onfi_timing_mode_default; - - /* Build the command and address cycles */ - rc = ndf_build_pre_cmd(tn, cmd1, addr_bytes, page, col, cmd2); - if (rc) { - dev_err(tn->dev, "Build pre command failed\n"); - return rc; - } - - /* This waits for some time, then waits for busy to be de-asserted. */ - rc = ndf_build_wait_busy(tn); - if (rc) { - dev_err(tn->dev, "Wait timeout\n"); - return rc; - } - - memset(&cmd, 0, sizeof(cmd)); - - if (timing_mode < 4) - cmd.u.rd_cmd.opcode = NDF_OP_RD_CMD; - else - cmd.u.rd_cmd.opcode = NDF_OP_RD_EDO_CMD; - - cmd.u.rd_cmd.data = len; - cmd.u.rd_cmd.rlen1 = t7; - cmd.u.rd_cmd.rlen2 = t3; - cmd.u.rd_cmd.rlen3 = t1; - cmd.u.rd_cmd.rlen4 = t7; - rc = ndf_submit(tn, &cmd); - if (rc) { - dev_err(tn->dev, "Error submitting command\n"); - return rc; - } - - start = (u64)bus_addr; - ndf_setup_dma(tn, 0, bus_addr, len); - - rc = ndf_build_post_cmd(tn, t2); - if (rc) { - dev_err(tn->dev, "Build post command failed\n"); - return rc; - } - - /* Wait for the DMA to complete */ - rc = ndf_wait(tn); - if (rc) { - dev_err(tn->dev, "DMA timed out\n"); - return rc; - } - - end = readq(tn->base + NDF_DMA_ADR); - bytes = end - start; - - /* Make sure NDF is really done */ - rc = ndf_wait_idle(tn); - if (rc) { - dev_err(tn->dev, "poll idle failed\n"); - return rc; - } - - pr_debug("%s: Read %d bytes\n", __func__, bytes); - return bytes; -} - -static int octeontx_nand_get_features(struct mtd_info *mtd, - struct nand_chip *chip, int feature_addr, - u8 *subfeature_para) -{ - struct nand_chip *nand = chip; - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - int len = 8; - int rc; - - pr_debug("%s: feature addr: 0x%x\n", __func__, feature_addr); - memset(tn->buf.dmabuf, 0xff, len); - tn->buf.data_index = 0; - tn->buf.data_len = 0; - rc = ndf_read(tn, NAND_CMD_GET_FEATURES, 1, feature_addr, 0, 0, len); - if (rc) - return rc; - - memcpy(subfeature_para, tn->buf.dmabuf, ONFI_SUBFEATURE_PARAM_LEN); - - return 0; -} - -static int octeontx_nand_set_features(struct mtd_info *mtd, - struct nand_chip *chip, int feature_addr, - u8 *subfeature_para) -{ - struct nand_chip *nand = chip; - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - const int len = ONFI_SUBFEATURE_PARAM_LEN; - int rc; - - rc = ndf_build_pre_cmd(tn, NAND_CMD_SET_FEATURES, - 1, feature_addr, 0, 0); - if (rc) - return rc; - - memcpy(tn->buf.dmabuf, subfeature_para, len); - memset(tn->buf.dmabuf + len, 0, 8 - len); - - ndf_setup_dma(tn, 1, tn->buf.dmaaddr, 8); - - rc = ndf_queue_cmd_write(tn, 8); - if (rc) - return rc; - - rc = ndf_build_wait_busy(tn); - if (rc) - return rc; - - rc = ndf_build_post_cmd(tn, t2); - if (rc) - return rc; - - return 0; -} - -/* - * Read a page from NAND. If the buffer has room, the out of band - * data will be included. - */ -static int ndf_page_read(struct octeontx_nfc *tn, u64 page, int col, int len) -{ - debug("%s(%p, 0x%llx, 0x%x, 0x%x) active: %p\n", __func__, - tn, page, col, len, tn->controller.active); - struct nand_chip *nand = tn->controller.active; - struct octeontx_nand_chip *chip = to_otx_nand(nand); - int addr_bytes = chip->row_bytes + chip->col_bytes; - - memset(tn->buf.dmabuf, 0xff, len); - return ndf_read(tn, NAND_CMD_READ0, addr_bytes, - page, col, NAND_CMD_READSTART, len); -} - -/* Erase a NAND block */ -static int ndf_block_erase(struct octeontx_nfc *tn, u64 page_addr) -{ - struct nand_chip *nand = tn->controller.active; - struct octeontx_nand_chip *chip = to_otx_nand(nand); - int addr_bytes = chip->row_bytes; - int rc; - - rc = ndf_build_pre_cmd(tn, NAND_CMD_ERASE1, addr_bytes, - page_addr, 0, NAND_CMD_ERASE2); - if (rc) - return rc; - - /* Wait for R_B to signal erase is complete */ - rc = ndf_build_wait_busy(tn); - if (rc) - return rc; - - rc = ndf_build_post_cmd(tn, t2); - if (rc) - return rc; - - /* Wait until the command queue is idle */ - return ndf_wait_idle(tn); -} - -/* - * Write a page (or less) to NAND. - */ -static int ndf_page_write(struct octeontx_nfc *tn, int page) -{ - int len, rc; - struct nand_chip *nand = tn->controller.active; - struct octeontx_nand_chip *chip = to_otx_nand(nand); - int addr_bytes = chip->row_bytes + chip->col_bytes; - - len = tn->buf.data_len - tn->buf.data_index; - chip->oob_only = (tn->buf.data_index >= nand->mtd.writesize); - WARN_ON_ONCE(len & 0x7); - - ndf_setup_dma(tn, 1, tn->buf.dmaaddr + tn->buf.data_index, len); - rc = ndf_build_pre_cmd(tn, NAND_CMD_SEQIN, addr_bytes, page, 0, 0); - if (rc) - return rc; - - rc = ndf_queue_cmd_write(tn, len); - if (rc) - return rc; - - rc = ndf_queue_cmd_cle(tn, NAND_CMD_PAGEPROG); - if (rc) - return rc; - - /* Wait for R_B to signal program is complete */ - rc = ndf_build_wait_busy(tn); - if (rc) - return rc; - - rc = ndf_build_post_cmd(tn, t2); - if (rc) - return rc; - - /* Wait for the DMA to complete */ - rc = ndf_wait(tn); - if (rc) - return rc; - - /* Data transfer is done but NDF is not, it is waiting for R/B# */ - return ndf_wait_idle(tn); -} - -static void octeontx_nand_cmdfunc(struct mtd_info *mtd, unsigned int command, - int column, int page_addr) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nand_chip *octeontx_nand = to_otx_nand(nand); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - int rc; - - tn->selected_chip = octeontx_nand->cs; - if (tn->selected_chip < 0 || tn->selected_chip >= NAND_MAX_CHIPS) { - dev_err(tn->dev, "invalid chip select\n"); - return; - } - - tn->use_status = false; - - pr_debug("%s(%p, 0x%x, 0x%x, 0x%x) cs: %d\n", __func__, mtd, command, - column, page_addr, tn->selected_chip); - switch (command) { - case NAND_CMD_READID: - tn->buf.data_index = 0; - octeontx_nand->oob_only = false; - rc = ndf_read(tn, command, 1, column, 0, 0, 8); - if (rc < 0) - dev_err(tn->dev, "READID failed with %d\n", rc); - else - tn->buf.data_len = rc; - break; - - case NAND_CMD_READOOB: - octeontx_nand->oob_only = true; - tn->buf.data_index = 0; - tn->buf.data_len = 0; - rc = ndf_page_read(tn, page_addr, column, mtd->oobsize); - if (rc < mtd->oobsize) - dev_err(tn->dev, "READOOB failed with %d\n", - tn->buf.data_len); - else - tn->buf.data_len = rc; - break; - - case NAND_CMD_READ0: - octeontx_nand->oob_only = false; - tn->buf.data_index = 0; - tn->buf.data_len = 0; - rc = ndf_page_read(tn, page_addr, column, - mtd->writesize + mtd->oobsize); - - if (rc < mtd->writesize + mtd->oobsize) - dev_err(tn->dev, "READ0 failed with %d\n", rc); - else - tn->buf.data_len = rc; - break; - - case NAND_CMD_STATUS: - /* used in oob/not states */ - tn->use_status = true; - rc = ndf_read(tn, command, 0, 0, 0, 0, 8); - if (rc < 0) - dev_err(tn->dev, "STATUS failed with %d\n", rc); - break; - - case NAND_CMD_RESET: - /* used in oob/not states */ - rc = octeontx_nand_reset(tn); - if (rc < 0) - dev_err(tn->dev, "RESET failed with %d\n", rc); - break; - - case NAND_CMD_PARAM: - octeontx_nand->oob_only = false; - tn->buf.data_index = 0; - rc = ndf_read(tn, command, 1, 0, 0, 0, - min(tn->buf.dmabuflen, 3 * 512)); - if (rc < 0) - dev_err(tn->dev, "PARAM failed with %d\n", rc); - else - tn->buf.data_len = rc; - break; - - case NAND_CMD_RNDOUT: - tn->buf.data_index = column; - break; - - case NAND_CMD_ERASE1: - if (ndf_block_erase(tn, page_addr)) - dev_err(tn->dev, "ERASE1 failed\n"); - break; - - case NAND_CMD_ERASE2: - /* We do all erase processing in the first command, so ignore - * this one. - */ - break; - - case NAND_CMD_SEQIN: - octeontx_nand->oob_only = (column >= mtd->writesize); - tn->buf.data_index = column; - tn->buf.data_len = column; - - octeontx_nand->selected_page = page_addr; - break; - - case NAND_CMD_PAGEPROG: - rc = ndf_page_write(tn, octeontx_nand->selected_page); - if (rc) - dev_err(tn->dev, "PAGEPROG failed with %d\n", rc); - break; - - case NAND_CMD_SET_FEATURES: - octeontx_nand->oob_only = false; - /* assume tn->buf.data_len == 4 of data has been set there */ - rc = octeontx_nand_set_features(mtd, nand, - page_addr, tn->buf.dmabuf); - if (rc) - dev_err(tn->dev, "SET_FEATURES failed with %d\n", rc); - break; - - case NAND_CMD_GET_FEATURES: - octeontx_nand->oob_only = false; - rc = octeontx_nand_get_features(mtd, nand, - page_addr, tn->buf.dmabuf); - if (!rc) { - tn->buf.data_index = 0; - tn->buf.data_len = 4; - } else { - dev_err(tn->dev, "GET_FEATURES failed with %d\n", rc); - } - break; - - default: - WARN_ON_ONCE(1); - dev_err(tn->dev, "unhandled nand cmd: %x\n", command); - } -} - -static int octeontx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) -{ - struct octeontx_nfc *tn = to_otx_nfc(chip->controller); - int ret; - - ret = ndf_wait_idle(tn); - return (ret < 0) ? -EIO : 0; -} - -/* check compatibility with ONFI timing mode#N, and optionally apply */ -/* TODO: Implement chipnr support? */ -static int octeontx_nand_setup_dat_intf(struct mtd_info *mtd, int chipnr, - const struct nand_data_interface *conf) -{ - static const bool check_only; - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nand_chip *chip = to_otx_nand(nand); - static u64 t_wc_n[MAX_ONFI_MODE + 2]; /* cache a mode signature */ - int mode; /* deduced mode number, for reporting and restricting */ - int rc; - - /* - * Cache timing modes for reporting, and reducing needless change. - * - * Challenge: caller does not pass ONFI mode#, but reporting the mode - * and restricting to a maximum, or a list, are useful for diagnosing - * new hardware. So use tWC_min, distinct and monotonic across modes, - * to discover the requested/accepted mode number - */ - for (mode = MAX_ONFI_MODE; mode >= 0 && !t_wc_n[0]; mode--) { - const struct nand_sdr_timings *t; - - t = onfi_async_timing_mode_to_sdr_timings(mode); - if (!t) - continue; - t_wc_n[mode] = t->tWC_min; - } - - if (!conf) { - rc = -EINVAL; - } else if (check_only) { - rc = 0; - } else if (nand->data_interface && - chip->iface_set && chip->iface_mode == mode) { - /* - * Cases: - * - called from nand_reset, which clears DDR timing - * mode back to SDR. BUT if we're already in SDR, - * timing mode persists over resets. - * While mtd/nand layer only supports SDR, - * this is always safe. And this driver only supports SDR. - * - * - called from post-power-event nand_reset (maybe - * NFC+flash power down, or system hibernate. - * Address this when CONFIG_PM support added - */ - rc = 0; - } else { - rc = octeontx_nfc_chip_set_timings(chip, &conf->timings.sdr); - if (!rc) { - chip->iface_mode = mode; - chip->iface_set = true; - } - } - return rc; -} - -static void octeontx_bch_reset(void) -{ -} - -/* - * Given a page, calculate the ECC code - * - * chip: Pointer to NAND chip data structure - * buf: Buffer to calculate ECC on - * code: Buffer to hold ECC data - * - * Return 0 on success or -1 on failure - */ -static int octeontx_nand_bch_calculate_ecc_internal(struct mtd_info *mtd, - dma_addr_t ihandle, - u8 *code) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - int rc; - int i; - static u8 *ecc_buffer; - static int ecc_size; - static unsigned long ecc_handle; - union bch_resp *r = tn->bch_resp; - - if (!ecc_buffer || ecc_size < nand->ecc.size) { - ecc_size = nand->ecc.size; - ecc_buffer = dma_alloc_coherent(ecc_size, - (unsigned long *)&ecc_handle); - } - - memset(ecc_buffer, 0, nand->ecc.bytes); - - r->u16 = 0; - __iowmb(); /* flush done=0 before making request */ - - rc = octeontx_bch_encode(bch_vf, ihandle, nand->ecc.size, - nand->ecc.strength, - (dma_addr_t)ecc_handle, tn->bch_rhandle); - - if (!rc) { - octeontx_bch_wait(bch_vf, r, tn->bch_rhandle); - } else { - dev_err(tn->dev, "octeontx_bch_encode failed\n"); - return -1; - } - - if (!r->s.done || r->s.uncorrectable) { - dev_err(tn->dev, - "%s timeout, done:%d uncorr:%d corr:%d erased:%d\n", - __func__, r->s.done, r->s.uncorrectable, - r->s.num_errors, r->s.erased); - octeontx_bch_reset(); - return -1; - } - - memcpy(code, ecc_buffer, nand->ecc.bytes); - - for (i = 0; i < nand->ecc.bytes; i++) - code[i] ^= tn->eccmask[i]; - - return tn->bch_resp->s.num_errors; -} - -/* - * Given a page, calculate the ECC code - * - * mtd: MTD block structure - * dat: raw data (unused) - * ecc_code: buffer for ECC - */ -static int octeontx_nand_bch_calculate(struct mtd_info *mtd, - const u8 *dat, u8 *ecc_code) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - dma_addr_t handle = dma_map_single((u8 *)dat, - nand->ecc.size, DMA_TO_DEVICE); - int ret; - - ret = octeontx_nand_bch_calculate_ecc_internal(mtd, handle, - (void *)ecc_code); - - return ret; -} - -/* - * Detect and correct multi-bit ECC for a page - * - * mtd: MTD block structure - * dat: raw data read from the chip - * read_ecc: ECC from the chip (unused) - * isnull: unused - * - * Returns number of bits corrected or -1 if unrecoverable - */ -static int octeontx_nand_bch_correct(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *isnull) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - int i = nand->ecc.size + nand->ecc.bytes; - static u8 *data_buffer; - static dma_addr_t ihandle; - static int buffer_size; - dma_addr_t ohandle; - union bch_resp *r = tn->bch_resp; - int rc; - - if (i > buffer_size) { - if (buffer_size) - free(data_buffer); - data_buffer = dma_alloc_coherent(i, - (unsigned long *)&ihandle); - if (!data_buffer) { - dev_err(tn->dev, - "%s: Could not allocate %d bytes for buffer\n", - __func__, i); - goto error; - } - buffer_size = i; - } - - memcpy(data_buffer, dat, nand->ecc.size); - memcpy(data_buffer + nand->ecc.size, read_ecc, nand->ecc.bytes); - - for (i = 0; i < nand->ecc.bytes; i++) - data_buffer[nand->ecc.size + i] ^= tn->eccmask[i]; - - r->u16 = 0; - __iowmb(); /* flush done=0 before making request */ - - ohandle = dma_map_single(dat, nand->ecc.size, DMA_FROM_DEVICE); - rc = octeontx_bch_decode(bch_vf, ihandle, nand->ecc.size, - nand->ecc.strength, ohandle, tn->bch_rhandle); - - if (!rc) - octeontx_bch_wait(bch_vf, r, tn->bch_rhandle); - - if (rc) { - dev_err(tn->dev, "octeontx_bch_decode failed\n"); - goto error; - } - - if (!r->s.done) { - dev_err(tn->dev, "Error: BCH engine timeout\n"); - octeontx_bch_reset(); - goto error; - } - - if (r->s.erased) { - debug("Info: BCH block is erased\n"); - return 0; - } - - if (r->s.uncorrectable) { - debug("Cannot correct NAND block, response: 0x%x\n", - r->u16); - goto error; - } - - return r->s.num_errors; - -error: - debug("Error performing bch correction\n"); - return -1; -} - -void octeontx_nand_bch_hwctl(struct mtd_info *mtd, int mode) -{ - /* Do nothing. */ -} - -static int octeontx_nand_hw_bch_read_page(struct mtd_info *mtd, - struct nand_chip *chip, u8 *buf, - int oob_required, int page) -{ - struct nand_chip *nand = mtd_to_nand(mtd); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - u8 *p; - u8 *ecc_code = chip->buffers->ecccode; - unsigned int max_bitflips = 0; - - /* chip->read_buf() insists on sequential order, we do OOB first */ - memcpy(chip->oob_poi, tn->buf.dmabuf + mtd->writesize, mtd->oobsize); - - /* Use private buffer as input for ECC correction */ - p = tn->buf.dmabuf; - - ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, - chip->ecc.total); - if (ret) - return ret; - - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - int stat; - - debug("Correcting block offset %lx, ecc offset %x\n", - p - buf, i); - stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); - - if (stat < 0) { - mtd->ecc_stats.failed++; - debug("Cannot correct NAND page %d\n", page); - } else { - mtd->ecc_stats.corrected += stat; - max_bitflips = max_t(unsigned int, max_bitflips, stat); - } - } - - /* Copy corrected data to caller's buffer now */ - memcpy(buf, tn->buf.dmabuf, mtd->writesize); - - return max_bitflips; -} - -static int octeontx_nand_hw_bch_write_page(struct mtd_info *mtd, - struct nand_chip *chip, - const u8 *buf, int oob_required, - int page) -{ - struct octeontx_nfc *tn = to_otx_nfc(chip->controller); - int i, eccsize = chip->ecc.size, ret; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - const u8 *p; - u8 *ecc_calc = chip->buffers->ecccalc; - - debug("%s(buf?%p, oob%d p%x)\n", - __func__, buf, oob_required, page); - for (i = 0; i < chip->ecc.total; i++) - ecc_calc[i] = 0xFF; - - /* Copy the page data from caller's buffers to private buffer */ - chip->write_buf(mtd, buf, mtd->writesize); - /* Use private date as source for ECC calculation */ - p = tn->buf.dmabuf; - - /* Hardware ECC calculation */ - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - int ret; - - ret = chip->ecc.calculate(mtd, p, &ecc_calc[i]); - - if (ret < 0) - debug("calculate(mtd, p?%p, &ecc_calc[%d]?%p) returned %d\n", - p, i, &ecc_calc[i], ret); - - debug("block offset %lx, ecc offset %x\n", p - buf, i); - } - - ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0, - chip->ecc.total); - if (ret) - return ret; - - /* Store resulting OOB into private buffer, will be sent to HW */ - chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); - - return 0; -} - -/** - * nand_write_page_raw - [INTERN] raw page write function - * @mtd: mtd info structure - * @chip: nand chip info structure - * @buf: data buffer - * @oob_required: must write chip->oob_poi to OOB - * @page: page number to write - * - * Not for syndrome calculating ECC controllers, which use a special oob layout. - */ -static int octeontx_nand_write_page_raw(struct mtd_info *mtd, - struct nand_chip *chip, - const u8 *buf, int oob_required, - int page) -{ - chip->write_buf(mtd, buf, mtd->writesize); - if (oob_required) - chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); - - return 0; -} - -/** - * octeontx_nand_write_oob_std - [REPLACEABLE] the most common OOB data write - * function - * @mtd: mtd info structure - * @chip: nand chip info structure - * @page: page number to write - */ -static int octeontx_nand_write_oob_std(struct mtd_info *mtd, - struct nand_chip *chip, - int page) -{ - int status = 0; - const u8 *buf = chip->oob_poi; - int length = mtd->oobsize; - - chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); - chip->write_buf(mtd, buf, length); - /* Send command to program the OOB data */ - chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); - - status = chip->waitfunc(mtd, chip); - - return status & NAND_STATUS_FAIL ? -EIO : 0; -} - -/** - * octeontx_nand_read_page_raw - [INTERN] read raw page data without ecc - * @mtd: mtd info structure - * @chip: nand chip info structure - * @buf: buffer to store read data - * @oob_required: caller requires OOB data read to chip->oob_poi - * @page: page number to read - * - * Not for syndrome calculating ECC controllers, which use a special oob layout. - */ -static int octeontx_nand_read_page_raw(struct mtd_info *mtd, - struct nand_chip *chip, - u8 *buf, int oob_required, int page) -{ - chip->read_buf(mtd, buf, mtd->writesize); - if (oob_required) - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); - return 0; -} - -static int octeontx_nand_read_oob_std(struct mtd_info *mtd, - struct nand_chip *chip, - int page) - -{ - chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); - chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); - return 0; -} - -static int octeontx_nand_calc_bch_ecc_strength(struct nand_chip *nand) -{ - struct mtd_info *mtd = nand_to_mtd(nand); - struct nand_ecc_ctrl *ecc = &nand->ecc; - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - int nsteps = mtd->writesize / ecc->size; - int oobchunk = mtd->oobsize / nsteps; - - /* ecc->strength determines ecc_level and OOB's ecc_bytes. */ - const u8 strengths[] = {4, 8, 16, 24, 32, 40, 48, 56, 60, 64}; - /* first set the desired ecc_level to match strengths[] */ - int index = ARRAY_SIZE(strengths) - 1; - int need; - - while (index > 0 && !(ecc->options & NAND_ECC_MAXIMIZE) && - strengths[index - 1] >= ecc->strength) - index--; - - do { - need = DIV_ROUND_UP(15 * strengths[index], 8); - if (need <= oobchunk - 2) - break; - } while (index > 0); - - debug("%s: steps ds: %d, strength ds: %d\n", __func__, - nand->ecc_step_ds, nand->ecc_strength_ds); - ecc->strength = strengths[index]; - ecc->bytes = need; - debug("%s: strength: %d, bytes: %d\n", __func__, ecc->strength, - ecc->bytes); - - if (!tn->eccmask) - tn->eccmask = devm_kzalloc(tn->dev, ecc->bytes, GFP_KERNEL); - if (!tn->eccmask) - return -ENOMEM; - - return 0; -} - -/* sample the BCH signature of an erased (all 0xff) page, - * to XOR into all page traffic, so erased pages have no ECC errors - */ -static int octeontx_bch_save_empty_eccmask(struct nand_chip *nand) -{ - struct mtd_info *mtd = nand_to_mtd(nand); - struct octeontx_nfc *tn = to_otx_nfc(nand->controller); - unsigned int eccsize = nand->ecc.size; - unsigned int eccbytes = nand->ecc.bytes; - u8 erased_ecc[eccbytes]; - unsigned long erased_handle; - unsigned char *erased_page = dma_alloc_coherent(eccsize, - &erased_handle); - int i; - int rc = 0; - - if (!erased_page) - return -ENOMEM; - - memset(erased_page, 0xff, eccsize); - memset(erased_ecc, 0, eccbytes); - - rc = octeontx_nand_bch_calculate_ecc_internal(mtd, - (dma_addr_t)erased_handle, - erased_ecc); - - free(erased_page); - - for (i = 0; i < eccbytes; i++) - tn->eccmask[i] = erased_ecc[i] ^ 0xff; - - return rc; -} - -static void octeontx_nfc_chip_sizing(struct nand_chip *nand) -{ - struct octeontx_nand_chip *chip = to_otx_nand(nand); - struct mtd_info *mtd = nand_to_mtd(nand); - struct nand_ecc_ctrl *ecc = &nand->ecc; - - chip->row_bytes = nand->onfi_params.addr_cycles & 0xf; - chip->col_bytes = nand->onfi_params.addr_cycles >> 4; - debug("%s(%p) row bytes: %d, col bytes: %d, ecc mode: %d\n", - __func__, nand, chip->row_bytes, chip->col_bytes, ecc->mode); - - /* - * HW_BCH using OcteonTX BCH engine, or SOFT_BCH laid out in - * HW_BCH-compatible fashion, depending on devtree advice - * and kernel config. - * BCH/NFC hardware capable of subpage ops, not implemented. - */ - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); - nand->options |= NAND_NO_SUBPAGE_WRITE; - debug("%s: start steps: %d, size: %d, bytes: %d\n", - __func__, ecc->steps, ecc->size, ecc->bytes); - debug("%s: step ds: %d, strength ds: %d\n", __func__, - nand->ecc_step_ds, nand->ecc_strength_ds); - - if (ecc->mode != NAND_ECC_NONE) { - int nsteps = ecc->steps ? ecc->steps : 1; - - if (ecc->size && ecc->size != mtd->writesize) - nsteps = mtd->writesize / ecc->size; - else if (mtd->writesize > def_ecc_size && - !(mtd->writesize & (def_ecc_size - 1))) - nsteps = mtd->writesize / def_ecc_size; - ecc->steps = nsteps; - ecc->size = mtd->writesize / nsteps; - ecc->bytes = mtd->oobsize / nsteps; - - if (nand->ecc_strength_ds) - ecc->strength = nand->ecc_strength_ds; - if (nand->ecc_step_ds) - ecc->size = nand->ecc_step_ds; - /* - * no subpage ops, but set subpage-shift to match ecc->steps - * so mtd_nandbiterrs tests appropriate boundaries - */ - if (!mtd->subpage_sft && !(ecc->steps & (ecc->steps - 1))) - mtd->subpage_sft = fls(ecc->steps) - 1; - - if (IS_ENABLED(CONFIG_NAND_OCTEONTX_HW_ECC)) { - debug("%s: ecc mode: %d\n", __func__, ecc->mode); - if (ecc->mode != NAND_ECC_SOFT && - !octeontx_nand_calc_bch_ecc_strength(nand)) { - struct octeontx_nfc *tn = - to_otx_nfc(nand->controller); - - debug("Using hardware BCH engine support\n"); - ecc->mode = NAND_ECC_HW_SYNDROME; - ecc->read_page = octeontx_nand_hw_bch_read_page; - ecc->write_page = - octeontx_nand_hw_bch_write_page; - ecc->read_page_raw = - octeontx_nand_read_page_raw; - ecc->write_page_raw = - octeontx_nand_write_page_raw; - ecc->read_oob = octeontx_nand_read_oob_std; - ecc->write_oob = octeontx_nand_write_oob_std; - - ecc->calculate = octeontx_nand_bch_calculate; - ecc->correct = octeontx_nand_bch_correct; - ecc->hwctl = octeontx_nand_bch_hwctl; - - debug("NAND chip %d using hw_bch\n", - tn->selected_chip); - debug(" %d bytes ECC per %d byte block\n", - ecc->bytes, ecc->size); - debug(" for %d bits of correction per block.", - ecc->strength); - octeontx_nand_calc_ecc_layout(nand); - octeontx_bch_save_empty_eccmask(nand); - } - } - } -} - -static int octeontx_nfc_chip_init(struct octeontx_nfc *tn, struct udevice *dev, - ofnode node) -{ - struct octeontx_nand_chip *chip; - struct nand_chip *nand; - struct mtd_info *mtd; - int ret; - - chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); - if (!chip) - return -ENOMEM; - - debug("%s: Getting chip select\n", __func__); - ret = ofnode_read_s32(node, "reg", &chip->cs); - if (ret) { - dev_err(dev, "could not retrieve reg property: %d\n", ret); - return ret; - } - - if (chip->cs >= NAND_MAX_CHIPS) { - dev_err(dev, "invalid reg value: %u (max CS = 7)\n", chip->cs); - return -EINVAL; - } - debug("%s: chip select: %d\n", __func__, chip->cs); - nand = &chip->nand; - nand->controller = &tn->controller; - if (!tn->controller.active) - tn->controller.active = nand; - - debug("%s: Setting flash node\n", __func__); - nand_set_flash_node(nand, node); - - nand->options = 0; - nand->select_chip = octeontx_nand_select_chip; - nand->cmdfunc = octeontx_nand_cmdfunc; - nand->waitfunc = octeontx_nand_waitfunc; - nand->read_byte = octeontx_nand_read_byte; - nand->read_buf = octeontx_nand_read_buf; - nand->write_buf = octeontx_nand_write_buf; - nand->onfi_set_features = octeontx_nand_set_features; - nand->onfi_get_features = octeontx_nand_get_features; - nand->setup_data_interface = octeontx_nand_setup_dat_intf; - - mtd = nand_to_mtd(nand); - debug("%s: mtd: %p\n", __func__, mtd); - mtd->dev->parent = dev; - - debug("%s: NDF_MISC: 0x%llx\n", __func__, - readq(tn->base + NDF_MISC)); - - /* TODO: support more then 1 chip */ - debug("%s: Scanning identification\n", __func__); - ret = nand_scan_ident(mtd, 1, NULL); - if (ret) - return ret; - - debug("%s: Sizing chip\n", __func__); - octeontx_nfc_chip_sizing(nand); - - debug("%s: Scanning tail\n", __func__); - ret = nand_scan_tail(mtd); - if (ret) { - dev_err(dev, "nand_scan_tail failed: %d\n", ret); - return ret; - } - - debug("%s: Registering mtd\n", __func__); - ret = nand_register(0, mtd); - - debug("%s: Adding tail\n", __func__); - list_add_tail(&chip->node, &tn->chips); - return 0; -} - -static int octeontx_nfc_chips_init(struct octeontx_nfc *tn) -{ - struct udevice *dev = tn->dev; - ofnode node = dev_ofnode(dev); - ofnode nand_node; - int nr_chips = of_get_child_count(node); - int ret; - - debug("%s: node: %s\n", __func__, ofnode_get_name(node)); - debug("%s: %d chips\n", __func__, nr_chips); - if (nr_chips > NAND_MAX_CHIPS) { - dev_err(dev, "too many NAND chips: %d\n", nr_chips); - return -EINVAL; - } - - if (!nr_chips) { - debug("no DT NAND chips found\n"); - return -ENODEV; - } - - pr_info("%s: scanning %d chips DTs\n", __func__, nr_chips); - - ofnode_for_each_subnode(nand_node, node) { - debug("%s: Calling octeontx_nfc_chip_init(%p, %s, %ld)\n", - __func__, tn, dev->name, nand_node.of_offset); - ret = octeontx_nfc_chip_init(tn, dev, nand_node); - if (ret) - return ret; - } - return 0; -} - -/* Reset NFC and initialize registers. */ -static int octeontx_nfc_init(struct octeontx_nfc *tn) -{ - const struct nand_sdr_timings *timings; - u64 ndf_misc; - int rc; - - /* Initialize values and reset the fifo */ - ndf_misc = readq(tn->base + NDF_MISC); - - ndf_misc &= ~NDF_MISC_EX_DIS; - ndf_misc |= (NDF_MISC_BT_DIS | NDF_MISC_RST_FF); - writeq(ndf_misc, tn->base + NDF_MISC); - debug("%s: NDF_MISC: 0x%llx\n", __func__, readq(tn->base + NDF_MISC)); - - /* Bring the fifo out of reset */ - ndf_misc &= ~(NDF_MISC_RST_FF); - - /* Maximum of co-processor cycles for glitch filtering */ - ndf_misc |= FIELD_PREP(NDF_MISC_WAIT_CNT, 0x3f); - - writeq(ndf_misc, tn->base + NDF_MISC); - - /* Set timing parameters to onfi mode 0 for probing */ - timings = onfi_async_timing_mode_to_sdr_timings(0); - if (IS_ERR(timings)) - return PTR_ERR(timings); - rc = set_default_timings(tn, timings); - if (rc) - return rc; - - return 0; -} - -static int octeontx_pci_nand_probe(struct udevice *dev) -{ - struct octeontx_nfc *tn = dev_get_priv(dev); - int ret; - static bool probe_done; - - debug("%s(%s) tn: %p\n", __func__, dev->name, tn); - if (probe_done) - return 0; - - if (IS_ENABLED(CONFIG_NAND_OCTEONTX_HW_ECC)) { - bch_vf = octeontx_bch_getv(); - if (!bch_vf) { - struct octeontx_probe_device *probe_dev; - - debug("%s: bch not yet initialized\n", __func__); - probe_dev = calloc(sizeof(*probe_dev), 1); - if (!probe_dev) { - printf("%s: Out of memory\n", __func__); - return -ENOMEM; - } - probe_dev->dev = dev; - INIT_LIST_HEAD(&probe_dev->list); - list_add_tail(&probe_dev->list, - &octeontx_pci_nand_deferred_devices); - debug("%s: Defering probe until after BCH initialization\n", - __func__); - return 0; - } - } - - tn->dev = dev; - INIT_LIST_HEAD(&tn->chips); - - tn->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); - if (!tn->base) { - ret = -EINVAL; - goto release; - } - debug("%s: bar at %p\n", __func__, tn->base); - tn->buf.dmabuflen = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE; - tn->buf.dmabuf = dma_alloc_coherent(tn->buf.dmabuflen, - (unsigned long *)&tn->buf.dmaaddr); - if (!tn->buf.dmabuf) { - ret = -ENOMEM; - debug("%s: Could not allocate DMA buffer\n", __func__); - goto unclk; - } - - /* one hw-bch response, for one outstanding transaction */ - tn->bch_resp = dma_alloc_coherent(sizeof(*tn->bch_resp), - (unsigned long *)&tn->bch_rhandle); - - tn->stat = dma_alloc_coherent(8, (unsigned long *)&tn->stat_addr); - if (!tn->stat || !tn->bch_resp) { - debug("%s: Could not allocate bch status or response\n", - __func__); - ret = -ENOMEM; - goto unclk; - } - - debug("%s: Calling octeontx_nfc_init()\n", __func__); - octeontx_nfc_init(tn); - debug("%s: Initializing chips\n", __func__); - ret = octeontx_nfc_chips_init(tn); - debug("%s: init chips ret: %d\n", __func__, ret); - if (ret) { - if (ret != -ENODEV) - dev_err(dev, "failed to init nand chips\n"); - goto unclk; - } - dev_info(dev, "probed\n"); - return 0; - -unclk: -release: - return ret; -} - -int octeontx_pci_nand_disable(struct udevice *dev) -{ - struct octeontx_nfc *tn = dev_get_priv(dev); - u64 dma_cfg; - u64 ndf_misc; - - debug("%s: Disabling NAND device %s\n", __func__, dev->name); - dma_cfg = readq(tn->base + NDF_DMA_CFG); - dma_cfg &= ~NDF_DMA_CFG_EN; - dma_cfg |= NDF_DMA_CFG_CLR; - writeq(dma_cfg, tn->base + NDF_DMA_CFG); - - /* Disable execution and put FIFO in reset mode */ - ndf_misc = readq(tn->base + NDF_MISC); - ndf_misc |= NDF_MISC_EX_DIS | NDF_MISC_RST_FF; - writeq(ndf_misc, tn->base + NDF_MISC); - ndf_misc &= ~NDF_MISC_RST_FF; - writeq(ndf_misc, tn->base + NDF_MISC); -#ifdef DEBUG - printf("%s: NDF_MISC: 0x%llx\n", __func__, readq(tn->base + NDF_MISC)); -#endif - /* Clear any interrupts and enable bits */ - writeq(~0ull, tn->base + NDF_INT_ENA_W1C); - writeq(~0ull, tn->base + NDF_INT); - debug("%s: NDF_ST_REG: 0x%llx\n", __func__, - readq(tn->base + NDF_ST_REG)); - return 0; -} - -/** - * Since it's possible (and even likely) that the NAND device will be probed - * before the BCH device has been probed, we may need to defer the probing. - * - * In this case, the initial probe returns success but the actual probing - * is deferred until the BCH VF has been probed. - * - * Return: 0 for success, otherwise error - */ -int octeontx_pci_nand_deferred_probe(void) -{ - int rc = 0; - struct octeontx_probe_device *pdev; - - debug("%s: Performing deferred probing\n", __func__); - list_for_each_entry(pdev, &octeontx_pci_nand_deferred_devices, list) { - debug("%s: Probing %s\n", __func__, pdev->dev->name); - dev_get_flags(pdev->dev) &= ~DM_FLAG_ACTIVATED; - rc = device_probe(pdev->dev); - if (rc && rc != -ENODEV) { - printf("%s: Error %d with deferred probe of %s\n", - __func__, rc, pdev->dev->name); - break; - } - } - return rc; -} - -static const struct pci_device_id octeontx_nfc_pci_id_table[] = { - { PCI_VDEVICE(CAVIUM, 0xA04F) }, - {} -}; - -static int octeontx_nand_of_to_plat(struct udevice *dev) -{ - return 0; -} - -static const struct udevice_id octeontx_nand_ids[] = { - { .compatible = "cavium,cn8130-nand" }, - { }, -}; - -U_BOOT_DRIVER(octeontx_pci_nand) = { - .name = OCTEONTX_NAND_DRIVER_NAME, - .id = UCLASS_MTD, - .of_match = of_match_ptr(octeontx_nand_ids), - .of_to_plat = octeontx_nand_of_to_plat, - .probe = octeontx_pci_nand_probe, - .priv_auto = sizeof(struct octeontx_nfc), - .remove = octeontx_pci_nand_disable, - .flags = DM_FLAG_OS_PREPARE, -}; - -U_BOOT_PCI_DEVICE(octeontx_pci_nand, octeontx_nfc_pci_id_table); - -void board_nand_init(void) -{ - struct udevice *dev; - int ret; - - if (IS_ENABLED(CONFIG_NAND_OCTEONTX_HW_ECC)) { - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(octeontx_pci_bchpf), - &dev); - if (ret && ret != -ENODEV) { - pr_err("Failed to initialize OcteonTX BCH PF controller. (error %d)\n", - ret); - } - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(octeontx_pci_bchvf), - &dev); - if (ret && ret != -ENODEV) { - pr_err("Failed to initialize OcteonTX BCH VF controller. (error %d)\n", - ret); - } - } - - ret = uclass_get_device_by_driver(UCLASS_MTD, - DM_DRIVER_GET(octeontx_pci_nand), - &dev); - if (ret && ret != -ENODEV) - pr_err("Failed to initialize OcteonTX NAND controller. (error %d)\n", - ret); -} diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index b78b4e60238..7bf54fa4654 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -1765,6 +1765,7 @@ static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info *in pdata->num_cs = dev_read_u32_default(dev, "num-cs", 1); if (pdata->num_cs != 1) { pr_err("pxa3xx driver supports single CS only\n"); + kfree(pdata); return -EINVAL; } diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 083ea4c5a74..21e3c88a55a 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -942,21 +942,21 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) addr = dev_read_addr_index(dev, mem_region); if (addr == FDT_ADDR_T_NONE) { dev_err(dev, "Resource data_base not found for cs%d", chip_cs); - return ret; + return -EINVAL; } nfc->data_base[chip_cs] = addr; addr = dev_read_addr_index(dev, mem_region + 1); if (addr == FDT_ADDR_T_NONE) { dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs); - return ret; + return -EINVAL; } nfc->cmd_base[chip_cs] = addr; addr = dev_read_addr_index(dev, mem_region + 2); if (addr == FDT_ADDR_T_NONE) { dev_err(dev, "Resource addr_base not found for cs%d", chip_cs); - return ret; + return -EINVAL; } nfc->addr_base[chip_cs] = addr; } @@ -1034,6 +1034,7 @@ static int stm32_fmc2_nfc_probe(struct udevice *dev) ecclayout->eccpos[i] = oob_index; ecclayout->oobfree->offset = oob_index; ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; + ecclayout->oobavail = ecclayout->oobfree->length; chip->ecc.layout = ecclayout; if (chip->options & NAND_BUSWIDTH_16) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 34197bb09a1..1ce09b56b80 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1403,8 +1403,10 @@ static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd, if (!data) return -ENOMEM; - if (ecc->size != 512 && ecc->size != 1024) + if (ecc->size != 512 && ecc->size != 1024) { + kfree(data); return -EINVAL; + } /* Prefer 1k ECC chunk over 512 ones */ if (ecc->size == 512 && mtd->writesize > 512) { @@ -1641,17 +1643,20 @@ static int sunxi_nand_chip_init(struct udevice *dev, struct sunxi_nfc *nfc, if (ret) { dev_err(dev, "could not retrieve reg property: %d\n", ret); + kfree(chip); return ret; } if (tmp > NFC_MAX_CS) { dev_err(dev, "invalid reg value: %u (max CS = 7)\n", tmp); + kfree(chip); return -EINVAL; } if (test_and_set_bit(tmp, &nfc->assigned_cs)) { dev_err(dev, "CS %d already assigned\n", tmp); + kfree(chip); return -EINVAL; } @@ -1678,12 +1683,14 @@ static int sunxi_nand_chip_init(struct udevice *dev, struct sunxi_nfc *nfc, dev_err(dev, "could not retrieve timings for ONFI mode 0: %d\n", ret); + kfree(chip); return ret; } ret = sunxi_nand_chip_set_timings(nfc, chip, timings); if (ret) { dev_err(dev, "could not configure chip timings: %d\n", ret); + kfree(chip); return ret; } @@ -1705,8 +1712,10 @@ static int sunxi_nand_chip_init(struct udevice *dev, struct sunxi_nfc *nfc, mtd = nand_to_mtd(nand); ret = nand_scan_ident(mtd, nsels, NULL); - if (ret) + if (ret) { + kfree(chip); return ret; + } if (nand->bbt_options & NAND_BBT_USE_FLASH) nand->bbt_options |= NAND_BBT_NO_OOB; @@ -1719,24 +1728,28 @@ static int sunxi_nand_chip_init(struct udevice *dev, struct sunxi_nfc *nfc, ret = sunxi_nand_chip_init_timings(nfc, chip); if (ret) { dev_err(dev, "could not configure chip timings: %d\n", ret); + kfree(chip); return ret; } ret = sunxi_nand_ecc_init(mtd, &nand->ecc); if (ret) { dev_err(dev, "ECC init failed: %d\n", ret); + kfree(chip); return ret; } ret = nand_scan_tail(mtd); if (ret) { dev_err(dev, "nand_scan_tail failed: %d\n", ret); + kfree(chip); return ret; } ret = nand_register(devnum, mtd); if (ret) { dev_err(dev, "failed to register mtd device: %d\n", ret); + kfree(chip); return ret; } diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 655bf3aaf81..76c33b24368 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3784,8 +3784,10 @@ static int s25_s28_mdp_ready(struct spi_nor *nor) for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) { ret = spansion_sr_ready(nor, addr, nor->rdsr_dummy); - if (!ret) + if (ret < 0) return ret; + else if (ret == 0) + return 0; } return 1; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index e7e97780d7c..0383175beb5 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -591,6 +591,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w77q51nw", 0xef8a1a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ diff --git a/drivers/net/MAINTAINERS b/drivers/net/MAINTAINERS new file mode 100644 index 00000000000..fd002295d0c --- /dev/null +++ b/drivers/net/MAINTAINERS @@ -0,0 +1,6 @@ +NETWORK DW XGMAC +M: Boon Khai Ng <boon.khai.ng@altera.com> +S: Supported +F: drivers/net/dwc_eth_xgmac.c +F: drivers/net/dwc_eth_xgmac.h +F: drivers/net/dwc_eth_xgmac_socfpga.c diff --git a/drivers/net/cortina_ni.c b/drivers/net/cortina_ni.c index 79026882800..21b7089176c 100644 --- a/drivers/net/cortina_ni.c +++ b/drivers/net/cortina_ni.c @@ -499,7 +499,7 @@ static int ca_phy_probe(struct udevice *dev) dev, priv->phy_interface); if (ext_phydev) { ext_phydev->supported &= PHY_GBIT_FEATURES; - ext_phydev->advertising = int_phydev->supported; + ext_phydev->advertising = ext_phydev->supported; phy_config(ext_phydev); } else { printf("CA NI %s: There is no external phy device\n", __func__); diff --git a/drivers/net/designware.c b/drivers/net/designware.c index fce3ef910cb..7ecedc3d7f0 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -486,7 +486,7 @@ static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, #ifdef CONFIG_ARCH_NPCM8XX if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { - unsigned int start; + ulong start; /* Indirect access to VR_MII_MMD registers */ writew((VR_MII_MMD >> 9), PCS_BA + PCS_IND_AC); @@ -532,7 +532,7 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) { struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - unsigned int start; + ulong start; int ret; writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index 7a28f2a3e83..57ac528ebf5 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -137,13 +137,15 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, const bool eth_ref_clk_sel = dev_read_bool(dev, "st,eth-ref-clk-sel"); /* SoC is STM32MP13xx with two ethernet MACs */ const bool is_mp13 = device_is_compatible(dev, "st,stm32mp13-dwmac"); + /* SoC is STM32MP25xx with two ethernet MACs */ + const bool is_mp2 = device_is_compatible(dev, "st,stm32mp25-dwmac"); /* Gigabit Ethernet 125MHz clock selection. */ const bool eth_clk_sel = dev_read_bool(dev, "st,eth-clk-sel"); /* Ethernet clock source is RCC. */ const bool ext_phyclk = dev_read_bool(dev, "st,ext-phyclk"); struct regmap *regmap; u32 regmap_mask; - u32 value; + u32 reg, value; regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscon"); if (IS_ERR(regmap)) @@ -163,7 +165,7 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx * supports only MII, ETH_SELMII is not present. */ - if (!is_mp13) /* Select MII mode on STM32MP15xx */ + if (!is_mp13 && !is_mp2) /* Select MII mode on STM32MP15xx */ value |= SYSCFG_PMCSETR_ETH_SELMII; break; case PHY_INTERFACE_MODE_GMII: /* STM32MP15xx only */ @@ -213,15 +215,39 @@ static int eqos_probe_syscfg_stm32(struct udevice *dev, return -EINVAL; } - /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ - value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK); + if (is_mp2) { + /* + * STM32MP25xx SYSCFG EthernetN control register + * has ETHn_CLK_SEL and ETHn_REF_CLK_SEL bits + * swapped, swizzle them back in place. Bitfield + * ETHn_SEL is shifted by 1 right, fix this up. + */ + value = ((value & SYSCFG_PMCSETR_ETH_SEL_MASK) >> 1) | + ((value & SYSCFG_PMCSETR_ETH_CLK_SEL) << 1) | + ((value & SYSCFG_PMCSETR_ETH_REF_CLK_SEL) >> 1); + + /* + * STM32MP25xx SYSCFG EthernetN control register + * bits always start at bit shift 0 and there is + * one register for each MAC, shift the register + * content in place. + */ + value >>= ffs(SYSCFG_PMCSETR_ETH1_MASK) - 1; + + reg = dev_read_u32_index_default(dev, "st,syscon", 1, 0); - /* Update PMCCLRR (clear register) */ - regmap_write(regmap, is_mp13 ? - SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15, - regmap_mask); + return regmap_write(regmap, reg, value); + } else { + /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ + value <<= ffs(regmap_mask) - ffs(SYSCFG_PMCSETR_ETH1_MASK); - return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value); + /* Update PMCCLRR (clear register) */ + regmap_write(regmap, is_mp13 ? + SYSCFG_PMCCLRR_MP13 : SYSCFG_PMCCLRR_MP15, + regmap_mask); + + return regmap_update_bits(regmap, SYSCFG_PMCSETR, regmap_mask, value); + } } static int eqos_probe_resources_stm32(struct udevice *dev) diff --git a/drivers/net/dwc_eth_xgmac.c b/drivers/net/dwc_eth_xgmac.c index 03959ea95a5..d29d871ea8c 100644 --- a/drivers/net/dwc_eth_xgmac.c +++ b/drivers/net/dwc_eth_xgmac.c @@ -1102,7 +1102,7 @@ static int xgmac_probe(struct udevice *dev) ret = xgmac->config->ops->xgmac_start_clks(dev); if (ret < 0) { pr_err("%s xgmac_start_clks() failed: %d\n", dev->name, ret); - return ret; + goto err_remove_resources_core; } if (IS_ENABLED(CONFIG_DM_ETH_PHY)) diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c b/drivers/net/dwc_eth_xgmac_socfpga.c index c89c8a188b7..f72f16b50ab 100644 --- a/drivers/net/dwc_eth_xgmac_socfpga.c +++ b/drivers/net/dwc_eth_xgmac_socfpga.c @@ -39,11 +39,9 @@ phy_interface_t dwxgmac_of_get_mac_mode(struct udevice *dev) if (!mac_mode) return PHY_INTERFACE_MODE_NA; - if (mac_mode) { - for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) { - if (!strcmp(mac_mode, phy_interface_strings[i])) - return i; - } + for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) { + if (!strcmp(mac_mode, phy_interface_strings[i])) + return i; } return PHY_INTERFACE_MODE_NA; } diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 54b08482b91..9ac72d25ef6 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1344,6 +1344,7 @@ static int fecmxc_probe(struct udevice *dev) while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { printf("FEC MXC: Timeout resetting chip\n"); + ret = -ETIMEDOUT; goto err_timeout; } udelay(10); diff --git a/drivers/net/ks8851_mll.c b/drivers/net/ks8851_mll.c index cc2e826257a..2c956154d09 100644 --- a/drivers/net/ks8851_mll.c +++ b/drivers/net/ks8851_mll.c @@ -347,11 +347,6 @@ static int ks8851_mll_detect_chip(struct ks_net *ks) debug("Read back KS8851 id 0x%x\n", val); - if ((val & 0xfff0) != CIDER_ID) { - printf(DRIVERNAME ": Unknown chip ID %04x\n", val); - return -1; - } - return 0; } diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index b72198ca530..94e62748239 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -458,7 +458,7 @@ static int ldpaa_eth_open(struct udevice *dev) link_state.up == 1 ? printf("up\n") : printf("error state\n"); #endif - memset(&d_queue, 0, sizeof(struct dpni_queue)); + memset(&d_queue, 0, sizeof(struct dpni_queue_id)); err = dpni_get_queue(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, DPNI_QUEUE_RX, 0, 0, &d_queue_cfg, &d_queue); diff --git a/drivers/net/mtk_eth/mtk_eth.c b/drivers/net/mtk_eth/mtk_eth.c index 5d6a42bceb4..b172838ba3a 100644 --- a/drivers/net/mtk_eth/mtk_eth.c +++ b/drivers/net/mtk_eth/mtk_eth.c @@ -1461,7 +1461,7 @@ static int mtk_eth_of_to_plat(struct udevice *dev) priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); if (priv->phy_addr < 0) { printf("error: phy address is not specified\n"); - return ret; + return priv->phy_addr; } } diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c index 557b6b2c8f6..f06c73c20f8 100644 --- a/drivers/net/mv88e6xxx.c +++ b/drivers/net/mv88e6xxx.c @@ -631,7 +631,7 @@ static int mv88e6xxx_port_enable(struct udevice *dev, int port, struct phy_devic dev_dbg(dev, "configure internal RGMII delays\n"); /* RGMII delays */ - val &= ~(PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK || + val &= ~(PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK | PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK); if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID || phy->interface == PHY_INTERFACE_MODE_RGMII_RXID) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 184c1f9a46a..f9e979c4d58 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -1722,8 +1722,7 @@ static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow) } /* Return first free tcam index, seeking from start to end */ -static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start, - unsigned char end) +static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, int start, int end) { int tid; @@ -2330,7 +2329,7 @@ static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, pe = kzalloc(sizeof(*pe), GFP_KERNEL); if (!pe) - return -1; + return -ENOMEM; mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); pe->index = tid; @@ -4735,7 +4734,7 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) int port_node = dev_of_offset(dev); int phy_node; u32 id; - u32 phyaddr = 0; + int phyaddr = 0; int fixed_link = 0; int ret; @@ -5354,7 +5353,7 @@ static int mvpp2_probe(struct udevice *dev) } else { port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "gop-port-id", -1); - if (port->id == -1) { + if (port->gop_id == -1) { dev_err(dev, "missing gop-port-id value\n"); return -EINVAL; } diff --git a/drivers/net/octeontx/nicvf_main.c b/drivers/net/octeontx/nicvf_main.c index 27d0327c88a..94e5d827614 100644 --- a/drivers/net/octeontx/nicvf_main.c +++ b/drivers/net/octeontx/nicvf_main.c @@ -232,7 +232,7 @@ static int nicvf_rcv_pkt_handler(struct nicvf *nic, size_t pkt_len; struct cqe_rx_t *cqe_rx = (struct cqe_rx_t *)cq_desc; - int err = 0; + int err; /* Check for errors */ err = nicvf_check_cqe_rx_errs(nic, cq, cq_desc); @@ -245,8 +245,7 @@ static int nicvf_rcv_pkt_handler(struct nicvf *nic, return -1; } - if (pkt) - *ppkt = pkt; + *ppkt = pkt; return pkt_len; } @@ -274,31 +273,29 @@ int nicvf_cq_handler(struct nicvf *nic, void **ppkt, int *pkt_len) cqe_head >>= 9; cqe_head &= 0xFFFF; - if (cqe_count) { - /* Get the CQ descriptor */ - cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); - cqe_head++; - cqe_head &= (cq->dmem.q_len - 1); - - switch (cq_desc->cqe_type) { - case CQE_TYPE_RX: - debug("%s: Got Rx CQE\n", nic->dev->name); - *pkt_len = nicvf_rcv_pkt_handler(nic, cq, cq_desc, - ppkt, CQE_TYPE_RX); - processed_rq_cqe++; - break; - case CQE_TYPE_SEND: - debug("%s: Got Tx CQE\n", nic->dev->name); - nicvf_snd_pkt_handler(nic, cq, cq_desc, CQE_TYPE_SEND); - processed_sq_cqe++; - break; - default: - debug("%s: Got CQ type %u\n", nic->dev->name, - cq_desc->cqe_type); - break; - } - processed_cqe++; + /* Get the CQ descriptor */ + cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head); + cqe_head++; + cqe_head &= (cq->dmem.q_len - 1); + + switch (cq_desc->cqe_type) { + case CQE_TYPE_RX: + debug("%s: Got Rx CQE\n", nic->dev->name); + *pkt_len = nicvf_rcv_pkt_handler(nic, cq, cq_desc, + ppkt, CQE_TYPE_RX); + processed_rq_cqe++; + break; + case CQE_TYPE_SEND: + debug("%s: Got Tx CQE\n", nic->dev->name); + nicvf_snd_pkt_handler(nic, cq, cq_desc, CQE_TYPE_SEND); + processed_sq_cqe++; + break; + default: + debug("%s: Got CQ type %u\n", nic->dev->name, + cq_desc->cqe_type); + break; } + processed_cqe++; /* Dequeue CQE */ nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR, diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c index 233c26f7319..217bcac2ce2 100644 --- a/drivers/net/octeontx/smi.c +++ b/drivers/net/octeontx/smi.c @@ -338,7 +338,8 @@ int octeontx_smi_probe(struct udevice *dev) if (!bus || !priv) { printf("Failed to allocate OcteonTX MDIO bus # %u\n", dev_seq(dev)); - return -1; + ret = -ENOMEM; + goto error_ret; } bus->read = octeontx_phy_read; @@ -355,9 +356,16 @@ int octeontx_smi_probe(struct udevice *dev) ret = mdio_register(bus); if (ret) - return ret; + goto error_ret; } return 0; + +error_ret: + if (bus) + free(bus); + if (priv) + free(priv); + return ret; } static const struct udevice_id octeontx_smi_ids[] = { diff --git a/drivers/net/octeontx2/nix.c b/drivers/net/octeontx2/nix.c index f596b6bca87..87d1f7a5dbf 100644 --- a/drivers/net/octeontx2/nix.c +++ b/drivers/net/octeontx2/nix.c @@ -298,6 +298,8 @@ int nix_lf_setup(struct nix *nix) goto error; } + err = -1; + /* Alloc memory for Qints HW contexts */ nix->qint_base = nix_memalloc(nix_af->qints, nix_af->qint_ctx_sz, "Qint CTX"); diff --git a/drivers/net/octeontx2/rvu_af.c b/drivers/net/octeontx2/rvu_af.c index 0d3a9ffe9ee..7bdfbc52e3b 100644 --- a/drivers/net/octeontx2/rvu_af.c +++ b/drivers/net/octeontx2/rvu_af.c @@ -114,7 +114,7 @@ struct nix_af *rvu_af_init(struct rvu_af *rvu_af) return nix_af; error: - if (nix_af->npa_af) { + if (nix_af && nix_af->npa_af) { free(nix_af->npa_af); memset(nix_af, 0, sizeof(*nix_af)); } diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 0a49015eb89..1c02e3efedc 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -134,6 +134,33 @@ static void bcm_phy_write_misc(struct phy_device *phydev, phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); } +/* Broadcom BCM54612E */ +static int bcm54612e_config(struct phy_device *phydev) +{ + u32 reg = 0; + + genphy_config_aneg(phydev); + + phy_reset(phydev); + + /* 125Mhz Clock Output Enable */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL); + reg |= 0xD34; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); + reg |= (1 << 1); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, reg); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL); + reg &= 0xfffff000; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg); + + genphy_restart_aneg(phydev); + + return 0; +} + /* Broadcom BCM5461S */ static int bcm5461_config(struct phy_device *phydev) { @@ -434,6 +461,16 @@ U_BOOT_PHY_DRIVER(bcm5461s) = { .shutdown = &genphy_shutdown, }; +U_BOOT_PHY_DRIVER(bcm54612e) = { + .name = "Broadcom BCM54612E", + .uid = 0x03625e6a, + .mask = 0xfffff0, + .features = PHY_GBIT_FEATURES, + .config = &bcm54612e_config, + .startup = &bcm54xx_startup, + .shutdown = &genphy_shutdown, +}; + U_BOOT_PHY_DRIVER(bcm5464s) = { .name = "Broadcom BCM5464S", .uid = 0x2060b0, diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 4867d1931b4..821d3878236 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -239,7 +239,7 @@ static int vsc8514_config(struct phy_device *phydev) while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--) val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); - if (0 == timeout) { + if (timeout == -1) { printf("PHY 8514 config failed\n"); return -1; } diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 62d3f39f071..f27587ac8bd 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -1110,8 +1110,10 @@ static int rswitch_probe(struct udevice *dev) return -EINVAL; priv->rsw_clk = devm_clk_get(dev, NULL); - if (ret) + if (IS_ERR(priv->rsw_clk)) { + ret = PTR_ERR(priv->rsw_clk); goto err_map; + } ret = clk_prepare_enable(priv->rsw_clk); if (ret) diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index c8038ddef1b..22e119370c8 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -558,7 +558,7 @@ static int axiemac_write_hwaddr(struct udevice *dev) /* Reset DMA engine */ static void axi_dma_init(struct axidma_priv *priv) { - u32 timeout = 500; + int timeout = 500; /* Reset the engine so the hardware starts from a known state */ writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control); @@ -571,11 +571,11 @@ static void axi_dma_init(struct axidma_priv *priv) if (!((readl(&priv->dmatx->control) | readl(&priv->dmarx->control)) & XAXIDMA_CR_RESET_MASK)) { - break; + return; } } - if (!timeout) - printf("%s: Timeout\n", __func__); + + printf("%s: Timeout\n", __func__); } static int axiemac_start(struct udevice *dev) diff --git a/drivers/pci/pci-rcar-gen4.c b/drivers/pci/pci-rcar-gen4.c index 87cd69f989d..41f0d958447 100644 --- a/drivers/pci/pci-rcar-gen4.c +++ b/drivers/pci/pci-rcar-gen4.c @@ -235,7 +235,7 @@ static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(23, 22), BIT(22)); clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(18, 16), GENMASK(17, 16)); clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(7, 6), BIT(6)); - clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(11, 0)); + clrsetbits_le32(rcar->phy_base + 0x148, GENMASK(2, 0), GENMASK(1, 0)); clrsetbits_le32(rcar->phy_base + 0x1d4, GENMASK(16, 15), GENMASK(16, 15)); clrsetbits_le32(rcar->phy_base + 0x514, BIT(26), BIT(26)); clrsetbits_le32(rcar->phy_base + 0x0f8, BIT(16), 0); diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c297fa03ea7..d36a5f00ef8 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -289,11 +289,11 @@ config PHY_NPCM_USB Support the USB PHY in NPCM SoCs config PHY_IMX8MQ_USB - bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver" + bool "NXP i.MX8MQ/i.MX8MP/i.MX95 USB PHY Driver" depends on PHY - depends on IMX8MQ || IMX8MP + depends on IMX8MQ || IMX8MP || IMX95 help - Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC + Support the USB3.0 PHY in NXP i.MX8MQ, i.MX8MP, and i.MX95 SoC config PHY_IMX8M_PCIE bool "NXP i.MX8MM/i.MX8MP PCIe PHY Driver" diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 2c9d5a12127..bd7ab9d1b77 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -225,11 +225,6 @@ static const struct reg_field pllctrl_lock = static const struct reg_field phy_iso_link_ctrl_1 = REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1); -static const char * const clk_names[] = { - [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc", - [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1", -}; - enum cdns_sierra_cmn_plllc { CMN_PLLLC, CMN_PLLLC1, @@ -602,7 +597,7 @@ static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp) struct udevice *dev = sp->dev; struct driver *cdns_sierra_clk_drv; struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel; - int i, rc; + int rc; cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk"); if (!cdns_sierra_clk_drv) { @@ -612,10 +607,8 @@ static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp) rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk", data, dev_ofnode(dev), NULL); - if (rc) { - dev_err(dev, "cannot bind driver for clock %s\n", - clk_names[i]); - } + if (rc) + dev_err(dev, "cannot bind driver for clock pll_mux_clk\n"); return 0; } diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 1f566d082f9..28fe026223c 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -719,6 +719,7 @@ static int cdns_torrent_phy_probe(struct udevice *dev) if (total_num_lanes > MAX_NUM_LANES) { dev_err(dev, "Invalid lane configuration\n"); + ret = -EINVAL; goto put_lnk_rst; } diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index a666a4e794e..a4121423873 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -28,7 +28,7 @@ static const char *get_speed_string(u32 speed) "10.3125 Gbps" }; - if (speed < 0 || speed > COMPHY_SPEED_MAX) + if (speed < 0 || speed >= COMPHY_SPEED_MAX) return "invalid"; return speed_strings[speed]; @@ -44,7 +44,7 @@ static const char *get_type_string(u32 type) "IGNORE" }; - if (type < 0 || type > COMPHY_TYPE_MAX) + if (type < 0 || type >= COMPHY_TYPE_MAX) return "invalid"; return type_strings[type]; diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h index f3d04939387..086a4d82f26 100644 --- a/drivers/phy/marvell/comphy_core.h +++ b/drivers/phy/marvell/comphy_core.h @@ -47,8 +47,8 @@ struct chip_serdes_phy_config { int (*rx_training)(struct chip_serdes_phy_config *, u32); void __iomem *comphy_base_addr; void __iomem *hpipe3_base_addr; - u32 comphy_lanes_count; - u32 comphy_mux_bitcount; + int comphy_lanes_count; + int comphy_mux_bitcount; const fdt32_t *comphy_mux_lane_order; u32 cp_index; struct comphy_map comphy_map_data[MAX_LANE_OPTIONS]; diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index 75763046adc..387db843c50 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -71,9 +71,57 @@ #define PHY_STS0_FSVPLUS BIT(3) #define PHY_STS0_FSVMINUS BIT(2) +#define TCA_CLK_RST 0x00 +#define TCA_CLK_RST_SW BIT(9) +#define TCA_CLK_RST_REF_CLK_EN BIT(1) +#define TCA_CLK_RST_SUSPEND_CLK_EN BIT(0) + +#define TCA_INTR_EN 0x04 +#define TCA_INTR_STS 0x08 + +#define TCA_GCFG 0x10 +#define TCA_GCFG_ROLE_HSTDEV BIT(4) +#define TCA_GCFG_OP_MODE GENMASK(1, 0) +#define TCA_GCFG_OP_MODE_SYSMODE 0 +#define TCA_GCFG_OP_MODE_SYNCMODE 1 + +#define TCA_TCPC 0x14 +#define TCA_TCPC_VALID BIT(4) +#define TCA_TCPC_LOW_POWER_EN BIT(3) +#define TCA_TCPC_ORIENTATION_NORMAL BIT(2) +#define TCA_TCPC_MUX_CONTRL GENMASK(1, 0) +#define TCA_TCPC_MUX_CONTRL_NO_CONN 0 +#define TCA_TCPC_MUX_CONTRL_USB_CONN 1 + +#define TCA_SYSMODE_CFG 0x18 +#define TCA_SYSMODE_TCPC_DISABLE BIT(3) +#define TCA_SYSMODE_TCPC_FLIP BIT(2) + +#define TCA_CTRLSYNCMODE_CFG0 0x20 +#define TCA_CTRLSYNCMODE_CFG1 0x20 + +#define TCA_PSTATE 0x30 +#define TCA_PSTATE_CM_STS BIT(4) +#define TCA_PSTATE_TX_STS BIT(3) +#define TCA_PSTATE_RX_PLL_STS BIT(2) +#define TCA_PSTATE_PIPE0_POWER_DOWN GENMASK(1, 0) + +#define TCA_GEN_STATUS 0x34 +#define TCA_GEN_DEV_POR BIT(12) +#define TCA_GEN_REF_CLK_SEL BIT(8) +#define TCA_GEN_TYPEC_FLIP_INVERT BIT(4) +#define TCA_GEN_PHY_TYPEC_DISABLE BIT(3) +#define TCA_GEN_PHY_TYPEC_FLIP BIT(2) + +#define TCA_VBUS_CTRL 0x40 +#define TCA_VBUS_STATUS 0x44 + +#define TCA_INFO 0xfc + enum imx8mpq_phy_type { IMX8MQ_PHY, IMX8MP_PHY, + IMX95_PHY, }; struct imx8mq_usb_phy { @@ -81,14 +129,49 @@ struct imx8mq_usb_phy { void __iomem *base; enum imx8mpq_phy_type type; struct udevice *vbus_supply; + void __iomem *tca_base; }; static const struct udevice_id imx8mq_usb_phy_of_match[] = { { .compatible = "fsl,imx8mq-usb-phy", .data = IMX8MQ_PHY }, { .compatible = "fsl,imx8mp-usb-phy", .data = IMX8MP_PHY }, + { .compatible = "fsl,imx95-usb-phy", .data = IMX95_PHY }, {}, }; +static void tca_blk_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + void __iomem *base = imx_phy->tca_base; + u32 val; + + /* reset XBar block */ + val = readl(base + TCA_CLK_RST); + val &= ~TCA_CLK_RST_SW; + writel(val, base + TCA_CLK_RST); + + udelay(100); + + /* clear reset */ + val |= TCA_CLK_RST_SW; + writel(val, base + TCA_CLK_RST); + + /* + * use Controller Synced Mode for TCA low power enable and + * put PHY to USB safe state. + */ + val = FIELD_PREP(TCA_GCFG_OP_MODE, TCA_GCFG_OP_MODE_SYNCMODE); + writel(val, base + TCA_GCFG); + + val = TCA_TCPC_VALID | TCA_TCPC_LOW_POWER_EN; + writel(val, base + TCA_TCPC); + + /* use System Configuration Mode for TCA mux control. */ + val = FIELD_PREP(TCA_GCFG_OP_MODE, TCA_GCFG_OP_MODE_SYSMODE); + writel(val, base + TCA_GCFG); +} + static int imx8mq_usb_phy_init(struct phy *usb_phy) { struct udevice *dev = usb_phy->dev; @@ -154,6 +237,9 @@ static int imx8mp_usb_phy_init(struct phy *usb_phy) value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); writel(value, imx_phy->base + PHY_CTRL1); + if (imx_phy->tca_base) + tca_blk_init(usb_phy); + return 0; } @@ -162,7 +248,7 @@ static int imx8mpq_usb_phy_init(struct phy *usb_phy) struct udevice *dev = usb_phy->dev; struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); - if (imx_phy->type == IMX8MP_PHY) + if (imx_phy->type == IMX8MP_PHY || imx_phy->type == IMX95_PHY) return imx8mp_usb_phy_init(usb_phy); else return imx8mq_usb_phy_init(usb_phy); @@ -264,6 +350,9 @@ int imx8mq_usb_phy_probe(struct udevice *dev) } } + if (priv->type == IMX95_PHY) + priv->tca_base = dev_read_addr_index_ptr(dev, 1); + return 0; } diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c b/drivers/phy/qcom/phy-qcom-snps-eusb2.c index b2655ac007c..28502c46f67 100644 --- a/drivers/phy/qcom/phy-qcom-snps-eusb2.c +++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c @@ -331,8 +331,9 @@ static int qcom_snps_eusb2_phy_probe(struct udevice *dev) qcom_snps_eusb2->ref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(qcom_snps_eusb2->ref_clk)) { + ret = PTR_ERR(qcom_snps_eusb2->ref_clk); printf("%s: failed to get ref clk %d\n", __func__, ret); - return PTR_ERR(qcom_snps_eusb2->ref_clk); + return ret; } ret = reset_get_bulk(dev, &qcom_snps_eusb2->resets); diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c index 88b33de1b2a..4ea6600ce7f 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -167,20 +167,27 @@ static struct phy_ops rockchip_usb2phy_ops = { .of_xlate = rockchip_usb2phy_of_xlate, }; -static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base, - const struct usb2phy_reg **clkout_ctl) +static int rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base, + const struct usb2phy_reg **clkout_ctl) { struct udevice *parent = dev_get_parent(clk->dev); struct rockchip_usb2phy *priv = dev_get_priv(parent); const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg; - if (priv->phy_cfg->clkout_ctl_phy.enable) { + // phy_cfg can be NULL if this function called before probe (when parent + // clocks are enabled) + if (!phy_cfg) + return -EINVAL; + + if (phy_cfg->clkout_ctl_phy.enable) { *base = priv->phy_base; *clkout_ctl = &phy_cfg->clkout_ctl_phy; } else { *base = priv->reg_base; *clkout_ctl = &phy_cfg->clkout_ctl; } + + return 0; } /** @@ -206,7 +213,8 @@ int rockchip_usb2phy_clk_enable(struct clk *clk) const struct usb2phy_reg *clkout_ctl; struct regmap *base; - rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); + if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl)) + return -ENOSYS; /* turn on 480m clk output if it is off */ if (!property_enabled(base, clkout_ctl)) { @@ -230,7 +238,8 @@ int rockchip_usb2phy_clk_disable(struct clk *clk) const struct usb2phy_reg *clkout_ctl; struct regmap *base; - rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl); + if (rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl)) + return -ENOSYS; /* turn off 480m clk output */ property_enable(base, clkout_ctl, false); @@ -456,6 +465,28 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = { { /* sentinel */ } }; +static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = { + { + .reg = 0x0000, + .clkout_ctl = { 0x0008, 0, 0, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x0000, 1, 0, 2, 1 }, + } + }, + }, + { + .reg = 0x2000, + .clkout_ctl = { 0x2008, 0, 0, 1, 0 }, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0x2000, 1, 0, 2, 1 }, + } + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = { { .reg = 0x0000, @@ -518,6 +549,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = { .data = (ulong)&rk3568_phy_cfgs, }, { + .compatible = "rockchip,rk3576-usb2phy", + .data = (ulong)&rk3576_phy_cfgs, + }, + { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs, }, @@ -538,7 +573,7 @@ U_BOOT_DRIVER(rockchip_usb2phy_clock) = { U_BOOT_DRIVER(rockchip_usb2phy) = { .name = "rockchip_usb2phy", - .id = UCLASS_PHY, + .id = UCLASS_NOP, .of_match = rockchip_usb2phy_ids, .probe = rockchip_usb2phy_probe, .bind = rockchip_usb2phy_bind, diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 5145b517aa4..d602f965d6a 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -37,6 +37,7 @@ struct rockchip_combphy_grfcfg { struct combphy_reg pipe_rxterm_set; struct combphy_reg pipe_txelec_set; struct combphy_reg pipe_txcomp_set; + struct combphy_reg pipe_clk_24m; struct combphy_reg pipe_clk_25m; struct combphy_reg pipe_clk_100m; struct combphy_reg pipe_phymode_sel; @@ -98,104 +99,41 @@ static int param_write(struct regmap *base, return regmap_write(base, reg->offset, val); } -static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for pcie\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for usb3\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_sata_init(struct rockchip_combphy_priv *priv) -{ - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for sata\n"); - return ret; - } - } - - return ret; -} - -static int rockchip_combphy_sgmii_init(struct rockchip_combphy_priv *priv) +static int rockchip_combphy_init(struct phy *phy) { - int ret = 0; - - if (priv->cfg->combphy_cfg) { - ret = priv->cfg->combphy_cfg(priv); - if (ret) { - dev_err(priv->dev, "failed to init phy for sgmii\n"); - return ret; - } - } + struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); + int ret; - return ret; -} + ret = clk_enable(&priv->ref_clk); + if (ret < 0 && ret != -ENOSYS) + return ret; -static int rockchip_combphy_set_mode(struct rockchip_combphy_priv *priv) -{ switch (priv->mode) { case PHY_TYPE_PCIE: - rockchip_combphy_pcie_init(priv); - break; case PHY_TYPE_USB3: - rockchip_combphy_usb3_init(priv); - break; case PHY_TYPE_SATA: - rockchip_combphy_sata_init(priv); - break; case PHY_TYPE_SGMII: case PHY_TYPE_QSGMII: - return rockchip_combphy_sgmii_init(priv); + if (priv->cfg->combphy_cfg) + ret = priv->cfg->combphy_cfg(priv); + else + ret = 0; + break; default: dev_err(priv->dev, "incompatible PHY type\n"); - return -EINVAL; + ret = -EINVAL; + break; } - return 0; -} - -static int rockchip_combphy_init(struct phy *phy) -{ - struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev); - int ret; - - ret = clk_enable(&priv->ref_clk); - if (ret < 0 && ret != -ENOSYS) - return ret; + if (ret) { + dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->mode); + goto err_clk; + } - ret = rockchip_combphy_set_mode(priv); + ret = reset_deassert_bulk(&priv->phy_rsts); if (ret) goto err_clk; - reset_deassert_bulk(&priv->phy_rsts); - return 0; err_clk: @@ -223,6 +161,7 @@ static int rockchip_combphy_xlate(struct phy *phy, struct ofnode_phandle_args *a return -EINVAL; } + phy->id = priv->id; priv->mode = args->args[0]; return 0; @@ -237,22 +176,19 @@ static const struct phy_ops rockchip_combphy_ops = { static int rockchip_combphy_parse_dt(struct udevice *dev, struct rockchip_combphy_priv *priv) { - struct udevice *syscon; int ret; - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-grf", &syscon); - if (ret) { - dev_err(dev, "failed to find peri_ctrl pipe-grf regmap"); - return ret; + priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf"); + if (IS_ERR(priv->pipe_grf)) { + dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); + return PTR_ERR(priv->pipe_grf); } - priv->pipe_grf = syscon_get_regmap(syscon); - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pipe-phy-grf", &syscon); - if (ret) { + priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-phy-grf"); + if (IS_ERR(priv->phy_grf)) { dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); - return ret; + return PTR_ERR(priv->phy_grf); } - priv->phy_grf = syscon_get_regmap(syscon); ret = clk_get_by_index(dev, 0, &priv->ref_clk); if (ret) { @@ -304,12 +240,109 @@ static int rockchip_combphy_probe(struct udevice *udev) } priv->dev = udev; - priv->mode = PHY_TYPE_SATA; + priv->mode = PHY_NONE; priv->cfg = phy_cfg; return rockchip_combphy_parse_dt(udev, priv); } +static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + 0x18); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x18); + + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + 0x18); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x18); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + 0x200); + val &= ~GENMASK(17, 17); + val |= 0x01 << 17; + writel(val, priv->mmio + 0x200); + + /* Set Rx squelch input filler bandwidth */ + val = readl(priv->mmio + 0x20c); + val &= ~GENMASK(2, 0); + val |= 0x06; + writel(val, priv->mmio + 0x20c); + + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true); + break; + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + + if (priv->mode == PHY_TYPE_PCIE) { + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + 0x18); + val &= ~(0x7 << 10); + val |= 0x2 << 10; + writel(val, priv->mmio + 0x18); + + /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */ + val = readl(priv->mmio + 0x108); + val &= ~(0x7f7); + val |= 0x4f0; + writel(val, priv->mmio + 0x108); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + /* pipe-grf */ + .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = { + .num_phys = 1, + .phy_ids = { + 0xffdc0000, + }, + .grfcfg = &rk3528_combphy_grfcfgs, + .combphy_cfg = rk3528_combphy_cfg, +}; + static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -453,6 +486,149 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { .combphy_cfg = rk3568_combphy_cfg, }; +static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + u32 val; + + switch (priv->mode) { + case PHY_TYPE_PCIE: + param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + val = readl(priv->mmio + (0x1f << 2)); + val &= ~GENMASK(5, 4); + val |= 0x01 << 4; + writel(val, priv->mmio + 0x7c); + + /* Enable adaptive CTLE for USB3.0 Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + + /* Set PLL KVCO fine tuning signals */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + writel(0x4, priv->mmio + (0xb << 2)); + + /* Set PLL input clock divider 1/2 */ + val = readl(priv->mmio + (0x5 << 2)); + val &= ~(0x3 << 6); + val |= 0x1 << 6; + writel(val, priv->mmio + (0x5 << 2)); + + /* Set PLL loop divider */ + writel(0x32, priv->mmio + (0x11 << 2)); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + writel(0xf0, priv->mmio + (0xa << 2)); + + /* Set Rx squelch input filler bandwidth */ + writel(0x0d, priv->mmio + (0x14 << 2)); + + param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + param_write(priv->phy_grf, &cfg->usb_mode_set, true); + param_write(priv->pipe_grf, &cfg->u3otg1_port_en, true); + break; + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx */ + val = readl(priv->mmio + (0x0e << 2)); + val &= ~GENMASK(0, 0); + val |= 0x01; + writel(val, priv->mmio + (0x0e << 2)); + /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */ + writel(0x8F, priv->mmio + (0x06 << 2)); + + param_write(priv->phy_grf, &cfg->con0_for_sata, true); + param_write(priv->phy_grf, &cfg->con1_for_sata, true); + param_write(priv->phy_grf, &cfg->con2_for_sata, true); + param_write(priv->phy_grf, &cfg->con3_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + /* 100MHz refclock signal is good */ + clk_set_rate(&priv->ref_clk, 100000000); + param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->mode == PHY_TYPE_PCIE) { + /* gate_tx_pck_sel length select work for L1SS */ + writel(0xc0, priv->mmio + 0x74); + + /* PLL KVCO tuning fine */ + val = readl(priv->mmio + (0x20 << 2)); + val &= ~(0x7 << 2); + val |= 0x2 << 2; + writel(val, priv->mmio + (0x20 << 2)); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + writel(0x4c, priv->mmio + (0x1b << 2)); + + /* Set up su_trim: T3_P1 650mv */ + writel(0x90, priv->mmio + (0xa << 2)); + writel(0x43, priv->mmio + (0xb << 2)); + writel(0x88, priv->mmio + (0xc << 2)); + writel(0x56, priv->mmio + (0xd << 2)); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, + .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, + /* php-grf */ + .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 }, + .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 }, + .u3otg1_port_en = { 0x0038, 15, 0, 0x0181, 0x1100 }, +}; + +static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = { + .num_phys = 2, + .phy_ids = { + 0x2b050000, + 0x2b060000, + }, + .grfcfg = &rk3576_combphy_grfcfgs, + .combphy_cfg = rk3576_combphy_cfg, +}; + static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) { const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; @@ -561,10 +737,18 @@ static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { static const struct udevice_id rockchip_combphy_ids[] = { { + .compatible = "rockchip,rk3528-naneng-combphy", + .data = (ulong)&rk3528_combphy_cfgs + }, + { .compatible = "rockchip,rk3568-naneng-combphy", .data = (ulong)&rk3568_combphy_cfgs }, { + .compatible = "rockchip,rk3576-naneng-combphy", + .data = (ulong)&rk3576_combphy_cfgs + }, + { .compatible = "rockchip,rk3588-naneng-combphy", .data = (ulong)&rk3588_combphy_cfgs }, diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index c48a5cd5267..66d1d32d25c 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -788,7 +788,7 @@ U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = { U_BOOT_DRIVER(rockchip_typec_phy) = { .name = "rockchip_typec_phy", - .id = UCLASS_PHY, + .id = UCLASS_NOP, .of_match = rockchip_typec_phy_ids, .probe = rockchip_tcphy_probe, .bind = rockchip_tcphy_bind, diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c index 9deec47ae46..cca67dd3611 100644 --- a/drivers/phy/rockchip/phy-rockchip-usbdp.c +++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c @@ -96,9 +96,7 @@ struct rockchip_udphy { /* PHY status management */ bool flip; - bool mode_change; u8 mode; - u8 status; /* utilized for USB */ bool hs; /* flag for high-speed */ @@ -525,80 +523,26 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev) return 0; } -static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) -{ - int ret; - - if (!(udphy->mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); - return 0; - } - - if (udphy->status == UDPHY_MODE_NONE) { - udphy->mode_change = false; - ret = udphy_setup(udphy); - if (ret) - return ret; - - if (udphy->mode & UDPHY_MODE_USB) - udphy_u3_port_disable(udphy, false); - } else if (udphy->mode_change) { - udphy->mode_change = false; - udphy->status = UDPHY_MODE_NONE; - if (udphy->mode == UDPHY_MODE_DP) - udphy_u3_port_disable(udphy, true); - - ret = udphy_disable(udphy); - if (ret) - return ret; - ret = udphy_setup(udphy); - if (ret) - return ret; - } - - udphy->status |= mode; - - return 0; -} - -static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) -{ - int ret; - - if (!(udphy->mode & mode)) { - dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode); - return 0; - } - - if (!udphy->status) - return 0; - - udphy->status &= ~mode; - - if (udphy->status == UDPHY_MODE_NONE) { - ret = udphy_disable(udphy); - if (ret) - return ret; - } - - return 0; -} - static int rockchip_u3phy_of_xlate(struct phy *phy, struct ofnode_phandle_args *args) { + struct rockchip_udphy *udphy = dev_get_priv(phy->dev); + if (args->args_count == 0) return -EINVAL; if (args->args[0] != PHY_TYPE_USB3) return -EINVAL; + phy->id = udphy->id; + return 0; } static int rockchip_u3phy_init(struct phy *phy) { struct rockchip_udphy *udphy = dev_get_priv(phy->dev); + int ret; /* DP only or high-speed, disable U3 port */ if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { @@ -606,7 +550,12 @@ static int rockchip_u3phy_init(struct phy *phy) return 0; } - return udphy_power_on(udphy, UDPHY_MODE_USB); + ret = udphy_setup(udphy); + if (ret) + return ret; + + udphy_u3_port_disable(udphy, false); + return 0; } static int rockchip_u3phy_exit(struct phy *phy) @@ -617,7 +566,7 @@ static int rockchip_u3phy_exit(struct phy *phy) if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) return 0; - return udphy_power_off(udphy, UDPHY_MODE_USB); + return udphy_disable(udphy); } static const struct phy_ops rockchip_u3phy_ops = { @@ -813,6 +762,28 @@ static const char * const rk3588_udphy_rst_l[] = { "init", "cmn", "lane", "pcs_apb", "pma_apb" }; +static const struct rockchip_udphy_cfg rk3576_udphy_cfgs = { + .num_phys = 1, + .phy_ids = { + 0x2b010000, + }, + .num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l), + .rst_list = rk3588_udphy_rst_l, + .grfcfg = { + /* u2phy-grf */ + .bvalid_phy_con = { 0x0010, 1, 0, 0x2, 0x3 }, + .bvalid_grf_con = { 0x0000, 15, 14, 0x1, 0x3 }, + + /* usb-grf */ + .usb3otg0_cfg = { 0x0030, 15, 0, 0x1100, 0x0188 }, + + /* usbdpphy-grf */ + .low_pwrn = { 0x0004, 13, 13, 0, 1 }, + .rx_lfps = { 0x0004, 14, 14, 0, 1 }, + }, + .combophy_init = rk3588_udphy_init, +}; + static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { .num_phys = 2, .phy_ids = { @@ -839,6 +810,10 @@ static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { static const struct udevice_id rockchip_udphy_dt_match[] = { { + .compatible = "rockchip,rk3576-usbdp-phy", + .data = (ulong)&rk3576_udphy_cfgs + }, + { .compatible = "rockchip,rk3588-usbdp-phy", .data = (ulong)&rk3588_udphy_cfgs }, diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 6fa203a3b86..665b76a7d4d 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -204,7 +204,7 @@ static int zynqmp_pinctrl_prepare_func_groups(u32 fid, const char **fgroups; char name[MAX_GROUP_NAME_LEN]; u16 resp[NUM_GROUPS_PER_RESP] = {0}; - int ret, index, i; + int ret = 0, index, i; fgroups = kcalloc(func->ngroups, sizeof(*fgroups), GFP_KERNEL); if (!fgroups) @@ -460,14 +460,14 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, case PIN_CFG_IOSTANDARD: param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS; ret = zynqmp_pm_pinctrl_get_config(pin, param, &value); - if (arg != value) + if (!ret && arg != value) dev_warn(dev, "Invalid IO Standard requested for pin %d\n", pin); break; case PIN_CONFIG_POWER_SOURCE: param = PM_PINCTRL_CONFIG_VOLTAGE_STATUS; ret = zynqmp_pm_pinctrl_get_config(pin, param, &value); - if (arg != value) + if (!ret && arg != value) dev_warn(dev, "Invalid IO Standard requested for pin %d\n", pin); break; diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index cb2496ff1fb..d4acae15d55 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -516,7 +516,9 @@ static const char *sa8775p_get_function_name(struct udevice *dev, static const char *sa8775p_get_pin_name(struct udevice *dev, unsigned int selector) { - if (selector >= 149 && selector <= 155) + if (selector > 153) + strcpy(pin_name, "unknown"); + else if (selector >= 149) snprintf(pin_name, MAX_PIN_NAME_LEN, msm_special_pins_data[selector - 149].name); else diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 3f55fc81c8e..24b42e94c7a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -72,7 +72,7 @@ static const char *sdm845_get_pin_name(struct udevice *dev, "sdc2_data", }; - if (selector >= 150 && selector <= 154) + if (selector >= 150 && selector <= 153) snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 150]); else snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index 3c751e9473a..4a75e0b2372 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -353,7 +353,7 @@ static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, /* The pin selector refers to a multiplexed pin */ int port = rzg2l_selector_decode(data, pin_selector, &pin); if (port < 0) { - dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); + dev_err(dev, "Invalid pin selector %u\n", pin_selector); return port; } @@ -550,7 +550,7 @@ static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector, port = rzg2l_selector_decode(data, selector, &pin); if (port < 0) { - dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); + dev_err(dev, "Invalid pin selector %u\n", selector); return port; } diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 03cfe23aaf8..fd357ab0d4e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -760,7 +760,7 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_pinctrl_desc = }; static const struct sunxi_pinctrl_function sun55i_a523_pinctrl_functions[] = { - { "emac0", 5 }, /* PI0-PI16 */ + { "gmac0", 5 }, /* PI0-PI16 */ { "gpio_in", 0 }, { "gpio_out", 1 }, { "mmc0", 2 }, /* PF0-PF5 */ diff --git a/drivers/power/pmic/rk8xx.c b/drivers/power/pmic/rk8xx.c index 3bc696d4caa..d11f7a7886e 100644 --- a/drivers/power/pmic/rk8xx.c +++ b/drivers/power/pmic/rk8xx.c @@ -89,11 +89,6 @@ void rk8xx_off_for_plugin(struct udevice *dev) } } -static struct reg_data rk806_init_reg[] = { - /* RST_FUN */ - { RK806_REG_SYS_CFG3, BIT(7), GENMASK(7, 6)}, -}; - static struct reg_data rk817_init_reg[] = { /* enable the under-voltage protection, * the under-voltage protection will shutdown the LDO3 and reset the PMIC @@ -306,12 +301,20 @@ static int rk8xx_probe(struct udevice *dev) value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4); pmic_reg_write(dev, RK817_POWER_EN_SAVE1, value); break; - case RK806_ID: + case RK806_ID: { + u32 rst_fun = 2; + on_source = RK806_ON_SOURCE; off_source = RK806_OFF_SOURCE; - init_data = rk806_init_reg; - init_data_num = ARRAY_SIZE(rk806_init_reg); - break; + + ret = dev_read_u32(dev, "rockchip,reset-mode", &rst_fun); + if (ret) + debug("rockchip,reset-mode property missing, defaulting to %d\n", + rst_fun); + + pmic_clrsetbits(dev, RK806_REG_SYS_CFG3, RK806_RST_FUN_MSK, + FIELD_PREP(RK806_RST_FUN_MSK, rst_fun)); + break; } default: printf("Unknown PMIC: RK%x!!\n", show_variant); return -EINVAL; diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c index ca8a7fb4783..3ed02e11f9e 100644 --- a/drivers/ram/renesas/dbsc5/dram.c +++ b/drivers/ram/renesas/dbsc5/dram.c @@ -3735,7 +3735,7 @@ static u32 dbsc5_read_vref_training(struct udevice *dev) if (vref_stop_index > 0x80) return 0; - for (i = 0; i <= vref_stop_index; i++) { + for (i = 0; i < vref_stop_index; i++) { r_foreach_vch(dev, ch) { reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); reg &= 0xF << 10; @@ -3819,7 +3819,7 @@ static u32 dbsc5_read_vref_training(struct udevice *dev) best_vref_byte0_index = 0; best_dvw_min_byte0 = dvw_min_byte0_table[ch][0]; - for (i = 0; i <= vref_stop_index; i++) { + for (i = 0; i < vref_stop_index; i++) { if (best_dvw_min_byte0 >= dvw_min_byte0_table[ch][i]) continue; @@ -3858,7 +3858,7 @@ static u32 dbsc5_read_vref_training(struct udevice *dev) vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); best_upper_vref = best_vref_byte0; outlier_cnt = vref_outlier; - for (i = best_vref_byte0_index; i <= vref_stop_index; i++) { + for (i = best_vref_byte0_index; i < vref_stop_index; i++) { if (dvw_min_byte0_table[ch][i] <= 0) break; @@ -3879,7 +3879,7 @@ static u32 dbsc5_read_vref_training(struct udevice *dev) best_vref_byte1 = vref_start; best_vref_byte1_index = 0; best_dvw_min_byte1 = dvw_min_byte1_table[ch][0]; - for (i = 0; i <= vref_stop_index; i++) { + for (i = 0; i < vref_stop_index; i++) { if (best_dvw_min_byte1 >= dvw_min_byte1_table[ch][i]) continue; @@ -3918,7 +3918,7 @@ static u32 dbsc5_read_vref_training(struct udevice *dev) vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); best_upper_vref = best_vref_byte1; outlier_cnt = vref_outlier; - for (i = best_vref_byte1_index; i <= vref_stop_index; i++) { + for (i = best_vref_byte1_index; i < vref_stop_index; i++) { if (dvw_min_byte1_table[ch][i] <= 0) break; diff --git a/drivers/remoteproc/k3_system_controller.c b/drivers/remoteproc/k3_system_controller.c index 71238a6058a..e59c010de7e 100644 --- a/drivers/remoteproc/k3_system_controller.c +++ b/drivers/remoteproc/k3_system_controller.c @@ -327,7 +327,7 @@ static const struct k3_sysctrler_desc k3_sysctrler_am654_desc = { static const struct udevice_id k3_sysctrler_ids[] = { { - .compatible = "ti,am654-system-controller", + .compatible = "ti,am654-tisci-rproc-r5", .data = (ulong)&k3_sysctrler_am654_desc, }, {} diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c index d854ea90044..8cf750e043c 100644 --- a/drivers/rng/rockchip_rng.c +++ b/drivers/rng/rockchip_rng.c @@ -394,6 +394,10 @@ static const struct udevice_id rockchip_rng_match[] = { .data = (ulong)&rk_trngv1_soc_data, }, { + .compatible = "rockchip,rk3576-rng", + .data = (ulong)&rkrng_soc_data, + }, + { .compatible = "rockchip,rkrng", .data = (ulong)&rkrng_soc_data, }, diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 78efed6b66a..05608399be1 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -228,13 +228,11 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, blocks = max_blks; scsi_setup_read_ext(pccb, start, blocks); start += max_blks; - blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; blocks = blks; scsi_setup_read_ext(pccb, start, blocks); start += blks; - blks = 0; } debug("scsi_read_ext: startblk " LBAF ", blccnt " LBAF " buffer %lX\n", @@ -244,6 +242,7 @@ static ulong scsi_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, blkcnt -= blks; break; } + blks -= blocks; buf_addr += pccb->datalen; } while (blks != 0); debug("scsi_read_ext: end startblk " LBAF @@ -286,13 +285,11 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, blocks = max_blks; scsi_setup_write_ext(pccb, start, blocks); start += max_blks; - blks -= max_blks; } else { pccb->datalen = block_dev->blksz * blks; blocks = blks; scsi_setup_write_ext(pccb, start, blocks); start += blks; - blks = 0; } debug("%s: startblk " LBAF ", blccnt " LBAF " buffer %lx\n", __func__, start, blocks, buf_addr); @@ -301,6 +298,7 @@ static ulong scsi_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, blkcnt -= blks; break; } + blks -= blocks; buf_addr += pccb->datalen; } while (blks != 0); @@ -322,7 +320,7 @@ static ulong scsi_erase(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt) struct blk_desc *block_dev = dev_get_uclass_plat(dev); struct udevice *bdev = dev->parent; struct scsi_plat *uc_plat = dev_get_uclass_plat(bdev); - lbaint_t start, blks, max_blks; + lbaint_t start, blks, max_blks, blocks; struct scsi_cmd *pccb = (struct scsi_cmd *)&tempccb; /* Setup device */ @@ -339,19 +337,20 @@ static ulong scsi_erase(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt) __func__, block_dev->devnum, start, blks); do { if (blks > max_blks) { + blocks = max_blks; scsi_setup_erase_ext(pccb, start, max_blks); start += max_blks; - blks -= max_blks; } else { + blocks = blks; scsi_setup_erase_ext(pccb, start, blks); start += blks; - blks = 0; } if (scsi_exec(bdev, pccb)) { scsi_print_error(pccb); blkcnt -= blks; break; } + blks -= blocks; } while (blks != 0); return blkcnt; } diff --git a/drivers/serial/serial_efi.c b/drivers/serial/serial_efi.c index 5733eaaf9d4..d3cd4de34a2 100644 --- a/drivers/serial/serial_efi.c +++ b/drivers/serial/serial_efi.c @@ -33,7 +33,7 @@ int serial_efi_setbrg(struct udevice *dev, int baudrate) static int serial_efi_get_key(struct serial_efi_priv *priv) { - int ret; + efi_status_t ret; if (priv->have_key) return 0; diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index cb6c09fdd09..0eb90f82a34 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -252,6 +252,10 @@ static int msm_serial_setbrg(struct udevice *dev, int baud) priv->baud = baud; clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div); + if (!clk_rate) { + pr_err("%s: Couldn't get clock division rate\n", __func__); + return -EINVAL; + } ret = geni_serial_set_clock_rate(dev, clk_rate); if (ret < 0) { pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret); @@ -284,23 +288,19 @@ static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset, unsigned int tx_fifo_depth; unsigned int tx_fifo_width; unsigned int fifo_bits; - unsigned long timeout_us = 10000; - - baud = 115200; - - if (priv) { - baud = priv->baud; - if (!baud) - baud = 115200; - tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base); - tx_fifo_width = geni_se_get_tx_fifo_width(priv->base); - fifo_bits = tx_fifo_depth * tx_fifo_width; - /* - * Total polling iterations based on FIFO worth of bytes to be - * sent at current baud. Add a little fluff to the wait. - */ - timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; - } + unsigned long timeout_us; + + baud = priv->baud; + if (!baud) + baud = 115200; + tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base); + tx_fifo_width = geni_se_get_tx_fifo_width(priv->base); + fifo_bits = tx_fifo_depth * tx_fifo_width; + /* + * Total polling iterations based on FIFO worth of bytes to be + * sent at current baud. Add a little fluff to the wait. + */ + timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; while (timeout_us) { diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index 0c45c781fef..4b69ff3de13 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -63,7 +63,7 @@ static const struct zynqmp_device zynqmp_devices[] = { { .id = 0x04688093, .device = 1, - .variants = ZYNQMP_VARIANT_EG, + .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, }, { .id = 0x04689093, diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 8aa7a83aef4..b2b96e1c4b9 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -615,7 +615,8 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, static int atmel_qspi_transfer(struct atmel_qspi *aq, const struct spi_mem_op *op, u32 offset) { - u32 sr, imr; + u32 imr, val = 0; + unsigned long timeout; /* Skip to the final steps if there is no data */ if (op->data.nbytes) { @@ -636,8 +637,16 @@ static int atmel_qspi_transfer(struct atmel_qspi *aq, /* Poll INSTruction End and Chip Select Rise flags. */ imr = QSPI_SR_INSTRE | QSPI_SR_CSR; - return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr, - ATMEL_QSPI_TIMEOUT); + + timeout = timer_get_us() + ATMEL_QSPI_TIMEOUT; + while (1) { + val |= readl(aq->regs + QSPI_SR) & imr; + if ((val & imr) == imr) + return 0; + + if (time_after(timer_get_us(), timeout)) + return -ETIMEDOUT; + } } static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index 1b9bf004b7c..7f2965f8321 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -105,14 +105,10 @@ static int spi_rx_tx(struct exynos_spi_priv *priv, int todo, uint out_bytes, in_bytes; int toread; unsigned start = get_timer(0); - int stopping; int step; out_bytes = in_bytes = todo; - stopping = priv->skip_preamble && (flags & SPI_XFER_END) && - !(priv->mode & SPI_SLAVE); - /* * Try to transfer words if we can. This helps read performance at * SPI clock speeds above about 20MHz. @@ -161,12 +157,10 @@ static int spi_rx_tx(struct exynos_spi_priv *priv, int todo, while (rx_lvl >= step) { temp = readl(®s->rx_data); if (priv->skip_preamble) { - if (temp == SPI_PREAMBLE_END_BYTE) { + if (temp == SPI_PREAMBLE_END_BYTE) priv->skip_preamble = 0; - stopping = 0; - } } else { - if (rxp || stopping) { + if (rxp) { if (step == 4) *(uint32_t *)rxp = temp; else diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c index 6f44792abb0..6ce30d9eaf0 100644 --- a/drivers/sysreset/sysreset_socfpga_soc64.c +++ b/drivers/sysreset/sysreset_socfpga_soc64.c @@ -1,19 +1,78 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Pepperl+Fuchs + * Copyright (C) 2025 Altera Corporation <www.altera.com> * Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> */ +#include <command.h> +#include <cpu_func.h> #include <dm.h> #include <errno.h> #include <sysreset.h> #include <asm/arch/mailbox_s10.h> +#include <asm/arch/reset_manager.h> +#include <asm/secure.h> + +#define GICD_CTRL_ADDRESS 0xfffc1000 + +static __always_inline void __l2_reset_cpu(void) +{ + asm volatile(/* Disable GIC distributor (IRQs). */ + "str wzr, [%3]\n" + /* Set Magic Number */ + "str %0, [%1]\n" + /* Increase timeout in rstmgr.hdsktimeout */ + "ldr x2, =0xFFFFFF\n" + "str w2, [%2, #0x64]\n" + "ldr w2, [%2, #0x10]\n" + /* + * Set l2flushen = 1, etrstallen = 1, + * fpgahsen = 1 and sdrselfrefen = 1 + * in rstmgr.hdsken to perform handshake + * in certain peripherals before trigger + * L2 reset. + */ + "ldr x3, =0x10D\n" + "orr x2, x2, x3\n" + "str w2, [%2, #0x10]\n" + /* Trigger L2 reset in rstmgr.coldmodrst */ + "ldr w2, [%2, #0x34]\n" + "orr x2, x2, #0x100\n" + "isb\n" + "dsb sy\n" + "str w2, [%2, #0x34]\n" + /* Put all cores into WFI mode */ + "1:\n" + " wfi\n" + " b 1b\n" + : : "r" (L2_RESET_DONE_STATUS), + "r" (L2_RESET_DONE_REG), + "r" (SOCFPGA_RSTMGR_ADDRESS), + "r" (GICD_CTRL_ADDRESS) + : "x1", "x2", "x3"); +} + +static void l2_reset_cpu(void) +{ + __l2_reset_cpu(); +} static int socfpga_sysreset_request(struct udevice *dev, enum sysreset_t type) { - puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); - mbox_reset_cold(); + if (type == SYSRESET_WARM) { + /* flush dcache */ + flush_dcache_all(); + + /* request a warm reset */ + puts("Do warm reset now...\n"); + l2_reset_cpu(); + } else { + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); + } + return -EINPROGRESS; } diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index a30c40ef80e..9eaf7e40ab6 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -557,10 +557,10 @@ static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep) trace_cdns3_wa2(priv_ep, "removes eldest request"); + list_del_init(&priv_req->list); kfree(priv_req->request.buf); cdns3_gadget_ep_free_request(&priv_ep->endpoint, &priv_req->request); - list_del_init(&priv_req->list); --priv_ep->wa2_counter; if (!chain) @@ -1959,10 +1959,10 @@ static int cdns3_gadget_ep_disable(struct usb_ep *ep) while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); + list_del_init(&priv_req->list); kfree(priv_req->request.buf); cdns3_gadget_ep_free_request(&priv_ep->endpoint, &priv_req->request); - list_del_init(&priv_req->list); --priv_ep->wa2_counter; } diff --git a/drivers/usb/common/dwc2_core.c b/drivers/usb/common/dwc2_core.c index 63062d5cc94..37007134e5b 100644 --- a/drivers/usb/common/dwc2_core.c +++ b/drivers/usb/common/dwc2_core.c @@ -17,7 +17,7 @@ int dwc2_core_reset(struct dwc2_core_regs *regs) bool host_mode = false; if (!(readl(®s->global_regs.gotgctl) & GOTGCTL_CONID_B) || - (readl(®s->global_regs.gusbcfg) & GUSBCFG_FORCEDEVMODE)) + (readl(®s->global_regs.gusbcfg) & GUSBCFG_FORCEHOSTMODE)) host_mode = true; /* Core Soft Reset */ diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 3cda2b74b7e..c09014aec60 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -698,7 +698,9 @@ static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "ti,am654-dwc3" }, { .compatible = "rockchip,rk3328-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3399-dwc3" }, + { .compatible = "rockchip,rk3528-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3568-dwc3", .data = (ulong)&rk_ops }, + { .compatible = "rockchip,rk3576-dwc3", .data = (ulong)&rk_ops }, { .compatible = "rockchip,rk3588-dwc3", .data = (ulong)&rk_ops }, { .compatible = "qcom,dwc3", .data = (ulong)&qcom_ops }, { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops }, diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 531f0b522af..c656cbe25ce 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -380,7 +380,7 @@ static int dwc3_ep0_handle_status(struct dwc3 *dwc, dep = dwc->eps[0]; dwc->ep0_usb_req.dep = dep; dwc->ep0_usb_req.request.length = sizeof(*response_pkt); - dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr; + dwc->ep0_usb_req.request.buf = (void *)(uintptr_t)dwc->setup_buf_addr; dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); @@ -662,7 +662,7 @@ static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dep = dwc->eps[0]; dwc->ep0_usb_req.dep = dep; dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; - dwc->ep0_usb_req.request.buf = (void *)dwc->setup_buf_addr; + dwc->ep0_usb_req.request.buf = (void *)(uintptr_t)dwc->setup_buf_addr; dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 46a83141481..0121f9872ae 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -86,6 +86,7 @@ config USB_GADGET_PRODUCT_NUM default 0x350a if ROCKCHIP_RK3568 default 0x350b if ROCKCHIP_RK3588 default 0x350c if ROCKCHIP_RK3528 + default 0x350e if ROCKCHIP_RK3576 default 0x0 help Product ID of the USB device emulated, reported to the host device. @@ -201,12 +202,13 @@ config USB_FUNCTION_MASS_STORAGE the eMMC/SD card content to HOST PC so it can be mounted. config USB_FUNCTION_ROCKUSB - bool "Enable USB rockusb gadget" - help - Rockusb protocol is widely used by Rockchip SoC based devices. It can - read/write info, image to/from devices. This enables the USB part of - the rockusb gadget.for more detail about Rockusb protocol, please see - doc/README.rockusb + bool "Enable USB rockusb gadget" + depends on ARCH_ROCKCHIP + help + Rockusb protocol is widely used by Rockchip SoC based devices. It can + read/write info, image to/from devices. This enables the USB part of + the rockusb gadget.for more detail about Rockusb protocol, please see + doc/README.rockusb config USB_FUNCTION_SDP bool "Enable USB SDP (Serial Download Protocol)" diff --git a/drivers/usb/host/dwc3-of-simple.c b/drivers/usb/host/dwc3-of-simple.c index d52e7d22d1a..362178b7900 100644 --- a/drivers/usb/host/dwc3-of-simple.c +++ b/drivers/usb/host/dwc3-of-simple.c @@ -91,6 +91,7 @@ static int dwc3_of_simple_remove(struct udevice *dev) static const struct udevice_id dwc3_of_simple_ids[] = { { .compatible = "amlogic,meson-gxl-dwc3" }, { .compatible = "rockchip,rk3399-dwc3" }, + { .compatible = "samsung,exynos850-dwusb3" }, { .compatible = "ti,dwc3" }, { } }; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index a8748cef7ad..25907f22612 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -537,7 +537,7 @@ static int ehci_usb_phy_mode(struct udevice *dev) plat->init_type = USB_INIT_DEVICE; else plat->init_type = USB_INIT_HOST; - } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) { + } else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx9()) { phy_status = (void __iomem *)(addr + USBNC_PHY_STATUS_OFFSET); val = readl(phy_status); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index dfe4b3b8a02..b5777da5218 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -691,6 +691,23 @@ config VIDEO_LCD_HITACHI_TX18D42VM lcd controller which needs to be initialized over SPI, once that is done they work like a regular LVDS panel. +config VIDEO_LCD_SONY_L4F00430T01 + tristate "Sony L4F00430T01 480x800 LCD panel support" + depends on PANEL + help + Say Y here if you want to enable support for Sony L4F00430T01 + LCD module found in Samsung Galaxy R. The panel has a + WVGA resolution (480x800) and is setup over SPI, video + data comes from RGB. + +config VIDEO_LCD_SAMSUNG_S6E63M0 + tristate "Samsung S6E63M0 controller based panel support" + depends on PANEL && BACKLIGHT + help + Say Y here if you want to enable support for Samsung S6E63M0 + controller found in some panels like on Samsung Captivate Glide. + Currently only DBI C panel is implemented. + config VIDEO_LCD_SPI_CS string "SPI CS pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM @@ -821,6 +838,13 @@ config BACKLIGHT_LP855x supported for now, PWM mode can be added if there will be any need in it. Supported backlight level range is from 0 to 255 with step of 1. +config BACKLIGHT_SAMSUNG_CMC623 + bool "Backlight Driver for Samsung CMC623" + depends on VIDEO_BRIDGE_SAMSUNG_CMC623 + help + Say Y to enable the backlight driver for Samsung CMC623 image converter + chip's PWM output to control backlight brightness. + source "drivers/video/ti/Kconfig" source "drivers/video/exynos/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index ebe4a3961fc..96c7ce7bb09 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_backlight.o obj-$(CONFIG_BACKLIGHT_LM3532) += lm3532_backlight.o obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o +obj-$(CONFIG_BACKLIGHT_SAMSUNG_CMC623) += cmc623_backlight.o obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ @@ -74,6 +75,8 @@ obj-$(CONFIG_VIDEO_LCD_SHARP_LQ079L1SX01) += sharp-lq079l1sx01.o obj-$(CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01) += sharp-lq101r1sx01.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o +obj-$(CONFIG_VIDEO_LCD_SONY_L4F00430T01) += sony-l4f00430t01.o +obj-$(CONFIG_VIDEO_LCD_SAMSUNG_S6E63M0) += samsung-s6e63m0.o obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o obj-${CONFIG_VIDEO_MESON} += meson/ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index be53034bd3d..a48cec7a138 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -66,3 +66,11 @@ config VIDEO_BRIDGE_LVDS_CODEC help Support for transparent LVDS encoders and decoders that don't require any configuration. + +config VIDEO_BRIDGE_SAMSUNG_CMC623 + bool "Samsung CMC623 Image Converter driver" + depends on VIDEO_BRIDGE && DM_GPIO + select DM_I2C + help + Samsung CMC623 image converter chip driver. + Found in several Samsung devices such as N1 diff --git a/drivers/video/bridge/Makefile b/drivers/video/bridge/Makefile index 63dc6e62c49..520f36a7a6f 100644 --- a/drivers/video/bridge/Makefile +++ b/drivers/video/bridge/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_VIDEO_BRIDGE_ANALOGIX_ANX6345) += anx6345.o obj-$(CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825) += ssd2825.o obj-$(CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768) += tc358768.o obj-$(CONFIG_VIDEO_BRIDGE_LVDS_CODEC) += lvds-codec.o +obj-$(CONFIG_VIDEO_BRIDGE_SAMSUNG_CMC623) += cmc623.o diff --git a/drivers/video/bridge/cmc623.c b/drivers/video/bridge/cmc623.c new file mode 100644 index 00000000000..78dafef8145 --- /dev/null +++ b/drivers/video/bridge/cmc623.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Ion Agorria <ion@agorria.com> + */ + +#include <clk.h> +#include <dm.h> +#include <dm/ofnode_graph.h> +#include <i2c.h> +#include <log.h> +#include <backlight.h> +#include <panel.h> +#include <video_bridge.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/math64.h> +#include <power/regulator.h> +#include <asm/gpio.h> + +static const char * const cmc623_supplies[] = { + "vdd3v0-supply", "vdd1v2-supply", "vddio1v8-supply" +}; + +struct cmc623_priv { + struct udevice *panel; + struct display_timing timing; + + struct udevice *supplies[ARRAY_SIZE(cmc623_supplies)]; + + struct gpio_desc enable_gpio; /* also known as FAILSAFE */ + struct gpio_desc bypass_gpio; +}; + +static int cmc623_attach(struct udevice *dev) +{ + struct cmc623_priv *priv = dev_get_priv(dev); + int ret; + + /* Perform panel setup */ + ret = panel_enable_backlight(priv->panel); + if (ret) + return ret; + + return 0; +} + +static int cmc623_set_backlight(struct udevice *dev, int percent) +{ + struct cmc623_priv *priv = dev_get_priv(dev); + + return panel_set_backlight(priv->panel, percent); +} + +static int cmc623_panel_timings(struct udevice *dev, struct display_timing *timing) +{ + struct cmc623_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->timing, sizeof(*timing)); + + return 0; +} + +static int cmc623_hw_init(struct udevice *dev) +{ + struct cmc623_priv *priv = dev_get_priv(dev); + struct video_bridge_priv *uc_priv = dev_get_uclass_priv(dev); + int i, ret; + + /* enable supplies */ + for (i = 0; i < ARRAY_SIZE(cmc623_supplies); i++) { + ret = regulator_set_enable_if_allowed(priv->supplies[i], 1); + if (ret) { + log_debug("%s: cannot enable %s %d\n", __func__, + cmc623_supplies[i], ret); + return ret; + } + } + + mdelay(10); + + ret = dm_gpio_set_value(&uc_priv->reset, 1); + if (ret) { + log_debug("%s: error at reset = 1 (%d)\n", __func__, ret); + return ret; + } + + ret = dm_gpio_set_value(&priv->enable_gpio, 0); + if (ret) { + log_debug("%s: error at enable = 0 (%d)\n", __func__, ret); + return ret; + } + + ret = dm_gpio_set_value(&priv->bypass_gpio, 0); + if (ret) { + log_debug("%s: error at bypass = 0 (%d)\n", __func__, ret); + return ret; + } + + ret = dm_gpio_set_value(&uc_priv->sleep, 0); + if (ret) { + log_debug("%s: error at sleep = 0 (%d)\n", __func__, ret); + return ret; + } + + udelay(2000); + + ret = dm_gpio_set_value(&priv->enable_gpio, 1); + if (ret) { + log_debug("%s: error at enable = 1 (%d)\n", __func__, ret); + return ret; + } + + udelay(2000); + + ret = dm_gpio_set_value(&priv->bypass_gpio, 1); + if (ret) { + log_debug("%s: error at bypass = 1 (%d)\n", __func__, ret); + return ret; + } + + udelay(2000); + + ret = dm_gpio_set_value(&uc_priv->sleep, 1); + if (ret) { + log_debug("%s: error at sleep = 1 (%d)\n", __func__, ret); + return ret; + } + + udelay(2000); + + ret = dm_gpio_set_value(&uc_priv->reset, 0); + if (ret) { + log_debug("%s: error at sleep = 0 (%d)\n", __func__, ret); + return ret; + } + + mdelay(10); + + ret = dm_gpio_set_value(&uc_priv->reset, 1); + if (ret) { + log_debug("%s: error at sleep = 1 (%d)\n", __func__, ret); + return ret; + } + + mdelay(10); + + return 0; +} + +static int cmc623_get_panel(struct udevice *dev) +{ + struct cmc623_priv *priv = dev_get_priv(dev); + int i, ret; + + u32 num = ofnode_graph_get_port_count(dev_ofnode(dev)); + + for (i = 0; i < num; i++) { + ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1); + + ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel); + if (!ret) + return 0; + } + + /* If this point is reached, no panels were found */ + return -ENODEV; +} + +static int cmc623_probe(struct udevice *dev) +{ + struct cmc623_priv *priv = dev_get_priv(dev); + int i, ret; + + /* get supplies */ + for (i = 0; i < ARRAY_SIZE(cmc623_supplies); i++) { + ret = device_get_supply_regulator(dev, cmc623_supplies[i], &priv->supplies[i]); + if (ret) { + log_debug("%s: cannot get %s %d\n", __func__, cmc623_supplies[i], ret); + if (ret != -ENOENT) + return log_ret(ret); + } + } + + /* get control gpios */ + ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: could not get enable-gpios (%d)\n", __func__, ret); + return ret; + } + + ret = gpio_request_by_name(dev, "bypass-gpios", 0, &priv->bypass_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: could not get bypass-gpios (%d)\n", __func__, ret); + return ret; + } + + ret = cmc623_hw_init(dev); + if (ret) { + log_debug("%s: error doing hw init, ret %d\n", __func__, ret); + return ret; + } + + ret = cmc623_get_panel(dev); + if (ret) { + log_debug("%s: panel not found, ret %d\n", __func__, ret); + return ret; + } + + panel_get_display_timing(priv->panel, &priv->timing); + + return 0; +} + +static const struct video_bridge_ops cmc623_ops = { + .attach = cmc623_attach, + .set_backlight = cmc623_set_backlight, + .get_display_timing = cmc623_panel_timings, +}; + +static const struct udevice_id cmc623_ids[] = { + { .compatible = "samsung,cmc623" }, + { } +}; + +U_BOOT_DRIVER(samsung_cmc623) = { + .name = "samsung_cmc623", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = cmc623_ids, + .ops = &cmc623_ops, + .bind = dm_scan_fdt_dev, + .probe = cmc623_probe, + .priv_auto = sizeof(struct cmc623_priv), +}; diff --git a/drivers/video/cmc623_backlight.c b/drivers/video/cmc623_backlight.c new file mode 100644 index 00000000000..84b01724a07 --- /dev/null +++ b/drivers/video/cmc623_backlight.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Ion Agorria <ion@agorria.com> + */ + +#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT + +#include <backlight.h> +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <linux/err.h> +#include <asm/gpio.h> +#include <power/regulator.h> + +#define CMC623_I2C_REG_SELBANK 0x00 +#define CMC623_I2C_REG_PWMCTRL 0xb4 +#define CMC623_I2C_REG_REGMASK 0x28 + +#define CMC623_BL_MIN_BRIGHTNESS 0 +#define CMC623_BL_DEF_BRIGHTNESS 50 +#define CMC623_BL_MAX_BRIGHTNESS 100 + +struct cmc623_backlight_priv { + struct gpio_desc enable_gpio; +}; + +static int cmc623_backlight_enable(struct udevice *dev) +{ + struct cmc623_backlight_priv *priv = dev_get_priv(dev); + + if (dm_gpio_is_valid(&priv->enable_gpio)) + dm_gpio_set_value(&priv->enable_gpio, 1); + + return 0; +} + +static int cmc623_i2c_write(struct udevice *dev, u8 reg, u16 value) +{ + u8 data[2]; + + data[0] = (value >> 8) & 0xff; + data[1] = value & 0xff; + + return dm_i2c_write(dev->parent, reg, data, 2); +} + +static int cmc623_backlight_set_brightness(struct udevice *dev, int percent) +{ + int ret; + u16 brightness; + + if (percent == BACKLIGHT_DEFAULT) + percent = CMC623_BL_DEF_BRIGHTNESS; + + if (percent < CMC623_BL_MIN_BRIGHTNESS) + percent = CMC623_BL_MIN_BRIGHTNESS; + + if (percent > CMC623_BL_MAX_BRIGHTNESS) + percent = CMC623_BL_MAX_BRIGHTNESS; + + brightness = 0x4000 | (percent << 4); + + ret = cmc623_i2c_write(dev, CMC623_I2C_REG_SELBANK, 0x0000); + if (ret) { + log_debug("%s: error at CMC623_I2C_REG_SELBANK (%d)\n", + __func__, ret); + return ret; + } + + ret = cmc623_i2c_write(dev, CMC623_I2C_REG_PWMCTRL, brightness); + if (ret) { + log_debug("%s: error at CMC623_I2C_REG_PWMCTRL (%d)\n", + __func__, ret); + return ret; + } + + ret = cmc623_i2c_write(dev, CMC623_I2C_REG_REGMASK, 0x0000); + if (ret) { + log_debug("%s: error at CMC623_I2C_REG_REGMASK (%d)\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int cmc623_backlight_of_to_plat(struct udevice *dev) +{ + struct cmc623_backlight_priv *priv = dev_get_priv(dev); + + gpio_request_by_name(dev, "enable-gpios", 0, + &priv->enable_gpio, GPIOD_IS_OUT); + + return 0; +} + +static int cmc623_backlight_probe(struct udevice *dev) +{ + if (device_get_uclass_id(dev->parent) != UCLASS_VIDEO_BRIDGE) + return -EPROTONOSUPPORT; + + return 0; +} + +static const struct backlight_ops cmc623_backlight_ops = { + .enable = cmc623_backlight_enable, + .set_brightness = cmc623_backlight_set_brightness, +}; + +static const struct udevice_id cmc623_backlight_ids[] = { + { .compatible = "samsung,cmc623-backlight" }, + { } +}; + +U_BOOT_DRIVER(cmc623_backlight) = { + .name = "cmc623_backlight", + .id = UCLASS_PANEL_BACKLIGHT, + .of_match = cmc623_backlight_ids, + .of_to_plat = cmc623_backlight_of_to_plat, + .probe = cmc623_backlight_probe, + .ops = &cmc623_backlight_ops, + .priv_auto = sizeof(struct cmc623_backlight_priv), +}; diff --git a/drivers/video/samsung-s6e63m0.c b/drivers/video/samsung-s6e63m0.c new file mode 100644 index 00000000000..7497fc0f53a --- /dev/null +++ b/drivers/video/samsung-s6e63m0.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Ion Agorria <ion@agorria.com> + */ + +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <malloc.h> +#include <spi.h> +#include <mipi_display.h> +#include <linux/delay.h> +#include <power/regulator.h> +#include <asm/gpio.h> + +#define S6E63M0_DCS_CMD 0 +#define S6E63M0_DCS_DATA 1 + +#define S6E63M0_INFO_FLAG_PGAMMACTL BIT(0) +#define S6E63M0_INFO_FLAG_GAMMA_DELTA BIT(1) + +#define S6E63M0_GTCON_FLAG_FLIP_H BIT(0) +#define S6E63M0_GTCON_FLAG_FLIP_V BIT(1) + +/* Manufacturer Command Set */ +#define MCS_PENTILE_1 0xb3 +#define MCS_GAMMA_DELTA_Y_RED 0xb5 +#define MCS_GAMMA_DELTA_X_RED 0xb6 +#define MCS_GAMMA_DELTA_Y_GREEN 0xb7 +#define MCS_GAMMA_DELTA_X_GREEN 0xb8 +#define MCS_GAMMA_DELTA_Y_BLUE 0xb9 +#define MCS_GAMMA_DELTA_X_BLUE 0xba +#define MCS_DISCTL 0xf2 +#define MCS_SRCCTL 0xf6 +#define MCS_IFCTL 0xf7 +#define MCS_PANELCTL 0xf8 +#define MCS_PGAMMACTL 0xfa + +#define MCS_PANELCTL_LEN 14 +#define MCS_IFCTL_LEN 3 +#define MCS_PGAMMACTL_LEN 22 +#define MCS_GAMMA_DELTA_Y_LEN 32 +#define MCS_GAMMA_DELTA_X_LEN 16 + +struct s6e63m0_priv { + struct udevice *vdd3; + struct udevice *vci; + + struct s6e63m0_info *info; + + struct gpio_desc reset_gpio; + + u8 gtcon; +}; + +struct s6e63m0_info { + const u32 flags; + struct display_timing timing; + const u8 cmd_mcs_panelctl[MCS_PANELCTL_LEN]; + const u8 cmd_mcs_pgammactl_1[MCS_PGAMMACTL_LEN]; + const u8 cmd_mcs_pgammactl_2; + const u8 cmd_mcs_gamma_delta_y[MCS_GAMMA_DELTA_Y_LEN]; + const u8 cmd_mcs_gamma_delta_x[MCS_GAMMA_DELTA_X_LEN]; +}; + +static const struct s6e63m0_info s6e63m0_generic_info = { + .flags = S6E63M0_INFO_FLAG_GAMMA_DELTA, + .timing = { + .pixelclock.typ = 25628, + .hactive.typ = 480, + .hfront_porch.typ = 16, + .hback_porch.typ = 16, + .hsync_len.typ = 2, + .vactive.typ = 800, + .vfront_porch.typ = 28, + .vback_porch.typ = 1, + .vsync_len.typ = 2, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, + }, + .cmd_mcs_panelctl = { + 0x01, /* DOCT */ 0x27, /* CLWEA */ + 0x27, /* CLWEB*/ 0x07, /* CLTE */ + 0x07, /* SHE */ 0x54, /* FLTE */ + 0x9F, /* FLWE */ 0x63, /* SCTE */ + 0x8F, /* SCWE */ 0x1A, /* INTE */ + 0x33, /* INWE */ 0x0D, /* EMPS */ + 0x00, /* E_INTE */ 0x00 /* E_INWE */ + }, + .cmd_mcs_pgammactl_1 = { + 0x00, 0x18, 0x08, 0x24, 0x64, 0x56, 0x33, 0xb6, + 0xba, 0xa8, 0xac, 0xb1, 0x9d, 0xc1, 0xc1, 0xb7, + 0x00, 0x9c, 0x00, 0x9f, 0x00, 0xd6 + }, + .cmd_mcs_pgammactl_2 = 0x01, + .cmd_mcs_gamma_delta_y = { + 0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17, 0x13, + 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b, 0x1a, 0x17, + 0x2b, 0x26, 0x22, 0x20, 0x3a, 0x34, 0x30, 0x2c, + 0x29, 0x26, 0x25, 0x23, 0x21, 0x20, 0x1e, 0x1e + }, + .cmd_mcs_gamma_delta_x = { + 0x00, 0x00, 0x11, 0x22, 0x33, 0x44, 0x44, 0x44, + 0x55, 0x55, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66 + }, +}; + +static const struct s6e63m0_info samsung_bose_panel_info = { + .flags = S6E63M0_INFO_FLAG_PGAMMACTL | S6E63M0_INFO_FLAG_GAMMA_DELTA, + .timing = { + .pixelclock.typ = 24000000, + .hactive.typ = 480, + .hfront_porch.typ = 16, + .hback_porch.typ = 14, + .hsync_len.typ = 2, + .vactive.typ = 800, + .vfront_porch.typ = 28, + .vback_porch.typ = 1, + .vsync_len.typ = 2, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_LOW | DISPLAY_FLAGS_PIXDATA_NEGEDGE, + }, + .cmd_mcs_panelctl = { + 0x01, /* DOCT */ 0x27, /* CLWEA */ + 0x27, /* CLWEB*/ 0x07, /* CLTE */ + 0x07, /* SHE */ 0x54, /* FLTE */ + 0x9F, /* FLWE */ 0x63, /* SCTE */ + 0x86, /* SCWE */ 0x1A, /* INTE */ + 0x33, /* INWE */ 0x0D, /* EMPS */ + 0x00, /* E_INTE */ 0x00 /* E_INWE */ + }, + .cmd_mcs_pgammactl_1 = { + 0x02, 0x18, 0x08, 0x24, 0x70, 0x6e, 0x4e, 0xbc, + 0xc0, 0xaf, 0xb3, 0xb8, 0xa5, 0xc5, 0xc7, 0xbb, + 0x00, 0xb9, 0x00, 0xb8, 0x00, 0xfc + }, + .cmd_mcs_pgammactl_2 = 0x03, + .cmd_mcs_gamma_delta_y = { + 0x2c, 0x12, 0x0c, 0x0a, 0x10, 0x0e, 0x17, 0x13, + 0x1f, 0x1a, 0x2a, 0x24, 0x1f, 0x1b, 0x1a, 0x17, + 0x2b, 0x26, 0x22, 0x20, 0x3a, 0x34, 0x30, 0x2c, + 0x29, 0x26, 0x25, 0x23, 0x21, 0x20, 0x1e, 0x1e + }, + .cmd_mcs_gamma_delta_x = { + 0x00, 0x00, 0x11, 0x22, 0x33, 0x44, 0x44, 0x44, + 0x55, 0x55, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66 + }, +}; + +static int s6e63m0_dcs_write(struct udevice *dev, u8 cmd, const u8 *seq, size_t len) +{ + int ret; + u8 data[2]; + int i; + + data[0] = S6E63M0_DCS_CMD; + data[1] = cmd; + + ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE); + if (ret) + return ret; + + for (i = 0; i < len; i++) { + data[0] = S6E63M0_DCS_DATA; + data[1] = seq[i]; + + ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE); + if (ret) + return ret; + } + + return 0; +} + +#define s6e63m0_dcs_write_seq_static(dev, cmd, seq ...) ({ \ + static const u8 d[] = { seq }; \ + ret = s6e63m0_dcs_write(dev, cmd, d, ARRAY_SIZE(d)); \ + if (ret) \ + return ret; \ +}) + +static int s6e63m0_enable_backlight(struct udevice *dev) +{ + struct s6e63m0_priv *priv = dev_get_priv(dev); + struct s6e63m0_info *info = priv->info; + u8 cmd_mcs_ifctl[MCS_IFCTL_LEN]; + int ret; + + ret = s6e63m0_dcs_write(dev, MCS_PANELCTL, info->cmd_mcs_panelctl, MCS_PANELCTL_LEN); + if (ret) + return ret; + + s6e63m0_dcs_write_seq_static(dev, MCS_DISCTL, + 0x02, /* Number of Line */ + 0x03, /* VBP */ + 0x1c, /* VFP */ + 0x10, /* HBP */ + 0x10); /* HFP */ + + cmd_mcs_ifctl[0] = priv->gtcon; /* GTCON */ + cmd_mcs_ifctl[1] = 0x00; /* Display Mode */ + cmd_mcs_ifctl[2] = 0x00; /* Vsync/Hsync, DOCCLK, RGB mode */ + ret = s6e63m0_dcs_write(dev, MCS_IFCTL, cmd_mcs_ifctl, MCS_IFCTL_LEN); + if (ret) + return ret; + + if (info->flags & S6E63M0_INFO_FLAG_PGAMMACTL) { + ret = s6e63m0_dcs_write(dev, MCS_PGAMMACTL, info->cmd_mcs_pgammactl_1, + MCS_PGAMMACTL_LEN); + if (ret) + return ret; + + s6e63m0_dcs_write(dev, MCS_PGAMMACTL, &info->cmd_mcs_pgammactl_2, 1); + } + + s6e63m0_dcs_write_seq_static(dev, MCS_SRCCTL, 0x00, 0x8e, 0x07); + s6e63m0_dcs_write_seq_static(dev, MCS_PENTILE_1, 0x6c); + + if (info->flags & S6E63M0_INFO_FLAG_GAMMA_DELTA) { + ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_Y_RED, info->cmd_mcs_gamma_delta_y, + MCS_GAMMA_DELTA_Y_LEN); + if (ret) + return ret; + + ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_X_RED, info->cmd_mcs_gamma_delta_x, + MCS_GAMMA_DELTA_X_LEN); + if (ret) + return ret; + + ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_Y_GREEN, info->cmd_mcs_gamma_delta_y, + MCS_GAMMA_DELTA_Y_LEN); + if (ret) + return ret; + + ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_X_GREEN, info->cmd_mcs_gamma_delta_x, + MCS_GAMMA_DELTA_X_LEN); + if (ret) + return ret; + + ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_Y_BLUE, info->cmd_mcs_gamma_delta_y, + MCS_GAMMA_DELTA_Y_LEN); + if (ret) + return ret; + + ret = s6e63m0_dcs_write(dev, MCS_GAMMA_DELTA_X_BLUE, info->cmd_mcs_gamma_delta_x, + MCS_GAMMA_DELTA_X_LEN); + if (ret) + return ret; + } + + s6e63m0_dcs_write_seq_static(dev, MIPI_DCS_EXIT_SLEEP_MODE); + s6e63m0_dcs_write_seq_static(dev, MIPI_DCS_SET_DISPLAY_ON); + + return 0; +} + +static int s6e63m0_set_backlight(struct udevice *dev, int percent) +{ + return 0; +} + +static int s6e63m0_get_display_timing(struct udevice *dev, struct display_timing *timing) +{ + struct s6e63m0_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->info->timing, sizeof(*timing)); + + return 0; +} + +static int s6e63m0_of_to_plat(struct udevice *dev) +{ + struct s6e63m0_priv *priv = dev_get_priv(dev); + int ret; + + ret = device_get_supply_regulator(dev, "vdd3-supply", &priv->vdd3); + if (ret) { + log_debug("%s: cannot get vdd3-supply: ret = %d\n", + __func__, ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vci-supply", &priv->vci); + if (ret) { + log_debug("%s: cannot get vci-supply: ret = %d\n", + __func__, ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: cannot decode reset-gpios (%d)\n", + __func__, ret); + return ret; + } + + if (dev_read_bool(dev, "flip-horizontal")) + priv->gtcon |= S6E63M0_GTCON_FLAG_FLIP_H; + + if (dev_read_bool(dev, "flip-vertical")) + priv->gtcon |= S6E63M0_GTCON_FLAG_FLIP_V; + + return 0; +} + +static int s6e63m0_hw_init(struct udevice *dev) +{ + struct s6e63m0_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: error entering reset (%d)\n", __func__, ret); + return ret; + } + + ret = regulator_set_enable_if_allowed(priv->vdd3, 1); + if (ret) { + log_debug("%s: enabling vdd3-supply failed (%d)\n", + __func__, ret); + return ret; + } + + mdelay(1); + + ret = regulator_set_enable_if_allowed(priv->vci, 1); + if (ret) { + log_debug("%s: enabling vci-supply failed (%d)\n", + __func__, ret); + return ret; + } + + mdelay(26); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: error exiting reset (%d)\n", __func__, ret); + return ret; + } + + mdelay(10); + + return 0; +} + +static int s6e63m0_probe(struct udevice *dev) +{ + struct s6e63m0_priv *priv = dev_get_priv(dev); + struct spi_slave *slave = dev_get_parent_priv(dev); + int ret; + + if (device_get_uclass_id(dev->parent) != UCLASS_SPI) + return -EPROTONOSUPPORT; + + ret = spi_claim_bus(slave); + if (ret) { + log_err("SPI bus allocation failed (%d)\n", ret); + return ret; + } + + priv->info = (struct s6e63m0_info *)dev_get_driver_data(dev); + + return s6e63m0_hw_init(dev); +} + +static const struct panel_ops s6e63m0_ops = { + .enable_backlight = s6e63m0_enable_backlight, + .set_backlight = s6e63m0_set_backlight, + .get_display_timing = s6e63m0_get_display_timing, +}; + +static const struct udevice_id s6e63m0_ids[] = { + { + .compatible = "samsung,s6e63m0", + .data = (ulong)&s6e63m0_generic_info + }, + { + .compatible = "samsung,bose-panel", + .data = (ulong)&samsung_bose_panel_info + }, + { } +}; + +U_BOOT_DRIVER(samsung_s6e63m0) = { + .name = "samsung_s6e63m0", + .id = UCLASS_PANEL, + .of_match = s6e63m0_ids, + .ops = &s6e63m0_ops, + .of_to_plat = s6e63m0_of_to_plat, + .probe = s6e63m0_probe, + .priv_auto = sizeof(struct s6e63m0_priv), +}; diff --git a/drivers/video/sony-l4f00430t01.c b/drivers/video/sony-l4f00430t01.c new file mode 100644 index 00000000000..2303eb86143 --- /dev/null +++ b/drivers/video/sony-l4f00430t01.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Ion Agorria <ion@agorria.com> + */ + +#include <backlight.h> +#include <dm.h> +#include <panel.h> +#include <log.h> +#include <spi.h> +#include <mipi_display.h> +#include <linux/delay.h> +#include <power/regulator.h> +#include <asm/gpio.h> + +#define SONY_L4F00430T01_DCS_CMD 0 +#define SONY_L4F00430T01_DCS_DATA 1 + +struct sony_l4f00430t01_priv { + struct udevice *vdd1v8; + struct udevice *vdd3v0; + + struct udevice *backlight; + + struct gpio_desc reset_gpio; +}; + +static struct display_timing default_timing = { + .pixelclock.typ = 24000000, + .hactive.typ = 480, + .hfront_porch.typ = 10, + .hback_porch.typ = 20, + .hsync_len.typ = 10, + .vactive.typ = 800, + .vfront_porch.typ = 3, + .vback_porch.typ = 4, + .vsync_len.typ = 2, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, +}; + +static int sony_l4f00430t01_write(struct udevice *dev, u8 cmd, const u8 *seq, int len) +{ + u8 data[2]; + int i, ret; + + data[0] = SONY_L4F00430T01_DCS_CMD; + data[1] = cmd; + + ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE); + if (ret) + return ret; + + for (i = 0; i < len; i++) { + data[0] = SONY_L4F00430T01_DCS_DATA; + data[1] = seq[i]; + + ret = dm_spi_xfer(dev, 9, &data, NULL, SPI_XFER_ONCE); + if (ret) + return ret; + } + + return 0; +} + +#define sony_l4f00430t01_write_seq(dev, cmd, seq...) do { \ + static const u8 b[] = { seq }; \ + sony_l4f00430t01_write(dev, cmd, b, ARRAY_SIZE(b)); \ + } while (0) + +static int sony_l4f00430t01_enable_backlight(struct udevice *dev) +{ + sony_l4f00430t01_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0xd4); + mdelay(25); + + sony_l4f00430t01_write_seq(dev, MIPI_DCS_EXIT_SLEEP_MODE); + mdelay(150); + + sony_l4f00430t01_write_seq(dev, MIPI_DCS_SET_DISPLAY_ON); + + return 0; +} + +static int sony_l4f00430t01_set_backlight(struct udevice *dev, int percent) +{ + struct sony_l4f00430t01_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_debug("%s: cannot get backlight: ret = %d\n", + __func__, ret); + return ret; + } + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + return backlight_set_brightness(priv->backlight, percent); +} + +static int sony_l4f00430t01_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int sony_l4f00430t01_of_to_plat(struct udevice *dev) +{ + struct sony_l4f00430t01_priv *priv = dev_get_priv(dev); + int ret; + + ret = device_get_supply_regulator(dev, "vdd1v8-supply", &priv->vdd1v8); + if (ret) { + log_debug("%s: cannot get vdd1v8-supply: ret = %d\n", + __func__, ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vdd3v0-supply", &priv->vdd3v0); + if (ret) { + log_debug("%s: cannot get vdd3v0-supply: ret = %d\n", + __func__, ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: cannot decode reset-gpios (%d)\n", + __func__, ret); + return ret; + } + + return 0; +} + +static int sony_l4f00430t01_hw_init(struct udevice *dev) +{ + struct sony_l4f00430t01_priv *priv = dev_get_priv(dev); + int ret; + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: error entering reset (%d)\n", __func__, ret); + return ret; + } + + ret = regulator_set_enable_if_allowed(priv->vdd1v8, 1); + if (ret) { + log_debug("%s: enabling vdd1v8-supply failed (%d)\n", + __func__, ret); + return ret; + } + + ret = regulator_set_enable_if_allowed(priv->vdd3v0, 1); + if (ret) { + log_debug("%s: enabling vdd3v0-supply failed (%d)\n", + __func__, ret); + return ret; + } + mdelay(15); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: error exiting reset (%d)\n", __func__, ret); + return ret; + } + mdelay(100); + + return 0; +} + +static int sony_l4f00430t01_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + int ret; + + ret = spi_claim_bus(slave); + if (ret) { + log_err("SPI bus allocation failed (%d)\n", ret); + return ret; + } + + return sony_l4f00430t01_hw_init(dev); +} + +static const struct panel_ops sony_l4f00430t01_ops = { + .enable_backlight = sony_l4f00430t01_enable_backlight, + .set_backlight = sony_l4f00430t01_set_backlight, + .get_display_timing = sony_l4f00430t01_get_display_timing, +}; + +static const struct udevice_id sony_l4f00430t01_ids[] = { + { .compatible = "sony,l4f00430t01" }, + { } +}; + +U_BOOT_DRIVER(sony_l4f00430t01) = { + .name = "sony_l4f00430t01", + .id = UCLASS_PANEL, + .of_match = sony_l4f00430t01_ids, + .ops = &sony_l4f00430t01_ops, + .of_to_plat = sony_l4f00430t01_of_to_plat, + .probe = sony_l4f00430t01_probe, + .priv_auto = sizeof(struct sony_l4f00430t01_priv), +}; diff --git a/drivers/video/tegra/dc.c b/drivers/video/tegra/dc.c index f0e3d2c993f..ced49718834 100644 --- a/drivers/video/tegra/dc.c +++ b/drivers/video/tegra/dc.c @@ -238,8 +238,24 @@ static void rgb_enable(struct tegra_lcd_priv *priv) else value &= ~LVS_OUTPUT_POLARITY_LOW; + /* configure pixel data signal polarity */ + if (dt->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) + value &= ~LSC0_OUTPUT_POLARITY_LOW; + else + value |= LSC0_OUTPUT_POLARITY_LOW; + writel(value, &com->pin_output_polarity[1]); + /* configure data enable signal polarity */ + value = readl(&com->pin_output_polarity[3]); + + if (dt->flags & DISPLAY_FLAGS_DE_LOW) + value |= LSPI_OUTPUT_POLARITY_LOW; + else + value &= ~LSPI_OUTPUT_POLARITY_LOW; + + writel(value, &com->pin_output_polarity[3]); + for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) writel(rgb_sel_tab[i], &com->pin_output_sel[i]); } diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 306fa5b3f68..3a40b12f6e5 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -349,9 +349,10 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num, /* TODO: allocate each queue chunk individually */ for (; num && vring_size(num, vring_align) > PAGE_SIZE; num /= 2) { - size_t sz = vring_size(num, vring_align); + vring.size = vring_size(num, vring_align); - queue = virtio_alloc_pages(vdev, DIV_ROUND_UP(sz, PAGE_SIZE)); + queue = virtio_alloc_pages(vdev, + DIV_ROUND_UP(vring.size, PAGE_SIZE)); if (queue) break; } @@ -362,6 +363,7 @@ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num, if (!queue) { /* Try to get a single page. You are my only hope! */ queue = virtio_alloc_pages(vdev, 1); + vring.size = PAGE_SIZE; } if (!queue) return NULL; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 56290b32bd9..9e149a75e81 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -31,7 +31,7 @@ config WATCHDOG_TIMEOUT_MSECS default 128000 if ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SNAPDRAGON - default 30000 if ARCH_SOCFPGA + default 10000 if ARCH_SOCFPGA default 16000 if ARCH_SUNXI default 5376 if ULP_WATCHDOG default 15000 if ARCH_BCM283X diff --git a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml index 3c2b06629b7..eb5bca31948 100644 --- a/dts/upstream/Bindings/mfd/rockchip,rk806.yaml +++ b/dts/upstream/Bindings/mfd/rockchip,rk806.yaml @@ -31,6 +31,27 @@ properties: system-power-controller: true + rockchip,reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + Mode to use when a reset of the PMIC is triggered. + + The reset can be triggered either programmatically, via one of + the PWRCTRL pins (provided additional configuration) or + asserting RESETB pin low. + + The following modes are supported + + - 0; restart PMU, + - 1; reset all power off reset registers and force state to + switch to ACTIVE mode, + - 2; same as mode 1 and also pull RESETB pin down for 5ms, + + For example, some hardware may require a full restart (mode 0) + in order to function properly as regulators are shortly + interrupted in this mode. + vcc1-supply: description: The input supply for dcdc-reg1. diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts index ebe77cdd24e..176925d0a1a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts @@ -10,6 +10,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/soc/rockchip,vop2.h> #include <dt-bindings/usb/pd.h> +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -693,6 +694,7 @@ vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = <RK806_RESTART>; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi index c4933a08dd1..b44e89e1bb1 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> +#include "rk8xx.h" #include "rk3588.dtsi" / { @@ -440,6 +441,7 @@ vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; vcca-supply = <&vcc5v0_sys>; + rockchip,reset-mode = <RK806_RESTART>; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; diff --git a/dts/upstream/src/arm64/rockchip/rk8xx.h b/dts/upstream/src/arm64/rockchip/rk8xx.h new file mode 100644 index 00000000000..a6fbef71c06 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk8xx.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Device Tree defines for Rockchip RK8xx PMICs + * + * Copyright 2025 Cherry Embedded Solutions GmbH + * + * Author: Quentin Schulz <quentin.schulz@cherry.de> + */ + +#ifndef _DT_MFD_ROCKCHIP_RK8XX_H +#define _DT_MFD_ROCKCHIP_RK8XX_H + +/* For use with rockchip,reset-mode property */ +#define RK806_RESTART 0 +#define RK806_RESET 1 +#define RK806_RESET_NOTIFY 2 + +#endif diff --git a/env/Kconfig b/env/Kconfig index c667e8f2da1..adea277470f 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -635,7 +635,7 @@ config ENV_OFFSET_REDUND config ENV_OFFSET_REDUND_RELATIVE_END bool "Offset is relative to the end of the partition" - depends on SYS_REDUNDAND_ENVIRONMENT + depends on ENV_REDUNDANT depends on ENV_IS_IN_MMC help Treat the redundant environment offset as relative to the end of the @@ -732,7 +732,7 @@ config ENV_MMC_USE_SW_PARTITION depends on ENV_IS_IN_MMC config ENV_MMC_SW_PARTITION - bool "SD/MMC environment software partition name" + string "SD/MMC environment software partition name" depends on ENV_MMC_USE_SW_PARTITION help SD/MMC software partition name used to save environment variables. @@ -957,6 +957,7 @@ config USE_BOOTFILE config BOOTFILE string "'bootfile' environment variable value" + default kernel.itb if SPL_ATF && TARGET_SOCFPGA_SOC64 depends on USE_BOOTFILE help The value to set the "bootfile" variable to. diff --git a/env/mtd.c b/env/mtd.c index d7ec30e183a..b26ee80985a 100644 --- a/env/mtd.c +++ b/env/mtd.c @@ -131,6 +131,8 @@ static int env_mtd_save(void) puts("done\n"); done: + put_mtd_device(mtd_env); + if (saved_buf) free(saved_buf); @@ -188,6 +190,8 @@ static int env_mtd_load(void) gd->env_valid = ENV_VALID; out: + put_mtd_device(mtd_env); + free(buf); return ret; @@ -197,7 +201,7 @@ static int env_mtd_erase(void) { struct mtd_info *mtd_env; u32 sect_size, sect_num; - char *saved_buf, *tmp; + char *saved_buf = NULL, *tmp; struct erase_info ei; size_t ret_len; int remaining; @@ -280,6 +284,8 @@ static int env_mtd_erase(void) ret = 0; done: + put_mtd_device(mtd_env); + if (saved_buf) free(saved_buf); diff --git a/env/nand.c b/env/nand.c index fdaa903cd61..709f8411eb6 100644 --- a/env/nand.c +++ b/env/nand.c @@ -275,7 +275,7 @@ int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result) int ret; ops.datbuf = NULL; - ops.mode = MTD_OOB_AUTO; + ops.mode = MTD_OPS_AUTO_OOB; ops.ooboffs = 0; ops.ooblen = ENV_OFFSET_SIZE; ops.oobbuf = (void *)oob_buf; diff --git a/include/ACEX1K.h b/include/ACEX1K.h index 7c5253c66cc..4d24545df2c 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -12,10 +12,6 @@ #include <altera.h> -extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size); -extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize); -extern int ACEX1K_info(Altera_desc *desc); - extern int CYC2_load(Altera_desc *desc, const void *image, size_t size); extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize); extern int CYC2_info(Altera_desc *desc); @@ -24,18 +20,6 @@ extern int CYC2_info(Altera_desc *desc); typedef struct { Altera_pre_fn pre; Altera_config_fn config; - Altera_clk_fn clk; - Altera_status_fn status; - Altera_done_fn done; - Altera_data_fn data; - Altera_abort_fn abort; - Altera_post_fn post; -} Altera_ACEX1K_Passive_Serial_fns; - -/* Slave Serial Implementation function table */ -typedef struct { - Altera_pre_fn pre; - Altera_config_fn config; Altera_status_fn status; Altera_done_fn done; Altera_write_fn write; @@ -45,16 +29,6 @@ typedef struct { /* Device Image Sizes *********************************************************************/ -/* ACEX1K */ -/* FIXME: Which size do we mean? - * Datasheet says 1337000/8=167125Bytes, - * Filesize of an *.rbf file is 166965 Bytes - */ -#if 0 -#define Altera_EP1K100_SIZE 1337000/8 /* 167125 Bytes */ -#endif -#define Altera_EP1K100_SIZE (166965*8) - #define Altera_EP2C8_SIZE 247942 #define Altera_EP2C20_SIZE 586562 #define Altera_EP2C35_SIZE 883905 @@ -70,10 +44,4 @@ typedef struct { #define ALTERA_EP4CE75_SIZE 2495719 /* 19965752 Bits */ #define ALTERA_EP4CE115_SIZE 3571462 /* 28571696 Bits */ -/* Descriptor Macros - *********************************************************************/ -/* ACEX1K devices */ -#define Altera_EP1K100_DESC(iface, fn_table, cookie) \ -{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie } - #endif /* _ACEX1K_H_ */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 266b77fbf68..8c29c940478 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -11,30 +11,13 @@ #ifndef __CONFIG_AM57XX_EVM_H #define __CONFIG_AM57XX_EVM_H -#include <env/ti/dfu.h> #include <linux/sizes.h> #define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#ifndef CONFIG_XPL_BUILD -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_QSPI -#else -#ifdef CONFIG_SPL_DFU -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_RAM -#endif -#endif - -#include <configs/ti_omap5_common.h> - /* CPSW Ethernet */ +#include <configs/ti_omap5_common.h> #endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 1ade6adfa0b..f1c432aa391 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -145,12 +145,14 @@ #else /* CONFIG_DISTRO_DEFAULTS */ # define BOOTENV +# define BOOTENV_DEV_SHARED_XSPI #endif /* CONFIG_DISTRO_DEFAULTS */ /* Initial environment variables */ #ifndef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ + "usb_pgood_delay=2000\0" \ BOOTENV \ BOOTENV_DEV_SHARED_XSPI \ DFU_ALT_INFO diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 3c960ca2ce2..9df7ef055bf 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -11,40 +11,16 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H -#include <env/ti/dfu.h> - #define CFG_MAX_MEM_MAPPED 0x80000000 #ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ #endif -#if (CONFIG_CONS_INDEX == 1) -#define CONSOLEDEV "ttyS0" -#elif (CONFIG_CONS_INDEX == 3) -#define CONSOLEDEV "ttyS2" -#endif #define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#ifndef CONFIG_XPL_BUILD -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_QSPI -#endif - -#ifdef CONFIG_XPL_BUILD -#ifdef CONFIG_SPL_DFU -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_RAM -#endif -#endif - #include <configs/ti_omap5_common.h> /* NAND support */ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index e7db0161126..ffd72a38bcb 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -11,10 +11,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_XPL_BUILD -#define CFG_MALLOC_F_ADDR 0x204D0000 -#endif - #ifdef CONFIG_ENV_MMC_DEVICE_INDEX #define IMX93_EVK_MMC_ENV_DEV CONFIG_ENV_MMC_DEVICE_INDEX #else diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h index 987fcacb999..c98c10774cb 100644 --- a/include/configs/imx93_frdm.h +++ b/include/configs/imx93_frdm.h @@ -11,10 +11,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_XPL_BUILD -#define CFG_MALLOC_F_ADDR 0x204D0000 -#endif - /* Link Definitions */ #define CFG_SYS_INIT_RAM_ADDR 0x80000000 diff --git a/include/configs/imx93_qsb.h b/include/configs/imx93_qsb.h index 5ddc191d17c..a7b94f7ab57 100644 --- a/include/configs/imx93_qsb.h +++ b/include/configs/imx93_qsb.h @@ -9,10 +9,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -#define CFG_MALLOC_F_ADDR 0x204D0000 -#endif - #define CFG_SYS_INIT_RAM_ADDR 0x80000000 #define CFG_SYS_INIT_RAM_SIZE 0x200000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 0c449e31099..52c3695ff8e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -18,7 +18,8 @@ #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ - "fdt_addr_r=0x01f00000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x04000000\0" diff --git a/include/configs/socfpga_agilex7m_socdk.h b/include/configs/socfpga_agilex7m_socdk.h new file mode 100644 index 00000000000..deff70ee67a --- /dev/null +++ b/include/configs/socfpga_agilex7m_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2025 Altera Corporation <www.altera.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX7M_H__ +#define __CONFIG_SOCFGPA_AGILEX7M_H__ + +#include <configs/socfpga_soc64_common.h> + +#endif /* __CONFIG_SOCFGPA_AGILEX7M_H__ */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 83b600c7fcc..3d09a06f63e 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -19,6 +19,20 @@ #define CPU_RELEASE_ADDR 0xFFD12210 /* + * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR + * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3. + */ +#define L2_RESET_DONE_REG 0xFFD12218 + +/* sysmgr.boot_scratch_cold8 bit 17 (1bit) will be used to check whether CPU0 + * is being powered off/on from kernel + */ +#define BOOT_SCRATCH_COLD8 0xFFD12220 + +/* Magic word to indicate L2 reset is completed */ +#define L2_RESET_DONE_STATUS 0x1228E5E7 + +/* * U-Boot console configurations */ @@ -39,6 +53,9 @@ * U-Boot environment configurations */ +#define CFG_SYS_NAND_U_BOOT_SIZE (1 * 1024 * 1024) +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE + /* * Environment variable */ @@ -159,6 +176,7 @@ " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ "scriptaddr=0x05FF0000\0" \ "scriptfile=boot.scr\0" \ + "nandroot=ubi0:rootfs\0" \ "socfpga_legacy_reset_compat=1\0" \ "smc_fid_rd=0xC2000007\0" \ "smc_fid_wr=0xC2000008\0" \ @@ -214,6 +232,10 @@ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ "then source ${scriptaddr}:script; fi\0" \ + "nandfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1; " \ + "bootm ${loadaddr}\0" \ + "nandfitload=ubi part root; ubi readvol ${loadaddr} kernel\0" \ "socfpga_legacy_reset_compat=1\0" \ "smc_fid_rd=0xC2000007\0" \ "smc_fid_wr=0xC2000008\0" \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 39102f15eb9..9e02b0d0040 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -39,216 +39,6 @@ #define DFUARGS #endif -#include <env/ti/mmc.h> -#include <env/ti/nand.h> - -#ifndef CONSOLEDEV -#define CONSOLEDEV "ttyS2" -#endif - -#ifndef PARTS_DEFAULT -/* - * Default GPT tables for eMMC (Linux and Android). Notes: - * 1. Keep partitions aligned to erase group size (512 KiB) when possible - * 2. Keep partitions in sync with DFU_ALT_INFO_EMMC (see dfu.h) - * 3. Keep 'bootloader' partition (U-Boot proper) start address in sync with - * CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (see common/spl/Kconfig) - */ -#define PARTS_DEFAULT \ - /* Linux partitions */ \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=bootloader,start=384K,size=1792K,uuid=${uuid_gpt_bootloader};" \ - "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \ - /* Android partitions */ \ - "partitions_android=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=xloader,start=128K,size=256K,uuid=${uuid_gpt_xloader};" \ - "name=bootloader,size=2048K,uuid=${uuid_gpt_bootloader};" \ - "name=uboot-env,start=2432K,size=256K,uuid=${uuid_gpt_reserved};" \ - "name=misc,size=128K,uuid=${uuid_gpt_misc};" \ - "name=boot_a,size=20M,uuid=${uuid_gpt_boot_a};" \ - "name=boot_b,size=20M,uuid=${uuid_gpt_boot_b};" \ - "name=dtbo_a,size=8M,uuid=${uuid_gpt_dtbo_a};" \ - "name=dtbo_b,size=8M,uuid=${uuid_gpt_dtbo_b};" \ - "name=vbmeta_a,size=64K,uuid=${uuid_gpt_vbmeta_a};" \ - "name=vbmeta_b,size=64K,uuid=${uuid_gpt_vbmeta_b};" \ - "name=recovery,size=64M,uuid=${uuid_gpt_recovery};" \ - "name=super,size=2560M,uuid=${uuid_gpt_super};" \ - "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \ - "name=userdata,size=-,uuid=${uuid_gpt_userdata}" -#endif /* PARTS_DEFAULT */ - -#if defined(CONFIG_CMD_AVB) -#define AVB_VERIFY_CHECK "if run avb_verify; then " \ - "echo AVB verification OK.;" \ - "set bootargs $bootargs $avb_bootargs;" \ - "else " \ - "echo AVB verification failed.;" \ - "exit; fi;" -#define AVB_VERIFY_CMD "avb_verify=avb init 1; avb verify $slot_suffix;\0" -#else -#define AVB_VERIFY_CHECK "" -#define AVB_VERIFY_CMD "" -#endif - -#define CONTROL_PARTITION "misc" - -#if defined(CONFIG_CMD_BCB) && defined(CONFIG_ANDROID_AB) -#define AB_SELECT_SLOT \ - "if part number mmc 1 " CONTROL_PARTITION " control_part_number; " \ - "then " \ - "echo " CONTROL_PARTITION \ - " partition number:${control_part_number};" \ - "bcb ab_select slot_name mmc ${mmcdev}:${control_part_number};" \ - "else " \ - "echo " CONTROL_PARTITION " partition not found;" \ - "exit;" \ - "fi;" \ - "setenv slot_suffix _${slot_name};" -#define AB_SELECT_ARGS \ - "setenv bootargs_ab androidboot.slot_suffix=${slot_suffix}; " \ - "echo A/B cmdline addition: ${bootargs_ab};" \ - "setenv bootargs ${bootargs} ${bootargs_ab};" -#else -#define AB_SELECT_SLOT "" -#define AB_SELECT_ARGS "" -#endif - -/* - * Prepares complete device tree blob for current board (for Android boot). - * - * Boot image or recovery image should be loaded into $loadaddr prior to running - * these commands. The logic of these commnads is next: - * - * 1. Read correct DTB for current SoC/board from boot image in $loadaddr - * to $fdtaddr - * 2. Merge all needed DTBO for current board from 'dtbo' partition into read - * DTB - * 3. User should provide $fdtaddr as 3rd argument to 'bootm' - */ -#define PREPARE_FDT \ - "echo Preparing FDT...; " \ - "if test $board_name = am57xx_evm_reva3; then " \ - "echo \" Reading DTBO partition...\"; " \ - "part start mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_start; " \ - "part size mmc ${mmcdev} dtbo${slot_suffix} p_dtbo_size; " \ - "mmc read ${dtboaddr} ${p_dtbo_start} ${p_dtbo_size}; " \ - "echo \" Reading DTB for AM57x EVM RevA3...\"; " \ - "abootimg get dtb --index=0 dtb_start dtb_size; " \ - "cp.b $dtb_start $fdtaddr $dtb_size; " \ - "fdt addr $fdtaddr 0x80000; " \ - "echo \" Applying DTBOs for AM57x EVM RevA3...\"; " \ - "adtimg addr $dtboaddr; " \ - "adtimg get dt --index=0 dtbo0_addr dtbo0_size; " \ - "fdt apply $dtbo0_addr; " \ - "adtimg get dt --index=1 dtbo1_addr dtbo1_size; " \ - "fdt apply $dtbo1_addr; " \ - "elif test $board_name = beagle_x15_revc; then " \ - "echo \" Reading DTB for Beagle X15 RevC...\"; " \ - "abootimg get dtb --index=0 dtb_start dtb_size; " \ - "cp.b $dtb_start $fdtaddr $dtb_size; " \ - "fdt addr $fdtaddr 0x80000; " \ - "else " \ - "echo Error: Android boot is not supported for $board_name; " \ - "exit; " \ - "fi; " \ - -#define DEFAULT_COMMON_BOOT_TI_ARGS \ - "console=" CONSOLEDEV ",115200n8\0" \ - "fdtfile=undefined\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - AVB_VERIFY_CMD \ - "partitions=" PARTS_DEFAULT "\0" \ - "optargs=\0" \ - "dofastboot=0\0" \ - "emmc_android_boot=" \ - "setenv mmcdev 1; " \ - "mmc dev $mmcdev; " \ - "mmc rescan; " \ - AB_SELECT_SLOT \ - "if bcb load " __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) " " \ - CONTROL_PARTITION "; then " \ - "setenv ardaddr -; " \ - "if bcb test command = bootonce-bootloader; then " \ - "echo Android: Bootloader boot...; " \ - "bcb clear command; bcb store; " \ - "fastboot 1; " \ - "exit; " \ - "elif bcb test command = boot-recovery; then " \ - "echo Android: Recovery boot...; " \ - "setenv ardaddr $loadaddr;" \ - "setenv apart recovery; " \ - "else " \ - "echo Android: Normal boot...; " \ - "setenv ardaddr $loadaddr; " \ - "setenv apart boot${slot_suffix}; " \ - "fi; " \ - "else " \ - "echo Warning: BCB is corrupted or does not exist; " \ - "echo Android: Normal boot...; " \ - "fi; " \ - "setenv eval_bootargs setenv bootargs $bootargs; " \ - "run eval_bootargs; " \ - "setenv machid fe6; " \ - AVB_VERIFY_CHECK \ - AB_SELECT_ARGS \ - "if part start mmc $mmcdev $apart boot_start; then " \ - "part size mmc $mmcdev $apart boot_size; " \ - "mmc read $loadaddr $boot_start $boot_size; " \ - PREPARE_FDT \ - "bootm $loadaddr $ardaddr $fdtaddr; " \ - "else " \ - "echo $apart partition not found; " \ - "exit; " \ - "fi;\0" - -#define DEFAULT_FDT_TI_ARGS \ - "findfdt="\ - "if test $board_name = omap5_uevm; then " \ - "setenv fdtfile omap5-uevm.dtb; fi; " \ - "if test $board_name = dra7xx; then " \ - "setenv fdtfile dra7-evm.dtb; fi;" \ - "if test $board_name = dra72x-revc; then " \ - "setenv fdtfile dra72-evm-revc.dtb; fi;" \ - "if test $board_name = dra72x; then " \ - "setenv fdtfile dra72-evm.dtb; fi;" \ - "if test $board_name = dra71x; then " \ - "setenv fdtfile dra71-evm.dtb; fi;" \ - "if test $board_name = dra76x_acd; then " \ - "setenv fdtfile dra76-evm.dtb; fi;" \ - "if test $board_name = beagle_x15; then " \ - "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ - "if test $board_name = beagle_x15_revb1; then " \ - "setenv fdtfile am57xx-beagle-x15-revb1.dtb; fi;" \ - "if test $board_name = beagle_x15_revc; then " \ - "setenv fdtfile am57xx-beagle-x15-revc.dtb; fi;" \ - "if test $board_name = am5729_beagleboneai; then " \ - "setenv fdtfile am5729-beagleboneai.dtb; fi;" \ - "if test $board_name = am572x_idk; then " \ - "setenv fdtfile am572x-idk.dtb; fi;" \ - "if test $board_name = am574x_idk; then " \ - "setenv fdtfile am574x-idk.dtb; fi;" \ - "if test $board_name = am57xx_evm; then " \ - "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ - "if test $board_name = am57xx_evm_reva3; then " \ - "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ - "if test $board_name = am571x_idk; then " \ - "setenv fdtfile am571x-idk.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" - -#define GET_OVERLAY_MMC_TI_ARGS \ - "get_overlay_mmc=" \ - "fdt address ${fdtaddr};" \ - "fdt resize 0x100000;" \ - "for overlay in $name_overlays;" \ - "do;" \ - "load mmc ${bootpart} ${dtboaddr} ${bootdir}/dtb/${overlay} &&" \ - "fdt apply ${dtboaddr};" \ - "done;\0" \ - #define BOOT_TARGET_DEVICES(func) \ func(TI_MMC, ti_mmc, na) \ func(MMC, mmc, 0) \ @@ -265,24 +55,6 @@ #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "get_name_kern=" \ - "if test $boot_fit -eq 1; then " \ - "setenv bootfile fitImage; " \ - "else " \ - "setenv bootfile zImage; " \ - "fi\0" \ - DEFAULT_FIT_TI_ARGS \ - "get_fit_config=setenv name_fit_config ${fdtfile}\0" \ - DEFAULT_COMMON_BOOT_TI_ARGS \ - DEFAULT_FDT_TI_ARGS \ - GET_OVERLAY_MMC_TI_ARGS \ - DFUARGS \ - NETARGS \ - NANDARGS \ BOOTENV /* diff --git a/include/configs/voyager.h b/include/configs/voyager.h new file mode 100644 index 00000000000..f6630b07ec9 --- /dev/null +++ b/include/configs/voyager.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Andes Technology Corporation + * Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define RISCV_MMODE_TIMERBASE 0xe6000000 +#define RISCV_MMODE_TIMER_FREQ 60000000 + +#define RISCV_SMODE_TIMER_FREQ 60000000 + +/* support JEDEC */ +#define PHYS_FLASH_1 0x8000000 /* BANK 0 */ +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CFG_SYS_FLASH_BANKS_SIZES { 0x4000000 } + +/* Enable distro boot */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x400600000\0" \ + "kernel_comp_addr_r=0x404600000\0" \ + "kernel_comp_size=0x04000000\0" \ + "pxefile_addr_r=0x408600000\0" \ + "scriptaddr=0x408700000\0" \ + "fdt_addr_r=0x408800000\0" \ + "ramdisk_addr_r=0x408900000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 5c0fd6d171b..6be59093160 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -79,6 +79,7 @@ enum uclass_id { UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_MUX, /* I2C multiplexer */ UCLASS_I2S, /* I2S bus */ + UCLASS_I3C, /* I3C bus */ UCLASS_IDE, /* IDE device */ UCLASS_IOMMU, /* IOMMU */ UCLASS_IRQ, /* Interrupt controller */ diff --git a/include/dw-i3c.h b/include/dw-i3c.h new file mode 100644 index 00000000000..c652de77404 --- /dev/null +++ b/include/dw-i3c.h @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#ifndef _DW_I3C_H_ +#define _DW_I3C_H_ + +#include <clk.h> +#include <i3c.h> +#include <reset.h> +#include <dm/device.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linker_lists.h> +#include <linux/i3c/master.h> + +#define DEVICE_CTRL 0x0 +#define DEV_CTRL_ENABLE BIT(31) +#define DEV_CTRL_RESUME BIT(30) +#define DEV_CTRL_HOT_JOIN_NACK BIT(8) +#define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7) + +#define DEVICE_ADDR 0x4 +#define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31) +#define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16)) + +#define HW_CAPABILITY 0x8 +#define COMMAND_QUEUE_PORT 0xc +#define COMMAND_PORT_TOC BIT(30) +#define COMMAND_PORT_READ_TRANSFER BIT(28) +#define COMMAND_PORT_SDAP BIT(27) +#define COMMAND_PORT_ROC BIT(26) +#define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21)) +#define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16)) +#define COMMAND_PORT_CP BIT(15) +#define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7)) +#define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3)) + +#define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16)) +#define COMMAND_PORT_ARG_DATA_LEN_MAX 65536 +#define COMMAND_PORT_TRANSFER_ARG 0x01 + +#define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24)) +#define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16)) +#define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8)) +#define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5) +#define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4) +#define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3) +#define COMMAND_PORT_SHORT_DATA_ARG 0x02 + +#define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21)) +#define COMMAND_PORT_ADDR_ASSGN_CMD 0x03 + +#define RESPONSE_QUEUE_PORT 0x10 +#define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28) +#define RESPONSE_NO_ERROR 0 +#define RESPONSE_ERROR_CRC 1 +#define RESPONSE_ERROR_PARITY 2 +#define RESPONSE_ERROR_FRAME 3 +#define RESPONSE_ERROR_IBA_NACK 4 +#define RESPONSE_ERROR_ADDRESS_NACK 5 +#define RESPONSE_ERROR_OVER_UNDER_FLOW 6 +#define RESPONSE_ERROR_TRANSF_ABORT 8 +#define RESPONSE_ERROR_I2C_W_NACK_ERR 9 +#define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24) +#define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0)) + +#define RX_TX_DATA_PORT 0x14 +#define IBI_QUEUE_STATUS 0x18 +#define QUEUE_THLD_CTRL 0x1c +#define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8) +#define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8) + +#define DATA_BUFFER_THLD_CTRL 0x20 +#define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8) + +#define IBI_QUEUE_CTRL 0x24 +#define IBI_MR_REQ_REJECT 0x2C +#define IBI_SIR_REQ_REJECT 0x30 +#define IBI_REQ_REJECT_ALL GENMASK(31, 0) + +#define RESET_CTRL 0x34 +#define RESET_CTRL_IBI_QUEUE BIT(5) +#define RESET_CTRL_RX_FIFO BIT(4) +#define RESET_CTRL_TX_FIFO BIT(3) +#define RESET_CTRL_RESP_QUEUE BIT(2) +#define RESET_CTRL_CMD_QUEUE BIT(1) +#define RESET_CTRL_SOFT BIT(0) + +#define SLV_EVENT_CTRL 0x38 +#define INTR_STATUS 0x3c +#define INTR_STATUS_EN 0x40 +#define INTR_SIGNAL_EN 0x44 +#define INTR_FORCE 0x48 +#define INTR_BUSOWNER_UPDATE_STAT BIT(13) +#define INTR_IBI_UPDATED_STAT BIT(12) +#define INTR_READ_REQ_RECV_STAT BIT(11) +#define INTR_DEFSLV_STAT BIT(10) +#define INTR_TRANSFER_ERR_STAT BIT(9) +#define INTR_DYN_ADDR_ASSGN_STAT BIT(8) +#define INTR_CCC_UPDATED_STAT BIT(6) +#define INTR_TRANSFER_ABORT_STAT BIT(5) +#define INTR_RESP_READY_STAT BIT(4) +#define INTR_CMD_QUEUE_READY_STAT BIT(3) +#define INTR_IBI_THLD_STAT BIT(2) +#define INTR_RX_THLD_STAT BIT(1) +#define INTR_TX_THLD_STAT BIT(0) +#define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \ + INTR_IBI_UPDATED_STAT | \ + INTR_READ_REQ_RECV_STAT | \ + INTR_DEFSLV_STAT | \ + INTR_TRANSFER_ERR_STAT | \ + INTR_DYN_ADDR_ASSGN_STAT | \ + INTR_CCC_UPDATED_STAT | \ + INTR_TRANSFER_ABORT_STAT | \ + INTR_RESP_READY_STAT | \ + INTR_CMD_QUEUE_READY_STAT | \ + INTR_IBI_THLD_STAT | \ + INTR_TX_THLD_STAT | \ + INTR_RX_THLD_STAT) + +#define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \ + INTR_RESP_READY_STAT) + +#define QUEUE_STATUS_LEVEL 0x4c +#define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24) +#define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16) +#define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8) +#define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0)) + +#define DATA_BUFFER_STATUS_LEVEL 0x50 +#define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0)) + +#define PRESENT_STATE 0x54 +#define CCC_DEVICE_STATUS 0x58 +#define DEVICE_ADDR_TABLE_POINTER 0x5c +#define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16) +#define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0)) + +#define DEV_CHAR_TABLE_POINTER 0x60 +#define VENDOR_SPECIFIC_REG_POINTER 0x6c +#define SLV_PID_VALUE 0x74 +#define SLV_CHAR_CTRL 0x78 +#define SLV_MAX_LEN 0x7c +#define MAX_READ_TURNAROUND 0x80 +#define MAX_DATA_SPEED 0x84 +#define SLV_DEBUG_STATUS 0x88 +#define SLV_INTR_REQ 0x8c +#define DEVICE_CTRL_EXTENDED 0xb0 +#define SCL_I3C_OD_TIMING 0xb4 +#define SCL_I3C_PP_TIMING 0xb8 +#define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) +#define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0)) +#define SCL_I3C_TIMING_CNT_MIN 5 + +#define SCL_I2C_FM_TIMING 0xbc +#define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16)) +#define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) + +#define SCL_I2C_FMP_TIMING 0xc0 +#define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) +#define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) + +#define SCL_EXT_LCNT_TIMING 0xc8 +#define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24)) +#define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16)) +#define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8)) +#define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0)) + +#define SCL_EXT_TERMN_LCNT_TIMING 0xcc +#define BUS_FREE_TIMING 0xd4 +#define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0)) + +#define BUS_IDLE_TIMING 0xd8 +#define I3C_VER_ID 0xe0 +#define I3C_VER_TYPE 0xe4 +#define EXTENDED_CAPABILITY 0xe8 +#define SLAVE_CONFIG 0xec + +#define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) +#define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16)) +#define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0)) +#define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2)) + +#define MAX_DEVS 32 + +#define I3C_BUS_SDR1_SCL_RATE 8000000 +#define I3C_BUS_SDR2_SCL_RATE 6000000 +#define I3C_BUS_SDR3_SCL_RATE 4000000 +#define I3C_BUS_SDR4_SCL_RATE 2000000 +#define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300 +#define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500 +#define I3C_BUS_THIGH_MAX_NS 41 + +#define XFER_TIMEOUT (msecs_to_jiffies(1000)) +#define readl_poll_timeout_atomic readl_poll_sleep_timeout +#define STRUCT_SZ(struct, count) (sizeof(struct) * (count)) + +#define I3C_MSG_READ 1 +#define I3C_MSG_WRITE 0 +#define POLL_SUCCESS 0 + +struct dw_i3c_master_caps { + u8 cmdfifodepth; + u8 datafifodepth; +}; + +struct dw_i3c_cmd { + u32 cmd_lo; + u32 cmd_hi; + u16 tx_len; + const void *tx_buf; + u16 rx_len; + void *rx_buf; + u8 error; +}; + +struct dw_i3c_xfer { + struct list_head node; + int ret; + unsigned int ncmds; + struct dw_i3c_cmd cmds[16]; +}; + +struct dw_i3c_master { + struct i3c_master_controller base; + u16 maxdevs; + u16 datstartaddr; + u32 free_pos; + struct { + struct list_head list; + struct dw_i3c_xfer *cur; + spinlock_t lock; /* spinlock for i3c transfer */ + } xferqueue; + struct dw_i3c_master_caps caps; + void __iomem *regs; + struct reset_ctl_bulk resets; + struct clk core_clk; + char version[5]; + char type[5]; + u8 addrs[MAX_DEVS]; + bool first_broadcast; + struct i3c_dev_desc *i3cdev[I3C_BUS_MAX_DEVS]; + u16 num_i3cdevs; +}; + +struct dw_i3c_i2c_dev_data { + u8 index; +}; + +#endif /*_DW_I3C_H_*/ diff --git a/include/env/ti/dfu.env b/include/env/ti/dfu.env new file mode 100644 index 00000000000..b925730c6f5 --- /dev/null +++ b/include/env/ti/dfu.env @@ -0,0 +1,53 @@ +dfu_alt_info_mmc= + boot part 0 1; + rootfs part 0 2; + MLO fat 0 1; + MLO.raw raw 0x100 0x200; + u-boot.img.raw raw 0x300 0x1000; + u-env.raw raw 0x1300 0x200; + spl-os-args.raw raw 0x1500 0x200; + spl-os-image.raw raw 0x1700 0x6900; + spl-os-args fat 0 1; + spl-os-image fat 0 1; + u-boot.img fat 0 1; + uEnv.txt fat 0 1 + +dfu_alt_info_emmc= + rawemmc raw 0 3751936; + boot part 1 1; + rootfs part 1 2; + MLO fat 1 1; + MLO.raw raw 0x100 0x200; + u-boot.img.raw raw 0x300 0x1000; + u-env.raw raw 0x1300 0x200; + spl-os-args.raw raw 0x1500 0x200; + spl-os-image.raw raw 0x1700 0x6900; + spl-os-args fat 1 1; + spl-os-image fat 1 1; + u-boot.img fat 1 1; + uEnv.txt fat 1 1 + +#if CONFIG_MTD_RAW_NAND +dfu_alt_info_nand= + SPL part 0 1; + SPL.backup1 part 0 2; + SPL.backup2 part 0 3; + SPL.backup3 part 0 4; + u-boot part 0 5; + u-boot-spl-os part 0 6; + kernel part 0 8; + rootfs part 0 9 +#endif + +dfu_alt_info_ram= + kernel ram 0x80200000 0x4000000; + fdt ram 0x80f80000 0x80000; + ramdisk ram 0x81000000 0x4000000 + +dfu_alt_info_qspi= + MLO raw 0x0 0x040000; + u-boot.img raw 0x040000 0x0100000; + u-boot-spl-os raw 0x140000 0x080000; + u-boot-env raw 0x1C0000 0x010000; + u-boot-env.backup raw 0x1D0000 0x010000; + kernel raw 0x1E0000 0x800000 diff --git a/include/fpga.h b/include/fpga.h index a144238e66a..20153b2082a 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -25,7 +25,6 @@ typedef enum { /* typedef fpga_type */ fpga_min_type, /* range check value */ fpga_xilinx, /* Xilinx Family) */ fpga_altera, /* unimplemented */ - fpga_lattice, /* Lattice family */ fpga_undefined /* invalid range check value */ } fpga_type; /* end, typedef fpga_type */ diff --git a/include/i3c.h b/include/i3c.h new file mode 100644 index 00000000000..e19c22a8852 --- /dev/null +++ b/include/i3c.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <linux/i3c/master.h> + +/** + * struct dm_i3c_ops - Driver operations for the I3C uclass + * + * This structure defines the set of operations that a driver must implement + * for interacting with an I3C controller in U-Boot. + * + */ +struct dm_i3c_ops { +/** + * @i3c_xfers: Transfer messages in I3C + * + * @dev: I3C controller device instance. + * @xfers: List of I3C private SDR transfer messages. + * @nxfers: The number of messages to transfer. + * + * Return: 0 on success, negative error code on failure. + */ + int (*i3c_xfers)(struct i3c_dev_desc *dev, + struct i3c_priv_xfer *xfers, + u32 nxfers); + +/** + * @read: Perform I3C read transaction. + * + * @dev: Chip to read from + * @dev_number: The target device number from the driver model. + * @buf: Place to put data + * @num_bytes: Number of bytes to read. + * + * Return: 0 on success, negative error code on failure. + */ + int (*read)(struct udevice *dev, u32 dev_number, + u8 *buf, u32 num_bytes); + +/** + * @write: Perform I3C write transaction. + * + * @dev: Chip to write to + * @dev_number: The target device number from the driver model. + * @buf: Buffer containing data to write + * @num_bytes: Number of bytes to write. + * + * Return: 0 on success, negative error code on failure. + */ + int (*write)(struct udevice *dev, u32 dev_number, + u8 *buf, u32 num_bytes); +}; + +/** + * i3c_get_ops - Retrieve the I3C operation functions for a device + * @dev: The I3C controller device. + * + * This macro returns the set of operation functions (`dm_i3c_ops`) implemented + * by the driver associated with the specified device. These operations define + * how the driver performs I3C communication tasks such as reading, writing, + * and message transfers. + * + * Return: The I3C operation structure for the device. + */ +#define i3c_get_ops(dev) ((struct dm_i3c_ops *)(dev)->driver->ops) + +/** + * dm_i3c_write - Perform I3C write transaction + * + * @dev: Chip to write to + * @dev_number: The target device number from the driver model. + * @buf: Buffer containing data to write + * @num_bytes: Number of bytes to write. + * + * Return: 0 on success, negative error code on failure. + */ +int dm_i3c_write(struct udevice *dev, u32 dev_number, + u8 *buf, u32 num_bytes); + +/** + * dm_i3c_read - Perform I3C read transaction + * + * @dev: Chip to read from + * @dev_number: The target device number from the driver model. + * @buf: Place to put data + * @num_bytes: Number of bytes to read. + * + * Return: 0 on success, negative error code on failure. + */ +int dm_i3c_read(struct udevice *dev, u32 dev_number, + u8 *buf, u32 num_bytes); diff --git a/include/lattice.h b/include/lattice.h deleted file mode 100644 index 80fafc00dcb..00000000000 --- a/include/lattice.h +++ /dev/null @@ -1,298 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Porting to U-Boot: - * - * (C) Copyright 2010 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * Lattice's ispVME Embedded Tool to load Lattice's FPGA: - * - * Lattice Semiconductor Corp. Copyright 2009 - */ - -#ifndef _VME_OPCODE_H -#define _VME_OPCODE_H - -#define VME_VERSION_NUMBER "12.1" - -/* Maximum declarations. */ - -#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */ -#define SCANMAX 64000L /* The maximum SDR/SIR burst. */ - -/* - * - * Supported JTAG state transitions. - * - */ - -#define RESET 0x00 -#define IDLE 0x01 -#define IRPAUSE 0x02 -#define DRPAUSE 0x03 -#define SHIFTIR 0x04 -#define SHIFTDR 0x05 -/* 11/15/05 Nguyen changed to support DRCAPTURE*/ -#define DRCAPTURE 0x06 - -/* - * Flow control register bit definitions. A set bit indicates - * that the register currently exhibits the corresponding mode. - */ - -#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */ -#define CASCADE 0x0002 /* Currently splitting large SDR. */ -#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */ -#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */ -#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */ -#define VERIFYUES 0x0200 /* Continue if fail is in effect. */ - -/* - * DataType register bit definitions. A set bit indicates - * that the register currently holds the corresponding type of data. - */ - -#define EXPRESS 0x0001 /* Simultaneous program and verify. */ -#define SIR_DATA 0x0002 /* SIR is the active SVF command. */ -#define SDR_DATA 0x0004 /* SDR is the active SVF command. */ -#define COMPRESS 0x0008 /* Data is compressed. */ -#define TDI_DATA 0x0010 /* TDI data is present. */ -#define TDO_DATA 0x0020 /* TDO data is present. */ -#define MASK_DATA 0x0040 /* MASK data is present. */ -#define HEAP_IN 0x0080 /* Data is from the heap. */ -#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */ -#define VARIABLE 0x0400 /* Data is from a declared variable. */ -#define CRC_DATA 0x0800 /* CRC data is pressent. */ -#define CMASK_DATA 0x1000 /* CMASK data is pressent. */ -#define RMASK_DATA 0x2000 /* RMASK data is pressent. */ -#define READ_DATA 0x4000 /* READ data is pressent. */ -#define DMASK_DATA 0x8000 /* DMASK data is pressent. */ - -/* - * - * Pin opcodes. - * - */ - -#define signalENABLE 0x1C /* ispENABLE pin. */ -#define signalTMS 0x1D /* TMS pin. */ -#define signalTCK 0x1E /* TCK pin. */ -#define signalTDI 0x1F /* TDI pin. */ -#define signalTRST 0x20 /* TRST pin. */ - -/* - * - * Supported vendors. - * - */ - -#define VENDOR 0x56 -#define LATTICE 0x01 -#define ALTERA 0x02 -#define XILINX 0x03 - -/* - * Opcode definitions. - * - * Note: opcodes must be unique. - */ - -#define ENDDATA 0x00 /* The end of the current SDR data stream. */ -#define RUNTEST 0x01 /* The duration to stay at the stable state. */ -#define ENDDR 0x02 /* The stable state after SDR. */ -#define ENDIR 0x03 /* The stable state after SIR. */ -#define ENDSTATE 0x04 /* The stable state after RUNTEST. */ -#define TRST 0x05 /* Assert the TRST pin. */ -#define HIR 0x06 /* - * The sum of the IR bits of the - * leading devices. - */ -#define TIR 0x07 /* - * The sum of the IR bits of the trailing - * devices. - */ -#define HDR 0x08 /* The number of leading devices. */ -#define TDR 0x09 /* The number of trailing devices. */ -#define ispEN 0x0A /* Assert the ispEN pin. */ -#define FREQUENCY 0x0B /* - * The maximum clock rate to run the JTAG state - * machine. - */ -#define STATE 0x10 /* Move to the next stable state. */ -#define SIR 0x11 /* The instruction stream follows. */ -#define SDR 0x12 /* The data stream follows. */ -#define TDI 0x13 /* The following data stream feeds into - the device. */ -#define TDO 0x14 /* - * The following data stream is compared against - * the device. - */ -#define MASK 0x15 /* The following data stream is used as mask. */ -#define XSDR 0x16 /* - * The following data stream is for simultaneous - * program and verify. - */ -#define XTDI 0x17 /* The following data stream is for shift in - * only. It must be stored for the next - * XSDR. - */ -#define XTDO 0x18 /* - * There is not data stream. The data stream - * was stored from the previous XTDI. - */ -#define MEM 0x19 /* - * The maximum memory needed to allocate in - * order hold one row of data. - */ -#define WAIT 0x1A /* The duration of delay to observe. */ -#define TCK 0x1B /* The number of TCK pulses. */ -#define SHR 0x23 /* - * Set the flow control register for - * right shift - */ -#define SHL 0x24 /* - * Set the flow control register for left shift. - */ -#define HEAP 0x32 /* The memory size needed to hold one loop. */ -#define REPEAT 0x33 /* The beginning of the loop. */ -#define LEFTPAREN 0x35 /* The beginning of data following the loop. */ -#define VAR 0x55 /* Plac holder for loop data. */ -#define SEC 0x1C /* - * The delay time in seconds that must be - * observed. - */ -#define SMASK 0x1D /* The mask for TDI data. */ -#define MAX_WAIT 0x1E /* The absolute maximum wait time. */ -#define ON 0x1F /* Assert the targeted pin. */ -#define OFF 0x20 /* Dis-assert the targeted pin. */ -#define SETFLOW 0x30 /* Change the flow control register. */ -#define RESETFLOW 0x31 /* Clear the flow control register. */ - -#define CRC 0x47 /* - * The following data stream is used for CRC - * calculation. - */ -#define CMASK 0x48 /* - * The following data stream is used as mask - * for CRC calculation. - */ -#define RMASK 0x49 /* - * The following data stream is used as mask - * for read and save. - */ -#define READ 0x50 /* - * The following data stream is used for read - * and save. - */ -#define ENDLOOP 0x59 /* The end of the repeat loop. */ -#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */ -#define VUES 0x61 /* Support continue if fail. */ -#define DMASK 0x62 /* - * The following data stream is used for dynamic - * I/O. - */ -#define COMMENT 0x63 /* Support SVF comments in the VME file. */ -#define HEADER 0x64 /* Support header in VME file. */ -#define FILE_CRC 0x65 /* Support crc-protected VME file. */ -#define LCOUNT 0x66 /* Support intelligent programming. */ -#define LDELAY 0x67 /* Support intelligent programming. */ -#define LSDR 0x68 /* Support intelligent programming. */ -#define LHEAP 0x69 /* - * Memory needed to hold intelligent data - * buffer - */ -#define CONTINUE 0x70 /* Allow continuation. */ -#define LVDS 0x71 /* Support LVDS. */ -#define ENDVME 0x7F /* End of the VME file. */ -#define ENDFILE 0xFF /* End of file. */ - -/* - * - * ispVM Embedded Return Codes. - * - */ - -#define VME_VERIFICATION_FAILURE -1 -#define VME_FILE_READ_FAILURE -2 -#define VME_VERSION_FAILURE -3 -#define VME_INVALID_FILE -4 -#define VME_ARGUMENT_FAILURE -5 -#define VME_CRC_FAILURE -6 - -#define g_ucPinTDI 0x01 -#define g_ucPinTCK 0x02 -#define g_ucPinTMS 0x04 -#define g_ucPinENABLE 0x08 -#define g_ucPinTRST 0x10 - -/* - * - * Type definitions. - * - */ - -/* Support LVDS */ -typedef struct { - unsigned short usPositiveIndex; - unsigned short usNegativeIndex; - unsigned char ucUpdate; -} LVDSPair; - -typedef enum { - min_lattice_iface_type, /* insert all new types after this */ - lattice_jtag_mode, /* jtag/tap */ - max_lattice_iface_type /* insert all new types before this */ -} Lattice_iface; - -typedef enum { - min_lattice_type, - Lattice_XP2, /* Lattice XP2 Family */ - max_lattice_type /* insert all new types before this */ -} Lattice_Family; - -typedef struct { - Lattice_Family family; /* part type */ - Lattice_iface iface; /* interface type */ - size_t size; /* bytes of data part can accept */ - void *iface_fns; /* interface function table */ - void *base; /* base interface address */ - int cookie; /* implementation specific cookie */ - char *desc; /* description string */ -} Lattice_desc; /* end, typedef Altera_desc */ - -/* Board specific implementation specific function types */ -typedef void (*Lattice_jtag_init)(void); -typedef void (*Lattice_jtag_set_tdi)(int v); -typedef void (*Lattice_jtag_set_tms)(int v); -typedef void (*Lattice_jtag_set_tck)(int v); -typedef int (*Lattice_jtag_get_tdo)(void); - -typedef struct { - Lattice_jtag_init jtag_init; - Lattice_jtag_set_tdi jtag_set_tdi; - Lattice_jtag_set_tms jtag_set_tms; - Lattice_jtag_set_tck jtag_set_tck; - Lattice_jtag_get_tdo jtag_get_tdo; -} lattice_board_specific_func; - -void writePort(unsigned char pins, unsigned char value); -unsigned char readPort(void); -void sclock(void); -void ispVMDelay(unsigned short int a_usMicroSecondDelay); -void calibration(void); - -int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize); -int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize); -int lattice_info(Lattice_desc *desc); - -void ispVMStart(void); -void ispVMEnd(void); -extern void ispVMFreeMem(void); -signed char ispVMCode(void); -void ispVMDelay(unsigned short int a_usMicroSecondDelay); -void ispVMCalculateCRC32(unsigned char a_ucData); -unsigned char GetByte(void); -void writePort(unsigned char pins, unsigned char value); -unsigned char readPort(void); -void sclock(void); -#endif diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h new file mode 100644 index 00000000000..73b0982cc51 --- /dev/null +++ b/include/linux/i3c/ccc.h @@ -0,0 +1,385 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Cadence Design Systems Inc. + * + * Author: Boris Brezillon <boris.brezillon@bootlin.com> + */ + +#ifndef I3C_CCC_H +#define I3C_CCC_H + +#include <linux/bitops.h> +#include <linux/i3c/device.h> + +/* I3C CCC (Common Command Codes) related definitions */ +#define I3C_CCC_DIRECT BIT(7) + +#define I3C_CCC_ID(id, broadcast) \ + ((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT)) + +/* Commands valid in both broadcast and unicast modes */ +#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast) +#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast) +#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast) +#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast) +#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast) +#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast) +#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98) +#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0)) + +/* Broadcast-only commands */ +#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true) +#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true) +#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true) +#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true) + +/* Unicast-only commands */ +#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false) +#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false) +#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false) +#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false) +#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false) +#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false) +#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false) +#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false) +#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false) +#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false) +#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false) +#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false) +#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false) + +#define I3C_CCC_EVENT_SIR BIT(0) +#define I3C_CCC_EVENT_MR BIT(1) +#define I3C_CCC_EVENT_HJ BIT(3) + +/** + * struct i3c_ccc_events - payload passed to ENEC/DISEC CCC + * + * @events: bitmask of I3C_CCC_EVENT_xxx events. + * + * Depending on the CCC command, the specific events coming from all devices + * (broadcast version) or a specific device (unicast version) will be + * enabled (ENEC) or disabled (DISEC). + */ +struct i3c_ccc_events { + u8 events; +}; + +/** + * struct i3c_ccc_mwl - payload passed to SETMWL/GETMWL CCC + * + * @len: maximum write length in bytes + * + * The maximum write length is only applicable to SDR private messages or + * extended Write CCCs (like SETXTIME). + */ +struct i3c_ccc_mwl { + __be16 len; +}; + +/** + * struct i3c_ccc_mrl - payload passed to SETMRL/GETMRL CCC + * + * @len: maximum read length in bytes + * @ibi_len: maximum IBI payload length + * + * The maximum read length is only applicable to SDR private messages or + * extended Read CCCs (like GETXTIME). + * The IBI length is only valid if the I3C slave is IBI capable + * (%I3C_BCR_IBI_REQ_CAP is set). + */ +struct i3c_ccc_mrl { + __be16 read_len; + u8 ibi_len; +} __packed; + +/** + * struct i3c_ccc_dev_desc - I3C/I2C device descriptor used for DEFSLVS + * + * @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is + * describing an I2C slave. + * @dcr: DCR value (not applicable to entries describing I2C devices) + * @lvr: LVR value (not applicable to entries describing I3C devices) + * @bcr: BCR value or 0 if this entry is describing an I2C slave + * @static_addr: static address or 0 if the device does not have a static + * address + * + * The DEFSLVS command should be passed an array of i3c_ccc_dev_desc + * descriptors (one entry per I3C/I2C dev controlled by the master). + */ +struct i3c_ccc_dev_desc { + u8 dyn_addr; + union { + u8 dcr; + u8 lvr; + }; + u8 bcr; + u8 static_addr; +}; + +/** + * struct i3c_ccc_defslvs - payload passed to DEFSLVS CCC + * + * @count: number of dev descriptors + * @master: descriptor describing the current master + * @slaves: array of descriptors describing slaves controlled by the + * current master + * + * Information passed to the broadcast DEFSLVS to propagate device + * information to all masters currently acting as slaves on the bus. + * This is only meaningful if you have more than one master. + */ +struct i3c_ccc_defslvs { + u8 count; + struct i3c_ccc_dev_desc master; + struct i3c_ccc_dev_desc slaves[0]; +} __packed; + +/** + * enum i3c_ccc_test_mode - enum listing all available test modes + * + * @I3C_CCC_EXIT_TEST_MODE: exit test mode + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode + */ +enum i3c_ccc_test_mode { + I3C_CCC_EXIT_TEST_MODE, + I3C_CCC_VENDOR_TEST_MODE, +}; + +/** + * struct i3c_ccc_enttm - payload passed to ENTTM CCC + * + * @mode: one of the &enum i3c_ccc_test_mode modes + * + * Information passed to the ENTTM CCC to instruct an I3C device to enter a + * specific test mode. + */ +struct i3c_ccc_enttm { + u8 mode; +}; + +/** + * struct i3c_ccc_setda - payload passed to SETNEWDA and SETDASA CCCs + * + * @addr: dynamic address to assign to an I3C device + * + * Information passed to the SETNEWDA and SETDASA CCCs to assign/change the + * dynamic address of an I3C device. + */ +struct i3c_ccc_setda { + u8 addr; +}; + +/** + * struct i3c_ccc_getpid - payload passed to GETPID CCC + * + * @pid: 48 bits PID in big endian + */ +struct i3c_ccc_getpid { + u8 pid[6]; +}; + +/** + * struct i3c_ccc_getbcr - payload passed to GETBCR CCC + * + * @bcr: BCR (Bus Characteristic Register) value + */ +struct i3c_ccc_getbcr { + u8 bcr; +}; + +/** + * struct i3c_ccc_getdcr - payload passed to GETDCR CCC + * + * @dcr: DCR (Device Characteristic Register) value + */ +struct i3c_ccc_getdcr { + u8 dcr; +}; + +#define I3C_CCC_STATUS_PENDING_INT(status) ((status) & GENMASK(3, 0)) +#define I3C_CCC_STATUS_PROTOCOL_ERROR BIT(5) +#define I3C_CCC_STATUS_ACTIVITY_MODE(status) \ + (((status) & GENMASK(7, 6)) >> 6) + +/** + * struct i3c_ccc_getstatus - payload passed to GETSTATUS CCC + * + * @status: status of the I3C slave (see I3C_CCC_STATUS_xxx macros for more + * information). + */ +struct i3c_ccc_getstatus { + __be16 status; +}; + +/** + * struct i3c_ccc_getaccmst - payload passed to GETACCMST CCC + * + * @newmaster: address of the master taking bus ownership + */ +struct i3c_ccc_getaccmst { + u8 newmaster; +}; + +/** + * struct i3c_ccc_bridged_slave_desc - bridged slave descriptor + * + * @addr: dynamic address of the bridged device + * @id: ID of the slave device behind the bridge + */ +struct i3c_ccc_bridged_slave_desc { + u8 addr; + __be16 id; +} __packed; + +/** + * struct i3c_ccc_setbrgtgt - payload passed to SETBRGTGT CCC + * + * @count: number of bridged slaves + * @bslaves: bridged slave descriptors + */ +struct i3c_ccc_setbrgtgt { + u8 count; + struct i3c_ccc_bridged_slave_desc bslaves[0]; +} __packed; + +/** + * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers + */ +enum i3c_sdr_max_data_rate { + I3C_SDR0_FSCL_MAX, + I3C_SDR1_FSCL_8MHZ, + I3C_SDR2_FSCL_6MHZ, + I3C_SDR3_FSCL_4MHZ, + I3C_SDR4_FSCL_2MHZ, +}; + +/** + * enum i3c_tsco - clock to data turn-around + */ +enum i3c_tsco { + I3C_TSCO_8NS, + I3C_TSCO_9NS, + I3C_TSCO_10NS, + I3C_TSCO_11NS, + I3C_TSCO_12NS, +}; + +#define I3C_CCC_MAX_SDR_FSCL_MASK GENMASK(2, 0) +#define I3C_CCC_MAX_SDR_FSCL(x) ((x) & I3C_CCC_MAX_SDR_FSCL_MASK) + +/** + * struct i3c_ccc_getmxds - payload passed to GETMXDS CCC + * + * @maxwr: write limitations + * @maxrd: read limitations + * @maxrdturn: maximum read turn-around expressed micro-seconds and + * little-endian formatted + */ +struct i3c_ccc_getmxds { + u8 maxwr; + u8 maxrd; + u8 maxrdturn[3]; +} __packed; + +#define I3C_CCC_HDR_MODE(mode) BIT(mode) + +/** + * struct i3c_ccc_gethdrcap - payload passed to GETHDRCAP CCC + * + * @modes: bitmap of supported HDR modes + */ +struct i3c_ccc_gethdrcap { + u8 modes; +} __packed; + +/** + * enum i3c_ccc_setxtime_subcmd - SETXTIME sub-commands + */ +enum i3c_ccc_setxtime_subcmd { + I3C_CCC_SETXTIME_ST = 0x7f, + I3C_CCC_SETXTIME_DT = 0xbf, + I3C_CCC_SETXTIME_ENTER_ASYNC_MODE0 = 0xdf, + I3C_CCC_SETXTIME_ENTER_ASYNC_MODE1 = 0xef, + I3C_CCC_SETXTIME_ENTER_ASYNC_MODE2 = 0xf7, + I3C_CCC_SETXTIME_ENTER_ASYNC_MODE3 = 0xfb, + I3C_CCC_SETXTIME_ASYNC_TRIGGER = 0xfd, + I3C_CCC_SETXTIME_TPH = 0x3f, + I3C_CCC_SETXTIME_TU = 0x9f, + I3C_CCC_SETXTIME_ODR = 0x8f, +}; + +/** + * struct i3c_ccc_setxtime - payload passed to SETXTIME CCC + * + * @subcmd: one of the sub-commands ddefined in &enum i3c_ccc_setxtime_subcmd + * @data: sub-command payload. Amount of data is determined by + * &i3c_ccc_setxtime->subcmd + */ +struct i3c_ccc_setxtime { + u8 subcmd; + u8 data[0]; +} __packed; + +#define I3C_CCC_GETXTIME_SYNC_MODE BIT(0) +#define I3C_CCC_GETXTIME_ASYNC_MODE(x) BIT((x) + 1) +#define I3C_CCC_GETXTIME_OVERFLOW BIT(7) + +/** + * struct i3c_ccc_getxtime - payload retrieved from GETXTIME CCC + * + * @supported_modes: bitmap describing supported XTIME modes + * @state: current status (enabled mode and overflow status) + * @frequency: slave's internal oscillator frequency in 500KHz steps + * @inaccuracy: slave's internal oscillator inaccuracy in 0.1% steps + */ +struct i3c_ccc_getxtime { + u8 supported_modes; + u8 state; + u8 frequency; + u8 inaccuracy; +} __packed; + +/** + * struct i3c_ccc_cmd_payload - CCC payload + * + * @len: payload length + * @data: payload data. This buffer must be DMA-able + */ +struct i3c_ccc_cmd_payload { + u16 len; + void *data; +}; + +/** + * struct i3c_ccc_cmd_dest - CCC command destination + * + * @addr: can be an I3C device address or the broadcast address if this is a + * broadcast CCC + * @payload: payload to be sent to this device or broadcasted + */ +struct i3c_ccc_cmd_dest { + u8 addr; + struct i3c_ccc_cmd_payload payload; +}; + +/** + * struct i3c_ccc_cmd - CCC command + * + * @rnw: true if the CCC should retrieve data from the device. Only valid for + * unicast commands + * @id: CCC command id + * @ndests: number of destinations. Should always be one for broadcast commands + * @dests: array of destinations and associated payload for this CCC. Most of + * the time, only one destination is provided + * @err: I3C error code + */ +struct i3c_ccc_cmd { + u8 rnw; + u8 id; + unsigned int ndests; + struct i3c_ccc_cmd_dest *dests; + enum i3c_error_code err; +}; + +#endif /* I3C_CCC_H */ diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h new file mode 100644 index 00000000000..9d4b472b869 --- /dev/null +++ b/include/linux/i3c/device.h @@ -0,0 +1,286 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Cadence Design Systems Inc. + * + * Author: Boris Brezillon <boris.brezillon@bootlin.com> + */ + +#ifndef I3C_DEV_H +#define I3C_DEV_H + +#include <dm/device.h> +#include <i2c.h> +#include <linux/bitops.h> +#include <linux/compat.h> + +/** + * enum i3c_error_code - I3C error codes + * + * These are the standard error codes as defined by the I3C specification. + * When -EIO is returned by the i3c_device_do_priv_xfers() or + * i3c_device_send_hdr_cmds() one can check the error code in + * &struct_i3c_priv_xfer.err or &struct i3c_hdr_cmd.err to get a better idea of + * what went wrong. + * + * @I3C_ERROR_UNKNOWN: unknown error, usually means the error is not I3C + * related + * @I3C_ERROR_M0: M0 error + * @I3C_ERROR_M1: M1 error + * @I3C_ERROR_M2: M2 error + */ +enum i3c_error_code { + I3C_ERROR_UNKNOWN = 0, + I3C_ERROR_M0 = 1, + I3C_ERROR_M1, + I3C_ERROR_M2, +}; + +/** + * enum i3c_hdr_mode - HDR mode ids + * @I3C_HDR_DDR: DDR mode + * @I3C_HDR_TSP: TSP mode + * @I3C_HDR_TSL: TSL mode + */ +enum i3c_hdr_mode { + I3C_HDR_DDR, + I3C_HDR_TSP, + I3C_HDR_TSL, +}; + +/** + * struct i3c_priv_xfer - I3C SDR private transfer + * @rnw: encodes the transfer direction. true for a read, false for a write + * @len: transfer length in bytes of the transfer + * @data: input/output buffer + * @data.in: input buffer. Must point to a DMA-able buffer + * @data.out: output buffer. Must point to a DMA-able buffer + * @err: I3C error code + */ +struct i3c_priv_xfer { + u8 rnw; + u16 len; + union { + void *in; + const void *out; + } data; + enum i3c_error_code err; +}; + +/** + * enum i3c_dcr - I3C DCR values + * @I3C_DCR_GENERIC_DEVICE: generic I3C device + */ +enum i3c_dcr { + I3C_DCR_GENERIC_DEVICE = 0, +}; + +#define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33) +#define I3C_PID_RND_LOWER_32BITS(pid) (!!((pid) & BIT_ULL(32))) +#define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0)) +#define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16) +#define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12) +#define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0)) + +#define I3C_BCR_DEVICE_ROLE(bcr) ((bcr) & GENMASK(7, 6)) +#define I3C_BCR_I3C_SLAVE (0 << 6) +#define I3C_BCR_I3C_MASTER BIT(6) +#define I3C_BCR_HDR_CAP BIT(5) +#define I3C_BCR_BRIDGE BIT(4) +#define I3C_BCR_OFFLINE_CAP BIT(3) +#define I3C_BCR_IBI_PAYLOAD BIT(2) +#define I3C_BCR_IBI_REQ_CAP BIT(1) +#define I3C_BCR_MAX_DATA_SPEED_LIM BIT(0) + +/* To determine what functionality is present */ + +#define I2C_FUNC_I2C 0x00000001 +#define I2C_FUNC_10BIT_ADDR 0x00000002 /* required for I2C_M_TEN */ +#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* required for I2C_M_IGNORE_NAK etc. */ +#define I2C_FUNC_SMBUS_PEC 0x00000008 +#define I2C_FUNC_NOSTART 0x00000010 /* required for I2C_M_NOSTART */ +#define I2C_FUNC_SLAVE 0x00000020 +#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 or later */ +#define I2C_FUNC_SMBUS_QUICK 0x00010000 +#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000 +#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000 +#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000 +#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000 +#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000 +#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000 +#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000 +#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000 /* required for I2C_M_RECV_LEN */ +#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000 +#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */ +#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */ +#define I2C_FUNC_SMBUS_HOST_NOTIFY 0x10000000 /* SMBus 2.0 or later */ + +#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \ + I2C_FUNC_SMBUS_WRITE_BYTE) +#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \ + I2C_FUNC_SMBUS_WRITE_BYTE_DATA) +#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \ + I2C_FUNC_SMBUS_WRITE_WORD_DATA) +#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \ + I2C_FUNC_SMBUS_WRITE_BLOCK_DATA) +#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \ + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK) + +#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \ + I2C_FUNC_SMBUS_BYTE | \ + I2C_FUNC_SMBUS_BYTE_DATA | \ + I2C_FUNC_SMBUS_WORD_DATA | \ + I2C_FUNC_SMBUS_PROC_CALL | \ + I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \ + I2C_FUNC_SMBUS_I2C_BLOCK | \ + I2C_FUNC_SMBUS_PEC) + +/** + * struct i3c_device_info - I3C device information + * @pid: Provisional ID + * @bcr: Bus Characteristic Register + * @dcr: Device Characteristic Register + * @static_addr: static/I2C address + * @dyn_addr: dynamic address + * @hdr_cap: supported HDR modes + * @max_read_ds: max read speed information + * @max_write_ds: max write speed information + * @max_ibi_len: max IBI payload length + * @max_read_turnaround: max read turn-around time in micro-seconds + * @max_read_len: max private SDR read length in bytes + * @max_write_len: max private SDR write length in bytes + * + * These are all basic information that should be advertised by an I3C device. + * Some of them are optional depending on the device type and device + * capabilities. + * For each I3C slave attached to a master with + * i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command + * to retrieve these data. + */ +struct i3c_device_info { + u64 pid; + u8 bcr; + u8 dcr; + u8 static_addr; + u8 dyn_addr; + u8 hdr_cap; + u8 max_read_ds; + u8 max_write_ds; + u8 max_ibi_len; + u32 max_read_turnaround; + u16 max_read_len; + u16 max_write_len; +}; + +/* + * I3C device internals are kept hidden from I3C device users. It's just + * simpler to refactor things when everything goes through getter/setters, and + * I3C device drivers should not have to worry about internal representation + * anyway. + */ +struct i3c_device; + +/* These macros should be used to i3c_device_id entries. */ +#define I3C_MATCH_MANUF_AND_PART (I3C_MATCH_MANUF | I3C_MATCH_PART) + +#define I3C_DEVICE(_manufid, _partid, _drvdata) \ + { \ + .match_flags = I3C_MATCH_MANUF_AND_PART, \ + .manuf_id = _manufid, \ + .part_id = _partid, \ + .data = _drvdata, \ + } + +#define I3C_DEVICE_EXTRA_INFO(_manufid, _partid, _info, _drvdata) \ + { \ + .match_flags = I3C_MATCH_MANUF_AND_PART | \ + I3C_MATCH_EXTRA_INFO, \ + .manuf_id = _manufid, \ + .part_id = _partid, \ + .extra_info = _info, \ + .data = _drvdata, \ + } + +#define I3C_CLASS(_dcr, _drvdata) \ + { \ + .match_flags = I3C_MATCH_DCR, \ + .dcr = _dcr, \ + } + +/** + * struct i3c_driver - I3C device driver + * @driver: inherit from driver + * @probe: I3C device probe method + * @remove: I3C device remove method + * @id_table: I3C device match table. Will be used by the framework to decide + * which device to bind to this driver + */ +struct i3c_driver { + struct driver driver; + int (*probe)(struct i3c_device *dev); + void (*remove)(struct i3c_device *dev); + const struct i3c_device_id *id_table; +}; + +static inline struct i3c_driver *drv_to_i3cdrv(const struct driver *drv) +{ + return container_of(drv, struct i3c_driver, driver); +} + +struct udevice *i3cdev_to_dev(struct i3c_device *i3cdev); +struct i3c_device *dev_to_i3cdev(struct udevice *dev); + +const struct i3c_device_id * +i3c_device_match_id(struct i3c_device *i3cdev, + const struct i3c_device_id *id_table); + +/** + * module_i3c_i2c_driver() - Register a module providing an I3C and an I2C + * driver + * @__i3cdrv: the I3C driver to register + * @__i2cdrv: the I3C driver to register + * + * Provide generic init/exit functions that simply register/unregister an I3C + * and an I2C driver. + * This macro can be used even if CONFIG_I3C is disabled, in this case, only + * the I2C driver will be registered. + * Should be used by any driver that does not require extra init/cleanup steps. + */ +#define module_i3c_i2c_driver(__i3cdrv, __i2cdrv) \ + module_driver(__i3cdrv, \ + i3c_i2c_driver_register, \ + i3c_i2c_driver_unregister) + +void i3c_device_get_info(struct i3c_device *dev, struct i3c_device_info *info); + +struct i3c_ibi_payload { + unsigned int len; + const void *data; +}; + +/** + * struct i3c_ibi_setup - IBI setup object + * @max_payload_len: maximum length of the payload associated to an IBI. If one + * IBI appears to have a payload that is bigger than this + * number, the IBI will be rejected. + * @num_slots: number of pre-allocated IBI slots. This should be chosen so that + * the system never runs out of IBI slots, otherwise you'll lose + * IBIs. + * @handler: IBI handler, every time an IBI is received. This handler is called + * in a workqueue context. It is allowed to sleep and send new + * messages on the bus, though it's recommended to keep the + * processing done there as fast as possible to avoid delaying + * processing of other queued on the same workqueue. + * + * Temporary structure used to pass information to i3c_device_request_ibi(). + * This object can be allocated on the stack since i3c_device_request_ibi() + * copies every bit of information and do not use it after + * i3c_device_request_ibi() has returned. + */ +struct i3c_ibi_setup { + unsigned int max_payload_len; + unsigned int num_slots; + void (*handler)(struct i3c_device *dev, + const struct i3c_ibi_payload *payload); +}; + +#endif /* I3C_DEV_H */ diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h new file mode 100644 index 00000000000..04017f34822 --- /dev/null +++ b/include/linux/i3c/master.h @@ -0,0 +1,698 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Cadence Design Systems Inc. + * + * Author: Boris Brezillon <boris.brezillon@bootlin.com> + */ + +#ifndef I3C_MASTER_H +#define I3C_MASTER_H + +#include <asm/bitops.h> +#include <hwspinlock.h> +#include <i2c.h> +#include <linux/bitops.h> +#include <linux/i3c/ccc.h> +#include <linux/i3c/device.h> + +#define I3C_HOT_JOIN_ADDR 0x2 +#define I3C_BROADCAST_ADDR 0x7e +#define I3C_MAX_ADDR GENMASK(6, 0) + +struct i3c_master_controller; +struct i3c_bus; +struct i2c_device; +struct i3c_device; + +/** + * struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor + * @node: node element used to insert the slot into the I2C or I3C device + * list + * @master: I3C master that instantiated this device. Will be used to do + * I2C/I3C transfers + * @master_priv: master private data assigned to the device. Can be used to + * add master specific information + * + * This structure is describing common I3C/I2C dev information. + */ +struct i3c_i2c_dev_desc { + struct list_head node; + struct i3c_master_controller *master; + void *master_priv; +}; + +#define I3C_LVR_I2C_INDEX_MASK GENMASK(7, 5) +#define I3C_LVR_I2C_INDEX(x) ((x) << 5) +#define I3C_LVR_I2C_FM_MODE BIT(4) + +#define I2C_MAX_ADDR GENMASK(6, 0) +#define I2C_NAME_SIZE 20 +#define I2C_MODULE_PREFIX "i2c:" +#define I2C_CLIENT_TEN 0x10 + +/** + * struct i2c_board_info - template for device creation + * @type: chip type, to initialize i2c_client.name + * @flags: to initialize i2c_client.flags + * @addr: stored in i2c_client.addr + * @dev_name: Overrides the default <busnr>-<addr> dev_name if set + * @platform_data: stored in i2c_client.dev.platform_data + * @of_node: pointer to OpenFirmware device node + * @fwnode: device node supplied by the platform firmware + * @swnode: software node for the device + * @resources: resources associated with the device + * @num_resources: number of resources in the @resources array + * @irq: stored in i2c_client.irq + * + * I2C doesn't actually support hardware probing, although controllers and + * devices may be able to use I2C_SMBUS_QUICK to tell whether or not there's + * a device at a given address. Drivers commonly need more information than + * that, such as chip type, configuration, associated IRQ, and so on. + * + * i2c_board_info is used to build tables of information listing I2C devices + * that are present. This information is used to grow the driver model tree. + * For mainboards this is done statically using i2c_register_board_info(); + * bus numbers identify adapters that aren't yet available. For add-on boards, + * i2c_new_client_device() does this dynamically with the adapter already known. + */ +struct i2c_board_info { + char type[I2C_NAME_SIZE]; + unsigned short flags; + unsigned short addr; + const char *dev_name; + void *platform_data; + struct device_node *of_node; +}; + +/** + * struct i2c_dev_boardinfo - I2C device board information + * @node: used to insert the boardinfo object in the I2C boardinfo list + * @base: regular I2C board information + * @lvr: LVR (Legacy Virtual Register) needed by the I3C core to know about + * the I2C device limitations + * + * This structure is used to attach board-level information to an I2C device. + * Each I2C device connected on the I3C bus should have one. + */ +struct i2c_dev_boardinfo { + struct list_head node; + struct i2c_board_info base; + u8 lvr; +}; + +/** + * struct i2c_dev_desc - I2C device descriptor + * @common: common part of the I2C device descriptor + * @boardinfo: pointer to the boardinfo attached to this I2C device + * @dev: I2C device object registered to the I2C framework + * @addr: I2C device address + * @lvr: LVR (Legacy Virtual Register) needed by the I3C core to know about + * the I2C device limitations + * + * Each I2C device connected on the bus will have an i2c_dev_desc. + * This object is created by the core and later attached to the controller + * using &struct_i3c_master_controller->ops->attach_i2c_dev(). + * + * &struct_i2c_dev_desc is the internal representation of an I2C device + * connected on an I3C bus. This object is also passed to all + * &struct_i3c_master_controller_ops hooks. + */ +struct i2c_dev_desc { + struct i3c_i2c_dev_desc common; + const struct i2c_dev_boardinfo *boardinfo; + struct i2c_client *dev; + u16 addr; + u8 lvr; +}; + +/** + * struct i3c_ibi_slot - I3C IBI (In-Band Interrupt) slot + * @work: work associated to this slot. The IBI handler will be called from + * there + * @dev: the I3C device that has generated this IBI + * @len: length of the payload associated to this IBI + * @data: payload buffer + * + * An IBI slot is an object pre-allocated by the controller and used when an + * IBI comes in. + * Every time an IBI comes in, the I3C master driver should find a free IBI + * slot in its IBI slot pool, retrieve the IBI payload and queue the IBI using + * i3c_master_queue_ibi(). + * + * How IBI slots are allocated is left to the I3C master driver, though, for + * simple kmalloc-based allocation, the generic IBI slot pool can be used. + */ +struct i3c_ibi_slot { + struct work_struct work; + struct i3c_dev_desc *dev; + unsigned int len; + void *data; +}; + +/** + * struct i3c_device_ibi_info - IBI information attached to a specific device + * @all_ibis_handled: used to be informed when no more IBIs are waiting to be + * processed. Used by i3c_device_disable_ibi() to wait for + * all IBIs to be dequeued + * @pending_ibis: count the number of pending IBIs. Each pending IBI has its + * work element queued to the controller workqueue + * @max_payload_len: maximum payload length for an IBI coming from this device. + * this value is specified when calling + * i3c_device_request_ibi() and should not change at run + * time. All messages IBIs exceeding this limit should be + * rejected by the master + * @num_slots: number of IBI slots reserved for this device + * @enabled: reflect the IBI status + * @handler: IBI handler specified at i3c_device_request_ibi() call time. This + * handler will be called from the controller workqueue, and as such + * is allowed to sleep (though it is recommended to process the IBI + * as fast as possible to not stall processing of other IBIs queued + * on the same workqueue). + * New I3C messages can be sent from the IBI handler + * + * The &struct_i3c_device_ibi_info object is allocated when + * i3c_device_request_ibi() is called and attached to a specific device. This + * object is here to manage IBIs coming from a specific I3C device. + * + * Note that this structure is the generic view of the IBI management + * infrastructure. I3C master drivers may have their own internal + * representation which they can associate to the device using + * controller-private data. + */ +struct i3c_device_ibi_info { + unsigned int max_payload_len; + unsigned int num_slots; + unsigned int enabled; + void (*handler)(struct i3c_device *dev, + const struct i3c_ibi_payload *payload); +}; + +/** + * struct i3c_dev_boardinfo - I3C device board information + * @node: used to insert the boardinfo object in the I3C boardinfo list + * @init_dyn_addr: initial dynamic address requested by the FW. We provide no + * guarantee that the device will end up using this address, + * but try our best to assign this specific address to the + * device + * @static_addr: static address the I3C device listen on before it's been + * assigned a dynamic address by the master. Will be used during + * bus initialization to assign it a specific dynamic address + * before starting DAA (Dynamic Address Assignment) + * @pid: I3C Provisional ID exposed by the device. This is a unique identifier + * that may be used to attach boardinfo to i3c_dev_desc when the device + * does not have a static address + * @of_node: optional DT node in case the device has been described in the DT + * + * This structure is used to attach board-level information to an I3C device. + * Not all I3C devices connected on the bus will have a boardinfo. It's only + * needed if you want to attach extra resources to a device or assign it a + * specific dynamic address. + */ +struct i3c_dev_boardinfo { + struct list_head node; + u8 init_dyn_addr; + u8 static_addr; + u64 pid; + struct device_node *of_node; +}; + +/** + * struct i3c_dev_desc - I3C device descriptor + * @common: common part of the I3C device descriptor + * @info: I3C device information. Will be automatically filled when you create + * your device with i3c_master_add_i3c_dev_locked() + * @ibi_lock: lock used to protect the &struct_i3c_device->ibi + * @ibi: IBI info attached to a device. Should be NULL until + * i3c_device_request_ibi() is called + * @dev: pointer to the I3C device object exposed to I3C device drivers. This + * should never be accessed from I3C master controller drivers. Only core + * code should manipulate it in when updating the dev <-> desc link or + * when propagating IBI events to the driver + * @boardinfo: pointer to the boardinfo attached to this I3C device + * + * Internal representation of an I3C device. This object is only used by the + * core and passed to I3C master controller drivers when they're requested to + * do some operations on the device. + * The core maintains the link between the internal I3C dev descriptor and the + * object exposed to the I3C device drivers (&struct_i3c_device). + */ +struct i3c_dev_desc { + struct i3c_i2c_dev_desc common; + struct i3c_device_info info; + struct mutex ibi_lock; /* lock used to protect the &struct_i3c_device->ibi */ + struct i3c_device_ibi_info *ibi; + struct i3c_device *dev; + const struct i3c_dev_boardinfo *boardinfo; +}; + +/** + * struct i3c_device - I3C device object + * @dev: device object to register the I3C dev to the device model + * @desc: pointer to an i3c device descriptor object. This link is updated + * every time the I3C device is rediscovered with a different dynamic + * address assigned + * @bus: I3C bus this device is attached to + * + * I3C device object exposed to I3C device drivers. The takes care of linking + * this object to the relevant &struct_i3c_dev_desc one. + * All I3C devs on the I3C bus are represented, including I3C masters. For each + * of them, we have an instance of &struct i3c_device. + */ +struct i3c_device { + struct udevice dev; + struct i3c_dev_desc *desc; + struct i3c_bus *bus; +}; + +/* + * The I3C specification says the maximum number of devices connected on the + * bus is 11, but this number depends on external parameters like trace length, + * capacitive load per Device, and the types of Devices present on the Bus. + * I3C master can also have limitations, so this number is just here as a + * reference and should be adjusted on a per-controller/per-board basis. + */ +#define I3C_BUS_MAX_DEVS 11 + +#define I3C_BUS_MAX_I3C_SCL_RATE 12900000 +#define I3C_BUS_TYP_I3C_SCL_RATE 12500000 +#define I3C_BUS_I2C_FM_PLUS_SCL_RATE 1000000 +#define I3C_BUS_I2C_FM_SCL_RATE 400000 +#define I3C_BUS_TLOW_OD_MIN_NS 200 +#define I3C_BUS_THIGH_INIT_OD_MIN_NS 200 + +/** + * enum i3c_bus_mode - I3C bus mode + * @I3C_BUS_MODE_PURE: only I3C devices are connected to the bus. No limitation + * expected + * @I3C_BUS_MODE_MIXED_FAST: I2C devices with 50ns spike filter are present on + * the bus. The only impact in this mode is that the + * high SCL pulse has to stay below 50ns to trick I2C + * devices when transmitting I3C frames + * @I3C_BUS_MODE_MIXED_LIMITED: I2C devices without 50ns spike filter are + * present on the bus. However they allow + * compliance up to the maximum SDR SCL clock + * frequency. + * @I3C_BUS_MODE_MIXED_SLOW: I2C devices without 50ns spike filter are present + * on the bus + */ +enum i3c_bus_mode { + I3C_BUS_MODE_PURE, + I3C_BUS_MODE_MIXED_FAST, + I3C_BUS_MODE_MIXED_LIMITED, + I3C_BUS_MODE_MIXED_SLOW, +}; + +/** + * enum i3c_addr_slot_status - I3C address slot status + * @I3C_ADDR_SLOT_FREE: address is free + * @I3C_ADDR_SLOT_RSVD: address is reserved + * @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device + * @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device + * @I3C_ADDR_SLOT_STATUS_MASK: address slot mask + * + * On an I3C bus, addresses are assigned dynamically, and we need to know which + * addresses are free to use and which ones are already assigned. + * + * Addresses marked as reserved are those reserved by the I3C protocol + * (broadcast address, ...). + */ +enum i3c_addr_slot_status { + I3C_ADDR_SLOT_FREE, + I3C_ADDR_SLOT_RSVD, + I3C_ADDR_SLOT_I2C_DEV, + I3C_ADDR_SLOT_I3C_DEV, + I3C_ADDR_SLOT_STATUS_MASK = 3, +}; + +/* + * i2c_adapter is the structure used to identify a physical i2c bus along + * with the access algorithms necessary to access it. + */ +struct i2c_adapter { + struct module *owner; + unsigned int class; + int timeout; /* in jiffies */ + int retries; + struct udevice dev; + int nr; + char name[48]; +}; + +/** + * struct i3c_bus - I3C bus object + * @cur_master: I3C master currently driving the bus. Since I3C is multi-master + * this can change over the time. Will be used to let a master + * know whether it needs to request bus ownership before sending + * a frame or not + * @id: bus ID. Assigned by the framework when register the bus + * @addrslots: a bitmap with 2-bits per-slot to encode the address status and + * ease the DAA (Dynamic Address Assignment) procedure (see + * &enum i3c_addr_slot_status) + * @mode: bus mode (see &enum i3c_bus_mode) + * @scl_rate.i3c: maximum rate for the clock signal when doing I3C SDR/priv + * transfers + * @scl_rate.i2c: maximum rate for the clock signal when doing I2C transfers + * @scl_rate: SCL signal rate for I3C and I2C mode + * @devs.i3c: contains a list of I3C device descriptors representing I3C + * devices connected on the bus and successfully attached to the + * I3C master + * @devs.i2c: contains a list of I2C device descriptors representing I2C + * devices connected on the bus and successfully attached to the + * I3C master + * @devs: 2 lists containing all I3C/I2C devices connected to the bus + * @lock: read/write lock on the bus. This is needed to protect against + * operations that have an impact on the whole bus and the devices + * connected to it. For example, when asking slaves to drop their + * dynamic address (RSTDAA CCC), we need to make sure no one is trying + * to send I3C frames to these devices. + * Note that this lock does not protect against concurrency between + * devices: several drivers can send different I3C/I2C frames through + * the same master in parallel. This is the responsibility of the + * master to guarantee that frames are actually sent sequentially and + * not interlaced + * + * The I3C bus is represented with its own object and not implicitly described + * by the I3C master to cope with the multi-master functionality, where one bus + * can be shared amongst several masters, each of them requesting bus ownership + * when they need to. + */ +struct i3c_bus { + struct i3c_dev_desc *cur_master; + int id; + unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG]; + enum i3c_bus_mode mode; + struct { + unsigned long i3c; + unsigned long i2c; + } scl_rate; + struct { + struct list_head i3c; + struct list_head i2c; + } devs; + struct rw_semaphore lock; +}; + +/** + * struct i3c_master_controller_ops - I3C master methods + * @bus_init: hook responsible for the I3C bus initialization. You should at + * least call master_set_info() from there and set the bus mode. + * You can also put controller specific initialization in there. + * This method is mandatory. + * @bus_cleanup: cleanup everything done in + * &i3c_master_controller_ops->bus_init(). + * This method is optional. + * @attach_i3c_dev: called every time an I3C device is attached to the bus. It + * can be after a DAA or when a device is statically declared + * by the FW, in which case it will only have a static address + * and the dynamic address will be 0. + * When this function is called, device information have not + * been retrieved yet. + * This is a good place to attach master controller specific + * data to I3C devices. + * This method is optional. + * @reattach_i3c_dev: called every time an I3C device has its addressed + * changed. It can be because the device has been powered + * down and has lost its address, or it can happen when a + * device had a static address and has been assigned a + * dynamic address with SETDASA. + * This method is optional. + * @detach_i3c_dev: called when an I3C device is detached from the bus. Usually + * happens when the master device is unregistered. + * This method is optional. + * @do_daa: do a DAA (Dynamic Address Assignment) procedure. This is procedure + * should send an ENTDAA CCC command and then add all devices + * discovered sure the DAA using i3c_master_add_i3c_dev_locked(). + * Add devices added with i3c_master_add_i3c_dev_locked() will then be + * attached or re-attached to the controller. + * This method is mandatory. + * @supports_ccc_cmd: should return true if the CCC command is supported, false + * otherwise. + * This method is optional, if not provided the core assumes + * all CCC commands are supported. + * @send_ccc_cmd: send a CCC command + * This method is mandatory. + * @priv_xfers: do one or several private I3C SDR transfers + * This method is mandatory. + * @attach_i2c_dev: called every time an I2C device is attached to the bus. + * This is a good place to attach master controller specific + * data to I2C devices. + * This method is optional. + * @detach_i2c_dev: called when an I2C device is detached from the bus. Usually + * happens when the master device is unregistered. + * This method is optional. + * @i2c_xfers: do one or several I2C transfers. Note that, unlike i3c + * transfers, the core does not guarantee that buffers attached to + * the transfers are DMA-safe. If drivers want to have DMA-safe + * buffers, they should use the i2c_get_dma_safe_msg_buf() + * and i2c_put_dma_safe_msg_buf() helpers provided by the I2C + * framework. + * This method is mandatory. + * @request_ibi: attach an IBI handler to an I3C device. This implies defining + * an IBI handler and the constraints of the IBI (maximum payload + * length and number of pre-allocated slots). + * Some controllers support less IBI-capable devices than regular + * devices, so this method might return -%EBUSY if there's no + * more space for an extra IBI registration + * This method is optional. + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI + * should have been disabled with ->disable_irq() prior to that + * This method is mandatory only if ->request_ibi is not NULL. + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called + * prior to ->enable_ibi(). The controller should first enable + * the IBI on the controller end (for example, unmask the hardware + * IRQ) and then send the ENEC CCC command (with the IBI flag set) + * to the I3C device. + * This method is mandatory only if ->request_ibi is not NULL. + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI + * flag set and then deactivate the hardware IRQ on the + * controller end. + * This method is mandatory only if ->request_ibi is not NULL. + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been + * processed by its handler. The IBI slot should be put back + * in the IBI slot pool so that the controller can re-use it + * for a future IBI + * This method is mandatory only if ->request_ibi is not + * NULL. + */ +struct i3c_master_controller_ops { + int (*bus_init)(struct i3c_master_controller *master); + void (*bus_cleanup)(struct i3c_master_controller *master); + int (*attach_i3c_dev)(struct i3c_dev_desc *dev); + int (*reattach_i3c_dev)(struct i3c_dev_desc *dev, u8 old_dyn_addr); + void (*detach_i3c_dev)(struct i3c_dev_desc *dev); + int (*do_daa)(struct i3c_master_controller *master); + bool (*supports_ccc_cmd)(struct i3c_master_controller *master, + const struct i3c_ccc_cmd *cmd); + int (*send_ccc_cmd)(struct i3c_master_controller *master, + struct i3c_ccc_cmd *cmd); + int (*priv_xfers)(struct i3c_dev_desc *dev, + struct i3c_priv_xfer *xfers, + u32 nxfers); + int (*attach_i2c_dev)(struct i2c_dev_desc *dev); + void (*detach_i2c_dev)(struct i2c_dev_desc *dev); + int (*i2c_xfers)(struct i2c_dev_desc *dev, + const struct i2c_msg *xfers, int nxfers); + int (*request_ibi)(struct i3c_dev_desc *dev, + const struct i3c_ibi_setup *req); + void (*free_ibi)(struct i3c_dev_desc *dev); + int (*enable_ibi)(struct i3c_dev_desc *dev); + int (*disable_ibi)(struct i3c_dev_desc *dev); + void (*recycle_ibi_slot)(struct i3c_dev_desc *dev, + struct i3c_ibi_slot *slot); +}; + +/** + * struct i3c_master_controller - I3C master controller object + * @dev: device to be registered to the device-model + * @this: an I3C device object representing this master. This device will be + * added to the list of I3C devs available on the bus + * @i2c: I2C adapter used for backward compatibility. This adapter is + * registered to the I2C subsystem to be as transparent as possible to + * existing I2C drivers + * @ops: master operations. See &struct i3c_master_controller_ops + * @secondary: true if the master is a secondary master + * @init_done: true when the bus initialization is done + * @boardinfo.i3c: list of I3C boardinfo objects + * @boardinfo.i2c: list of I2C boardinfo objects + * @boardinfo: board-level information attached to devices connected on the bus + * @bus: I3C bus exposed by this master + * @wq: workqueue used to execute IBI handlers. Can also be used by master + * drivers if they need to postpone operations that need to take place + * in a thread context. Typical examples are Hot Join processing which + * requires taking the bus lock in maintenance, which in turn, can only + * be done from a sleep-able context + * + * A &struct i3c_master_controller has to be registered to the I3C subsystem + * through i3c_master_register(). None of &struct i3c_master_controller fields + * should be set manually, just pass appropriate values to + * i3c_master_register(). + */ +struct i3c_master_controller { + struct udevice *dev; + struct i3c_dev_desc *this; + struct i2c_adapter i2c; + const struct i3c_master_controller_ops *ops; + unsigned int secondary : 1; + unsigned int init_done : 1; + struct { + struct list_head i3c; + struct list_head i2c; + } boardinfo; + struct i3c_bus bus; + struct workqueue_struct *wq; +}; + +/** + * i3c_bus_for_each_i2cdev() - iterate over all I2C devices present on the bus + * @bus: the I3C bus + * @dev: an I2C device descriptor pointer updated to point to the current slot + * at each iteration of the loop + * + * Iterate over all I2C devs present on the bus. + */ +#define i3c_bus_for_each_i2cdev(bus, dev) \ + list_for_each_entry(dev, &(bus)->devs.i2c, common.node) + +/** + * i3c_bus_for_each_i3cdev() - iterate over all I3C devices present on the bus + * @bus: the I3C bus + * @dev: and I3C device descriptor pointer updated to point to the current slot + * at each iteration of the loop + * + * Iterate over all I3C devs present on the bus. + */ +#define i3c_bus_for_each_i3cdev(bus, dev) \ + list_for_each_entry(dev, &(bus)->devs.i3c, common.node) + +int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr, + u8 evts); +int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr, + u8 evts); +int i3c_master_entdaa_locked(struct i3c_master_controller *master); +int i3c_master_defslvs_locked(struct i3c_master_controller *master); + +int i3c_master_get_free_addr(struct i3c_master_controller *master, + u8 start_addr); + +int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, + u8 addr); +int i3c_master_do_daa(struct i3c_master_controller *master); + +int i3c_master_set_info(struct i3c_master_controller *master, + const struct i3c_device_info *info); + +int i3c_master_register(struct i3c_master_controller *master, + struct udevice *parent, + const struct i3c_master_controller_ops *ops, + bool secondary); +int i3c_master_unregister(struct i3c_master_controller *master); + +/** + * i3c_dev_get_master_data() - get master private data attached to an I3C + * device descriptor + * @dev: the I3C device descriptor to get private data from + * + * Return: the private data previously attached with i3c_dev_set_master_data() + * or NULL if no data has been attached to the device. + */ +static inline void *i3c_dev_get_master_data(const struct i3c_dev_desc *dev) +{ + return dev->common.master_priv; +} + +/** + * i3c_dev_set_master_data() - attach master private data to an I3C device + * descriptor + * @dev: the I3C device descriptor to attach private data to + * @data: private data + * + * This functions allows a master controller to attach per-device private data + * which can then be retrieved with i3c_dev_get_master_data(). + */ +static inline void i3c_dev_set_master_data(struct i3c_dev_desc *dev, + void *data) +{ + dev->common.master_priv = data; +} + +/** + * i2c_dev_get_master_data() - get master private data attached to an I2C + * device descriptor + * @dev: the I2C device descriptor to get private data from + * + * Return: the private data previously attached with i2c_dev_set_master_data() + * or NULL if no data has been attached to the device. + */ +static inline void *i2c_dev_get_master_data(const struct i2c_dev_desc *dev) +{ + return dev->common.master_priv; +} + +/** + * i2c_dev_set_master_data() - attach master private data to an I2C device + * descriptor + * @dev: the I2C device descriptor to attach private data to + * @data: private data + * + * This functions allows a master controller to attach per-device private data + * which can then be retrieved with i2c_device_get_master_data(). + */ +static inline void i2c_dev_set_master_data(struct i2c_dev_desc *dev, + void *data) +{ + dev->common.master_priv = data; +} + +/** + * i3c_dev_get_master() - get master used to communicate with a device + * @dev: I3C dev + * + * Return: the master controller driving @dev + */ +static inline struct i3c_master_controller * +i3c_dev_get_master(struct i3c_dev_desc *dev) +{ + return dev->common.master; +} + +/** + * i2c_dev_get_master() - get master used to communicate with a device + * @dev: I2C dev + * + * Return: the master controller driving @dev + */ +static inline struct i3c_master_controller * +i2c_dev_get_master(struct i2c_dev_desc *dev) +{ + return dev->common.master; +} + +/** + * i3c_master_get_bus() - get the bus attached to a master + * @master: master object + * + * Return: the I3C bus @master is connected to + */ +static inline struct i3c_bus * +i3c_master_get_bus(struct i3c_master_controller *master) +{ + return &master->bus; +} + +struct i3c_generic_ibi_pool; + +struct i3c_generic_ibi_pool * +i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev, + const struct i3c_ibi_setup *req); +void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool); + +struct i3c_ibi_slot * +i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool); +void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool, + struct i3c_ibi_slot *slot); + +void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot); + +struct i3c_ibi_slot *i3c_master_get_free_ibi_slot(struct i3c_dev_desc *dev); + +#endif /* I3C_MASTER_H */ diff --git a/include/mpfs-mailbox.h b/include/mpfs-mailbox.h new file mode 100644 index 00000000000..c0ff327a4ce --- /dev/null +++ b/include/mpfs-mailbox.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * + * Microchip PolarFire SoC (MPFS) + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * + */ + +#ifndef _MPFS_MAILBOX_H__ +#define _MPFS_MAILBOX_H__ + +#include <linux/types.h> + +#define BYTES_4 4 + +struct udevice; + +/** + * struct mpfs_mss_msg - PolarFire SoC message structure + * @cmd_opcode: Command opcode + * @cmd_data_size: Size of the command data. + * @response: Pointer to the response data. + * @cmd_data: Pointer to the command data. + * @mbox_offset: Mailbox offset + * @resp_offset: Response offset + * + */ +struct mpfs_mss_msg { + u8 cmd_opcode; + u16 cmd_data_size; + struct mpfs_mss_response *response; + u8 *cmd_data; + u16 mbox_offset; + u16 resp_offset; +}; + +/** + * struct mpfs_mss_response - PolarFire SoC response structure + * @resp_status: Response status + * @resp_msg: Pointer to response message. + * @resp_size: Size of the response message. + * + */ +struct mpfs_mss_response { + u32 resp_status; + u32 *resp_msg; + u16 resp_size; +}; + +struct mpfs_syscontroller_priv; + +struct mpfs_sys_serv { + struct udevice *dev; + struct mpfs_syscontroller_priv *sys_controller; + struct mpfs_mss_msg *msg; +}; + +int mpfs_syscontroller_run_service(struct mpfs_syscontroller_priv *sys_controller, struct mpfs_mss_msg *msg); +int mpfs_syscontroller_read_sernum(struct mpfs_sys_serv *sys_serv_priv, u8 *device_serial_number); +void mpfs_syscontroller_process_dtbo(struct mpfs_sys_serv *sys_serv_priv); +struct mpfs_syscontroller_priv *mpfs_syscontroller_get(struct udevice *dev); + +#endif /* __MPFS_MAILBOX_H__ */ + diff --git a/include/net-legacy.h b/include/net-legacy.h index a7dbcec1506..9564e97d238 100644 --- a/include/net-legacy.h +++ b/include/net-legacy.h @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * LiMon Monitor (LiMon) - Network. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * * History * 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added @@ -316,7 +315,7 @@ extern u32 net_boot_file_size; /* Boot file size in blocks as reported by the DHCP server */ extern u32 net_boot_file_expected_size_in_blocks; -#if defined(CONFIG_CMD_DNS) +#if defined(CONFIG_DNS) extern char *net_dns_resolve; /* The host to resolve */ extern char *net_dns_env_var; /* the env var to put the ip into */ #endif diff --git a/include/net-lwip.h b/include/net-lwip.h index f54f23471f1..e88e2186635 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -18,6 +18,8 @@ extern size_t cacert_size; extern enum auth_mode cacert_auth_mode; extern bool cacert_initialized; +extern int net_try_count; + int set_cacert_builtin(void); enum proto_t { diff --git a/include/net/tftp.h b/include/net/tftp.h index c411c9b2e65..c7e14817280 100644 --- a/include/net/tftp.h +++ b/include/net/tftp.h @@ -1,10 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * LiMon - BOOTP/TFTP. * * Copyright 1994, 1995, 2000 Neil Russell. * Copyright 2011 Comelit Group SpA * Luca Ceresoli <luca.ceresoli@comelit.it> - * (See License) */ #ifndef __TFTP_H__ diff --git a/include/power/rk8xx_pmic.h b/include/power/rk8xx_pmic.h index 31221aa46b6..913b6ebe6d9 100644 --- a/include/power/rk8xx_pmic.h +++ b/include/power/rk8xx_pmic.h @@ -212,6 +212,8 @@ enum { #define RK817_POWER_EN_SAVE0 0x99 #define RK817_POWER_EN_SAVE1 0xa4 +#define RK806_RST_FUN_MSK GENMASK(7, 6) + #define RK806_POWER_EN(x) (0x00 + (x)) /* POWER_ENx register lower 4 bits are write-protected unless the associated top bit is set */ #define RK806_POWER_EN_CLRSETBITS(bit, val) (((val) << (bit)) | (1 << ((bit) + 4))) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index c2aa88f59fb..900113ca3e9 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -195,6 +195,7 @@ endchoice config EFI_VARIABLES_PRESEED bool "Initial values for UEFI variables" + depends on !COMPILE_TEST depends on !EFI_MM_COMM_TEE help Include a file with the initial values for non-volatile UEFI variables @@ -564,6 +565,7 @@ config EFI_HTTP_BOOT bool "EFI HTTP Boot support" depends on NET || NET_LWIP select CMD_NET + select CMD_DHCP select CMD_DNS select CMD_WGET select BLKMAP diff --git a/lib/lwip/lwip/src/apps/tftp/tftp.c b/lib/lwip/lwip/src/apps/tftp/tftp.c index 63b1e0e0e20..ecb6c55ae11 100644 --- a/lib/lwip/lwip/src/apps/tftp/tftp.c +++ b/lib/lwip/lwip/src/apps/tftp/tftp.c @@ -79,6 +79,14 @@ enum tftp_error { #include <string.h> +struct tftp_req { + ip_addr_t addr; + u16_t port; + u16_t opcode; + enum tftp_transfer_mode mode; + char* fname; +}; + struct tftp_state { const struct tftp_context *ctx; void *handle; @@ -97,14 +105,33 @@ struct tftp_state { }; static struct tftp_state tftp_state; +static struct tftp_req tftp_req; static void tftp_tmr(void *arg); +static void tftp_req_tmr(void *arg); +static const char *mode_to_string(enum tftp_transfer_mode mode); + +static void +clear_req(void) +{ + ip_addr_set_any(0, &tftp_req.addr); + tftp_req.port = 0; + tftp_req.opcode = 0; + free(tftp_req.fname); + tftp_req.fname = NULL; + tftp_req.mode = 0; + + sys_untimeout(tftp_req_tmr, NULL); +} static void close_handle(void) { + clear_req(); + tftp_state.port = 0; ip_addr_set_any(0, &tftp_state.addr); + tftp_state.retries = 0; if (tftp_state.last_data != NULL) { pbuf_free(tftp_state.last_data); @@ -210,6 +237,12 @@ send_ack(const ip_addr_t *addr, u16_t port, u16_t blknum) } static err_t +resend_request(void) +{ + return send_request(&tftp_req.addr, tftp_req.port, tftp_req.opcode, tftp_req.fname, mode_to_string(tftp_req.mode)); +} + +static err_t resend_data(const ip_addr_t *addr, u16_t port) { err_t ret; @@ -336,6 +369,9 @@ tftp_recv(void *arg, struct udp_pcb *upcb, struct pbuf *p, const ip_addr_t *addr tftp_state.last_pkt = tftp_state.timer; tftp_state.retries = 0; + if (tftp_req.fname) + clear_req(); + switch (opcode) { case PP_HTONS(TFTP_RRQ): /* fall through */ case PP_HTONS(TFTP_WRQ): { @@ -542,6 +578,26 @@ tftp_tmr(void *arg) } } +static void +tftp_req_tmr(void *arg) +{ + if (tftp_state.handle == NULL) { + return; + } + + sys_timeout(TFTP_TIMER_MSECS, tftp_req_tmr, NULL); + + if (tftp_state.retries < TFTP_MAX_RETRIES) { + LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, ("tftp: req timeout, retrying\n")); + resend_request(); + tftp_state.retries++; + } else { + LWIP_DEBUGF(TFTP_DEBUG | LWIP_DBG_STATE, ("tftp: req timeout\n")); + tftp_state.ctx->error(tftp_state.handle, -1, "Request timeout", strlen("Request timeout")); + close_handle(); + } +} + /** * Initialize TFTP client/server. * @param mode TFTP mode (client/server) @@ -638,6 +694,20 @@ mode_to_string(enum tftp_transfer_mode mode) } err_t +start_send_requests(const ip_addr_t *addr, u16_t port, u16_t opcode, const char* fname, enum tftp_transfer_mode mode) +{ + tftp_req.addr = *addr; + tftp_req.port = port; + tftp_req.opcode = opcode; + tftp_req.fname = strdup(fname); + tftp_req.mode = mode; + if (!tftp_req.fname) + return ERR_MEM; + sys_timeout(TFTP_TIMER_MSECS, tftp_req_tmr, NULL); + return resend_request(); +} + +err_t tftp_get(void* handle, const ip_addr_t *addr, u16_t port, const char* fname, enum tftp_transfer_mode mode) { LWIP_ERROR("TFTP client is not enabled (tftp_init)", (tftp_state.tftp_mode & LWIP_TFTP_MODE_CLIENT) != 0, return ERR_VAL); @@ -647,7 +717,7 @@ tftp_get(void* handle, const ip_addr_t *addr, u16_t port, const char* fname, enu tftp_state.handle = handle; tftp_state.blknum = 1; tftp_state.mode_write = 1; /* We want to receive data */ - return send_request(addr, port, TFTP_RRQ, fname, mode_to_string(mode)); + return start_send_requests(addr, port, TFTP_RRQ, fname, mode); } err_t @@ -660,7 +730,7 @@ tftp_put(void* handle, const ip_addr_t *addr, u16_t port, const char* fname, enu tftp_state.handle = handle; tftp_state.blknum = 1; tftp_state.mode_write = 0; /* We want to send data */ - return send_request(addr, port, TFTP_WRQ, fname, mode_to_string(mode)); + return start_send_requests(addr, port, TFTP_WRQ, fname, mode); } #endif /* LWIP_UDP */ diff --git a/lib/lwip/lwip/src/core/ipv4/icmp.c b/lib/lwip/lwip/src/core/ipv4/icmp.c index 9a82a67aa93..6d588349c4a 100644 --- a/lib/lwip/lwip/src/core/ipv4/icmp.c +++ b/lib/lwip/lwip/src/core/ipv4/icmp.c @@ -80,9 +80,9 @@ void icmp_input(struct pbuf *p, struct netif *inp) { u8_t type; -#ifdef LWIP_DEBUG +#if defined(LWIP_DEBUG) || defined(ICMP_DEST_UNREACH_CB) u8_t code; -#endif /* LWIP_DEBUG */ +#endif struct icmp_echo_hdr *iecho; const struct ip_hdr *iphdr_in; u16_t hlen; @@ -103,11 +103,11 @@ icmp_input(struct pbuf *p, struct netif *inp) } type = *((u8_t *)p->payload); -#ifdef LWIP_DEBUG +#if defined(LWIP_DEBUG) || defined(ICMP_DEST_UNREACH_CB) code = *(((u8_t *)p->payload) + 1); /* if debug is enabled but debug statement below is somehow disabled: */ LWIP_UNUSED_ARG(code); -#endif /* LWIP_DEBUG */ +#endif switch (type) { case ICMP_ER: /* This is OK, echo reply might have been parsed by a raw PCB @@ -257,6 +257,15 @@ icmp_input(struct pbuf *p, struct netif *inp) default: if (type == ICMP_DUR) { MIB2_STATS_INC(mib2.icmpindestunreachs); +#ifdef ICMP_DEST_UNREACH_CB + /* + * The callback receives the IP packet (not the ICMP message) so that + * it can extract the source address for example + */ + pbuf_add_header(p, IP_HLEN); + ICMP_DEST_UNREACH_CB(code, p); + pbuf_remove_header(p, IP_HLEN); +#endif } else if (type == ICMP_TE) { MIB2_STATS_INC(mib2.icmpintimeexcds); } else if (type == ICMP_PP) { diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h index 04ab94d6b70..849c79c5a8d 100644 --- a/lib/lwip/u-boot/arch/cc.h +++ b/lib/lwip/u-boot/arch/cc.h @@ -56,4 +56,11 @@ static inline const char *sntp_format_time(time_t t) } #define sntp_format_time sntp_format_time + +#ifdef CONFIG_LWIP_ICMP_SHOW_UNREACH +struct pbuf; +void net_lwip_icmp_dest_unreach(int code, struct pbuf *p); + +#define ICMP_DEST_UNREACH_CB(_c, _p) net_lwip_icmp_dest_unreach(_c, _p) +#endif #endif /* LWIP_ARCH_CC_H */ diff --git a/lib/lwip/u-boot/lwipopts.h b/lib/lwip/u-boot/lwipopts.h index 46af91f9410..80b93ea172d 100644 --- a/lib/lwip/u-boot/lwipopts.h +++ b/lib/lwip/u-boot/lwipopts.h @@ -80,7 +80,11 @@ #define IP_DEFAULT_TTL 255 +#if defined(CONFIG_PROT_ICMP_LWIP) +#define LWIP_ICMP 1 +#else #define LWIP_ICMP 0 +#endif #if defined(CONFIG_PROT_RAW_LWIP) #define LWIP_RAW 1 diff --git a/net/Kconfig b/net/Kconfig index 24508026200..40ec6bbce76 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -244,11 +244,17 @@ config NET_RANDOM_ETHADDR generated. It will be saved to the appropriate environment variable, too. +config DNS + bool "Enable DNS resolutions" + select PROT_DNS_LWIP if NET_LWIP + help + Selecting this will allow the network stack to use server names + in addition to IP addresses. + config WGET bool "Enable wget" select PROT_TCP if NET select PROT_TCP_LWIP if NET_LWIP - select PROT_DNS_LWIP if NET_LWIP help Selecting this will enable wget, an interface to send HTTP requests via the network stack. diff --git a/net/Makefile b/net/Makefile index d63f62b7c8a..468820186cf 100644 --- a/net/Makefile +++ b/net/Makefile @@ -10,7 +10,7 @@ ifeq ($(CONFIG_NET),y) obj-$(CONFIG_NET) += arp.o obj-$(CONFIG_CMD_BOOTP) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o -obj-$(CONFIG_CMD_DNS) += dns.o +obj-$(CONFIG_DNS) += dns.o obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o obj-$(CONFIG_IPV6) += ndisc.o obj-$(CONFIG_$(PHASE_)DM_ETH) += net.o diff --git a/net/arp.c b/net/arp.c index bc1e25f941f..4801dca6213 100644 --- a/net/arp.c +++ b/net/arp.c @@ -1,9 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copied from Linux Monitor (LiMon) - Networking. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de diff --git a/net/arp.h b/net/arp.h index c50885fb9a5..882f3ec31fc 100644 --- a/net/arp.h +++ b/net/arp.h @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copied from Linux Monitor (LiMon) - Networking. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de diff --git a/net/bootp.c b/net/bootp.c index 95d906e3b2d..19e7453daed 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -1,8 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Based on LiMon - BOOTP. * * Copyright 1994, 1995, 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2004 Wolfgang Denk, wd@denx.de diff --git a/net/bootp.h b/net/bootp.h index 68320bf66cf..47c743479e7 100644 --- a/net/bootp.h +++ b/net/bootp.h @@ -1,8 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copied from LiMon - BOOTP. * * Copyright 1994, 1995, 2000 Neil Russell. - * (See License) * Copyright 2000 Paolo Scaffardi */ diff --git a/net/cdp.c b/net/cdp.c index d4cfc587ee3..6e404981d4a 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -1,9 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copied from Linux Monitor (LiMon) - Networking. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de diff --git a/net/cdp.h b/net/cdp.h index 16ccbf4b59e..606fabba957 100644 --- a/net/cdp.h +++ b/net/cdp.h @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copied from Linux Monitor (LiMon) - Networking. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de diff --git a/net/lwip/Kconfig b/net/lwip/Kconfig index d28a8a7df94..5789766fe62 100644 --- a/net/lwip/Kconfig +++ b/net/lwip/Kconfig @@ -4,6 +4,16 @@ if NET_LWIP +config LWIP_ICMP_SHOW_UNREACH + bool "Print ICMP Destination Unreachable messages" + default y + depends on CMD_TFTPBOOT || CMD_SNTP + select PROT_ICMP_LWIP + help + Prints a message whenever an ICMP Destination Unreachable message is + received while running a network command that sends requests via UDP. + Enabling this can make troubleshooting easier. + config LWIP_DEBUG bool "Enable debug traces in the lwIP library" help @@ -31,6 +41,9 @@ config PROT_DNS_LWIP bool select PROT_UDP_LWIP +config PROT_ICMP_LWIP + bool + config PROT_RAW_LWIP bool diff --git a/net/lwip/Makefile b/net/lwip/Makefile index 97299d9b542..1b48ae4d508 100644 --- a/net/lwip/Makefile +++ b/net/lwip/Makefile @@ -2,6 +2,8 @@ ccflags-y += -I$(srctree)/lib/lwip/lwip/src/include -I$(srctree)/lib/lwip/u-boot obj-$(CONFIG_$(PHASE_)DM_ETH) += net-lwip.o obj-$(CONFIG_CMD_DHCP) += dhcp.o +obj-$(CONFIG_DNS) += dns.o +obj-$(CONFIG_LWIP_ICMP_SHOW_UNREACH) += icmp_unreach.o obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o obj-$(CONFIG_WGET) += wget.o diff --git a/net/lwip/dns.c b/net/lwip/dns.c new file mode 100644 index 00000000000..9964003195f --- /dev/null +++ b/net/lwip/dns.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (C) 2024 Linaro Ltd. */ + +#include <command.h> +#include <console.h> +#include <env.h> +#include <lwip/dns.h> +#include <lwip/timeouts.h> +#include <net.h> +#include <time.h> + +#define DNS_RESEND_MS 1000 +#define DNS_TIMEOUT_MS 10000 + +struct dns_cb_arg { + ip_addr_t host_ipaddr; + const char *var; + bool done; +}; + +static void do_dns_tmr(void *arg) +{ + dns_tmr(); +} + +static void dns_cb(const char *name, const ip_addr_t *ipaddr, void *arg) +{ + struct dns_cb_arg *dns_cb_arg = arg; + char *ipstr = ip4addr_ntoa(ipaddr); + + dns_cb_arg->done = true; + + if (!ipaddr) { + printf("DNS: host not found\n"); + dns_cb_arg->host_ipaddr.addr = 0; + return; + } + + dns_cb_arg->host_ipaddr.addr = ipaddr->addr; + + if (dns_cb_arg->var) + env_set(dns_cb_arg->var, ipstr); +} + +static int dns_loop(struct udevice *udev, const char *name, const char *var) +{ + struct dns_cb_arg dns_cb_arg = { }; + struct netif *netif; + ip_addr_t ipaddr; + ulong start; + int ret; + + dns_cb_arg.var = var; + + netif = net_lwip_new_netif(udev); + if (!netif) + return CMD_RET_FAILURE; + + if (net_lwip_dns_init()) { + net_lwip_remove_netif(netif); + return CMD_RET_FAILURE; + } + + dns_cb_arg.done = false; + + ret = dns_gethostbyname(name, &ipaddr, dns_cb, &dns_cb_arg); + + if (ret == ERR_OK) { + dns_cb(name, &ipaddr, &dns_cb_arg); + } else if (ret == ERR_INPROGRESS) { + start = get_timer(0); + sys_timeout(DNS_RESEND_MS, do_dns_tmr, NULL); + do { + net_lwip_rx(udev, netif); + if (dns_cb_arg.done) + break; + if (ctrlc()) { + printf("\nAbort\n"); + break; + } + } while (get_timer(start) < DNS_TIMEOUT_MS); + sys_untimeout(do_dns_tmr, NULL); + } + + net_lwip_remove_netif(netif); + + if (dns_cb_arg.done && dns_cb_arg.host_ipaddr.addr != 0) { + if (!var) + printf("%s\n", ipaddr_ntoa(&ipaddr)); + return CMD_RET_SUCCESS; + } + + return CMD_RET_FAILURE; +} + +int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + char *name; + char *var = NULL; + + if (argc == 1 || argc > 3) + return CMD_RET_USAGE; + + name = argv[1]; + + if (argc == 3) + var = argv[2]; + + if (net_lwip_eth_start() < 0) + return CMD_RET_FAILURE; + + return dns_loop(eth_get_dev(), name, var); +} diff --git a/net/lwip/icmp_unreach.c b/net/lwip/icmp_unreach.c new file mode 100644 index 00000000000..9e8a05f5717 --- /dev/null +++ b/net/lwip/icmp_unreach.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (C) 2025 Linaro Ltd. */ + +#include <lwip/icmp.h> +#include <lwip/ip4_addr.h> +#include <lwip/pbuf.h> +#include <lwip/prot/ip4.h> + +static const char *code_to_str(int code) +{ + switch (code) { + case ICMP_DUR_NET: + return "network unreachable"; + case ICMP_DUR_HOST: + return "host unreachable"; + case ICMP_DUR_PROTO: + return "protocol unreachable"; + case ICMP_DUR_PORT: + return "port unreachable"; + case ICMP_DUR_FRAG: + return "fragmentation needed and DF set"; + case ICMP_DUR_SR: + return "source route failed"; + default: + break; + } + return "unknown cause"; +} + +void net_lwip_icmp_dest_unreach(int code, struct pbuf *p) +{ + struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; + ip4_addr_t src; + + ip4_addr_copy(src, iphdr->src); + printf("ICMP destination unreachable (%s) from %s\n", + code_to_str(code), ip4addr_ntoa(&src)); +} diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index 660ceb10cbe..1a70cedfb58 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -27,7 +27,7 @@ #if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER) void (*push_packet)(void *, int len) = 0; #endif -static int net_try_count; +int net_try_count; static int net_restarted; int net_restart_wrap; static uchar net_pkt_buf[(PKTBUFSRX) * PKTSIZE_ALIGN + PKTALIGN]; @@ -147,7 +147,7 @@ static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip, */ int net_lwip_dns_init(void) { -#if CONFIG_IS_ENABLED(CMD_DNS) +#if CONFIG_IS_ENABLED(DNS) bool has_server = false; ip_addr_t ns; char *nsenv; @@ -364,7 +364,7 @@ int net_lwip_rx(struct udevice *udev, struct netif *netif) */ int net_lwip_dns_resolve(char *name_or_ip, ip_addr_t *ip) { -#if defined(CONFIG_CMD_DNS) +#if defined(CONFIG_DNS) char *var = "_dnsres"; char *argv[] = { "dns", name_or_ip, var, NULL }; int argc = ARRAY_SIZE(argv) - 1; @@ -373,7 +373,7 @@ int net_lwip_dns_resolve(char *name_or_ip, ip_addr_t *ip) if (ipaddr_aton(name_or_ip, ip)) return 0; -#if defined(CONFIG_CMD_DNS) +#if defined(CONFIG_DNS) if (do_dns(NULL, 0, argc, argv) != CMD_RET_SUCCESS) return -1; diff --git a/net/net.c b/net/net.c index 5219367e391..f579f6ac5bc 100644 --- a/net/net.c +++ b/net/net.c @@ -1,9 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copied from Linux Monitor (LiMon) - Networking. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de @@ -115,7 +114,7 @@ #include "bootp.h" #include "cdp.h" #include "dhcpv6.h" -#if defined(CONFIG_CMD_DNS) +#if defined(CONFIG_DNS) #include "dns.h" #endif #include "link_local.h" @@ -288,7 +287,7 @@ static int on_vlan(const char *name, const char *value, enum env_op op, } U_BOOT_ENV_CALLBACK(vlan, on_vlan); -#if defined(CONFIG_CMD_DNS) +#if defined(CONFIG_DNS) static int on_dnsip(const char *name, const char *value, enum env_op op, int flags) { @@ -582,7 +581,7 @@ restart: nc_start(); break; #endif -#if defined(CONFIG_CMD_DNS) +#if defined(CONFIG_DNS) case DNS: dns_start(); break; @@ -1507,7 +1506,7 @@ static int net_check_prereq(enum proto_t protocol) } goto common; #endif -#if defined(CONFIG_CMD_DNS) +#if defined(CONFIG_DNS) case DNS: if (net_dns_server.s_addr == 0) { puts("*** ERROR: DNS server address not given\n"); @@ -1540,7 +1539,7 @@ static int net_check_prereq(enum proto_t protocol) return 1; } #if defined(CONFIG_CMD_PING) || \ - defined(CONFIG_CMD_DNS) || defined(CONFIG_PROT_UDP) + defined(CONFIG_DNS) || defined(CONFIG_PROT_UDP) common: #endif /* Fall through */ diff --git a/net/net_rand.h b/net/net_rand.h index 686e85f2b53..e21dff8569b 100644 --- a/net/net_rand.h +++ b/net/net_rand.h @@ -1,8 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copied from LiMon - BOOTP. * * Copyright 1994, 1995, 2000 Neil Russell. - * (See License) * Copyright 2000 Paolo Scaffardi */ diff --git a/net/ping.c b/net/ping.c index 075df3663fe..fb981f62084 100644 --- a/net/ping.c +++ b/net/ping.c @@ -1,9 +1,8 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* * Copied from Linux Monitor (LiMon) - Networking. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de diff --git a/net/ping.h b/net/ping.h index 76ac225fc07..739f128408e 100644 --- a/net/ping.h +++ b/net/ping.h @@ -1,9 +1,8 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copied from Linux Monitor (LiMon) - Networking. * * Copyright 1994 - 2000 Neil Russell. - * (See License) * Copyright 2000 Roland Borde * Copyright 2000 Paolo Scaffardi * Copyright 2000-2002 Wolfgang Denk, wd@denx.de diff --git a/net/wget.c b/net/wget.c index 428ee072330..d3642958bf0 100644 --- a/net/wget.c +++ b/net/wget.c @@ -393,7 +393,7 @@ int wget_do_request(ulong dst_addr, char *uri) if (string_to_ip(host_name).s_addr) { s = host_name; } else { -#if IS_ENABLED(CONFIG_CMD_DNS) +#if IS_ENABLED(CONFIG_DNS) net_dns_resolve = host_name; net_dns_env_var = "httpserverip"; if (net_loop(DNS) < 0) { diff --git a/scripts/Makefile.xpl b/scripts/Makefile.xpl index 03a2f151d91..3e940bf562d 100644 --- a/scripts/Makefile.xpl +++ b/scripts/Makefile.xpl @@ -390,7 +390,6 @@ $(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin endif $(obj)/u-boot-spl.ldr: $(obj)/u-boot-spl - $(CREATE_LDR_ENV) $(LDR) -T $(CONFIG_LDR_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) diff --git a/scripts/dtc/pylibfdt/setup.py b/scripts/dtc/pylibfdt/setup.py index 0f7485de9b5..fb2106be0f0 100755 --- a/scripts/dtc/pylibfdt/setup.py +++ b/scripts/dtc/pylibfdt/setup.py @@ -158,7 +158,6 @@ setup( long_description_content_type="text/plain", url="https://git.kernel.org/pub/scm/utils/dtc/dtc.git", license="GPL-2.0-or-later OR BSD-2-Clause", - license_files=["Licenses/gpl-2.0.txt", "Licenses/bsd-2-clause.txt"], classifiers=[ "Programming Language :: Python :: 3", diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 595e4cfcada..e71c80a5b2e 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_CMD_FDT) += fdt.o obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o obj-$(CONFIG_CMD_HASH) += hash.o obj-$(CONFIG_CMD_HISTORY) += history.o +obj-$(CONFIG_CMD_I3C) += i3c.o obj-$(CONFIG_CMD_LOADM) += loadm.o obj-$(CONFIG_CMD_MEMINFO) += meminfo.o obj-$(CONFIG_CMD_MEMORY) += mem_copy.o diff --git a/test/cmd/i3c.c b/test/cmd/i3c.c new file mode 100644 index 00000000000..04baad2a4b2 --- /dev/null +++ b/test/cmd/i3c.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <dm.h> +#include <dm/test.h> +#include <test/test.h> +#include <test/ut.h> + +/* Basic test for probing i3c controller with invalid name */ +static int dm_test_i3c_cmd_probe_invalid_master(struct unit_test_state *uts) +{ + ut_asserteq(1, run_command("i3c any", 0)); + ut_assert_nextline("i3c0 (i3c_sandbox)"); + ut_assert_nextline("i3c1 (i3c_sandbox)"); + ut_assert_nextline("i3c: Host controller not initialized: any"); + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_i3c_cmd_probe_invalid_master, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_DM); + +/* Basic test of the i3c controller for valid name as per test DT */ +static int dm_test_i3c_cmd_probe_valid_master(struct unit_test_state *uts) +{ + ut_asserteq(0, run_command("i3c i3c0", 0)); + ut_assert_nextline("i3c: Current controller: i3c0"); + ut_assert_console_end(); + + ut_asserteq(0, run_command("i3c current", 0)); + ut_assert_nextline("i3c: Current controller: i3c0"); + ut_assert_console_end(); + + ut_asserteq(0, run_command("i3c i3c1", 0)); + ut_assert_nextline("i3c: Current controller: i3c1"); + ut_assert_console_end(); + + ut_asserteq(0, run_command("i3c current", 0)); + ut_assert_nextline("i3c: Current controller: i3c1"); + ut_assert_console_end(); + + ut_asserteq(0, run_command("i3c list", 0)); + ut_assert_nextline("i3c0 (i3c_sandbox)"); + ut_assert_nextline("i3c1 (i3c_sandbox)"); + ut_assert_console_end(); + + return 0; +} +DM_TEST(dm_test_i3c_cmd_probe_valid_master, UTF_SCAN_PDATA | UTF_SCAN_FDT | UTF_DM);
\ No newline at end of file diff --git a/test/dm/Makefile b/test/dm/Makefile index d15859eca30..474e77a2151 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_mdata.o obj-$(CONFIG_SANDBOX) += host.o obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o obj-$(CONFIG_DM_I2C) += i2c.o +obj-$(CONFIG_I3C) += i3c.o obj-$(CONFIG_SOUND) += i2s.o obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o obj-$(CONFIG_IOMMU) += iommu.o diff --git a/test/dm/i3c.c b/test/dm/i3c.c new file mode 100644 index 00000000000..81336e67555 --- /dev/null +++ b/test/dm/i3c.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <dm.h> +#include <i3c.h> +#include <dm/test.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Basic test of the i3c uclass */ +static int dm_test_i3c_base(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_get_device(UCLASS_I3C, 0, &dev)); + ut_assertok(dm_i3c_read(dev, 0, NULL, 1)); + ut_assertok(dm_i3c_read(dev, 0, NULL, 4)); + ut_assertok(dm_i3c_write(dev, 0, "AABB", 2)); + ut_assertok(dm_i3c_write(dev, 0, "AABBCCDD", 4)); + + ut_assertok(uclass_get_device(UCLASS_I3C, 1, &dev)); + ut_assertok(dm_i3c_read(dev, 1, NULL, 1)); + ut_assertok(dm_i3c_read(dev, 1, NULL, 4)); + ut_assertok(dm_i3c_write(dev, 1, "AABB", 2)); + ut_assertok(dm_i3c_write(dev, 1, "AABBCCDD", 4)); + + ut_asserteq(-ENODEV, uclass_get_device(UCLASS_I3C, 2, &dev)); + + return 0; +} +DM_TEST(dm_test_i3c_base, UTF_SCAN_PDATA | UTF_SCAN_FDT); diff --git a/test/py/tests/test_fit_mkimage_validate.py b/test/py/tests/test_fit_mkimage_validate.py index ef974c8c762..170b2a8cbbb 100644 --- a/test/py/tests/test_fit_mkimage_validate.py +++ b/test/py/tests/test_fit_mkimage_validate.py @@ -57,6 +57,8 @@ def test_fit_invalid_image_reference(ubman): assert result.returncode != 0, "mkimage should fail due to missing image reference" assert "references undefined image 'notexist'" in result.stderr +@pytest.mark.boardspec('sandbox') +@pytest.mark.requiredtool('dtc') def test_fit_invalid_default_config(ubman): """Test that mkimage fails when default config is missing""" diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst index 12a39d070e4..8922d6cd070 100644 --- a/tools/binman/entries.rst +++ b/tools/binman/entries.rst @@ -1689,6 +1689,18 @@ together. See imx95_evk.rst for how to get DDR PHY Firmware Images. +.. _etype_nxp_imx9image: + +Entry: nxp_imx9image: data file generator and mkimage invocation +----------------------------------------------------------------------------- + +This entry is used to generate a data file that is passed to mkimage with the -n +option. Each line in this data file represents a command defined in the enum +imx8image_cmd. The imx8image_copy_image() function parses all commands and +constructs a .bin file accordingly. + + + .. _etype_opensbi: Entry: opensbi: RISC-V OpenSBI fw_dynamic blob diff --git a/tools/binman/etype/nxp_imx9image.py b/tools/binman/etype/nxp_imx9image.py new file mode 100644 index 00000000000..e0e806f2b7f --- /dev/null +++ b/tools/binman/etype/nxp_imx9image.py @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2025 NXP + +import os +from binman.etype.mkimage import Entry_mkimage +from dtoc import fdt_util +from u_boot_pylib import tools + +class Entry_nxp_imx9image(Entry_mkimage): + """NXP i.MX9 .bin configuration file generator and mkimage invocation + + Properties arguments: + - append: appends the specified blob file as-is + - boot-from: indicates the boot device to be used + - cntr-version: sets the image container format version + - container: indicates that it is a new container + - dummy-ddr: specifies the memory address for storing the DDR training + data image + - dummy-v2x: specifies the memory address for storing V2X firmware + - hold: reserves a specified number of bytes after the previous image + - image: defines the option type, image filename, and the memory address + where the image will be stored + - soc-type: specifies the target SoC for which the .bin file is generated + """ + + def __init__(self, section, etype, node): + super().__init__(section, etype, node) + self.config_filename = None + + def ReadNode(self): + super().ReadNode() + cfg_path = fdt_util.GetString(self._node, 'cfg-path') + self.config_filename = tools.get_output_filename(cfg_path) + accepted_keys = [ + 'append', 'boot-from', 'cntr-version', 'container', 'dummy-ddr', + 'dummy-v2x', 'hold', 'image', 'soc-type' + ] + external_files = ['oei-m33-tcm.bin', 'm33_image.bin', 'bl31.bin'] + + with open(self.config_filename, 'w', encoding='utf-8') as f: + for prop in self._node.props.values(): + key = prop.name + value = prop.value + + if not any(key.startswith(prefix) for prefix in accepted_keys): + continue + + formatted_key = key.replace('-', '_') + + if key.startswith('image') and isinstance(value, list) and len(value) == 3: + file = value[1] + image_path = os.path.join(tools.get_output_dir(), value[1]) + value[1] = image_path + combined = ' '.join(map(str, value)) + + if file in external_files and not os.path.exists(value[1]): + print(f"file '{image_path}' does not exist. flash.bin may be not-functional.") + else: + f.write(f'image {combined}\n') + elif isinstance(value, str): + if key.startswith('append'): + file_path = os.path.join(tools.get_output_dir(), value) + if os.path.exists(file_path): + f.write(f'append {file_path}\n') + else: + print(f"file '{file_path}' does not exist. flash.bin may be not-functional.") + else: + f.write(f'{formatted_key} {value}\n') + elif isinstance(value, bool): + f.write(f'{formatted_key}\n') + elif isinstance(value, bytes): + hex_value = hex(int.from_bytes(value, byteorder='big')) + f.write(f'{formatted_key} {hex_value}\n') + + def BuildSectionData(self, required): + data, input_fname, uniq = self.collect_contents_to_file(self._entries.values(), 'imx9image') + + outfile = f'imx9image-out.{uniq}' + output_fname = tools.get_output_filename(outfile) + + args = [ + '-d', input_fname, '-n', self.config_filename, '-T', 'imx8image', + output_fname + ] + + result = self.mkimage.run_cmd(*args) + if result is not None and os.path.exists(output_fname): + return tools.read_file(output_fname) diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py index a90db3c9351..925c39a530e 100644 --- a/tools/binman/ftest.py +++ b/tools/binman/ftest.py @@ -7906,6 +7906,17 @@ fdt fdtmap Extract the devicetree blob from the fdtmap len(IMX_LPDDR_DMEM_DATA).to_bytes(4, 'little') + IMX_LPDDR_IMEM_DATA + IMX_LPDDR_DMEM_DATA, data) + def testNxpImx9Image(self): + """Test that binman can generate a .bin file""" + testdir = tempfile.mkdtemp(prefix='binman.') + image_path = os.path.join(testdir, 'image.bin') + with open(image_path, 'w') as f: + pass + container_path = os.path.join(testdir, 'mx95b0-ahab-container.img') + with open(container_path, 'w') as f: + f.write(bytes([0x87]).decode('latin1') * 32768) + self._DoTestFile('350_nxp_imx95.dts', output_dir=testdir) + def testFitSignSimple(self): """Test that image with FIT and signature nodes can be signed""" if not elf.ELF_TOOLS: diff --git a/tools/binman/test/350_nxp_imx95.dts b/tools/binman/test/350_nxp_imx95.dts new file mode 100644 index 00000000000..3fc2de44b4a --- /dev/null +++ b/tools/binman/test/350_nxp_imx95.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + binman { + u-boot { + type = "nxp-imx9image"; + cfg-path = "u-boot-container.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + append0 = "mx95b0-ahab-container.img"; + append1 = "container.img"; + container; + image0 = "a55", "bl31.bin", "0x8a200000"; + image1 = "a55", "image.bin", "0x90200000"; + }; + }; +}; diff --git a/tools/buildman/buildman.rst b/tools/buildman/buildman.rst index 8c45a841024..9e850b26ec0 100644 --- a/tools/buildman/buildman.rst +++ b/tools/buildman/buildman.rst @@ -6,7 +6,7 @@ Buildman build tool Quick-start ----------- -If you just want to quickly set up buildman so you can build something (for +If you just want to quickly set up Buildman so you can build something (for example Raspberry Pi 2): .. code-block:: bash @@ -22,12 +22,12 @@ example Raspberry Pi 2): What is this? ------------- -This tool handles building U-Boot to check that you have not broken it -with your patch series. It can build each individual commit and report -which boards fail on which commits, and which errors come up. It aims -to make full use of multi-processor machines. +This tool builds U-Boot to check that you have not broken it with your +patch series. It can build each individual commit and report which boards +fail on which commits, and which errors come up. It aims to make full use +of multi-processor machines. -A key feature of buildman is its output summary, which allows warnings, +A key feature of Buildman is its output summary, which allows warnings, errors or image size increases in a particular commit or board to be quickly identified and the offending commit pinpointed. This can be a big help for anyone working with >10 patches at a time. @@ -63,7 +63,7 @@ can be run repeatedly on the same branch after making changes to commits on that branch. In this case it will automatically rebuild commits which have changed (and remove its old results for that commit). It is possible to build a branch for one board, then later build it for another board. This adds to -the output, so now you have results for two boards. If you want buildman to +the output, so now you have results for two boards. If you want Buildman to re-build a commit it has already built (e.g. because of a toolchain update), use the -f flag. @@ -81,9 +81,9 @@ a time. A thread starts at the first commit, configures the source for your board and builds it. Then it checks out the next commit and does an incremental build (i.e. not using 'make xxx_defconfig' unless you use -C). Eventually the thread reaches the last commit and stops. If a commit causes -an error or warning, buildman will try it again after reconfiguring (but see +an error or warning, Buildman will try it again after reconfiguring (but see -Q). Thus some commits may be built twice, with the first result silently -discarded. Lots of errors and warnings will causes lots of reconfigures and your +discarded. Lots of errors and warnings will cause lots of reconfigures and your build will be very slow. This is because a file that produces just a warning would not normally be rebuilt in an incremental build. Once a thread finishes building all the commits for a board, it starts on the commits for another @@ -100,14 +100,14 @@ threads do not affect the state of your git repository. Any checkouts done by the thread affect only the working directory for that thread. Buildman automatically selects the correct tool chain for each board. You -must supply suitable tool chains (see --fetch-arch), but buildman takes care -of selecting the right one. +must supply suitable tool chains (see ``--fetch-arch``), but Buildman takes +care of selecting the right one. Buildman generally builds a branch (with the -b flag), and in this case builds the upstream commit as well, for comparison. So even if you have one commit in your branch, two commits will be built. Put all your commits in a branch, set the branch's upstream to a valid value, and all will be well. -Otherwise buildman will perform random actions. Use -n to check what the +Otherwise Buildman will perform random actions. Use -n to check what the random actions might be. Buildman effectively has two modes: without -s it builds, with -s it @@ -115,7 +115,7 @@ summarises the results of previous (or active) builds. If you just want to build the current source tree, leave off the -b flag. This will display results and errors as they happen. You can still look at -them later using -se. Note that buildman will assume that the source has +them later using -se. Note that Buildman will assume that the source has changed, and will build all specified boards in this case. Buildman is optimised for building many commits at once, for many boards. @@ -153,9 +153,9 @@ You can also use -x to specifically exclude some boards. For example: means to build all arm boards except nvidia, freescale and anything ending with 'ball'. -For building specific boards you can use the --boards (or --bo) option, which -takes a comma-separated list of board target names and be used multiple times -on the command line: +For building specific boards you can use the ``--boards`` (or ``--bo``) option, +which takes a comma-separated list of board target names and can be used +multiple times on the command line: .. code-block:: bash @@ -183,7 +183,7 @@ Setting up git checkout -b my-branch origin/master # Add some commits to the branch, reading for testing -#. Create ~/.buildman to tell buildman where to find tool chains (see +#. Create ~/.buildman to tell Buildman where to find tool chains (see buildman_settings_ for details). As an example:: # Buildman settings file @@ -212,7 +212,7 @@ Setting up The toolchain-alias section indicates that the i386 toolchain should be used to build x86 commits. - Note that you can also specific exactly toolchain prefixes if you like:: + Note that you can also specify toolchain prefixes if you like:: [toolchain-prefix] arm: /opt/arm-eabi-4.6/bin/arm-eabi- @@ -222,18 +222,18 @@ Setting up [toolchain-prefix] arm: /opt/arm-eabi-4.6/bin/arm-eabi-gcc - This tells buildman that you want to use this exact toolchain for the arm + This tells Buildman that you want to use this exact toolchain for the arm architecture. This will override any toolchains found by searching using the [toolchain] settings. - Since the toolchain prefix is an explicit request, buildman will report an + Since the toolchain prefix is an explicit request, Buildman will report an error if a toolchain is not found with that prefix. The current PATH will be searched, so it is possible to use:: [toolchain-prefix] arm: arm-none-eabi- - and buildman will find arm-none-eabi-gcc in /usr/bin if you have it + and Buildman will find arm-none-eabi-gcc in /usr/bin if you have it installed. Another example:: @@ -241,11 +241,11 @@ Setting up [toolchain-wrapper] wrapper: ccache - This tells buildman to use a compiler wrapper in front of CROSS_COMPILE. In + This tells Buildman to use a compiler wrapper in front of CROSS_COMPILE. In this example, ccache. It doesn't affect the toolchain scan. The wrapper is - added when CROSS_COMPILE environtal variable is set. The name in this - section is ignored. If more than one line is provided, only the last one - is taken. + added when the CROSS_COMPILE environment variable is set. The tag name in + this section is not important. If more than one line is provided, only the + last one is used. #. Make sure you have the required Python pre-requisites @@ -440,7 +440,7 @@ Setting up You can download toolchains and update the [toolchain] section of the settings file to find them. - To make this easier, buildman can automatically download and install + To make this easier, Buildman can automatically download and install toolchains from kernel.org. First list the available architectures:: $ ./tools/buildman/buildman --fetch-arch list @@ -476,15 +476,28 @@ Setting up Buildman should now be set up to use your new toolchain. - At the time of writing, U-Boot has these architectures: + At the time of writing, U-Boot supports these architectures: - arc, arm, m68k, microblaze, mips, nios2, powerpc, sandbox, sh, x86, xtensa + - ARC (arc) + - ARM (arm) + - Motorola 68k (m68k) + - MicroBlaze (microblaze) + - MIPS (mips) + - Nios II (nios2) + - PowerPC (powerpc) + - RISC-V (riscv) + - Sandbox (sandbox) + - SuperH (sh) + - x86 (x86) + - Xtensa (xtensa) + + Each entry list the architecture's name, followed by its code name in U-Boot. How to run it ------------- -First do a dry run using the -n flag: (replace <branch> with a real, local +First do a dry run using the -n flag (replace <branch> with a real, local branch with a valid upstream): .. code-block:: bash @@ -492,7 +505,7 @@ branch with a valid upstream): ./tools/buildman/buildman -b <branch> -n If it can't detect the upstream branch, try checking out the branch, and -doing something like 'git branch --set-upstream-to upstream/master' +doing something like ``git branch --set-upstream-to upstream/master`` or something similar. Buildman will try to guess a suitable upstream branch if it can't find one (you will see a message like "Guessing upstream as ..."). You can also use the -c option to manually specify the number of commits to @@ -528,7 +541,7 @@ As an example:: This shows that it will build all 1059 boards, using 4 threads (because we have a 4-core CPU). Each thread will run with -j1, meaning that each make job will use a single CPU. The list of commits to be built helps you -confirm that things look about right. Notice that buildman has chosen a +confirm that things look about right. Notice that Buildman has chosen a 'base' directory for you, immediately above your source tree. Buildman works entirely inside the base directory, here ../lcd9b, @@ -640,7 +653,7 @@ But if you did want to see just the errors for lubbock, use: If you see error lines marked with '-', that means that the errors were fixed by that commit. Sometimes commits can be in the wrong order, so that a breakage is introduced for a few commits and fixed by later commits. This -shows up clearly with buildman. You can then reorder the commits and try +shows up clearly with Buildman. You can then reorder the commits and try again. At commit 16, the error moves: you can see that the old error at line 120 @@ -670,7 +683,7 @@ err Output from stderr, if any. Errors and warnings appear here. log - Output from stdout. Normally there isn't any since buildman runs in silent + Output from stdout. Normally there isn't any since Buildman runs in silent mode. Use -V to force a verbose build (this passes V=1 to 'make') toolchain @@ -731,17 +744,17 @@ Note that the 'text' region and 'rodata' are split out. You should add the two together to get the total read-only size (reported as the first column in the output from binutil's 'size' utility). -A useful option is --step which lets you skip some commits. For example ---step 2 will show the image sizes for only every 2nd commit (so it will +A useful option is ``--step`` which lets you skip some commits. For example +``--step 2`` will show the image sizes for only every 2nd commit (so it will compare the image sizes of the 1st, 3rd, 5th... commits). You can also use ---step 0 which will compare only the first and last commits. This is useful +``--step 0`` which will compare only the first and last commits. This is useful for an overview of how your entire series affects code size. It will build only the upstream commit and your final branch commit. You can also use -d to see a detailed size breakdown for each board. This list is sorted in order from largest growth to largest reduction. -It is even possible to go a little further with the -B option (--bloat). This +It is even possible to go a little further with the -B option (``--bloat``). This shows where U-Boot has bloated, breaking the size change down to the function level. Example output is below:: @@ -898,7 +911,7 @@ The .buildman settings file The .buildman file provides information about the available toolchains and also allows build flags to be passed to 'make'. It consists of several -sections, with the section name in square brackets. Within each section are +sections, with the section name in square brackets. Within each section there are a set of (tag, value) pairs. '[global]' section @@ -924,8 +937,8 @@ a set of (tag, value) pairs. This lists the available toolchains. The tag here doesn't matter, but make sure it is unique. The value is the path to the toolchain. Buildman will look in that path for a file ending in 'gcc'. It will then execute - it to check that it is a C compiler, passing only the --version flag to - it. If the return code is 0, buildman assumes that it is a valid C + it to check that it is a C compiler, passing only the ``--version`` flag to + it. If the return code is 0, Buildman assumes that it is a valid C compiler. It uses the first part of the name as the architecture and strips off the last part when setting the CROSS_COMPILE environment variable (parts are delimited with a hyphen). @@ -939,8 +952,7 @@ a set of (tag, value) pairs. '[toolchain-prefix]' section This can be used to provide the full toolchain-prefix for one or more architectures. The full CROSS_COMPILE prefix must be provided. These - typically have a higher priority than matches in the '[toolchain]', due to - this prefix. + typically have a higher priority than matches in the '[toolchain]'. The tilde character ``~`` is supported in paths, to represent the home directory. @@ -949,12 +961,12 @@ a set of (tag, value) pairs. This converts toolchain architecture names to U-Boot names. For example, if an x86 toolchains is called i386-linux-gcc it will not normally be used for architecture 'x86'. Adding 'x86: i386 x86_64' to this section - will tell buildman that the i386 and x86_64 toolchains can be used for + will tell Buildman that the i386 and x86_64 toolchains can be used for the x86 architecture. '[make-flags]' section U-Boot's build system supports a few flags (such as BUILD_TAG) which - affect the build product. These flags can be specified in the buildman + affect the build product. These flags can be specified in the Buildman settings file. They can also be useful when building U-Boot against other open source software. @@ -983,7 +995,7 @@ Quick Sanity Check ------------------ If you have made changes and want to do a quick sanity check of the -currently checked-out source, run buildman without the -b flag. This will +currently checked-out source, run Buildman without the -b flag. This will build the selected boards and display build status as it runs (i.e. -v is enabled automatically). Use -e to see errors/warnings as well. @@ -1002,29 +1014,29 @@ will build commits in us-buildman that are not in upstream/master. Building Faster --------------- -By default, buildman doesn't execute 'make mrproper' prior to building the +By default, Buildman doesn't execute 'make mrproper' prior to building the first commit for each board. This reduces the amount of work 'make' does, and hence speeds up the build. To force use of 'make mrproper', use -the -m flag. -This flag will slow down any buildman invocation, since it increases the amount -of work done on any build. An alternative is to use the --fallback-mrproper +This flag will slow down any Buildman invocation, since it increases the amount +of work done on any build. An alternative is to use the ``--fallback-mrproper`` flag, which retries the build with 'make mrproper' only after a build failure. -One possible application of buildman is as part of a continual edit, build, -edit, build, ... cycle; repeatedly applying buildman to the same change or +One possible application of Buildman is as part of a continual edit, build, +edit, build, ... cycle; repeatedly applying Buildman to the same change or series of changes while making small incremental modifications to the source each time. This provides quick feedback regarding the correctness of recent -modifications. In this scenario, buildman's default choice of build directory +modifications. In this scenario, Buildman's default choice of build directory causes more build work to be performed than strictly necessary. -By default, each buildman thread uses a single directory for all builds. When a +By default, each Buildman thread uses a single directory for all builds. When a thread builds multiple boards, the configuration built in this directory will cycle through various different configurations, one per board built by the thread. Variations in the configuration will force a rebuild of affected source -files when a thread switches between boards. Ideally, such buildman-induced +files when a thread switches between boards. Ideally, such Buildman-induced rebuilds would not happen, thus allowing the build to operate as efficiently as -the build system and source changes allow. buildman's -P flag may be used to +the build system and source changes allow. Buildman's -P flag may be used to enable this; -P causes each board to be built in a separate (board-specific) -directory, thus avoiding any buildman-induced configuration changes in any +directory, thus avoiding any Buildman-induced configuration changes in any build directory. U-Boot's build system embeds information such as a build timestamp into the @@ -1041,9 +1053,9 @@ of the source tree, thus allowing rapid tested evolution of the code:: ./tools/buildman/buildman -Pr tegra -Note also the `--dtc-skip` option which uses the system device-tree compiler to +Note also the ``--dtc-skip`` option which uses the system device-tree compiler to avoid needing to build it for each board. This can save 10-20% of build time. -An alternative is to set DTC=/path/to/dtc when running buildman. +An alternative is to set DTC=/path/to/dtc when running Buildman. Checking configuration ---------------------- @@ -1062,7 +1074,7 @@ For example:: + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 - am335x_evm_usbspl : + am335x_evm_usbspl: + u-boot.cfg: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_NET=1 + u-boot-spl.cfg: CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 + all: CONFIG_SPL_ENV_SUPPORT=1 CONFIG_SPL_MMC=1 CONFIG_SPL_NAND_SUPPORT=1 CONFIG_SPL_NET=1 @@ -1073,15 +1085,15 @@ This shows that commit 44 enabled three new options for the board am335x_evm_usbspl which were not enabled in commit 43. There is also a summary for 'arm' showing all the changes detected for that architecture. In this case there is only one board with changes, so 'arm' output is the -same as 'am335x_evm_usbspl'/ +same as 'am335x_evm_usbspl'. The -K option uses the u-boot.cfg, spl/u-boot-spl.cfg and tpl/u-boot-tpl.cfg files which are produced by a build. If all you want is to check the -configuration you can in fact avoid doing a full build, using --config-only. -This tells buildman to configuration U-Boot and create the .cfg files, but not +configuration you can in fact avoid doing a full build, using ``--config-only``. +This tells Buildman to configure U-Boot and create the .cfg files, but not actually build the source. This is 5-10 times faster than doing a full build. -By default buildman considers the follow two configuration methods +By default Buildman considers the following two configuration methods equivalent:: #define CONFIG_SOME_OPTION @@ -1089,9 +1101,9 @@ equivalent:: CONFIG_SOME_OPTION=y The former would appear in a header filer and the latter in a defconfig -file. The achieve this, buildman considers 'y' to be '1' in configuration +file. To achieve this, Buildman considers 'y' to be '1' in configuration variables. This avoids lots of useless output when converting a CONFIG -option to Kconfig. To disable this behaviour, use --squash-config-y. +option to Kconfig. To disable this behaviour, use ``--squash-config-y``. Checking the environment @@ -1120,7 +1132,7 @@ and 'brppt1_spi', removing a trailing semicolon. 'brppt1_nand' gained an a value for 'altbootcmd', but lost one for ' altbootcmd'. The -U option uses the u-boot.env files which are produced by a build. -Internally, buildman writes out an out-env file into the build directory for +Internally, Buildman writes out an out-env file into the build directory for later comparison. defconfig fragments @@ -1166,7 +1178,7 @@ Link-time optimisation (LTO) is designed to reduce code size by globally optimising the U-Boot build. Unfortunately this can dramatically slow down builds. This is particularly noticeable when running a lot of builds. -Use the -L (--no-lto) flag to disable LTO. +Use the -L (``--no-lto``) flag to disable LTO. .. code-block:: bash @@ -1176,7 +1188,7 @@ Use the -L (--no-lto) flag to disable LTO. Doing a simple build -------------------- -In some cases you just want to build a single board and get the full output, use +In case you want to build a single board and get the full output, use the -w option, for example: .. code-block:: bash @@ -1190,13 +1202,13 @@ specify the output directory with -o when using -w. Support for IDEs (Integrated Development Environments) ------------------------------------------------------ -Normally buildman summarises the output and shows information indicating the +Normally Buildman summarises the output and shows information indicating the meaning of each line of output. For example a '+' symbol appears at the start of -each error line. Also, buildman prints information about what it is about to do, +each error line. Also, Buildman prints information about what it is about to do, along with a summary at the end. -When using buildman from an IDE, it is helpful to drop this behaviour. Use the --I/--ide option for that. You might find -W helpful also so that warnings do +When using Buildman from an IDE, it is helpful to drop this behaviour. Use the +``-I/--ide`` option for that. You might also find -W helpful so that warnings do not cause the build to fail: .. code-block:: bash @@ -1215,12 +1227,12 @@ Typically a missing external blob causes a build failure. For build testing of a lot of boards, or boards for which you do not have the blobs, you can use the -M flag to allow missing blobs. This marks the build as if it succeeded, although with warnings shown, including 'Some images are invalid'. If any boards -fail in this way, buildman exits with status 101. +fail in this way, Buildman exits with status 101. -To convert warnings to errors, use -E. To make buildman return success with +To convert warnings to errors, use -E. To make Buildman return success with these warnings, use -W. -It is generally safe to default to enabling -M for all runs of buildman, so long +It is generally safe to default to enabling -M for all runs of Buildman, so long as you check the exit code. To do this, add:: allow-missing = "always" @@ -1261,11 +1273,12 @@ Some options have values, in which case you can change them: buildman -a 'BOOTCOMMAND="echo hello"' CONFIG_SYS_LOAD_ADDR=0x1000 -Note that you must put quotes around string options and the whole thing must be -in single quotes, to make sure the shell leave it alone. +Note that you must put quotes around string options and the whole argument must +be in single quotes to ensure that the shell recognizes it as a single +argument. If you try to set an option that does not exist, or that cannot be changed for -some other reason (e.g. it is 'selected' by another option), then buildman +some other reason (e.g. it is 'selected' by another option), then Buildman shows an error:: $ buildman --board sandbox -a FRED @@ -1279,18 +1292,18 @@ shows an error:: FRED Missing expected line: CONFIG_FRED=y -One major caveat with this feature with branches (-b) is that buildman does not +One major caveat with this feature with branches (-b) is that Buildman does not name the output directories differently when you change the configuration, so -doing the same build again with different configuration will not trigger a -rebuild. You can use -f to work around that. +re-launching Buildman with an updated configuration will not trigger a rebuild. +You can use -f to work around that. Other options ------------- -Buildman has various other command-line options. Try --help to see them. +Buildman has various other command-line options. Try ``--help`` to see them. -To find out what toolchain prefix buildman will use for a build, use the -A +To find out what toolchain prefix Buildman will use for a build, use the -A option. To request that compiler warnings be promoted to errors, use -E. This passes the @@ -1313,29 +1326,29 @@ warnings are found. Note that it can be useful to combine -E and -W. This means that all compiler warnings will produce failures (code 100) and all other warnings will produce success (since 101 is changed to 0). -If there are both warnings and errors, errors win, so buildman returns 100. +If there are both warnings and errors, errors win, so Buildman returns 100. The -y option is provided (for use with -s) to ignore the bountiful device-tree -warnings. Similarly, -Y tells buildman to ignore the migration warnings. +warnings. Similarly, -Y tells Buildman to ignore the migration warnings. -Sometimes you might get an error in a thread that is not handled by buildman, +Sometimes you might get an error in a thread that is not handled by Buildman, perhaps due to a failure of a tool that it calls. You might see the output, but -then buildman hangs. Failing to handle any eventuality is a bug in buildman and +then Buildman hangs. Failing to handle any eventuality is a bug in Buildman and should be reported. But you can use -T0 to disable threading and hopefully figure out the root cause of the build failure. -For situations where buildman is invoked from multiple running processes, it is -sometimes useful to have buildman wait until the others have finished. Use the ---process-limit option for this: --process-limit 1 will allow only one buildman -to process jobs at a time. +For situations where Buildman is invoked from multiple running processes, it is +sometimes useful to have Buildman wait until the others have finished. Use the +``--process-limit`` option for this: ``--process-limit 1`` will allow only one +Buildman to process jobs at a time. To build a particular target, rather than the default U-Boot target, use the -`--target` option. This is unlikely to be useful unless you are building a +``--target`` option. This is unlikely to be useful unless you are building a single board. Buildman normally builds out-of-tree, meaning that the source directory is not disturbed by the build. Use `-i` to do an in-tree build instead. Note that this -does not affect the source directory, since buildman creates a separate git +does not affect the source directory, since Buildman creates a separate git 'worktree' for each board. This means that it is possible to do an in-tree build of an entire branch, or even a 'current source' build for multiple boards. As a special case, you can use `-wi` to do an in-tree build in the current @@ -1344,7 +1357,7 @@ directory. Build summary ------------- -When buildman finishes it shows a summary, something like this:: +When Buildman finishes, it displays a summary, similar to the following: Completed: 5 total built, duration 0:00:21, rate 0.24 @@ -1357,14 +1370,14 @@ U-Boot build. Using boards.cfg ---------------- -This file is no-longer needed by buildman but it is still generated in the +This file is no-longer needed by Buildman but it is still generated in the working directory. This helps avoid a delay on every build, since scanning all -the Kconfig files takes a few seconds. Use the `-R <filename>` flag to force -regeneration of the file - in that case buildman exits after writing the file +the Kconfig files takes a few seconds. Use the ``-R <filename>`` flag to force +regeneration of the file - in that case Buildman exits after writing the file with exit code 2 if there was an error in the maintainer files. To use the default filename, use a hyphen, i.e. `-R -`. -You should use 'buildman -nv <criteria>' instead of greoing the boards.cfg file, +You should use 'buildman -nv <criteria>' instead of greping the boards.cfg file, since it may be dropped altogether in future. @@ -1372,16 +1385,16 @@ Checking maintainers -------------------- Sometimes a board is added without a corresponding entry in a MAINTAINERS file. -Use the `--maintainer-check` option to check this:: +Use the ``--maintainer-check`` option to check this:: $ buildman --maintainer-check WARNING: board/mikrotik/crs3xx-98dx3236/MAINTAINERS: missing defconfig ending at line 7 WARNING: no maintainers for 'clearfog_spi' -Buildman returns with an exit code of 2 if there area any warnings. +Buildman returns with an exit code of 2 if there are any warnings. -An experimental `--full-check option` also checks for boards which don't have a -CONFIG_TARGET_xxx where xxx corresponds to their defconfig filename. This is +An experimental ``--full-check option`` also checks for boards which don't have +a CONFIG_TARGET_xxx where xxx corresponds to their defconfig filename. This is not strictly necessary, but may be useful information. diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index fb6c57f77c1..0f41cdb64f5 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -168,6 +168,7 @@ static int read_bin_file(char *bin, uint8_t **data, off_t *bin_size) if (size < bin_stat.st_size) { fprintf(stderr, "read failed (%zx)\n", size); ret = -1; + free(buf); goto err; } |