diff options
72 files changed, 1181 insertions, 144 deletions
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index fc921a4be26..5fb3240acc5 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -534,8 +534,7 @@ int board_late_init(void) env_set_hex("ramdisk_addr_r", addr) : 1; status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? env_set_hex("kernel_comp_addr_r", addr) : 1; - status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? - env_set_hex("kernel_comp_size", addr) : 1; + status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); status |= !lmb_alloc(SZ_4M, &addr) ? env_set_hex("scriptaddr", addr) : 1; status |= !lmb_alloc(SZ_4M, &addr) ? @@ -544,9 +543,13 @@ int board_late_init(void) if (IS_ENABLED(CONFIG_FASTBOOT)) { status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ? env_set_hex("fastboot_addr_r", addr) : 1; - /* override loadaddr for memory rich soc */ - status |= !lmb_alloc(SZ_128M, &addr) ? - env_set_hex("loadaddr", addr) : 1; + /* + * Override loadaddr for memory rich soc since ${loadaddr} and + * ${kernel_addr_r} need to be different for the Android boot image + * flow. It's typically safe for ${loadaddr} to be the same address + * as the fastboot buffer. + */ + status |= env_set_hex("loadaddr", addr); } fdt_status |= !lmb_alloc(SZ_2M, &addr) ? diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8c6feae5735..04eb0e6f23c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350" +config TARGET_ANDES_VOYAGER + bool "Support Andes Voyager Board" + config TARGET_BANANAPI_F3 bool "Support BananaPi F3 Board" @@ -101,6 +104,7 @@ config SPL_ZERO_MEM_BEFORE_USE # board-specific options below source "board/andestech/ae350/Kconfig" +source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 15c4e14599d..d5123e4b7d9 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -608,14 +608,14 @@ static inline bool supports_extension(char ext) static int riscv_cpu_probe(void) { -#ifdef CONFIG_CPU - int ret; + if (CONFIG_IS_ENABLED(CPU)) { + int ret; - /* probe cpus so that RISC-V timer can be bound */ - ret = cpu_probe_all(); - if (ret) - return log_msg_ret("RISC-V cpus probe failed\n", ret); -#endif + /* probe cpus so that RISC-V timer can be bound */ + ret = cpu_probe_all(); + if (ret) + return log_msg_ret("RISC-V cpus probe failed\n", ret); + } return 0; } diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 2b10c2d6c01..a637727b76b 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb @@ -14,6 +15,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/qilai-voyager.dts b/arch/riscv/dts/qilai-voyager.dts new file mode 100644 index 00000000000..44933529f89 --- /dev/null +++ b/arch/riscv/dts/qilai-voyager.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "binman.dtsi" +#include "voyager-u-boot.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "andestech,voyager", "andestech,qilai"; + model = "Voyager"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlycon=sbi debug loglevel=7"; + stdout-path = "uart0:115200n8"; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + timebase-frequency = <0x3938700>; + + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU0_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU1_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU2_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU3_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + L2: l2-cache@200000 { + compatible = "cache"; + cache-level = <0x2>; + cache-size = <0x40000>; + reg = <0x0 0x00200000 0x0 0x100000>; + andes,inst-prefetch = <0x3>; + andes,data-prefetch = <0x3>; + andes,tag-ram-ctl = <0x0 0x0>; + andes,data-ram-ctl = <0x0 0x0>; + }; + + memory@400000000 { + device_type = "memory"; + reg = <0x04 0x00000000 0x0 0x40000000>; + }; + + soc { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "simple-bus"; + ranges; + + plic0: interrupt-controller@2000000 { + compatible = "riscv,plic0"; + #address-cells = <0x2>; + #interrupt-cells = <0x2>; + interrupt-controller; + reg = <0x0 0x02000000 0x0 0x2000000>; + riscv,ndev = <0x47>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 + &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 + &CPU3_intc 11 &CPU3_intc 9>; + }; + + plic1: interrupt-controller@400000 { + compatible = "andestech,plicsw"; + #address-cells = <0x2>; + #interrupt-cells = <0x2>; + interrupt-controller; + reg = <0x0 0x00400000 0x0 0x400000>; + riscv,ndev = <0x1>; + interrupts-extended = <&CPU0_intc 3 + &CPU1_intc 3 + &CPU2_intc 3 + &CPU3_intc 3>; + }; + + plmt0@100000 { + compatible = "andestech,plmt0"; + reg = <0x0 0x00100000 0x0 0x100000>; + interrupts-extended = <&CPU0_intc 7 + &CPU1_intc 7 + &CPU2_intc 7 + &CPU3_intc 7>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0x0>; + compatible = "fixed-clock"; + clock-frequency = <0x5f5e100>; + }; + + serial0: serial@30300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x0 0x30300000 0x0 0x1000>; + interrupts = <0x9 0x4>; + clock-frequency = <0x12c0000>; + reg-shift = <0x2>; + reg-offset = <0x20>; + no-loopback-test = <0x1>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@30c00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <0x5f5e100>; + clock-freq-min-max = <0x61a80 0x5f5e100>; + fifo-depth = <0x10>; + reg = <0x0 0x30c00000 0x0 0x1000>; + interrupts = <0x12 0x4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + dma-coherent; + }; + + spi: spi@30900000 { + compatible = "andestech,atcspi200"; + reg = <0x0 0x30900000 0x0 0x100000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + num-cs = <0x1>; + clocks = <&spiclk>; + interrupts = <0x4 0x4>; + interrupt-parent = <&plic0>; + + flash@0 { + compatible = "mx25u1635e", "jedec,spi-nor"; + spi-max-frequency = <0x2faf080>; + reg = <0x0>; + spi-cpol; + spi-cpha; + }; + }; +}; diff --git a/arch/riscv/dts/voyager-u-boot.dtsi b/arch/riscv/dts/voyager-u-boot.dtsi new file mode 100644 index 00000000000..cef0aa08b37 --- /dev/null +++ b/arch/riscv/dts/voyager-u-boot.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + cpus { + bootph-pre-ram; + CPU0: cpu@0 { + bootph-pre-ram; + CPU0_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU1: cpu@1 { + bootph-pre-ram; + CPU1_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU2: cpu@2 { + bootph-pre-ram; + CPU2_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU3: cpu@3 { + bootph-pre-ram; + CPU3_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + }; + + memory@0 { + bootph-pre-ram; + }; + + soc { + bootph-pre-ram; + + plic1: interrupt-controller@400000 { + bootph-pre-ram; + }; + + plmt0@100000 { + bootph-pre-ram; + }; + }; + + serial0: serial@30300000 { + bootph-pre-ram; + }; + +}; diff --git a/arch/riscv/dts/xilinx-binman.dts b/arch/riscv/dts/xilinx-binman.dts new file mode 100644 index 00000000000..715080ed763 --- /dev/null +++ b/arch/riscv/dts/xilinx-binman.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * binman file for AMD MicroBlaze V + * + * (C) Copyright 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "binman.dtsi" diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 4050ce2f051..f7a3e076fd5 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -2,15 +2,13 @@ /* * dts file for AMD MicroBlaze V * - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <1>; #size-cells = <1>; @@ -26,6 +24,7 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv32imafdc"; + mmu-type = "riscv,sv39"; i-cache-size = <32768>; d-cache-size = <32768>; clock-frequency = <100000000>; @@ -70,7 +69,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts index 4d65d338ecb..e6235ed2f52 100644 --- a/arch/riscv/dts/xilinx-mbv64.dts +++ b/arch/riscv/dts/xilinx-mbv64.dts @@ -2,15 +2,13 @@ /* * dts file for AMD MicroBlaze V * - * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <2>; #size-cells = <2>; @@ -26,6 +24,7 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; i-cache-size = <32768>; d-cache-size = <32768>; clock-frequency = <100000000>; @@ -70,7 +69,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S index 9884077c933..e5479bbe84e 100644 --- a/arch/riscv/lib/memcpy.S +++ b/arch/riscv/lib/memcpy.S @@ -125,6 +125,14 @@ WEAK(memcpy) .copy_end: ret +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define M_SLL sll +#define M_SRL srl +#else +#define M_SLL srl +#define M_SRL sll +#endif + .Lmisaligned_word_copy: /* * Misaligned word-wise copy. @@ -144,10 +152,10 @@ WEAK(memcpy) addi t0, t0, -(SZREG-1) /* At least one iteration will be executed here, no check */ 1: - srl a4, a5, t3 + M_SRL a4, a5, t3 REG_L a5, SZREG(a1) addi a1, a1, SZREG - sll a2, a5, t4 + M_SLL a2, a5, t4 or a2, a2, a4 REG_S a2, 0(a0) addi a0, a0, SZREG diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S index fbe6701dbe4..b2c1c736713 100644 --- a/arch/riscv/lib/memmove.S +++ b/arch/riscv/lib/memmove.S @@ -91,6 +91,14 @@ WEAK(memmove) mv a0, t0 ret +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define M_SLL sll +#define M_SRL srl +#else +#define M_SLL srl +#define M_SRL sll +#endif + .Lmisaligned_word_copy: /* * Misaligned word-wise copy. @@ -110,10 +118,10 @@ WEAK(memmove) addi t0, t0, SZREG-1 /* At least one iteration will be executed here, no check */ 1: - sll a4, a5, t4 + M_SLL a4, a5, t4 addi a1, a1, -SZREG REG_L a5, 0(a1) - srl a2, a5, t3 + M_SRL a2, a5, t3 or a2, a2, a4 addi a0, a0, -SZREG REG_S a2, 0(a0) diff --git a/board/andestech/voyager/Kconfig b/board/andestech/voyager/Kconfig new file mode 100644 index 00000000000..b2e212c3fee --- /dev/null +++ b/board/andestech/voyager/Kconfig @@ -0,0 +1,44 @@ +if TARGET_ANDES_VOYAGER + +config SYS_CPU + default "andes" + +config SYS_BOARD + default "voyager" + +config SYS_VENDOR + default "andestech" + +config SYS_SOC + default "qilai" + +config SYS_CONFIG_NAME + default "voyager" + +config ENV_SIZE + default 0x2000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x1F0000 if ENV_IS_IN_SPI_FLASH + +config SPL_TEXT_BASE + default 0x400800000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x400000000 + +config SYS_FDT_BASE + hex + default 0x81E0000 if OF_SEPARATE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RISCV_ANDES + select SUPPORT_SPL + select BINMAN if SPL + imply SMP + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE + imply OF_HAS_PRIOR_STAGE + +endif diff --git a/board/andestech/voyager/MAINTAINERS b/board/andestech/voyager/MAINTAINERS new file mode 100644 index 00000000000..b87026ee383 --- /dev/null +++ b/board/andestech/voyager/MAINTAINERS @@ -0,0 +1,8 @@ +Andestech Voyager BOARD +M: Randolph <randolph@andestech.com> +S: Maintained +F: board/andestech/voyager/ +F: configs/voyager_spl_defconfig +F: doc/board/andestech/voyager.rst +F: include/configs/qilai.h + diff --git a/board/andestech/voyager/Makefile b/board/andestech/voyager/Makefile new file mode 100644 index 00000000000..d293e3e2d89 --- /dev/null +++ b/board/andestech/voyager/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Andes Technology Corporation. +# Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + +obj-y := voyager.o diff --git a/board/andestech/voyager/voyager.c b/board/andestech/voyager/voyager.c new file mode 100644 index 00000000000..dc8f1347775 --- /dev/null +++ b/board/andestech/voyager/voyager.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Andes Technology Corporation + * Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + */ + +#include <asm/csr.h> +#include <asm/global_data.h> +#include <asm/sbi.h> +#include <config.h> +#include <cpu_func.h> +#include <dm.h> +#include <env.h> +#include <fdtdec.h> +#include <flash.h> +#include <image.h> +#include <init.h> +#include <linux/io.h> +#include <net.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_R +int board_early_init_r(void) +{ + /* enable andes-l2 cache */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + enable_caches(); + + return 0; +} +#endif + +#ifdef CONFIG_SPL +void board_boot_order(u32 *spl_boot_list) +{ + u8 i; + u32 boot_devices[] = { +#ifdef CONFIG_SPL_RAM_SUPPORT + BOOT_DEVICE_RAM, +#endif +#ifdef CONFIG_SPL_MMC + BOOT_DEVICE_MMC1, +#endif + }; + + for (i = 0; i < ARRAY_SIZE(boot_devices); i++) + spl_boot_list[i] = boot_devices[i]; +} +#endif diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 6e8c479e955..760dffc488b 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -59,5 +59,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply MTD_SPI_NAND imply CMD_MTD imply CMD_MTDPARTS + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER endif diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index ba622e38ee5..739a9b6cd76 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -4,52 +4,21 @@ * Padmarao Begari <padmarao.begari@microchip.com> */ -#include <dm.h> -#include <env.h> -#include <init.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/sections.h> +#include <dm.h> +#include <dm/devres.h> +#include <env.h> +#include <linux/compat.h> +#include <mpfs-mailbox.h> DECLARE_GLOBAL_DATA_PTR; -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) -#define MPFS_SYS_SERVICE_CR ((unsigned int *)0x37020050) -#define MPFS_SYS_SERVICE_SR ((unsigned int *)0x37020054) -#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800) - +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) #define PERIPH_RESET_VALUE 0x1e8u -#define SERVICE_CR_REQ 0x1u -#define SERVICE_SR_BUSY 0x2u -static void read_device_serial_number(u8 *response, u8 response_size) -{ - u8 idx; - u8 *response_buf; - unsigned int val; - - response_buf = (u8 *)response; - - writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR); - /* - * REQ bit will remain set till the system controller starts - * processing. - */ - do { - val = readl(MPFS_SYS_SERVICE_CR); - } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ)); - - /* - * Once system controller starts processing the busy bit will - * go high and service is completed when busy bit is gone low - */ - do { - val = readl(MPFS_SYS_SERVICE_SR); - } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY)); - - for (idx = 0; idx < response_size; idx++) - response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx); -} +static unsigned char mac_addr[6]; #if defined(CONFIG_MULTI_DTB_FIT) int board_fit_config_name_match(const char *name) @@ -145,13 +114,35 @@ int board_late_init(void) { u32 ret; int node; - u8 idx; - u8 device_serial_number[16] = { 0 }; - unsigned char mac_addr[6]; - char icicle_mac_addr[20]; + u8 device_serial_number[16] = {0}; void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = kzalloc(sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; - read_device_serial_number(device_serial_number, 16); + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } /* Update MAC address with device serial number */ mac_addr[0] = 0x00; @@ -170,19 +161,6 @@ int board_late_init(void) } } - icicle_mac_addr[0] = '['; - - sprintf(&icicle_mac_addr[1], "%pM", mac_addr); - - icicle_mac_addr[18] = ']'; - icicle_mac_addr[19] = '\0'; - - for (idx = 0; idx < 20; idx++) { - if (icicle_mac_addr[idx] == ':') - icicle_mac_addr[idx] = ' '; - } - env_set("icicle_mac_addr0", icicle_mac_addr); - mac_addr[5] = device_serial_number[0] + 1; node = fdt_path_offset(blob, "/soc/ethernet@20110000"); @@ -194,18 +172,33 @@ int board_late_init(void) } } - icicle_mac_addr[0] = '['; + return 0; +} - sprintf(&icicle_mac_addr[1], "%pM", mac_addr); +int ft_board_setup(void *blob, struct bd_info *bd) +{ + u32 ret; + int node; - icicle_mac_addr[18] = ']'; - icicle_mac_addr[19] = '\0'; + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mac_addr[5] -= 1; - for (idx = 0; idx < 20; idx++) { - if (icicle_mac_addr[idx] == ':') - icicle_mac_addr[idx] = ' '; + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20112000\n"); + return -ENODEV; + } } - env_set("icicle_mac_addr1", icicle_mac_addr); return 0; } diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index 010e386e64d..17a44020bcf 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -275,7 +275,7 @@ static int prog_eeprom(unsigned int size) if (is_match_magic()) { printf("MAGIC ERROR, Please check the data@%p.\n", pbuf.buf); - return -1; + return CMD_RET_FAILURE; } ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, @@ -285,7 +285,7 @@ static int prog_eeprom(unsigned int size) if (ret) { printf("Get i2c bus:%d addr:%d fail.\n", CONFIG_SYS_EEPROM_BUS_NUM, CONFIG_SYS_I2C_EEPROM_ADDR); - return ret; + return CMD_RET_FAILURE; } for (i = 0, p = (u8 *)pbuf.buf; i < size; ) { @@ -314,11 +314,11 @@ static int prog_eeprom(unsigned int size) if (ret) { has_been_read = -1; printf("Programming failed.\n"); - return -1; + return CMD_RET_FAILURE; } printf("Programming passed.\n"); - return 0; + return CMD_RET_SUCCESS; } /** diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index c52ba1870b0..68acd8955ae 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS imply SPL_RAM_DEVICE imply CMD_SBI imply CMD_PING - imply OF_HAS_PRIOR_STAGE source "board/xilinx/Kconfig" diff --git a/boot/Kconfig b/boot/Kconfig index 2ff6f003738..54ef7052c5c 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -1057,7 +1057,7 @@ config SYS_BOOTM_LEN hex "Maximum size of a decompresed OS image" depends on CMD_BOOTM || CMD_BOOTI || CMD_BOOTZ || \ LEGACY_IMAGE_FORMAT || SPL_LEGACY_IMAGE_FORMAT - default 0x4000000 if PPC || ARM64 + default 0x4000000 if PPC || ARM64 || RISCV default 0x1000000 if X86 || ARCH_MX6 || ARCH_MX7 default 0x800000 help diff --git a/boot/bootmeth_rauc.c b/boot/bootmeth_rauc.c index cc6180221ed..7c1a895139e 100644 --- a/boot/bootmeth_rauc.c +++ b/boot/bootmeth_rauc.c @@ -410,7 +410,7 @@ static int distro_rauc_bootmeth_bind(struct udevice *dev) struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev); plat->desc = "RAUC distro boot from MMC"; - plat->flags = BOOTMETHF_GLOBAL; + plat->flags = BOOTMETHF_ANY_PART; return 0; } diff --git a/common/spl/spl.c b/common/spl/spl.c index ed443c645a7..55ad497c86d 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -278,8 +278,8 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) } else { spl_image->entry_point = CONFIG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; - log_debug("Default load addr %x (u_boot_pos=%lx)\n", - CONFIG_TEXT_BASE, u_boot_pos); + log_debug("Default load addr %lx (u_boot_pos=%lx)\n", + spl_image->load_addr, u_boot_pos); } spl_image->os = IH_OS_U_BOOT; spl_image->name = xpl_name(xpl_next_phase()); diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 467d61d73df..e87782005f1 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -7,7 +7,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_falcon_defconfig b/configs/ae350_rv32_falcon_defconfig index 66b809d2376..f1d88f8560f 100644 --- a/configs/ae350_rv32_falcon_defconfig +++ b/configs/ae350_rv32_falcon_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_falcon_xip_defconfig b/configs/ae350_rv32_falcon_xip_defconfig index a2f8d4cd236..2355bac5019 100644 --- a/configs/ae350_rv32_falcon_xip_defconfig +++ b/configs/ae350_rv32_falcon_xip_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 098cf7686d6..6655cbd4a96 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 23927888c87..44a6b6534b8 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -10,7 +10,6 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 75eb0618454..15f3b5c378b 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -7,7 +7,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 932739e5dec..78b9fc439ac 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -6,7 +6,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y diff --git a/configs/ae350_rv64_falcon_defconfig b/configs/ae350_rv64_falcon_defconfig index c9417175ce7..81bebb1a1d4 100644 --- a/configs/ae350_rv64_falcon_defconfig +++ b/configs/ae350_rv64_falcon_defconfig @@ -8,7 +8,6 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_falcon_xip_defconfig b/configs/ae350_rv64_falcon_xip_defconfig index e072f7c2ae9..8e1b8e20052 100644 --- a/configs/ae350_rv64_falcon_xip_defconfig +++ b/configs/ae350_rv64_falcon_xip_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 83ce28077f0..7950074642e 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -8,7 +8,6 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 5ad1751686c..d5882af1de1 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -9,7 +9,6 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000000 CONFIG_SPL_TEXT_BASE=0x80000000 CONFIG_SPL_BSS_START_ADDR=0x400000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_SPL=y CONFIG_TARGET_ANDES_AE350=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 5ec2cba670b..46ce063c484 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -6,7 +6,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index f088aec8716..8e8259f291d 100644 --- a/configs/ibex-ast2700_defconfig +++ b/configs/ibex-ast2700_defconfig @@ -15,7 +15,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_TEXT_BASE=0x14bc0080 CONFIG_SPL_BSS_START_ADDR=0x14bd7800 CONFIG_SPL_BSS_MAX_SIZE=0x800 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x83000000 CONFIG_SPL_SIZE_LIMIT=0x16000 CONFIG_SPL=y diff --git a/configs/k230_canmv_defconfig b/configs/k230_canmv_defconfig index a43412f0290..8781c12d3fd 100644 --- a/configs/k230_canmv_defconfig +++ b/configs/k230_canmv_defconfig @@ -4,6 +4,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80400000 CONFIG_DEFAULT_DEVICE_TREE="k230-canmv" +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0xc000000 CONFIG_TARGET_K230_CANMV=y CONFIG_ARCH_RV64I=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 6937aa224a1..9f933592c9d 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -5,6 +5,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-icicle-kit" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SYS_MEM_TOP_HIDE=0x400000 # CONFIG_DEBUG_UART is not set @@ -13,6 +14,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 @@ -20,6 +22,7 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_PROMPT="RISC-V # " CONFIG_OF_UPSTREAM=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 70393de5736..f1f3930564b 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -5,7 +5,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000 CONFIG_DEFAULT_DEVICE_TREE="cv1800b-milkv-duo" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_IDENT_STRING="milkv_duo" CONFIG_TARGET_MILKV_DUO=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index bf39a1da723..e22585a705a 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_FIT=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 2a876aefecd..c588d01a676 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_MONITOR_LEN=786432 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_RISCV_SMODE=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 36f8b457586..d1c43575c2a 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -6,7 +6,6 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_BSS_START_ADDR=0x84000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index a9ff831be91..cb91dfd9432 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -4,7 +4,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 8384fe78a31..2ef67d40269 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -4,7 +4,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_TARGET_QEMU_VIRT=y CONFIG_ARCH_RV64I=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 34e14b8f8df..04dec72ceac 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -5,7 +5,6 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64" CONFIG_SPL_BSS_START_ADDR=0x84000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_TARGET_QEMU_VIRT=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 01963a4e54e..f341e3e0735 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -11,7 +11,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe70 CONFIG_SPL_BSS_START_ADDR=0x85000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index acbea7fe1bb..0a736f2ba95 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -12,7 +12,6 @@ CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe60 CONFIG_SPL_BSS_START_ADDR=0x85000000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/configs/sipeed_licheerv_nano_defconfig b/configs/sipeed_licheerv_nano_defconfig index fc7f82e878a..9aa3ede10c5 100644 --- a/configs/sipeed_licheerv_nano_defconfig +++ b/configs/sipeed_licheerv_nano_defconfig @@ -5,7 +5,6 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000 CONFIG_DEFAULT_DEVICE_TREE="sg2002-licheerv-nano-b" -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_IDENT_STRING="licheerv_nano" CONFIG_TARGET_LICHEERV_NANO=y diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index 9fcdfb4a8fe..bb9e7f7d903 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -5,6 +5,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_SF_DEFAULT_BUS=3 CONFIG_TARGET_SIPEED_MAIX=y diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig index 11d78688780..aadadbcab3f 100644 --- a/configs/sipeed_maix_smode_defconfig +++ b/configs/sipeed_maix_smode_defconfig @@ -6,6 +6,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x803fffff CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0xfff000 CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_SF_DEFAULT_BUS=3 CONFIG_TARGET_SIPEED_MAIX=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 3e34e4a87f8..544140c03f7 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -18,7 +18,6 @@ CONFIG_SPL_STACK=0x8180000 CONFIG_SPL_TEXT_BASE=0x8000000 CONFIG_SPL_BSS_START_ADDR=0x8040000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index 2763cbb428a..48cd8991591 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -10,7 +10,6 @@ CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a" CONFIG_SPL_STACK=0xffe0170000 CONFIG_SPL_BSS_START_ADDR=0xffe0160000 CONFIG_SPL_BSS_MAX_SIZE=0x10000 -CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL=y CONFIG_TARGET_TH1520_LPI4A=y diff --git a/configs/voyager_spl_defconfig b/configs/voyager_spl_defconfig new file mode 100644 index 00000000000..f7390405dac --- /dev/null +++ b/configs/voyager_spl_defconfig @@ -0,0 +1,65 @@ +CONFIG_RISCV=y +CONFIG_TEXT_BASE=0x401800000 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x410000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="qilai-voyager" +CONFIG_SPL_BSS_START_ADDR=0x400400000 +CONFIG_SYS_LOAD_ADDR=0x400100000 +CONFIG_SPL=y +CONFIG_TARGET_ANDES_VOYAGER=y +CONFIG_NR_CPUS=4 +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +# CONFIG_AVAILABLE_HARTS is not set +CONFIG_SYS_MONITOR_BASE=0x88000000 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x410000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_CONSOLE_RECORD=y +CONFIG_CONSOLE_RECORD_OUT_SIZE_F=0x2000 +CONFIG_SYS_PBSIZE=1050 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_SPL_CYCLIC is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_WDT=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_BOOTP_PREFER_SERVERIP=y +CONFIG_CMD_CACHE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_MMC=y +CONFIG_FTSDC010=y +CONFIG_FTSDC010_SDIO=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 +CONFIG_SYS_CFI_FLASH_STATUS_POLL=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FTMAC100=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_ATCSPI200_SPI=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +CONFIG_WDT_ATCWDT200=y +# CONFIG_BINMAN_FDT is not set diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 92f7aa04ec0..e3341179a68 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -40,5 +41,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index b61ec90d096..c95b4497395 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -44,5 +45,6 @@ CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig index c4d458370b6..a3cc1a5669e 100644 --- a/configs/xilinx_mbv64_defconfig +++ b/configs/xilinx_mbv64_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -41,5 +42,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig index 2d7227c9e33..3d49670c60c 100644 --- a/configs/xilinx_mbv64_smode_defconfig +++ b/configs/xilinx_mbv64_smode_defconfig @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64" CONFIG_SPL_STACK=0x80200000 CONFIG_SPL_BSS_START_ADDR=0x84000000 CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_SYS_LOAD_ADDR=0x80200000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL=y @@ -45,5 +46,6 @@ CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y # CONFIG_BINMAN_FDT is not set +CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb" CONFIG_PANIC_HANG=y CONFIG_SPL_GZIP=y diff --git a/doc/board/andestech/index.rst b/doc/board/andestech/index.rst index cacc5791a91..5ef93308b49 100644 --- a/doc/board/andestech/index.rst +++ b/doc/board/andestech/index.rst @@ -8,3 +8,4 @@ Andes Tech adp-ag101p ae350 + voyager diff --git a/doc/board/andestech/voyager.rst b/doc/board/andestech/voyager.rst new file mode 100644 index 00000000000..63553216d60 --- /dev/null +++ b/doc/board/andestech/voyager.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Voyager +======= + +Qilai RISC-V SoC +---------------- +The QiLai SoC chip is Andes' first RISC-V SoC. It includes high performance +quad-core Andes AX45MP cluster and one NX27V vector processor. + +The Voyager development platform is based on Qilai and capable of running Linux. + +Mainline support +---------------- + +The support for following drivers are already enabled: + +1. UART driver +2. MMC driver +3. SPI driver + +Building +~~~~~~~~ + +How to build U-Boot SPL +~~~~~~~~~~~~~~~~~~~~~~~ +Before building U-Boot SPL, OpenSBI must be build first. +OpenSBI can be cloned and build for Voyager as below: + +1. Get the RISC-V toolchain. +2. Setup cross compilation environment variable. + +.. code-block:: none + + git clone https://github.com/riscv-software-src/opensbi.git + cd opensbi + make PLATFORM=generic + +Copy OpenSBI FW_DYNAMIC image (build/platform/generic/firmware/fw_dynamic.bin) +into U-Boot root directory, then + +.. code-block:: console + + export CROSS_COMPILE=riscv64-linux-gnu- + cd <U-Boot-dir> + cp fw_dynamic.bin . + make voyager_spl_defconfig + make + +Booting +~~~~~~~ + +Currently, we rely on vendor ROM code to initialize the DDR +and load the u-boot image, then boot from it. + +Sample boot log from Voyager board +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code-block:: none + + U-Boot SPL 2025.10-rc1-00130-ga28bcbba4778-dirty (Aug 06 2025 - 17:46:10 +0800) + Trying to boot from RAM + + U-Boot 2025.10-rc1-00130-ga28bcbba4778-dirty (Aug 06 2025 - 17:46:10 +0800) + + CPU: riscv + Model: andestech,ax45 + DRAM: 16 GiB + Core: 25 devices, 14 uclasses, devicetree: board + MMC: mmc@30c00000: 0 + Loading Environment from SPIFlash... SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB + *** Warning - bad CRC, using default environment + + In: serial@30300000 + Out: serial@30300000 + Err: serial@30300000 + Net: No ethernet found. + Hit any key to stop autoboot: 0 + No ethernet found. + No ethernet found. + RISC-V # diff --git a/drivers/button/button-qcom-pmic.c b/drivers/button/button-qcom-pmic.c index 85addfe32a2..b823490d6d5 100644 --- a/drivers/button/button-qcom-pmic.c +++ b/drivers/button/button-qcom-pmic.c @@ -195,8 +195,9 @@ static int button_qcom_pmic_bind(struct udevice *parent) continue; } + label = ofnode_get_name(node); ret = device_bind_driver_to_node(parent, "qcom_pwrkey", - ofnode_get_name(node), + label, node, &dev); if (ret) { printf("Failed to bind %s! %d\n", label, ret); diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 4d9f004ebad..f9531c1627c 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -28,6 +28,13 @@ config IMX_MU_MBOX Enable support for i.MX Messaging Unit for communication with other processors on the SoC using mailbox interface +config MPFS_MBOX + bool "Enable MPFS system controller support" + depends on DM_MAILBOX && ARCH_RV64I + help + Enable support for the mailboxes that provide a communication + channel with the system controller integrated on PolarFire SoC. + config SANDBOX_MBOX bool "Enable the sandbox mailbox test driver" depends on DM_MAILBOX && SANDBOX diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index e8c745f7d79..b54fbdfff15 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_$(PHASE_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o +obj-$(CONFIG_MPFS_MBOX) += mpfs-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o diff --git a/drivers/mailbox/mpfs-mbox.c b/drivers/mailbox/mpfs-mbox.c new file mode 100644 index 00000000000..55238847ecd --- /dev/null +++ b/drivers/mailbox/mpfs-mbox.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip's PolarFire SoC (MPFS) Mailbox Driver + * + * Copyright (C) 2024 Microchip Technology Inc. All rights reserved. + * + * Author: Jamie Gibbons <jamie.gibbons@microchip.com> + * + */ + +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <dm/ofnode.h> +#include <linux/bitops.h> +#include <linux/compat.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <log.h> +#include <mailbox-uclass.h> +#include <malloc.h> +#include <mpfs-mailbox.h> + +#define SERVICES_CR_OFFSET 0x50u +#define SERVICES_SR_OFFSET 0x54u + +#define SERVICE_CR_REQ_MASK 0x1u +#define SERVICE_SR_BUSY_MASK 0x2u +#define SERVICE_SR_STATUS_SHIFT 16 +#define SERVICE_CR_COMMAND_SHIFT 16 +#define MASK_8BIT 0xFF + +struct mpfs_mbox { + struct udevice *dev; + void __iomem *ctrl_base; + void __iomem *mbox_base; + struct mbox_chan *chan; +}; + +static bool mpfs_mbox_busy(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = dev_get_priv(chan->dev); + uint16_t status; + + status = readl(mbox->ctrl_base + SERVICES_SR_OFFSET); + + return status & SERVICE_SR_BUSY_MASK; +} + +static int mpfs_mbox_send(struct mbox_chan *chan, const void *data) +{ + struct mpfs_mbox *mbox = dev_get_priv(chan->dev); + struct mpfs_mss_msg *msg = (struct mpfs_mss_msg *)data; + u32 mailbox_val, cmd_shifted, value; + u8 *byte_buf; + u8 idx, byte_idx, byte_offset; + + u32 *word_buf = (u32 *)msg->cmd_data; + + if (mpfs_mbox_busy(chan)) + return -EBUSY; + + for (idx = 0; idx < (msg->cmd_data_size / BYTES_4); idx++) + writel(word_buf[idx], mbox->mbox_base + msg->mbox_offset + idx * BYTES_4); + + if ((msg->cmd_data_size % BYTES_4) > 0) { + byte_offset = (msg->cmd_data_size / BYTES_4) * BYTES_4; + byte_buf = (u8 *)(msg->cmd_data + byte_offset); + mailbox_val = readl(mbox->mbox_base + msg->mbox_offset + idx * BYTES_4); + + for (byte_idx = 0; byte_idx < (msg->cmd_data_size % BYTES_4); byte_idx++) { + mailbox_val &= ~(MASK_8BIT << (byte_idx * 0x8u)); + mailbox_val |= (u32)byte_buf[byte_idx] << (byte_idx * 0x8u); + } + writel(mailbox_val, mbox->mbox_base + msg->mbox_offset + idx * BYTES_4); + } + + cmd_shifted = msg->cmd_opcode << SERVICE_CR_COMMAND_SHIFT; + cmd_shifted |= SERVICE_CR_REQ_MASK; + writel(cmd_shifted, mbox->ctrl_base + SERVICES_CR_OFFSET); + + do { + value = readl(mbox->ctrl_base + SERVICES_CR_OFFSET); + } while (SERVICE_CR_REQ_MASK == (value & SERVICE_CR_REQ_MASK)); + + do { + value = readl(mbox->ctrl_base + SERVICES_SR_OFFSET); + } while (SERVICE_SR_BUSY_MASK == (value & SERVICE_SR_BUSY_MASK)); + + msg->response->resp_status = (value >> SERVICE_SR_STATUS_SHIFT); + if (msg->response->resp_status) + return -EBADMSG; + + return 0; +} + +static int mpfs_mbox_recv(struct mbox_chan *chan, void *data) +{ + struct mpfs_mbox *mbox = dev_get_priv(chan->dev); + struct mpfs_mss_msg *msg = data; + struct mpfs_mss_response *response = msg->response; + u8 idx; + + if (!response->resp_msg) { + dev_err(chan->dev, "failed to assign memory for response %d\n", -ENOMEM); + return -EINVAL; + } + + if (mpfs_mbox_busy(chan)) { + dev_err(chan->dev, "mailbox is busy\n"); + response->resp_status = 0xDEAD; + return -EINVAL; + } + + for (idx = 0; idx < response->resp_size; idx++) + *((u8 *)(response->resp_msg) + idx) = readb(mbox->mbox_base + msg->resp_offset + idx); + + return 0; +} + +static const struct mbox_ops mpfs_mbox_ops = { + .send = mpfs_mbox_send, + .recv = mpfs_mbox_recv, +}; + +static int mpfs_mbox_probe(struct udevice *dev) +{ + struct mpfs_mbox *mbox; + struct resource regs; + ofnode node; + int ret; + + node = dev_ofnode(dev); + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + ret = ofnode_read_resource(node, 0, ®s); + if (ret) { + dev_err(dev, "No reg property for controller base\n"); + return ret; + }; + + mbox->ctrl_base = devm_ioremap(dev, regs.start, regs.start - regs.end); + + ret = ofnode_read_resource(node, 2, ®s); + if (ret) { + dev_err(dev, "No reg property for mailbox base\n"); + return ret; + }; + + mbox->mbox_base = devm_ioremap(dev, regs.start, regs.start - regs.end); + + mbox->dev = dev; + dev_set_priv(dev, mbox); + mbox->chan->con_priv = mbox; + + return 0; +} + +static const struct udevice_id mpfs_mbox_ids[] = { + {.compatible = "microchip,mpfs-mailbox"}, + { } +}; + +U_BOOT_DRIVER(mpfs_mbox) = { + .name = "mpfs-mbox", + .id = UCLASS_MAILBOX, + .of_match = mpfs_mbox_ids, + .probe = mpfs_mbox_probe, + .priv_auto = sizeof(struct mpfs_mbox), + .ops = &mpfs_mbox_ops, +}; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0f753b9dbb9..29b84430ff5 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -658,6 +658,15 @@ config MICROCHIP_FLEXCOM Only one function can be used at a time and is chosen at boot time according to the device tree. +config MPFS_SYSCONTROLLER + bool "Enable Microchip PolarFire SoC (MPFS) System Services support" + depends on MISC + depends on MPFS_MBOX + help + This driver adds support for the PolarFire SoC (MPFS) system controller. + + If unsure, say N. + config K3_AVS0 depends on ARCH_K3 && SPL_DM_REGULATOR bool "AVS class 0 support for K3 devices" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f7422c8e95a..dc5eb3af19c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o +obj-$(CONFIG_MPFS_SYSCONTROLLER) += mpfs_syscontroller.o obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o obj-$(CONFIG_K3_BIST) += k3_bist.o diff --git a/drivers/misc/mpfs_syscontroller.c b/drivers/misc/mpfs_syscontroller.c new file mode 100644 index 00000000000..41e80815ab5 --- /dev/null +++ b/drivers/misc/mpfs_syscontroller.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Microchip's PolarFire SoC (MPFS) System Controller Driver + * + * Copyright (C) 2024 Microchip Technology Inc. All rights reserved. + * + * Author: Jamie Gibbons <jamie.gibbons@microchip.com> + * + */ + +#include <asm/system.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <env.h> +#include <errno.h> +#include <linux/compat.h> +#include <linux/completion.h> +#include <linux/err.h> +#include <linux/mtd/mtd.h> +#include <log.h> +#include <mailbox.h> +#include <misc.h> +#include <mpfs-mailbox.h> + +/* Descriptor table */ +#define CMD_OPCODE 0x0u +#define CMD_DATA_SIZE 0U +#define CMD_DATA NULL +#define MBOX_OFFSET 0x0 +#define RESP_OFFSET 0x0 +#define RESP_BYTES 16U + +/** + * struct mpfs_syscontroller_priv - Structure representing System Controller data. + * @chan: Mailbox channel + * @c: Completion signal + */ +struct mpfs_syscontroller_priv { + struct mbox_chan chan; + struct completion c; +}; + +/** + * mpfs_syscontroller_run_service() - Run the MPFS system service + * @sys_controller: corresponding MPFS system service device + * @msg: Message to send + * + * Return: 0 if all goes good, else appropriate error message. + */ +int mpfs_syscontroller_run_service(struct mpfs_syscontroller_priv *sys_controller, struct mpfs_mss_msg *msg) +{ + int ret; + + reinit_completion(&sys_controller->c); + + /* Run the System Service Request */ + ret = mbox_send(&sys_controller->chan, msg); + if (ret < 0) + dev_warn(sys_controller->chan.dev, "MPFS sys controller service timeout\n"); + + debug("%s: Service successful %s\n", + __func__, sys_controller->chan.dev->name); + + return ret; +} +EXPORT_SYMBOL_GPL(mpfs_syscontroller_run_service); + +/** + * mpfs_syscontroller_read_sernum() - Use system service to read the device serial number + * @sys_serv_priv: system service private data + * @device_serial_number: device serial number + * + * Return: 0 if all went ok, else return appropriate error + */ +int mpfs_syscontroller_read_sernum(struct mpfs_sys_serv *sys_serv_priv, u8 *device_serial_number) +{ + unsigned long timeoutsecs = 300; + int ret; + + struct mpfs_mss_response response = { + .resp_status = 0U, + .resp_msg = (u32 *)device_serial_number, + .resp_size = RESP_BYTES}; + struct mpfs_mss_msg msg = { + .cmd_opcode = CMD_OPCODE, + .cmd_data_size = CMD_DATA_SIZE, + .response = &response, + .cmd_data = CMD_DATA, + .mbox_offset = MBOX_OFFSET, + .resp_offset = RESP_OFFSET}; + + ret = mpfs_syscontroller_run_service(sys_serv_priv->sys_controller, &msg); + if (ret) { + dev_err(sys_serv_priv->sys_controller->chan.dev, "Service failed: %d, abort\n", ret); + return ret; + } + + /* Receive the response */ + ret = mbox_recv(&sys_serv_priv->sys_controller->chan, &msg, timeoutsecs); + if (ret) { + dev_err(sys_serv_priv->sys_controller->chan.dev, "Service failed: %d, abort. Failure: %u\n", ret, msg.response->resp_status); + return ret; + } + + debug("%s: Read successful %s\n", + __func__, sys_serv_priv->sys_controller->chan.dev->name); + + return 0; +} +EXPORT_SYMBOL(mpfs_syscontroller_read_sernum); + +static int mpfs_syscontroller_probe(struct udevice *dev) +{ + struct mpfs_syscontroller_priv *sys_controller = dev_get_priv(dev); + int ret; + + ret = mbox_get_by_index(dev, 0, &sys_controller->chan); + if (ret) { + dev_err(dev, "%s: Acquiring mailbox channel failed. ret = %d\n", + __func__, ret); + return ret; + } + + init_completion(&sys_controller->c); + dev_info(dev, "Registered MPFS system controller\n"); + + return 0; +} + +static const struct udevice_id mpfs_syscontroller_ids[] = { + { .compatible = "microchip,mpfs-sys-controller" }, + { } +}; + +struct mpfs_syscontroller_priv *mpfs_syscontroller_get(struct udevice *dev) +{ + struct mpfs_syscontroller_priv *sys_controller; + + sys_controller = dev_get_priv(dev); + if (!sys_controller) { + debug("%s: MPFS system controller found but could not register as a sub device %p\n", + __func__, sys_controller); + return ERR_PTR(-EPROBE_DEFER); + } + + return sys_controller; +} +EXPORT_SYMBOL(mpfs_syscontroller_get); + +U_BOOT_DRIVER(mpfs_syscontroller) = { + .name = "mpfs_syscontroller", + .id = UCLASS_MISC, + .of_match = mpfs_syscontroller_ids, + .probe = mpfs_syscontroller_probe, + .priv_auto = sizeof(struct mpfs_syscontroller_priv), +}; diff --git a/drivers/phy/qcom/phy-qcom-snps-eusb2.c b/drivers/phy/qcom/phy-qcom-snps-eusb2.c index b2655ac007c..28502c46f67 100644 --- a/drivers/phy/qcom/phy-qcom-snps-eusb2.c +++ b/drivers/phy/qcom/phy-qcom-snps-eusb2.c @@ -331,8 +331,9 @@ static int qcom_snps_eusb2_phy_probe(struct udevice *dev) qcom_snps_eusb2->ref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(qcom_snps_eusb2->ref_clk)) { + ret = PTR_ERR(qcom_snps_eusb2->ref_clk); printf("%s: failed to get ref clk %d\n", __func__, ret); - return PTR_ERR(qcom_snps_eusb2->ref_clk); + return ret; } ret = reset_get_bulk(dev, &qcom_snps_eusb2->resets); diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index cb2496ff1fb..d4acae15d55 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -516,7 +516,9 @@ static const char *sa8775p_get_function_name(struct udevice *dev, static const char *sa8775p_get_pin_name(struct udevice *dev, unsigned int selector) { - if (selector >= 149 && selector <= 155) + if (selector > 153) + strcpy(pin_name, "unknown"); + else if (selector >= 149) snprintf(pin_name, MAX_PIN_NAME_LEN, msm_special_pins_data[selector - 149].name); else diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 3f55fc81c8e..24b42e94c7a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -72,7 +72,7 @@ static const char *sdm845_get_pin_name(struct udevice *dev, "sdc2_data", }; - if (selector >= 150 && selector <= 154) + if (selector >= 150 && selector <= 153) snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 150]); else snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index cb6c09fdd09..0eb90f82a34 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -252,6 +252,10 @@ static int msm_serial_setbrg(struct udevice *dev, int baud) priv->baud = baud; clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div); + if (!clk_rate) { + pr_err("%s: Couldn't get clock division rate\n", __func__); + return -EINVAL; + } ret = geni_serial_set_clock_rate(dev, clk_rate); if (ret < 0) { pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret); @@ -284,23 +288,19 @@ static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset, unsigned int tx_fifo_depth; unsigned int tx_fifo_width; unsigned int fifo_bits; - unsigned long timeout_us = 10000; - - baud = 115200; - - if (priv) { - baud = priv->baud; - if (!baud) - baud = 115200; - tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base); - tx_fifo_width = geni_se_get_tx_fifo_width(priv->base); - fifo_bits = tx_fifo_depth * tx_fifo_width; - /* - * Total polling iterations based on FIFO worth of bytes to be - * sent at current baud. Add a little fluff to the wait. - */ - timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; - } + unsigned long timeout_us; + + baud = priv->baud; + if (!baud) + baud = 115200; + tx_fifo_depth = geni_se_get_tx_fifo_depth(priv->base); + tx_fifo_width = geni_se_get_tx_fifo_width(priv->base); + fifo_bits = tx_fifo_depth * tx_fifo_width; + /* + * Total polling iterations based on FIFO worth of bytes to be + * sent at current baud. Add a little fluff to the wait. + */ + timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; while (timeout_us) { diff --git a/env/Kconfig b/env/Kconfig index 1df7ebd547e..03c189b7266 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -732,7 +732,7 @@ config ENV_MMC_USE_SW_PARTITION depends on ENV_IS_IN_MMC config ENV_MMC_SW_PARTITION - bool "SD/MMC environment software partition name" + string "SD/MMC environment software partition name" depends on ENV_MMC_USE_SW_PARTITION help SD/MMC software partition name used to save environment variables. diff --git a/include/configs/voyager.h b/include/configs/voyager.h new file mode 100644 index 00000000000..f6630b07ec9 --- /dev/null +++ b/include/configs/voyager.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Andes Technology Corporation + * Randolph Lin, Andes Technology Corporation <randolph@andestech.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define RISCV_MMODE_TIMERBASE 0xe6000000 +#define RISCV_MMODE_TIMER_FREQ 60000000 + +#define RISCV_SMODE_TIMER_FREQ 60000000 + +/* support JEDEC */ +#define PHYS_FLASH_1 0x8000000 /* BANK 0 */ +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CFG_SYS_FLASH_BANKS_SIZES { 0x4000000 } + +/* Enable distro boot */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x400600000\0" \ + "kernel_comp_addr_r=0x404600000\0" \ + "kernel_comp_size=0x04000000\0" \ + "pxefile_addr_r=0x408600000\0" \ + "scriptaddr=0x408700000\0" \ + "fdt_addr_r=0x408800000\0" \ + "ramdisk_addr_r=0x408900000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ diff --git a/include/mpfs-mailbox.h b/include/mpfs-mailbox.h new file mode 100644 index 00000000000..c0ff327a4ce --- /dev/null +++ b/include/mpfs-mailbox.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * + * Microchip PolarFire SoC (MPFS) + * + * Copyright (c) 2020 Microchip Corporation. All rights reserved. + * + * + */ + +#ifndef _MPFS_MAILBOX_H__ +#define _MPFS_MAILBOX_H__ + +#include <linux/types.h> + +#define BYTES_4 4 + +struct udevice; + +/** + * struct mpfs_mss_msg - PolarFire SoC message structure + * @cmd_opcode: Command opcode + * @cmd_data_size: Size of the command data. + * @response: Pointer to the response data. + * @cmd_data: Pointer to the command data. + * @mbox_offset: Mailbox offset + * @resp_offset: Response offset + * + */ +struct mpfs_mss_msg { + u8 cmd_opcode; + u16 cmd_data_size; + struct mpfs_mss_response *response; + u8 *cmd_data; + u16 mbox_offset; + u16 resp_offset; +}; + +/** + * struct mpfs_mss_response - PolarFire SoC response structure + * @resp_status: Response status + * @resp_msg: Pointer to response message. + * @resp_size: Size of the response message. + * + */ +struct mpfs_mss_response { + u32 resp_status; + u32 *resp_msg; + u16 resp_size; +}; + +struct mpfs_syscontroller_priv; + +struct mpfs_sys_serv { + struct udevice *dev; + struct mpfs_syscontroller_priv *sys_controller; + struct mpfs_mss_msg *msg; +}; + +int mpfs_syscontroller_run_service(struct mpfs_syscontroller_priv *sys_controller, struct mpfs_mss_msg *msg); +int mpfs_syscontroller_read_sernum(struct mpfs_sys_serv *sys_serv_priv, u8 *device_serial_number); +void mpfs_syscontroller_process_dtbo(struct mpfs_sys_serv *sys_serv_priv); +struct mpfs_syscontroller_priv *mpfs_syscontroller_get(struct udevice *dev); + +#endif /* __MPFS_MAILBOX_H__ */ + |