diff options
321 files changed, 7853 insertions, 1443 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 966a66ff567..8209d2b329c 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2022 ubuntu_vm: ubuntu-24.04 macos_vm: macOS-14 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20250714-25Jul2025 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -531,10 +531,11 @@ stages: TEST_PY_BD: "r2dplus" TEST_PY_ID: "--id tulip_qemu" TEST_PY_TEST_SPEC: "not sleep" - sifive_unleashed_sdcard: - TEST_PY_BD: "sifive_unleashed" - TEST_PY_ID: "--id sdcard_qemu" - TEST_PY_TEST_SPEC: "not sleep" +# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945 +# sifive_unleashed_sdcard: +# TEST_PY_BD: "sifive_unleashed" +# TEST_PY_ID: "--id sdcard_qemu" +# TEST_PY_TEST_SPEC: "not sleep" sifive_unleashed_spi-nor: TEST_PY_BD: "sifive_unleashed" TEST_PY_ID: "--id spi-nor_qemu" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2dfeda9985d..85401d3e09b 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -20,7 +20,7 @@ workflow: # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250404-29Apr2025 +image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20250714-25Jul2025 # We run some tests in different order, to catch some failures quicker. stages: @@ -519,12 +519,13 @@ r2dplus_tulip test.py: TEST_PY_ID: "--id tulip_qemu" <<: *buildman_and_testpy_dfn -sifive_unleashed_sdcard test.py: - variables: - TEST_PY_BD: "sifive_unleashed" - TEST_PY_TEST_SPEC: "not sleep" - TEST_PY_ID: "--id sdcard_qemu" - <<: *buildman_and_testpy_dfn +# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945 +#sifive_unleashed_sdcard test.py: +# variables: +# TEST_PY_BD: "sifive_unleashed" +# TEST_PY_TEST_SPEC: "not sleep" +# TEST_PY_ID: "--id sdcard_qemu" +# <<: *buildman_and_testpy_dfn sifive_unleashed_spi-nor test.py: variables: diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 17795f8f746..0dc7e190eb9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -760,7 +760,6 @@ dtb-y += \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ - imx6dl-sielaff.dtb \ imx6dl-wandboard-revd1.dtb endif @@ -918,6 +917,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-librem5-r4.dtb dtb-$(CONFIG_ARCH_IMX9) += \ + imx93-11x11-frdm.dtb \ imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \ diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index cb8ce8b6b6f..a048951fa18 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -794,7 +794,7 @@ uart11: serial@1e790500 { compatible = "ns16550a"; - reg = <0x1e790400 0x20>; + reg = <0x1e790500 0x20>; reg-shift = <2>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; clocks = <&scu ASPEED_CLK_GATE_UART11CLK>; diff --git a/arch/arm/dts/imx6dl-sielaff.dts b/arch/arm/dts/imx6dl-sielaff.dts deleted file mode 100644 index 7de8d5f2651..00000000000 --- a/arch/arm/dts/imx6dl-sielaff.dts +++ /dev/null @@ -1,533 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2022 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6dl.dtsi" -#include <dt-bindings/clock/imx6qdl-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "Sielaff i.MX6 Solo"; - compatible = "sielaff,imx6dl-board", "fsl,imx6dl"; - - chosen { - stdout-path = &uart2; - }; - - backlight: pwm-backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm3 0 50000 0>; - brightness-levels = <0 0 64 88 112 136 184 232 255>; - default-brightness-level = <4>; - enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - power-supply = <®_backlight>; - }; - - cec { - compatible = "cec-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_cec>; - cec-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; - hdmi-phandle = <&hdmi>; - }; - - enet_ref: clock-enet-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - clock-output-names = "enet-ref"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - key-0 { - gpios = <&gpio2 16 0>; - debounce-interval = <10>; - linux,code = <1>; - }; - - key-1 { - gpios = <&gpio3 27 0>; - debounce-interval = <10>; - linux,code = <2>; - }; - - key-2 { - gpios = <&gpio5 4 0>; - debounce-interval = <10>; - linux,code = <3>; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-debug { - label = "debug-led"; - gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - device_type = "memory"; - }; - - osc_eth_phy: clock-osc-eth-phy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "osc-eth-phy"; - }; - - panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight>; - power-supply = <®_3v3>; - - port { - panel_in_lvds: endpoint { - remote-endpoint = <&lvds_out>; - }; - }; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_backlight: regulator-backlight { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_backlight>; - enable-active-high; - gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; - regulator-name = "backlight"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - reg_usb_otg_vbus: regulator-usb-otg-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec { - /* - * Set PTP clock to external instead of internal reference, as the - * REF_CLK from the PHY is fed back into the i.MX6 and the GPR - * register needs to be set accordingly (see mach-imx6q.c). - */ - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&enet_ref>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-connection-type = "rmii"; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@1 { - reg = <1>; - clocks = <&osc_eth_phy>; - clock-names = "rmii-ref"; - micrel,led-mode = <1>; - reset-assert-us = <500>; - reset-deassert-us = <100>; - reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "key-out", "key-in", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio2 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "lan9500a-rst", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&hdmi { - ddc-i2c-bus = <&i2c4>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; - status = "okay"; - - touchscreen@55 { - compatible = "sitronix,st1633"; - reg = <0x55>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - interrupt-parent = <&gpio5>; - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - status = "disabled"; - }; - - touchscreen@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio5>; - irq-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - status = "disabled"; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - clock-frequency = <100000>; - status = "okay"; -}; - -&ldb { - status = "okay"; - - lvds: lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@4 { - reg = <4>; - - lvds_out: endpoint { - remote-endpoint = <&panel_in_lvds>; - }; - }; - }; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - disable-over-current; - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - usb1@1 { - compatible = "usb4b4,6570"; - reg = <1>; - clocks = <&clks IMX6QDL_CLK_CKO>; - - assigned-clocks = <&clks IMX6QDL_CLK_CKO>, - <&clks IMX6QDL_CLK_CKO2_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, - <&clks IMX6QDL_CLK_OSC>; - assigned-clock-rates = <12000000 0>; - }; -}; - -&usbotg { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - dr_mode = "host"; - over-current-active-low; - vbus-supply = <®_usb_otg_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x1b0b0 /* PMIC_IRQ */ - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x100b1 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 - >; - }; - - pinctrl_gpio_keys: gpiokeysgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b080 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b080 - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b080 - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 - >; - }; - - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_hdmi_cec: hdmicecgrp { - fsl,pins = < - MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_reg_backlight: regbacklightgrp { - fsl,pins = < - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b1 - >; - }; - - pinctrl_reg_usbotg_vbus: regusbotgvbusgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b1 - >; - }; - - pinctrl_touch: touchgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0 - >; - }; - - pinctrl_usbh1: usbh1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b1 - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b1 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x100b1 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi new file mode 100644 index 00000000000..41111b1a95a --- /dev/null +++ b/arch/arm/dts/imx93-11x11-frdm-u-boot.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "imx93-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&A55_0 { + clocks = <&clk IMX93_CLK_A55_SEL>; +}; + +&A55_1 { + clocks = <&clk IMX93_CLK_A55_SEL>; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; +}; + +&lpi2c2 { + bootph-pre-ram; +}; + +&lpi2c3 { + bootph-pre-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25} { + bootph-pre-ram; +}; + +&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} { + bootph-pre-ram; +}; + +&pinctrl_lpi2c2 { + bootph-pre-ram; +}; + +&pinctrl_lpi2c3 { + bootph-pre-ram; +}; + +&fec { + phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +ðphy1 { + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&usbotg2 { + status = "okay"; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx93-11x11-frdm.dts b/arch/arm/dts/imx93-11x11-frdm.dts new file mode 100644 index 00000000000..993567e767d --- /dev/null +++ b/arch/arm/dts/imx93-11x11-frdm.dts @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx93.dtsi" + +/ { + compatible = "fsl,imx93-11x11-frdm", "fsl,imx93"; + model = "NXP i.MX93 11X11 FRDM board"; + + aliases { + mmc0 = &usdhc1; /* EMMC */ + mmc1 = &usdhc2; /* uSD */ + rtc0 = &pcf2131; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + eee-broken-1000t; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&iomuxc { + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; +}; diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index 6deebdadf09..a9bd5a2be84 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -25,7 +25,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -69,7 +69,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -105,7 +105,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index 6822a5dac89..f743c4353b4 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -67,7 +67,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -103,7 +103,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi index bfbba28269c..65fef6e4790 100644 --- a/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am625-verdin-wifi-dev-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -67,7 +67,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -103,7 +103,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index fd340101532..9bcdf74ffe4 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -30,7 +30,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -74,7 +74,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -110,7 +110,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 877a513a241..0685bdd7e0c 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -27,7 +27,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -71,7 +71,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c3a800>; @@ -107,7 +107,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index d65e5c4d4e1..feb59edcd83 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -25,7 +25,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; @@ -72,7 +72,7 @@ content-sysfw-data = <&combined_tifs_cfg_hs>; content-sysfw-inner-cert = <&sysfw_inner_cert_hs>; content-dm-data = <&combined_dm_cfg_hs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi index 13fac18d7aa..b1591faaf0a 100644 --- a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi @@ -25,7 +25,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; @@ -74,7 +74,7 @@ content-sysfw-data = <&combined_tifs_cfg_hs>; content-sysfw-inner-cert = <&sysfw_inner_cert_hs>; content-dm-data = <&combined_dm_cfg_hs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c4a800>; diff --git a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi index 2a0023fb7c3..0e810e7f492 100644 --- a/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi +++ b/arch/arm/dts/k3-am67a-beagley-ai-u-boot.dtsi @@ -75,7 +75,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; @@ -125,7 +125,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; diff --git a/arch/arm/dts/k3-j7200-binman.dtsi b/arch/arm/dts/k3-j7200-binman.dtsi index b74bd1657f9..b4e0ce8bfcf 100644 --- a/arch/arm/dts/k3-j7200-binman.dtsi +++ b/arch/arm/dts/k3-j7200-binman.dtsi @@ -24,7 +24,7 @@ content-sysfw-data = <&combined_tifs_cfg_sr1>; content-sysfw-inner-cert = <&sysfw_inner_cert_sr1>; content-dm-data = <&combined_dm_cfg_sr1>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -67,7 +67,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -112,7 +112,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs_sr1>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs_sr1>; content-dm-data = <&combined_dm_cfg_fs_sr1>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -155,7 +155,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x7f000>; load-dm-data = <0x41c80000>; @@ -192,7 +192,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-j721s2-binman.dtsi b/arch/arm/dts/k3-j721s2-binman.dtsi index 4f524e58ceb..f79b3e543ae 100644 --- a/arch/arm/dts/k3-j721s2-binman.dtsi +++ b/arch/arm/dts/k3-j721s2-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x41c80000>; @@ -66,7 +66,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x41c80000>; @@ -103,7 +103,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/k3-j722s-binman.dtsi b/arch/arm/dts/k3-j722s-binman.dtsi index 57e966ea666..278b7bfac7f 100644 --- a/arch/arm/dts/k3-j722s-binman.dtsi +++ b/arch/arm/dts/k3-j722s-binman.dtsi @@ -23,7 +23,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; @@ -73,7 +73,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x43c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x67000>; load-dm-data = <0x43c7a800>; diff --git a/arch/arm/dts/k3-j784s4-binman.dtsi b/arch/arm/dts/k3-j784s4-binman.dtsi index a7ce1ee2b03..34b2cc1e681 100644 --- a/arch/arm/dts/k3-j784s4-binman.dtsi +++ b/arch/arm/dts/k3-j784s4-binman.dtsi @@ -27,7 +27,7 @@ content-sysfw-data = <&combined_tifs_cfg>; content-sysfw-inner-cert = <&sysfw_inner_cert>; content-dm-data = <&combined_dm_cfg>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x66800>; load-dm-data = <0x41c80000>; @@ -74,7 +74,7 @@ content-sysfw-data = <&combined_tifs_cfg_fs>; content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; content-dm-data = <&combined_dm_cfg_fs>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; load-sysfw = <0x40000>; load-sysfw-data = <0x66800>; load-dm-data = <0x41c80000>; @@ -114,7 +114,7 @@ combined; dm-data; content-sbl = <&u_boot_spl_unsigned>; - load = <0x41c00000>; + load = <CONFIG_SPL_TEXT_BASE>; content-sysfw = <&ti_fs_gp>; load-sysfw = <0x40000>; content-sysfw-data = <&combined_tifs_cfg_gp>; diff --git a/arch/arm/dts/zynqmp-binman-som.dts b/arch/arm/dts/zynqmp-binman-som.dts index a70123feead..469b94bbde6 100644 --- a/arch/arm/dts/zynqmp-binman-som.dts +++ b/arch/arm/dts/zynqmp-binman-som.dts @@ -20,7 +20,6 @@ binman: binman { multiple-images; -#ifdef CONFIG_SPL fit-dtb.blob { filename = "fit-dtb.blob"; pad-byte = <0>; @@ -109,6 +108,7 @@ }; }; +#ifdef CONFIG_SPL /* Generation in a static way */ itb { filename = U_BOOT_ITB_FILENAME; diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index 0dd2d62b9ef..a8e3f7354c7 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -118,6 +118,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate); void ddrphy_init_read_msg_block(enum fw_type type); void get_trained_CDD(unsigned int fsp); +u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr); ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr); diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 95bd1823531..4e0e194690b 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -66,6 +66,14 @@ config TARGET_IMX93_11X11_EVK imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND +config TARGET_IMX93_FRDM + bool "imx93_frdm" + select OF_BOARD_FIXUP + select IMX93 + select IMX9_LPDDR4X + imply BOOTSTD_FULL + imply BOOTSTD_BOOTCOMMAND + config TARGET_IMX93_VAR_SOM bool "imx93_var_som" select IMX93 @@ -90,6 +98,7 @@ endchoice source "board/freescale/imx91_evk/Kconfig" source "board/freescale/imx93_evk/Kconfig" +source "board/freescale/imx93_frdm/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 0f11511bda0..53f152ccd9c 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -17,6 +17,7 @@ #include <dm/pinctrl.h> #include <mmc.h> #include <remoteproc.h> +#include <k3_bist.h> #include "../sysfw-loader.h" #include "../common.h" @@ -122,6 +123,48 @@ static void setup_navss_nb(void) writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); } +/* Execute and check results of BIST executed on MCU1_x and MCU4_O */ +static void run_bist_j784s4(struct udevice *dev) +{ + struct bist_ops *ops; + struct ti_sci_handle *handle; + int ret; + + ops = (struct bist_ops *)device_get_ops(dev); + handle = get_ti_sci_handle(); + + /* get status of HW POST PBIST on MCU1_x */ + if (ops->run_pbist_post()) + panic("HW POST LBIST on MCU1_x failed\n"); + + /* trigger PBIST tests on MCU4_0 */ + ret = prepare_pbist(handle); + ret |= ops->run_pbist_neg(); + ret |= deprepare_pbist(handle); + + ret |= prepare_pbist(handle); + ret |= ops->run_pbist(); + ret |= deprepare_pbist(handle); + + ret |= prepare_pbist(handle); + ret |= ops->run_pbist_rom(); + ret |= deprepare_pbist(handle); + + if (ret) + panic("PBIST on MCU4_0 failed: %d\n", ret); + + /* get status of HW POST PBIST on MCU1_x */ + if (ops->run_lbist_post()) + panic("HW POST LBIST on MCU1_x failed\n"); + + /* trigger LBIST tests on MCU1_x */ + ret = prepare_lbist(handle); + ret |= ops->run_lbist(); + ret |= deprepare_lbist(handle); + if (ret) + panic("LBIST on MCU4_0 failed: %d\n", ret); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -266,6 +309,15 @@ void board_init_f(ulong dummy) printf("AVS init failed: %d\n", ret); } + if (!IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_BIST)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(k3_bist), + &dev); + if (ret) + panic("Failed to get BIST device: %d\n", ret); + run_bist_j784s4(dev); + } + if (IS_ENABLED(CONFIG_CPU_V7R)) setup_navss_nb(); diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c index 01ba53cf68d..1bea5a60513 100644 --- a/board/Marvell/octeontx2/board.c +++ b/board/Marvell/octeontx2/board.c @@ -93,11 +93,6 @@ int board_early_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - int timer_init(void) { return 0; diff --git a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c index f9412071737..fc0057746e0 100644 --- a/board/amlogic/odroid-go-ultra/odroid-go-ultra.c +++ b/board/amlogic/odroid-go-ultra/odroid-go-ultra.c @@ -13,8 +13,3 @@ int mmc_get_env_dev(void) return 1; return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 3ad77f51949..16d0e679c3e 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -77,11 +77,6 @@ static struct mm_region corstone1000_mem_map[] = { struct mm_region *mem_map = corstone1000_mem_map; -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = PHYS_SDRAM_1_SIZE; diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index 75bc6b0631f..12bb6defab2 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -70,11 +70,6 @@ int misc_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/beacon/imx8mm/imx8mm_beacon.c b/board/beacon/imx8mm/imx8mm_beacon.c index 204235a3f8e..6459a99cb9d 100644 --- a/board/beacon/imx8mm/imx8mm_beacon.c +++ b/board/beacon/imx8mm/imx8mm_beacon.c @@ -6,8 +6,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/beacon/imx8mn/imx8mn_beacon.c b/board/beacon/imx8mn/imx8mn_beacon.c index 204235a3f8e..6459a99cb9d 100644 --- a/board/beacon/imx8mn/imx8mn_beacon.c +++ b/board/beacon/imx8mn/imx8mn_beacon.c @@ -6,8 +6,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index 99eb8972cf3..500fcc58ed8 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -45,11 +45,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 78635810585..9bc9ca30e95 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/beagle/beagley-ai/beagley-ai.c b/board/beagle/beagley-ai/beagley-ai.c index 9786f628f6d..26fa54e27bb 100644 --- a/board/beagle/beagley-ai/beagley-ai.c +++ b/board/beagle/beagley-ai/beagley-ai.c @@ -21,11 +21,6 @@ void set_dfu_alt_info(char *interface, char *devstr) } #endif -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c index a6ced92565f..1ab6224011c 100644 --- a/board/broadcom/bcmbca/board.c +++ b/board/broadcom/bcmbca/board.c @@ -5,11 +5,6 @@ #include <fdtdec.h> -int board_init(void) -{ - return 0; -} - int dram_init(void) { if (fdtdec_setup_mem_size_base() != 0) diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 45cc62936ce..47a01227a35 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -31,11 +31,6 @@ int board_late_init(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { } diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c index e655f610c84..e7313d8c431 100644 --- a/board/broadcom/bcmstb/bcmstb.c +++ b/board/broadcom/bcmstb/bcmstb.c @@ -32,11 +32,6 @@ union reg_value_union { const phys_addr_t *address; }; -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { } diff --git a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c index c9989687399..c4a85c4aa44 100644 --- a/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c +++ b/board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c @@ -6,11 +6,6 @@ #include <asm/arch/sys_proto.h> #include <env.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (is_usb_boot()) { diff --git a/board/canaan/k230_canmv/board.c b/board/canaan/k230_canmv/board.c index a705ee8f67b..7d012df214f 100644 --- a/board/canaan/k230_canmv/board.c +++ b/board/canaan/k230_canmv/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2025, Junhui Liu <junhui.liu@pigmoral.tech> */ -int board_init(void) -{ - return 0; -} diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index b1a805c1360..4c477ad551c 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -72,11 +72,6 @@ static struct mm_region thunderx_mem_map[] = { struct mm_region *mem_map = thunderx_mem_map; -int board_init(void) -{ - return 0; -} - int timer_init(void) { return 0; diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 339702e8392..e271d060efa 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -16,11 +16,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index 138acd36ad2..d6f0a917023 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -46,11 +46,6 @@ enum env_location env_get_location(enum env_operation op, int prio) return prio ? ENVL_UNKNOWN : ENVL_MMC; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 4275436b128..3a890c5920c 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -153,11 +153,6 @@ void dh_add_item_number_and_serial_to_env(struct eeprom_id_page *eip) } } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { u8 eeprom_buffer[DH_EEPROM_ID_PAGE_MAX_SIZE] = { 0 }; diff --git a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c index 219efdddcb5..04b3bc8caf5 100644 --- a/board/emcraft/imx8mp_navqp/imx8mp_navqp.c +++ b/board/emcraft/imx8mp_navqp/imx8mp_navqp.c @@ -4,7 +4,3 @@ * Copyright 2024 Gilles Talis <gilles.talis@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 31f5a775137..38f0ec5f2fb 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -102,11 +102,6 @@ static struct mm_region qemu_arm64_mem_map[] = { struct mm_region *mem_map = qemu_arm64_mem_map; #endif -int board_init(void) -{ - return 0; -} - int board_late_init(void) { /* diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 40d295dbf06..58de4a05296 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -170,9 +170,9 @@ int misc_init_r(void) * Detect the presence of the platform bus node, and * create a virtual memory mapping for it. */ - for (ret = uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev); + for (uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev); dev; - ret = uclass_find_next_device(&dev)) { + uclass_find_next_device(&dev)) { if (device_is_compatible(dev, "qemu,platform")) { struct simple_bus_plat *plat = dev_get_uclass_plat(dev); diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 70190ebe8fc..97c8211c100 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -28,11 +28,6 @@ int is_flash_available(void) } #endif -int board_init(void) -{ - return 0; -} - int board_late_init(void) { /* start usb so that usb keyboard can be used as input device */ diff --git a/board/emulation/qemu-sbsa/qemu-sbsa.c b/board/emulation/qemu-sbsa/qemu-sbsa.c index cf1d5acf5cb..30b3a41a9e9 100644 --- a/board/emulation/qemu-sbsa/qemu-sbsa.c +++ b/board/emulation/qemu-sbsa/qemu-sbsa.c @@ -93,11 +93,6 @@ int board_late_init(void) return 0; } -int board_init(void) -{ - return 0; -} - /** * dtb_dt_qemu - Return the address of the QEMU provided FDT. * diff --git a/board/emulation/qemu-xtensa/qemu-xtensa.c b/board/emulation/qemu-xtensa/qemu-xtensa.c index 0ca83341c25..2e2a5a26d94 100644 --- a/board/emulation/qemu-xtensa/qemu-xtensa.c +++ b/board/emulation/qemu-xtensa/qemu-xtensa.c @@ -13,11 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - unsigned long get_board_sys_clk(void) { return gd->cpu_clk ? gd->cpu_clk : 40000000; diff --git a/board/engicam/stm32mp1/stm32mp1.c b/board/engicam/stm32mp1/stm32mp1.c index 56557d56429..82278a48ae8 100644 --- a/board/engicam/stm32mp1/stm32mp1.c +++ b/board/engicam/stm32mp1/stm32mp1.c @@ -34,12 +34,6 @@ int checkboard(void) return 0; } -/* board dependent setup after realloc */ -int board_init(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 2a9ba7df2bb..732c0fa561d 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -28,12 +28,6 @@ struct efi_capsule_update_info update_info = { }; #endif /* EFI_HAVE_CAPSULE_SUPPORT */ - -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #if CONFIG_IS_ENABLED(ENV_IS_IN_MMC) diff --git a/board/freescale/imx91_evk/imx91_evk.c b/board/freescale/imx91_evk/imx91_evk.c index 83bfca2f22d..cbd0a72bf4b 100644 --- a/board/freescale/imx91_evk/imx91_evk.c +++ b/board/freescale/imx91_evk/imx91_evk.c @@ -9,11 +9,6 @@ #include <netdev.h> #include <asm/arch/sys_proto.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS index 34ba278fcdf..eb6e669bd17 100644 --- a/board/freescale/imx93_evk/MAINTAINERS +++ b/board/freescale/imx93_evk/MAINTAINERS @@ -1,4 +1,4 @@ -i.MX93 MEK BOARD +i.MX93 EVK BOARD M: Peng Fan <peng.fan@nxp.com> S: Maintained F: board/freescale/imx93_evk/ diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index d84d56be5e1..d62f94dc418 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -13,11 +13,8 @@ #include <asm/arch/sys_proto.h> #include <asm/arch-imx9/imx93_pins.h> #include <asm/arch/clock.h> -#include <power/pmic.h> #include <dm/device.h> #include <dm/uclass.h> -#include <usb.h> -#include <dwc3-uboot.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/imx93_frdm/Kconfig b/board/freescale/imx93_frdm/Kconfig new file mode 100644 index 00000000000..5f5ac7f8f04 --- /dev/null +++ b/board/freescale/imx93_frdm/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX93_FRDM + +config SYS_BOARD + default "imx93_frdm" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx93_frdm" + +endif diff --git a/board/freescale/imx93_frdm/MAINTAINERS b/board/freescale/imx93_frdm/MAINTAINERS new file mode 100644 index 00000000000..59595bb2118 --- /dev/null +++ b/board/freescale/imx93_frdm/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX93 FRDM BOARD +M: Fabio Estevam <festevam@gmail.com> +S: Maintained +F: board/freescale/imx93_frdm/ +F: include/configs/imx93_frdm.h +F: configs/imx93_frdm_defconfig diff --git a/board/freescale/imx93_frdm/Makefile b/board/freescale/imx93_frdm/Makefile new file mode 100644 index 00000000000..9612b1fa55b --- /dev/null +++ b/board/freescale/imx93_frdm/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2025 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx93_frdm.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +endif diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c new file mode 100644 index 00000000000..c74fd85712f --- /dev/null +++ b/board/freescale/imx93_frdm/imx93_frdm.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include <env.h> +#include <efi_loader.h> +#include <init.h> +#include <asm/global_data.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch-imx9/imx93_pins.h> +#include <asm/arch/clock.h> +#include <dm/device.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) +#define IMX_BOOT_IMAGE_GUID \ + EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \ + 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21) + +struct efi_fw_image fw_images[] = { + { + .image_type_id = IMX_BOOT_IMAGE_GUID, + .fw_name = u"IMX93-11X11-FRDM-RAW", + .image_index = 1, + }, +}; + +struct efi_capsule_update_info update_info = { + .dfu_string = "mmc 0=flash-bin raw 0 0x2000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), + .images = fw_images, +}; +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) || IS_ENABLED(CONFIG_ENV_IS_IN_NOWHERE)) + board_late_mmc_env_init(); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + env_set("board_name", "11X11_FRDM"); + env_set("board_rev", "iMX93"); + } + + return 0; +} diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env new file mode 100644 index 00000000000..528a953c8df --- /dev/null +++ b/board/freescale/imx93_frdm/imx93_frdm.env @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_targets=mmc0 mmc1 +boot_fit=no +bootm_size=0x10000000 +cntr_addr=0x98000000 +cntr_file=os_cntr_signed.bin +console=ttyLP0,115200 +fdt_addr_r=0x83000000 +fdt_addr=0x83000000 +fdtfile=CONFIG_DEFAULT_FDT_FILE +image=Image +mmcdev=1 +mmcpart=1 +mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console} root=${mmcroot} +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +boot_os=booti ${loadaddr} - ${fdt_addr_r} + +bsp_bootcmd= + echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; + run mmcargs; + run loadimage; + run loadfdt; + run boot_os; + +scriptaddr=0x83500000 diff --git a/board/freescale/imx93_frdm/lpddr4_timing.h b/board/freescale/imx93_frdm/lpddr4_timing.h new file mode 100644 index 00000000000..192bc9e1519 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4_timing.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 Marek Vasut <marex@denx.de> + */ + +#ifndef __LPDDR4_TIMING_H__ +#define __LPDDR4_TIMING_H__ + +extern struct dram_timing_info dram_timing_1GB; +extern struct dram_timing_info dram_timing_2GB; + +#endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c new file mode 100644 index 00000000000..17549206ee4 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4x_1gb_timing.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.3.0_7.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24A0321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2E3233}, + {0x4e30010C, 0x0005C18B}, + {0x4e300124, 0x1C790000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x00FE00FE}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x00FE2213}, + {0x4e300308, 0x0A380E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x124F2100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816E4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x007B007B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 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{0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_1GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c new file mode 100644 index 00000000000..cd129e12959 --- /dev/null +++ b/board/freescale/imx93_frdm/lpddr4x_2gb_timing.c @@ -0,0 +1,1995 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 NXP + * + * Code generated with DDR Tool v3.4.0_8.3-4e2b550a. + * DDR PHY FW2022.01 + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000ff}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000512}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24AB321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2EE233}, + {0x4e30010C, 0x0005E18B}, + {0x4e300124, 0x1C760000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x015B015B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x015B2213}, + {0x4e300308, 0x0A3C0E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x12552100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816B4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x00AA00AA}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00061000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E62FA48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00340034}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x32}, + {0x0b, 0x46}, + {0x0c, 0x11}, + {0x0e, 0x11}, + {0x16, 0x04}, + }, + 1, + }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x4}, + {0x100a1, 0x5}, + {0x100a2, 0x6}, + {0x100a3, 0x7}, + {0x100a4, 0x0}, + {0x100a5, 0x1}, + {0x100a6, 0x2}, + {0x100a7, 0x3}, + {0x110a0, 0x3}, + {0x110a1, 0x2}, + {0x110a2, 0x0}, + {0x110a3, 0x1}, + {0x110a4, 0x7}, + {0x110a5, 0x6}, + {0x110a6, 0x4}, + {0x110a7, 0x5}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0xe00}, + {0x10149, 0xe00}, + {0x11049, 0xe00}, + {0x11149, 0xe00}, + {0x110049, 0xe00}, + {0x110149, 0xe00}, + {0x111049, 0xe00}, + {0x111149, 0xe00}, + {0x210049, 0xe00}, + {0x210149, 0xe00}, + {0x211049, 0xe00}, + {0x211149, 0xe00}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x10c}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x10c}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x10c}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x321b}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x321b}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1100}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1100}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x3209}, + {0x54034, 0x4600}, + {0x54035, 0x11}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x3209}, + {0x5403a, 0x4600}, + {0x5403b, 0x11}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x15}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x32}, + {0x5401b, 0x1146}, + {0x5401c, 0x1108}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x32}, + {0x54021, 0x1146}, + {0x54022, 0x1108}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x3236}, + {0x54034, 0x4600}, + {0x54035, 0x811}, + {0x54036, 0x11}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x3236}, + {0x5403a, 0x4600}, + {0x5403b, 0x811}, + {0x5403c, 0x11}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/freescale/imx93_frdm/spl.c b/board/freescale/imx93_frdm/spl.c new file mode 100644 index 00000000000..006c752d071 --- /dev/null +++ b/board/freescale/imx93_frdm/spl.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "lpddr4_timing.h" + +#include <init.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/trdc.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/global_data.h> +#include <asm/sections.h> +#include <dm/device.h> +#include <dm/device-internal.h> +#include <dm/uclass.h> +#include <dm/uclass-internal.h> +#include <linux/delay.h> +#include <power/pca9450.h> +#include <power/pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SRC_DDRC_SW_CTRL (0x44461020) +#define SRC_DDRPHY_SINGLE_RESET_SW_CTRL (0x44461424) + +static struct _drams { + u8 mr8; + struct dram_timing_info *pdram_timing; + char *name; +} frdm_drams[2] = { + {0x10, &dram_timing_1GB, "1GB DRAM" }, + {0x18, &dram_timing_2GB, "2GB DRAM" }, +}; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + int i; + int ret; + + for (i = 0; i < ARRAY_SIZE(frdm_drams); i++) { + struct dram_timing_info *ptiming = frdm_drams[i].pdram_timing; + + printf("DDR: %uMTS\n", ptiming->fsp_msg[0].drate); + ret = ddr_init(ptiming); + if (ret == 0) { + if (lpddr4_mr_read(1, 8) == frdm_drams[i].mr8) { + printf("found DRAM %s matched\n", frdm_drams[i].name); + break; + } + + /* Power down and Power up DDR Mixer */ + + /* Clear PwrOkIn via DDRMIX register */ + setbits_32(SRC_DDRPHY_SINGLE_RESET_SW_CTRL, BIT(0)); + /* Power off the DDRMIX */ + setbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + + udelay(50); + + /* Power up the DDRMIX */ + clrbits_32(SRC_DDRC_SW_CTRL, BIT(31)); + setbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + clrbits_32(SRC_DDRC_SW_CTRL, BIT(0)); + udelay(10); + } + } +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* Enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8V for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85V for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9V for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* Set standby voltage to 0.65V */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_early_init_f(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init Sentinel API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_clk(get_cpu_speed_grade_hz()); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx93_qsb/imx93_qsb.c b/board/freescale/imx93_qsb/imx93_qsb.c index 388d99106db..503a8667245 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.c +++ b/board/freescale/imx93_qsb/imx93_qsb.c @@ -9,11 +9,6 @@ #include <netdev.h> #include <asm/arch/sys_proto.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/board/freescale/imx95_evk/imx95_evk.c b/board/freescale/imx95_evk/imx95_evk.c index d5f5e310b6b..fe0111be508 100644 --- a/board/freescale/imx95_evk/imx95_evk.c +++ b/board/freescale/imx95_evk/imx95_evk.c @@ -15,11 +15,6 @@ int board_early_init_f(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) diff --git a/board/freescale/mx6memcal/mx6memcal.c b/board/freescale/mx6memcal/mx6memcal.c index 17095c34e92..a58ab93f27d 100644 --- a/board/freescale/mx6memcal/mx6memcal.c +++ b/board/freescale/mx6memcal/mx6memcal.c @@ -13,11 +13,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int checkboard(void) { puts("Board: mx6memcal\n"); diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 29165266630..5e60ab9d7b7 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -372,11 +372,6 @@ int misc_init_r(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MMC static int init_dwmmc(void) diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 8dcc2ea54f6..2e387038395 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -116,11 +116,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size); } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { if (!fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-n802x-som") || diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 0baf5c63f18..8a9502037fb 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -51,11 +51,6 @@ int board_early_init_f(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_eth_init(struct bd_info *bis) { return pci_eth_init(bis); diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index 9d24c8cd412..405f393aade 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -10,8 +10,3 @@ #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7981/mt7981_rfb.c b/board/mediatek/mt7981/mt7981_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7981/mt7981_rfb.c +++ b/board/mediatek/mt7981/mt7981_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7986/mt7986_rfb.c b/board/mediatek/mt7986/mt7986_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7986/mt7986_rfb.c +++ b/board/mediatek/mt7986/mt7986_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7987/mt7987_rfb.c b/board/mediatek/mt7987/mt7987_rfb.c index fcb844deed8..c5cb33f06f7 100644 --- a/board/mediatek/mt7987/mt7987_rfb.c +++ b/board/mediatek/mt7987/mt7987_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt7988/mt7988_rfb.c b/board/mediatek/mt7988/mt7988_rfb.c index 846c715ca05..0ca87a88aed 100644 --- a/board/mediatek/mt7988/mt7988_rfb.c +++ b/board/mediatek/mt7988/mt7988_rfb.c @@ -4,7 +4,3 @@ * Author: Sam Shih <sam.shih@mediatek.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/mediatek/mt8365_evk/mt8365_evk.c b/board/mediatek/mt8365_evk/mt8365_evk.c index 723a50fec00..41a6febf03d 100644 --- a/board/mediatek/mt8365_evk/mt8365_evk.c +++ b/board/mediatek/mt8365_evk/mt8365_evk.c @@ -6,11 +6,6 @@ #include <asm/armv8/mmu.h> -int board_init(void) -{ - return 0; -} - static struct mm_region mt8365_evk_mem_map[] = { { /* DDR */ diff --git a/board/mediatek/mt8516/mt8516_pumpkin.c b/board/mediatek/mt8516/mt8516_pumpkin.c index 930bfec3483..c383d194357 100644 --- a/board/mediatek/mt8516/mt8516_pumpkin.c +++ b/board/mediatek/mt8516/mt8516_pumpkin.c @@ -6,11 +6,6 @@ #include <dm.h> #include <net.h> -int board_init(void) -{ - return 0; -} - int board_late_init(void) { struct udevice *dev; diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index 699e5ca54a7..16dbaa96e8c 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -22,11 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_size_t get_effective_memsize(void) { /* Use bank0 only */ diff --git a/board/nuvoton/poleg_evb/poleg_evb.c b/board/nuvoton/poleg_evb/poleg_evb.c index 2faa34954eb..0a3c052a019 100644 --- a/board/nuvoton/poleg_evb/poleg_evb.c +++ b/board/nuvoton/poleg_evb/poleg_evb.c @@ -14,11 +14,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int dram_init(void) { struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; diff --git a/board/openpiton/riscv64/openpiton-riscv64.c b/board/openpiton/riscv64/openpiton-riscv64.c index 4c957e88992..62007f2f81d 100644 --- a/board/openpiton/riscv64/openpiton-riscv64.c +++ b/board/openpiton/riscv64/openpiton-riscv64.c @@ -25,8 +25,3 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[i] = boot_devices[i]; } #endif - -int board_init(void) -{ - return 0; -} diff --git a/board/phytec/phycore_am62ax/phycore-am62ax.c b/board/phytec/phycore_am62ax/phycore-am62ax.c index 14b8959c07a..3e1c4102cc1 100644 --- a/board/phytec/phycore_am62ax/phycore-am62ax.c +++ b/board/phytec/phycore_am62ax/phycore-am62ax.c @@ -11,11 +11,6 @@ #include "../common/am6_som_detection.h" -int board_init(void) -{ - return 0; -} - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index b199fdaa59b..51da864aa80 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - static u8 phytec_get_am62_ddr_size_default(void) { int ret; diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c index f14c87f5c72..33c39376ceb 100644 --- a/board/phytec/phycore_am64x/phycore-am64x.c +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -19,11 +19,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - static u8 phytec_get_am64_ddr_size_default(void) { int ret; diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index 402d967ab7d..b3f09154328 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -1,65 +1,15 @@ -#include <env/phytec/rauc.env> - -bootcmd= - mmc dev ${mmcdev}; - if mmc rescan; then - if test ${doraucboot} = 1; then - run raucinit; - fi; - if run loadimage; then - run mmcboot; - else - run netboot; - fi; - fi; -console=ttymxc2,115200 +console=ttymxc2,CONFIG_BAUDRATE emmc_dev=2 -fdt_addr_r=0x48000000 fdtfile=CONFIG_DEFAULT_FDT_FILE -image=Image +fdt_addr_r=0x40480000 +fdt_overlay_addr_r=0x404a0000 +kernel_addr_r=0x40a00000 +kernel_comp_addr_r=0x43a00000 +kernel_comp_size=0x1e00000 +pxefile_addr_r=0x45800000 +ramdisk_addr_r=0x45802000 +scriptaddr=0x47600000 +script_offset_f=0x0 +script_size_f=0x2000 ip_dyn=yes -loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} -loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} -mmcargs= - setenv bootargs console=${console} - root=/dev/mmcblk${mmcdev}p${mmcroot} ${raucargs} rootwait rw -mmcautodetect=yes -mmcboot= - echo Booting from mmc ...; - run mmcargs; - if run loadfdt; then - if test ${dofitboot} = 1; then - booti ${loadaddr} - ${fdt_addr_r} - else - echo WARN: Cannot load the DT; - fi; - fi; -mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX -mmcpart=1 -mmcroot=2 -netargs= - setenv bootargs console=${console} root=/dev/nfs ip=dhcp - nfsroot=${serverip}:${nfsroot},v3,tcp -netboot= - echo Booting from net ...; - if test ${ip_dyn} = yes; then - setenv get_cmd dhcp; - else - setenv get_cmd tftp; - fi; - ${get_cmd} ${loadaddr} ${image}; - run netargs; - if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then - booti ${loadaddr} - ${fdt_addr_r}; - else - echo WARN: Cannot load the DT; - fi; nfsroot=/srv/nfs -update_bootimg= - mmc dev ${mmcdev}; - if dhcp ${loadaddr} ${update_filepath}/${update_filename}; then - setexpr fw_sz ${filesize} / 0x200; - mmc write ${loadaddr} ${update_offset} ${fw_sz}; - fi; -update_filename=flash.bin -update_offset=0x42 diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index a55795e0603..8d2caf8bbef 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -6,10 +6,7 @@ * Copyright (C) 2024 PHYTEC Messtechnik GmbH */ -#include <asm/arch-imx9/ccm_regs.h> #include <asm/arch/sys_proto.h> -#include <asm/arch-imx9/imx93_pins.h> -#include <asm/arch/clock.h> #include <asm/global_data.h> #include <asm/mach-imx/boot_mode.h> #include <env.h> diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c index a4d2aaac320..7b5d38d438f 100644 --- a/board/phytec/phycore_imx93/spl.c +++ b/board/phytec/phycore_imx93/spl.c @@ -14,9 +14,7 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/ele_api.h> #include <asm/sections.h> -#include <hang.h> #include <init.h> -#include <log.h> #include <power/pmic.h> #include <power/pca9450.h> #include <spl.h> @@ -25,11 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* - * Will be part of drivers/power/regulator/pca9450.c - * when pca9451a support is added. - */ -#define PCA9450_REG_PWRCTRL_TOFF_DEB BIT(5) #define EEPROM_ADDR 0x50 /* diff --git a/board/phytium/durian/durian.c b/board/phytium/durian/durian.c index 01e210fcdd1..9fc63febdac 100644 --- a/board/phytium/durian/durian.c +++ b/board/phytium/durian/durian.c @@ -37,11 +37,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/phytium/pe2201/pe2201.c b/board/phytium/pe2201/pe2201.c index fbbf6789b50..6824454cdf4 100644 --- a/board/phytium/pe2201/pe2201.c +++ b/board/phytium/pe2201/pe2201.c @@ -50,11 +50,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 0ea335e7486..3984ddc4594 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -32,11 +32,6 @@ int dram_init(void) return 0; } -int board_init(void) -{ - return 0; -} - void reset_cpu(void) { struct arm_smccc_res res; diff --git a/board/renesas/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c index 78b8cb4ac34..6ea903f2d62 100644 --- a/board/renesas/r2dplus/r2dplus.c +++ b/board/renesas/r2dplus/r2dplus.c @@ -17,11 +17,6 @@ int checkboard(void) return 0; } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { return 0; diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c index 0f6d6e7f514..509c5dbb156 100644 --- a/board/renesas/rzg2l/rzg2l.c +++ b/board/renesas/rzg2l/rzg2l.c @@ -51,8 +51,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) { return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c index 4e034b9bd3b..a6c264d1248 100644 --- a/board/samsung/e850-96/e850-96.c +++ b/board/samsung/e850-96/e850-96.c @@ -92,11 +92,6 @@ static void setup_serial(void) env_set("serial#", serial_str); } -int board_init(void) -{ - return 0; -} - int board_late_init(void) { int err; diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 43f4edc39e9..0dc23a27dfc 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -104,11 +104,6 @@ int dram_init(void) return 0; } -int board_init(void) -{ - return 0; -} - int ft_board_setup(void *fdt, struct bd_info *bd) { /* Create an arbitrary reservation to allow testing OF_BOARD_SETUP.*/ diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index 161210c60a9..c75f4a0d084 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -367,11 +367,6 @@ static void m2_connector_setup(void) m2_overlay_prepare(); } -int board_init(void) -{ - return 0; -} - int dram_init(void) { struct udevice *sysinfo; diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index 08077a1f9e1..f76e1ae75a1 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -43,8 +43,3 @@ int board_early_init_f(void) { return sram_init(); } - -int board_init(void) -{ - return 0; -} diff --git a/board/sophgo/licheerv_nano/board.c b/board/sophgo/licheerv_nano/board.c index eaa47be1739..e6099d35dbf 100644 --- a/board/sophgo/licheerv_nano/board.c +++ b/board/sophgo/licheerv_nano/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/spacemit/bananapi-f3/board.c b/board/spacemit/bananapi-f3/board.c index 2631cdd49e0..ea416621544 100644 --- a/board/spacemit/bananapi-f3/board.c +++ b/board/spacemit/bananapi-f3/board.c @@ -3,7 +3,3 @@ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com> */ -int board_init(void) -{ - return 0; -} diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index 8ad593cccdd..f5174720434 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -32,11 +32,6 @@ void enable_caches(void) } #endif -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_USB_DWC3 int g_dnl_board_usb_cable_connected(void) { diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 22d751b44d3..4b0defda1ec 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -45,11 +45,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index db59ebb838e..88c825334a8 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -39,11 +39,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 134d207d95d..7aab7f71d0c 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -39,11 +39,6 @@ int dram_init_banksize(void) return 0; } -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 35ef9ff9e28..d00f55379c5 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -34,8 +34,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 35ef9ff9e28..d00f55379c5 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -34,8 +34,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c index be0884bdeb4..645685a64f1 100644 --- a/board/st/stm32h747-disco/stm32h747-disco.c +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -35,8 +35,3 @@ int dram_init_banksize(void) return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 75aa4d139fb..31c85c6816e 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -44,8 +44,3 @@ int board_late_init(void) { return 0; } - -int board_init(void) -{ - return 0; -} diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 3351544c5b3..a445f983255 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -16,11 +16,6 @@ #include "../common/fdt_ops.h" -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 379d1a5b316..2e85363cf5f 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 3051a0a27a1..d7b07a0d34d 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -74,11 +74,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 35fd30dbceb..8e89b3b15df 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -54,11 +54,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 6658794a137..5c45a33eac9 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -45,11 +45,6 @@ enum { DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index b1ed29af001..1527eaf1e16 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -66,11 +66,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 8c8f8e2a265..5d3b84607d8 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -28,11 +28,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c index f085ecfd37e..d2b94913c12 100644 --- a/board/ti/j722s/evm.c +++ b/board/ti/j722s/evm.c @@ -15,11 +15,6 @@ #include <asm/arch/k3-ddr.h> #include "../common/fdt_ops.h" -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index c8d01bf0ca8..6335676081a 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -41,11 +41,6 @@ struct efi_capsule_update_info update_info = { .images = fw_images, }; -int board_init(void) -{ - return 0; -} - #if defined(CONFIG_XPL_BUILD) void spl_perform_fixups(struct spl_image_info *spl_image) { diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index a89c5bf2c19..869656eee7a 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -183,6 +183,7 @@ const struct toradex_som toradex_modules[] = { { AQUILA_AM69O_16GB_IT, "Aquila AM69 Octa 16GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, { AQUILA_AM69O_8GB_WB_IT, "Aquila AM69 Octa 8GB WB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, { AQUILA_AM69O_8GB_IT, "Aquila AM69 Octa 8GB IT", TARGET_IS_ENABLED(AQUILA_AM69_A72) }, + { VERDIN_IMX8MMQ_WB_IT_64G, "Verdin iMX8M Mini Quad 2GB WB IT", TARGET_IS_ENABLED(VERDIN_IMX8MM) }, }; struct pid4list { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index db612811c5c..d002b969bdf 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -141,6 +141,7 @@ enum { AQUILA_AM69O_16GB_IT, AQUILA_AM69O_8GB_WB_IT, AQUILA_AM69O_8GB_IT, /* 215 */ + VERDIN_IMX8MMQ_WB_IT_64G, }; enum { diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.c b/board/toradex/smarc-imx8mp/smarc-imx8mp.c index bbe371516cc..915b413b15e 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.c +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.c @@ -10,11 +10,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int board_phys_sdram_size(phys_size_t *size) { if (!size) diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 100cfb90eb1..069aa6c7909 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -22,11 +22,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c index a7124ecf823..7c631f380ff 100644 --- a/board/toradex/verdin-am62p/verdin-am62p.c +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -55,11 +55,6 @@ static void read_hw_cfg(void) printf("0x%02x\n", hw_cfg); } -int board_init(void) -{ - return 0; -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index 04c918a079f..b4402415845 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -85,7 +85,8 @@ static void select_dt_from_module_version(void) is_wifi = (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMDL_WIFI_BT_IT) || (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WIFI_BT_IT_NO_CAN) || - (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET); + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_4G_WIFI_BT_ET) || + (tdx_hw_tag.prodid == VERDIN_IMX8MMQ_WB_IT_64G); } switch (get_pcb_revision()) { diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c index 80c84e64241..14aa93c527b 100644 --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c @@ -44,11 +44,6 @@ struct var_imx8_eeprom_info { u8 partnumber2[5]; /* Part number 2 */ } __packed; -int board_init(void) -{ - return 0; -} - int board_mmc_get_env_dev(int devno) { return devno; diff --git a/board/xen/xenguest_arm64/xenguest_arm64.c b/board/xen/xenguest_arm64/xenguest_arm64.c index 216a022aa15..174752f6b07 100644 --- a/board/xen/xenguest_arm64/xenguest_arm64.c +++ b/board/xen/xenguest_arm64/xenguest_arm64.c @@ -33,11 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define GUEST_VIRTIO_MMIO_BASE 0x2000000 #define GUEST_VIRTIO_MMIO_SIZE 0x100000 -int board_init(void) -{ - return 0; -} - /* * Use fdt provided by Xen: according to * https://www.kernel.org/doc/Documentation/arm64/booting.txt diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c index c478f7e04a0..ed3fe16af7b 100644 --- a/board/xilinx/mbv/board.c +++ b/board/xilinx/mbv/board.c @@ -7,11 +7,6 @@ #include <spl.h> -int board_init(void) -{ - return 0; -} - #ifdef CONFIG_SPL u32 spl_boot_device(void) { diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c index 0c62b0013c4..c34a7c5ecae 100644 --- a/board/xilinx/zynqmp_r5/board.c +++ b/board/xilinx/zynqmp_r5/board.c @@ -7,11 +7,6 @@ #include <init.h> #include <linux/errno.h> -int board_init(void) -{ - return 0; -} - int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 3791ebfcb42..3f8dc2c3c4e 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -213,10 +213,12 @@ void bootdev_list(bool probe) device_active(dev) ? '+' : ' ', ret ? simple_itoa(-ret) : "OK", dev_get_uclass_name(dev_get_parent(dev)), dev->name); - if (probe) + if (probe) { ret = uclass_next_device_check(&dev); - else - ret = uclass_find_next_device(&dev); + } else { + uclass_find_next_device(&dev); + ret = 0; + } } printf("--- ------ ------ -------- ------------------\n"); printf("(%d bootdev%s)\n", i, i != 1 ? "s" : ""); diff --git a/cmd/fpga.c b/cmd/fpga.c index 9dc7b63db5d..d51c380d7b3 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -28,7 +28,7 @@ static long do_fpga_get_device(char *arg) if (dev == FPGA_INVALID_DEVICE && arg) dev = simple_strtol(arg, NULL, 16); - debug("%s: device = %ld\n", __func__, dev); + log_debug("device = %ld\n", dev); return dev; } @@ -40,26 +40,26 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size, size_t local_data_size; long local_fpga_data; - debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs); + log_debug("%d, %d\n", argc, cmdtp->maxargs); if (argc != cmdtp->maxargs) { - debug("fpga: incorrect parameters passed\n"); - return CMD_RET_USAGE; + log_err("Incorrect number of parameters passed\n"); + return CMD_RET_FAILURE; } *dev = do_fpga_get_device(argv[0]); local_fpga_data = simple_strtol(argv[1], NULL, 16); if (!local_fpga_data) { - debug("fpga: zero fpga_data address\n"); - return CMD_RET_USAGE; + log_err("Zero fpga_data address\n"); + return CMD_RET_FAILURE; } *fpga_data = local_fpga_data; local_data_size = hextoul(argv[2], NULL); if (!local_data_size) { - debug("fpga: zero size\n"); - return CMD_RET_USAGE; + log_err("Zero size\n"); + return CMD_RET_FAILURE; } *data_size = local_data_size; @@ -70,51 +70,52 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size, static int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { + struct fpga_secure_info fpga_sec_info; + const int pos_userkey = 5; size_t data_size = 0; long fpga_data, dev; int ret; - struct fpga_secure_info fpga_sec_info; memset(&fpga_sec_info, 0, sizeof(fpga_sec_info)); - if (argc < 5) { - debug("fpga: incorrect parameters passed\n"); - return CMD_RET_USAGE; + if (argc < pos_userkey) { + log_err("Too few parameters passed\n"); + return CMD_RET_FAILURE; } - if (argc == 6) + if (argc == pos_userkey + 1) fpga_sec_info.userkey_addr = (u8 *)(uintptr_t) - simple_strtoull(argv[5], + simple_strtoull(argv[pos_userkey], NULL, 16); else /* * If 6th parameter is not passed then do_fpga_check_params * will get 5 instead of expected 6 which means that function - * return CMD_RET_USAGE. Increase number of params +1 to pass + * return CMD_RET_FAILURE. Increase number of params +1 to pass * this. */ argc++; + ret = do_fpga_check_params(&dev, &fpga_data, &data_size, + cmdtp, argc, argv); + if (ret) + return ret; + fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL); fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL); if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH && fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) { - debug("fpga: Use <fpga load> for NonSecure bitstream\n"); - return CMD_RET_USAGE; + log_err("Use <fpga load> for NonSecure bitstream\n"); + return CMD_RET_FAILURE; } if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY && !fpga_sec_info.userkey_addr) { - debug("fpga: User key not provided\n"); - return CMD_RET_USAGE; + log_err("User key not provided\n"); + return CMD_RET_FAILURE; } - ret = do_fpga_check_params(&dev, &fpga_data, &data_size, - cmdtp, argc, argv); - if (ret) - return ret; - return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info); } #endif @@ -245,23 +246,23 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, ulong dev = do_fpga_get_device(argv[0]); char *datastr = env_get("fpgadata"); - debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr); + log_debug("argc %x, dev %lx, datastr %s\n", argc, dev, datastr); if (dev == FPGA_INVALID_DEVICE) { - debug("fpga: Invalid fpga device\n"); - return CMD_RET_USAGE; + log_err("Invalid fpga device\n"); + return CMD_RET_FAILURE; } if (argc == 0 && !datastr) { - debug("fpga: No datastr passed\n"); - return CMD_RET_USAGE; + log_err("No datastr passed\n"); + return CMD_RET_FAILURE; } if (argc == 2) { datastr = argv[1]; - debug("fpga: Full command with two args\n"); + log_debug("Full command with two args\n"); } else if (argc == 1 && !datastr) { - debug("fpga: Dev is setup - fpgadata passed\n"); + log_debug("Dev is setup - fpgadata passed\n"); datastr = argv[0]; } @@ -269,20 +270,20 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, if (fit_parse_subimage(datastr, (ulong)fpga_data, &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; - debug("* fpga: subimage '%s' from FIT image ", - fit_uname); - debug("at 0x%08lx\n", fit_addr); + log_debug("* fpga: subimage '%s' from FIT image ", + fit_uname); + log_debug("at 0x%08lx\n", fit_addr); } else #endif { fpga_data = (void *)hextoul(datastr, NULL); - debug("* fpga: cmdline image address = 0x%08lx\n", - (ulong)fpga_data); + log_debug("* fpga: cmdline image address = 0x%08lx\n", + (ulong)fpga_data); } - debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data); + log_debug("fpga_data = 0x%lx\n", (ulong)fpga_data); if (!fpga_data) { - puts("Zero fpga_data address\n"); - return CMD_RET_USAGE; + log_err("Zero fpga_data address\n"); + return CMD_RET_FAILURE; } switch (genimg_get_format(fpga_data)) { @@ -301,15 +302,15 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, data = image_get_load(hdr); - if (gunzip((void *)data, ~0UL, (void *)image_buf, + if (gunzip((void *)data, ~0U, (void *)image_buf, &image_size) != 0) { - puts("GUNZIP: error\n"); + log_err("Gunzip error\n"); return CMD_RET_FAILURE; } data_size = image_size; #else - puts("Gunzip image is not supported\n"); - return 1; + log_err("Gunzip image is not supported\n"); + return CMD_RET_FAILURE; #endif } else { data = (ulong)image_get_data(hdr); @@ -327,12 +328,12 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, const void *fit_data; if (!fit_uname) { - puts("No FIT subimage unit name\n"); + log_err("No FIT subimage unit name\n"); return CMD_RET_FAILURE; } if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) { - puts("Bad FIT image format\n"); + log_err("Bad FIT image format\n"); return CMD_RET_FAILURE; } @@ -348,7 +349,7 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc, } #endif default: - puts("** Unknown image type\n"); + log_err("Unknown image type\n"); return CMD_RET_FAILURE; } } @@ -390,16 +391,16 @@ static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, fpga_cmd = find_cmd_tbl(argv[1], fpga_commands, ARRAY_SIZE(fpga_commands)); if (!fpga_cmd) { - debug("fpga: non existing command\n"); - return CMD_RET_USAGE; + log_err("Non existing command\n"); + return CMD_RET_FAILURE; } argc -= 2; argv += 2; if (argc > fpga_cmd->maxargs) { - debug("fpga: more parameters passed\n"); - return CMD_RET_USAGE; + log_err("Too many parameters passed\n"); + return CMD_RET_FAILURE; } ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv); diff --git a/cmd/regulator.c b/cmd/regulator.c index da298090bb7..8d743c8d269 100644 --- a/cmd/regulator.c +++ b/cmd/regulator.c @@ -96,11 +96,11 @@ static int do_list(struct cmd_tbl *cmdtp, int flag, int argc, LIMIT_OFNAME, LIMIT_OFNAME, "regulator-name", "Parent"); - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret) - continue; + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) + return ret; + for (; dev; uclass_find_next_device(&dev)) { uc_pdata = dev_get_uclass_plat(dev); printf("| %-*.*s| %-*.*s| %s\n", LIMIT_DEVNAME, LIMIT_DEVNAME, dev->name, diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index b3565efb225..79d021f81dc 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -31,7 +31,7 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, ulong container_offset) { struct boot_img_t *images; - ulong offset, overhead, size; + ulong offset, size; void *buf, *trampoline; if (image_index > container->num_images) { @@ -54,7 +54,7 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, debug("%s: container: %p offset: %lu size: %lu\n", __func__, container, offset, size); - buf = map_sysmem(images[image_index].dst - overhead, images[image_index].size); + buf = map_sysmem(images[image_index].dst, images[image_index].size); if (IS_ENABLED(CONFIG_SPL_IMX_CONTAINER_USE_TRAMPOLINE) && arch_check_dst_in_secure(buf, size)) { trampoline = arch_get_container_trampoline(); diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 52df6e0ca3f..64886986c42 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -27,6 +27,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index 21a381e8113..c9592d7b6c4 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am62x_a53_usbdfu.config b/configs/am62x_a53_usbdfu.config index 373b1d0ed64..04f360668b6 100644 --- a/configs/am62x_a53_usbdfu.config +++ b/configs/am62x_a53_usbdfu.config @@ -1,3 +1,4 @@ +# CONFIG_BOARD_INIT is not set CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 099a4828a7f..ce503000e4c 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index ba6396c9dfc..18ffc991b25 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index fd2b28a1c6e..ae261f2fa01 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index fdf5d7803bb..491e0dd102e 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x180000 diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index 438ec8a1c56..bf44c19befe 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -39,6 +39,7 @@ CONFIG_BOOTSTD_BOOTCOMMAND=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index 7d3eb6f8c93..6733dcfdd85 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x58000 diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 63ba94ff90e..37b5c6a43e7 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -29,6 +29,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x58000 diff --git a/configs/am67a_beagley_ai_a53_defconfig b/configs/am67a_beagley_ai_a53_defconfig index 013529d26da..4693f3bc9b3 100644 --- a/configs/am67a_beagley_ai_a53_defconfig +++ b/configs/am67a_beagley_ai_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb; run set_led_state_fail_load" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 diff --git a/configs/am67a_beagley_ai_r5_defconfig b/configs/am67a_beagley_ai_r5_defconfig index b0a95da1086..00c6ba6e2b5 100644 --- a/configs/am67a_beagley_ai_r5_defconfig +++ b/configs/am67a_beagley_ai_r5_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x6ce00 diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 34c4e9a3f74..8572ad204d8 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -25,6 +25,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 diff --git a/configs/bananapi-f3_defconfig b/configs/bananapi-f3_defconfig index a8b4cc675ab..a726ce84775 100644 --- a/configs/bananapi-f3_defconfig +++ b/configs/bananapi-f3_defconfig @@ -14,6 +14,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_ENV_OVERWRITE=y CONFIG_PINCTRL=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 040ef695fec..ca09351384d 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -20,6 +20,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};" CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=536 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 1eafadf2535..185d6e24bd4 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -21,6 +21,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="fdt addr ${fdtcontroladdr};fdt move ${fdtcontroladdr} ${fdtsaveaddr};fdt addr ${fdtsaveaddr};" CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=536 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot>" diff --git a/configs/bcm947622_defconfig b/configs/bcm947622_defconfig index 566f9f2920f..1481e03f980 100644 --- a/configs/bcm947622_defconfig +++ b/configs/bcm947622_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM47622" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm94908_defconfig b/configs/bcm94908_defconfig index a19b112f86a..90eaacd8878 100644 --- a/configs/bcm94908_defconfig +++ b/configs/bcm94908_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM4908" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig index 46bbfb67980..859bb78c248 100644 --- a/configs/bcm94912_defconfig +++ b/configs/bcm94912_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM4912" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963138_defconfig b/configs/bcm963138_defconfig index aa582b79bc8..f59e4e245ea 100644 --- a/configs/bcm963138_defconfig +++ b/configs/bcm963138_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63138" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig index 239a8a10fa5..5deea27ee34 100644 --- a/configs/bcm963146_defconfig +++ b/configs/bcm963146_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63146" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963148_defconfig b/configs/bcm963148_defconfig index 48bc620e181..8b8a46c321c 100644 --- a/configs/bcm963148_defconfig +++ b/configs/bcm963148_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63148" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig index a6cfea6cd79..df78621c1e7 100644 --- a/configs/bcm963158_defconfig +++ b/configs/bcm963158_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63158" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig index 95c9c8e396e..2015b71f36e 100644 --- a/configs/bcm963178_defconfig +++ b/configs/bcm963178_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM63178" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig index bfd309c25f5..0bd4ccb377a 100644 --- a/configs/bcm96756_defconfig +++ b/configs/bcm96756_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6756" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96813_defconfig b/configs/bcm96813_defconfig index 7f165231648..a3909c67474 100644 --- a/configs/bcm96813_defconfig +++ b/configs/bcm96813_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6813" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96846_defconfig b/configs/bcm96846_defconfig index 8bc6ac18be9..d26e4db2a96 100644 --- a/configs/bcm96846_defconfig +++ b/configs/bcm96846_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6846" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_NAND=y diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig index 342be0a0e17..de113ef4746 100644 --- a/configs/bcm96855_defconfig +++ b/configs/bcm96855_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6855" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig index 5f22186966f..710440f9c79 100644 --- a/configs/bcm96856_defconfig +++ b/configs/bcm96856_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6856" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig index 682cb14e898..62e767fc830 100644 --- a/configs/bcm96858_defconfig +++ b/configs/bcm96858_defconfig @@ -15,6 +15,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6858" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig index ad65187c30c..9689c6a9a15 100644 --- a/configs/bcm96878_defconfig +++ b/configs/bcm96878_defconfig @@ -16,6 +16,7 @@ CONFIG_IDENT_STRING=" Broadcom BCM6878" CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_NAND=y CONFIG_CMD_CACHE=y diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig index c53c6fffbc4..21e7c684a47 100644 --- a/configs/bcmns_defconfig +++ b/configs/bcmns_defconfig @@ -20,6 +20,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl" CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="northstar> " CONFIG_CMD_BOOTZ=y diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig index 80163580f85..527a679b785 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_LOGLEVEL=7 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="corstone1000# " # CONFIG_CMD_CONSOLE is not set diff --git a/configs/durian_defconfig b/configs/durian_defconfig index 336c7a5269e..448332d4667 100644 --- a/configs/durian_defconfig +++ b/configs/durian_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="durian#" # CONFIG_CMD_LZMADEC is not set # CONFIG_CMD_UNZIP is not set diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index e334efd4d5f..b4066d87460 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -21,6 +21,7 @@ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y CONFIG_BOOTSTD_FULL=y CONFIG_DEFAULT_FDT_FILE="exynos850-e850-96.dtb" # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_ABOOTIMG=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 59c2101110e..476bfc3af10 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_PBSIZE=532 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y diff --git a/configs/imx6dl_sielaff_defconfig b/configs/imx6dl_sielaff_defconfig index 6673e1e6915..a4271ea071a 100644 --- a/configs/imx6dl_sielaff_defconfig +++ b/configs/imx6dl_sielaff_defconfig @@ -14,7 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6S=y CONFIG_TARGET_MX6S_SIELAFF=y CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sielaff" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-sielaff" CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SF_DEFAULT_BUS=1 @@ -61,6 +61,7 @@ CONFIG_CMD_UBI=y CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y @@ -114,5 +115,6 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x17ffffc0 CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config index 07390037c46..4634a0972f0 100644 --- a/configs/imx8m_data_modul.config +++ b/configs/imx8m_data_modul.config @@ -11,6 +11,7 @@ CONFIG_ARCH_IMX8M=y CONFIG_ARCH_MISC_INIT=y CONFIG_ARM=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_BOOTCOMMAND="run dmo_update_env ; load ${devtype} ${devnum}:${devpart} ${loadaddr} boot/fitImage && source ${loadaddr}:bootscr-boot.cmd ; reset" CONFIG_BOOTCOUNT_ALTBOOTCMD="run bootcmd" diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 7c8a2060b1a..7369c0a05ac 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -9,7 +9,6 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phygate-tauri-l" -CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x56000000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y @@ -20,16 +19,15 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x47602000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;" -CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_DEFAULT_FDT_FILE="imx8mm-phygate-tauri-l" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y @@ -44,7 +42,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -60,15 +57,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 06cc4bb7dde..7c520f6e4b5 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_HAVE_INIT_STACK=y CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 5e60c9d3a08..0cefcadff6a 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -33,6 +33,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_PAD_TO=0x0 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index b71cdbb2e4e..c757a2180c0 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -40,6 +40,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index bb483653db2..ddaea0c68bd 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -40,6 +40,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index f163871bfaa..4a49355195a 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -39,6 +39,7 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index c83f6a99a7e..dafef23650a 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -31,7 +31,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index 58550c6c332..ee12de0deea 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -32,7 +32,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2pro.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 875ddcaaaa4..b9f3b9b8999 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -36,7 +36,7 @@ CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-var-som-symphony.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2067 CONFIG_BOARD_TYPES=y -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx8mp_dhsom.config b/configs/imx8mp_dhsom.config index 226c58c0277..406529346c5 100644 --- a/configs/imx8mp_dhsom.config +++ b/configs/imx8mp_dhsom.config @@ -3,6 +3,7 @@ CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y # CONFIG_INPUT is not set CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset" CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 46039fd0c03..0ad1acb94b6 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -36,6 +36,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig index 552665d27ca..216831b0ede 100644 --- a/configs/imx8mp_navqp_defconfig +++ b/configs/imx8mp_navqp_defconfig @@ -31,6 +31,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mp-navqp.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig index b92754074a0..809885c0873 100644 --- a/configs/imx91_11x11_evk_defconfig +++ b/configs/imx91_11x11_evk_defconfig @@ -35,7 +35,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig index 8a5222b6540..e7fa6b2f730 100644 --- a/configs/imx91_11x11_evk_inline_ecc_defconfig +++ b/configs/imx91_11x11_evk_inline_ecc_defconfig @@ -35,7 +35,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx91-11x11-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 99c349a9295..be250abb0b1 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -32,6 +32,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig index 0966f166ec6..3cb9ee3daf3 100644 --- a/configs/imx93_9x9_qsb_inline_ecc_defconfig +++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig @@ -32,6 +32,7 @@ CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx93-9x9-qsb.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig new file mode 100644 index 00000000000..4f837ca9282 --- /dev/null +++ b/configs/imx93_frdm_defconfig @@ -0,0 +1,124 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-frdm" +CONFIG_TARGET_IMX93_FRDM=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x20519dd0 +CONFIG_SPL_TEXT_BASE=0x2049A000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x2051a000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +CONFIG_EFI_VAR_BUF_SIZE=139264 +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_CPU=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SPAWN=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_ADC=y +CONFIG_ADC_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_CLK_IMX93=y +CONFIG_DFU_MMC=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +CONFIG_SHA384=y +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_UTHREAD=y diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig index 814570ee2ae..73818a82627 100644 --- a/configs/imx95_19x19_evk_defconfig +++ b/configs/imx95_19x19_evk_defconfig @@ -38,8 +38,8 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx95-19x19-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 -CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index a88e697d9fa..077992b5fab 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -46,6 +46,7 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run start_watchdog; run distro_bootcmd" CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 3987bab5679..36274804881 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -39,6 +39,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index dca757fe057..d97d331fdbd 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index 00ed3d91242..e7f708a60c5 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -37,6 +37,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run set_led_state_start_load; run envboot; bootflow scan -lb;run set_led_state_fail_load" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j721e_beagleboneai64_r5_defconfig b/configs/j721e_beagleboneai64_r5_defconfig index 99e96c90ef9..50a9d95d7bf 100644 --- a/configs/j721e_beagleboneai64_r5_defconfig +++ b/configs/j721e_beagleboneai64_r5_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xf59f0 diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 02e3ac343d9..42e1dd21d0b 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -36,6 +36,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index 3a54a4c97d1..ceb2e273b54 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xf59f0 diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index ac584f50b94..8ea9decf15b 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -36,6 +36,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index f4c0862d0a8..aaf8fd32879 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xc0000 diff --git a/configs/j722s_evm_a53_defconfig b/configs/j722s_evm_a53_defconfig index 19f4a3b0e92..83ac99c922a 100644 --- a/configs/j722s_evm_a53_defconfig +++ b/configs/j722s_evm_a53_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index f4562bd0d68..8e2741c8d42 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x6ce00 diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 6b1306cf7af..67aa18a16da 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 CONFIG_BOOTSTD_FULL=y CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" CONFIG_LOGLEVEL=7 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0xc0000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index 9e4170028f4..cc340a2fe76 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 CONFIG_USE_BOOTCOMMAND=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0xc0000 diff --git a/configs/k230_canmv_defconfig b/configs/k230_canmv_defconfig index 47fa1add2a9..a43412f0290 100644 --- a/configs/k230_canmv_defconfig +++ b/configs/k230_canmv_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k230-canmv" CONFIG_SYS_LOAD_ADDR=0xc000000 CONFIG_TARGET_K230_CANMV=y CONFIG_ARCH_RV64I=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="K230# " CONFIG_CMD_USB=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index cdf8e406483..4f08f2c572c 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -41,6 +41,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=276 CONFIG_BOARD_TYPES=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 6ddd21bd295..e97534ecc0a 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -47,6 +47,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_USE_BOOTARGS=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y # CONFIG_HWCONFIG is not set CONFIG_PCI_INIT_R=y diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index 08a88e1f33d..7213c878830 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -16,6 +16,7 @@ CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7622> " CONFIG_SYS_MAXARGS=8 CONFIG_CMD_BOOTMENU=y diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig index dac7d341131..4f96cc50b40 100644 --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig index 80f7a7ff924..3b950a0db84 100644 --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig index 47203ff4e64..0f56ca8a37c 100644 --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7981> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig index 696741d4264..9d7554c5da7 100644 --- a/configs/mt7986_rfb_defconfig +++ b/configs/mt7986_rfb_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7986> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig index ef6a4822c18..153c1934bd0 100644 --- a/configs/mt7986a_bpir3_emmc_defconfig +++ b/configs/mt7986a_bpir3_emmc_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="BPI-R3> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig index 3d971f5c313..ad9711da614 100644 --- a/configs/mt7986a_bpir3_sd_defconfig +++ b/configs/mt7986a_bpir3_sd_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="BPI-R3> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7987_emmc_rfb_defconfig b/configs/mt7987_emmc_rfb_defconfig index 022ca32169b..26be8ea4491 100644 --- a/configs/mt7987_emmc_rfb_defconfig +++ b/configs/mt7987_emmc_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7987> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig index c6a88e7e9d3..ea43483d7ed 100644 --- a/configs/mt7987_rfb_defconfig +++ b/configs/mt7987_rfb_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7987> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7987_sd_rfb_defconfig b/configs/mt7987_sd_rfb_defconfig index ca7714b1242..70eb5afb999 100644 --- a/configs/mt7987_sd_rfb_defconfig +++ b/configs/mt7987_sd_rfb_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7987> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig index eebf7fb43ba..f492ad8da58 100644 --- a/configs/mt7988_rfb_defconfig +++ b/configs/mt7988_rfb_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7988> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig index 99469985c5c..a07362c84fc 100644 --- a/configs/mt7988_sd_rfb_defconfig +++ b/configs/mt7988_sd_rfb_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=1049 CONFIG_LOGLEVEL=7 CONFIG_LOG=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="MT7988> " # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/mt8365_evk_defconfig b/configs/mt8365_evk_defconfig index 6ec3aa834b1..9d8ea72370e 100644 --- a/configs/mt8365_evk_defconfig +++ b/configs/mt8365_evk_defconfig @@ -10,6 +10,7 @@ CONFIG_TARGET_MT8365=y CONFIG_SYS_LOAD_ADDR=0x4c000000 CONFIG_IDENT_STRING=" mt8365-evk" CONFIG_DEFAULT_FDT_FILE="mt8365-evk" +# CONFIG_BOARD_INIT is not set CONFIG_CLK=y CONFIG_MMC_MTK=y CONFIG_BAUDRATE=921600 diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig index 756d974278a..72ff8c79153 100644 --- a/configs/mt8516_pumpkin_defconfig +++ b/configs/mt8516_pumpkin_defconfig @@ -23,6 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="mt8516-pumpkin" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 4011b8ef7ff..53e9804b0dd 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_PBSIZE=528 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 92592ad2195..381fa6bb3dd 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -37,6 +37,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus= CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_CMD_MD5SUM=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index f77d515706b..fc7ad18656e 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -37,6 +37,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus= CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Marvell> " CONFIG_CMD_MD5SUM=y diff --git a/configs/odroid-go-ultra_defconfig b/configs/odroid-go-ultra_defconfig index 97c44b1115b..f2c8b1d237c 100644 --- a/configs/odroid-go-ultra_defconfig +++ b/configs/odroid-go-ultra_defconfig @@ -23,6 +23,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig index 1e693c621eb..31b0dd58c17 100644 --- a/configs/openpiton_riscv64_defconfig +++ b/configs/openpiton_riscv64_defconfig @@ -23,6 +23,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="openpiton$ " # CONFIG_CMD_CPU is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/openpiton_riscv64_spl_defconfig b/configs/openpiton_riscv64_spl_defconfig index 13d956aea32..92f4c16ff76 100644 --- a/configs/openpiton_riscv64_spl_defconfig +++ b/configs/openpiton_riscv64_spl_defconfig @@ -29,6 +29,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="fdt addr ${fdtcontroladdr}; fdt move ${fdtcontroladdr} ${fdt_addr_r}; load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; booti ${kernel_addr_r} - ${fdt_addr_r}; " CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x100000 # CONFIG_SPL_LEGACY_IMAGE_FORMAT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y diff --git a/configs/pe2201_defconfig b/configs/pe2201_defconfig index 020a2d49e60..9cc0710aaf5 100644 --- a/configs/pe2201_defconfig +++ b/configs/pe2201_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="earlycon=pl011,0x2800c000 root=/dev/sda2 rw" # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="pe2201#" CONFIG_CMD_BOOTMETH=y # CONFIG_CMD_LZMADEC is not set diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 96eacec1d23..4d6bce26f07 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x3C0000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-phyboard-polis-rdk" -CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x56000000 +CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000 CONFIG_TARGET_PHYCORE_IMX8MM=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=524288 @@ -23,7 +23,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x47602000 CONFIG_SF_DEFAULT_BUS=3 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 @@ -31,8 +31,9 @@ CONFIG_PCI=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTD_FULL=y CONFIG_OF_SYSTEM_SETUP=y -CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_DEFAULT_FDT_FILE="imx8mm-phyboard-polis-rdk" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y @@ -48,7 +49,6 @@ CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SPL_WATCHDOG=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -66,15 +66,9 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index bdd7e288aa4..05849d05be4 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -42,6 +42,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_PAD_TO=0x0 diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig index 8ee6ed73adc..01d100842de 100644 --- a/configs/phycore_am62ax_r5_defconfig +++ b/configs/phycore_am62ax_r5_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 92a159e7466..978604b0232 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -46,6 +46,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 73517e04d0a..0368d4ef474 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 9f98b3522dc..62c9eec971d 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -41,6 +41,7 @@ CONFIG_BOOTSTD_FULL=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -lb; run ${boot}boot" CONFIG_DEFAULT_FDT_FILE="oftree" +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x180000 CONFIG_SPL_BOARD_INIT=y diff --git a/configs/phycore_am64x_r5_defconfig b/configs/phycore_am64x_r5_defconfig index 189d0706ce5..d1ac992dc7a 100644 --- a/configs/phycore_am64x_r5_defconfig +++ b/configs/phycore_am64x_r5_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x180000 diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 365f6434f83..a87e918117c 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -23,6 +23,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run common_bootargs; run romboot" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot>" CONFIG_SYS_MAXARGS=32 CONFIG_CMD_FUSE=y diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig index f7070543260..87e8e2271ff 100644 --- a/configs/pomelo_defconfig +++ b/configs/pomelo_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=280 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="pomelo#" CONFIG_OF_CONTROL=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/qemu-arm-sbsa_defconfig b/configs/qemu-arm-sbsa_defconfig index 3819670defe..76e07cac7b6 100644 --- a/configs/qemu-arm-sbsa_defconfig +++ b/configs/qemu-arm-sbsa_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_QEMU_ARM_SBSA=y CONFIG_EFI_VARIABLE_NO_STORE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="bootflow scan" +# CONFIG_BOARD_INIT is not set CONFIG_EFI_PARTITION=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_EFI_MEDIA=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index cdffda26281..bf39a1da723 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 3d065b6a9fb..2a876aefecd 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -13,6 +13,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 15f1a5d973d..36f8b457586 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index bf9a0b07400..a9ff831be91 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -12,6 +12,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 6cc42817970..8384fe78a31 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -15,6 +15,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 1c7cef056c4..34e14b8f8df 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_SYS_MALLOC=y # CONFIG_CMD_MII is not set diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 39afb837e41..358bb1aeeb9 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -25,6 +25,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_PCI_INIT_R=y CONFIG_BLOBLIST=y CONFIG_CMD_SMBIOS=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index 92ba48f6af9..d5890bf87fb 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -27,6 +27,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_PCI_INIT_R=y CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_CMD_NVEDIT_EFI=y diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index e7c0a7e1eae..c2bdc521018 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -19,6 +19,7 @@ CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y CONFIG_SYS_PBSIZE=2068 # CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_MALLOC_BOOTPARAMS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CLK=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 374dcb1d5ba..fc027b6d0fd 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -27,6 +27,7 @@ CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000 CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_ANDROID_AB=y CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 2eba02e1f07..0c030f4a792 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -49,6 +49,7 @@ CONFIG_LOG_MAX_LEVEL=9 CONFIG_LOG_DEFAULT_LEVEL=6 CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_STACKPROTECTOR=y CONFIG_ANDROID_AB=y CONFIG_CMD_CPU=y @@ -77,6 +78,11 @@ CONFIG_CMD_MX_CYCLIC=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_DEMO=y +CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y +CONFIG_CMD_FPGA_LOADFS=y +CONFIG_CMD_FPGA_LOADMK=y +CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPIO_READ=y CONFIG_CMD_PWM=y @@ -197,6 +203,20 @@ CONFIG_SANDBOX_DMA=y CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_ARM_FFA_TRANSPORT=y +CONFIG_FPGA_ALTERA=y +CONFIG_FPGA_STRATIX_II=y +CONFIG_FPGA_STRATIX_V=y +CONFIG_FPGA_ACEX1K=y +CONFIG_FPGA_CYCLON2=y +CONFIG_FPGA_LATTICE=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_SPARTAN2=y +CONFIG_FPGA_SPARTAN3=y +CONFIG_FPGA_VIRTEX2=y +CONFIG_SYS_FPGA_CHECK_BUSY=y +CONFIG_SYS_FPGA_CHECK_CTRLC=y +CONFIG_DM_FPGA=y +CONFIG_SANDBOX_FPGA=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_QCOM_PMIC_GPIO=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index e81941fb14f..b9c378cf696 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -26,6 +26,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x6000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_CMD_CPU=y CONFIG_CMD_LICENSE=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index a0702d6f6e1..806ca6334d4 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -33,6 +33,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index f1c48c84b62..dca5ed956a2 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -28,6 +28,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 9d75bb5f933..e1e11ca222f 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -39,6 +39,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_BLOBLIST_SIZE=0x5000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y diff --git a/configs/sipeed_licheerv_nano_defconfig b/configs/sipeed_licheerv_nano_defconfig index 14fefa968c6..fc7f82e878a 100644 --- a/configs/sipeed_licheerv_nano_defconfig +++ b/configs/sipeed_licheerv_nano_defconfig @@ -18,6 +18,7 @@ CONFIG_SD_BOOT=y CONFIG_BOOTCOMMAND="run distro_bootcmd" CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="licheerv_nano# " # CONFIG_CMD_BOOTDEV is not set CONFIG_CMD_MBR=y diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig index b2e21c7d7ae..9fcdfb4a8fe 100644 --- a/configs/sipeed_maix_bitm_defconfig +++ b/configs/sipeed_maix_bitm_defconfig @@ -16,6 +16,7 @@ CONFIG_BOOTCOMMAND="run k210_bootcmd" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" diff --git a/configs/sipeed_maix_smode_defconfig b/configs/sipeed_maix_smode_defconfig index d838b252d53..11d78688780 100644 --- a/configs/sipeed_maix_smode_defconfig +++ b/configs/sipeed_maix_smode_defconfig @@ -17,6 +17,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run k210_bootcmd" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y CONFIG_MTDIDS_DEFAULT="nor0=spi3:0" CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)" diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index c0992f397f6..8282271d0ed 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -20,6 +20,7 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAS1,115200 CONSOLE=/dev/ttyAS1 consoleblank=0 root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait mem=992M@0x40000000 vmalloc=256m" CONFIG_SYS_PBSIZE=1058 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="stih410-b2260 => " CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index 36e57edbb4d..45dc8bb0cee 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -19,6 +19,7 @@ CONFIG_BOOTARGS="console=ttySTM0,115200 earlyprintk consoleblank=0 ignore_loglev CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index a2ce8c80e20..02fc2dc521a 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -14,6 +14,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 7a1fe576cc3..f0aab073bae 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -15,6 +15,7 @@ CONFIG_BOOTDELAY=3 CONFIG_SYS_PBSIZE=1050 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_CYCLIC_MAX_CPU_TIME_US=50000 +# CONFIG_BOARD_INIT is not set CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_IMLS=y diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig index 38312e9a5f1..5818e68ff7e 100644 --- a/configs/stm32h743-disco_defconfig +++ b/configs/stm32h743-disco_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="stm32h743i-disco" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig index fcbf7177690..3ee8d082da8 100644 --- a/configs/stm32h743-eval_defconfig +++ b/configs/stm32h743-eval_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="stm32h743i-eval" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32h747-disco_defconfig b/configs/stm32h747-disco_defconfig index 5bb87eee510..bea1fa5a809 100644 --- a/configs/stm32h747-disco_defconfig +++ b/configs/stm32h747-disco_defconfig @@ -20,6 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="stm32h747i-disco" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig index 8a7c45f74a4..971d5c00d88 100644 --- a/configs/stm32h750-art-pi_defconfig +++ b/configs/stm32h750-art-pi_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_GPT=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index cfbe5a4ae91..2e86abac801 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index f6ca1700a5f..b800b4c4073 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index 16524245ce1..870e17e451a 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 3348b3f0546..88ee89aa13a 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -20,6 +20,7 @@ CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" CONFIG_SYS_PBSIZE=1050 +# CONFIG_BOARD_INIT is not set CONFIG_SPL_FOOTPRINT_LIMIT=y CONFIG_SPL_MAX_FOOTPRINT=0x3db00 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 7dd75bfe365..7fe0d87a3e2 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="ThunderX_88XX> " diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index c90dfe517d6..42ec5957510 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_BOOTI=n CONFIG_CMD_ELF=n CONFIG_CMD_EXTENSION=n CONFIG_CMD_DATE=n +CONFIG_BOARD_INIT=n CONFIG_OF_CONTROL=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index 0489f444115..f8a984f1e6b 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -46,7 +46,7 @@ CONFIG_SYS_PBSIZE=2081 CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_ARCH_MISC_INIT=y +# CONFIG_BOARD_INIT is not set CONFIG_SPL_MAX_SIZE=0x26000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index cce58d31994..74dcc455f7a 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_BLOBLIST=y CONFIG_BLOBLIST_PASSAGE_MANDATORY=y CONFIG_SYS_PROMPT="TOTAL_COMPUTE# " diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index e36b55faec1..9fc5184e74a 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -41,6 +41,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am625-verdin-${variant}- CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x58000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y diff --git a/configs/verdin-am62_r5_defconfig b/configs/verdin-am62_r5_defconfig index 5cc7d050c33..efba857ad70 100644 --- a/configs/verdin-am62_r5_defconfig +++ b/configs/verdin-am62_r5_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/verdin-am62p_a53_defconfig b/configs/verdin-am62p_a53_defconfig index 7e6132cde53..3daf22ff8ff 100644 --- a/configs/verdin-am62p_a53_defconfig +++ b/configs/verdin-am62p_a53_defconfig @@ -42,6 +42,7 @@ CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am62p5-verdin-${variant} CONFIG_LOG=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_MAX_SIZE=0x80000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y diff --git a/configs/verdin-am62p_r5_defconfig b/configs/verdin-am62p_r5_defconfig index 42361523ab3..a8b0e942b61 100644 --- a/configs/verdin-am62p_r5_defconfig +++ b/configs/verdin-am62p_r5_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_MAX_SIZE=0x3B000 diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index e9a5219a7c4..161fa1a6eff 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -12,6 +12,7 @@ CONFIG_IDENT_STRING=" xenguest" CONFIG_BOOTDELAY=10 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1051 +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="xenguest# " # CONFIG_CMD_BDI is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/xenguest_arm64_virtio_defconfig b/configs/xenguest_arm64_virtio_defconfig index acf131fc837..ebd2c9b483a 100644 --- a/configs/xenguest_arm64_virtio_defconfig +++ b/configs/xenguest_arm64_virtio_defconfig @@ -14,6 +14,7 @@ CONFIG_PCI=y CONFIG_BOOTDELAY=10 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_PBSIZE=1051 +# CONFIG_BOARD_INIT is not set CONFIG_PCI_INIT_R=y CONFIG_SYS_PROMPT="xenguest# " # CONFIG_CMD_BDI is not set diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 7dde2fc0a8f..92f7aa04ec0 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index b96b02c6125..b61ec90d096 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig index 77fcf4d6865..c4d458370b6 100644 --- a/configs/xilinx_mbv64_defconfig +++ b/configs/xilinx_mbv64_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig index e53c0771baf..2d7227c9e33 100644 --- a/configs/xilinx_mbv64_smode_defconfig +++ b/configs/xilinx_mbv64_smode_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_BOARD_INIT is not set # CONFIG_BOARD_LATE_INIT is not set CONFIG_SPL_MAX_SIZE=0x40000 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index f164580c501..41444271f0d 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_XILINX_MINI=y CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set CONFIG_SYS_MEMTEST_START=0x00000000 CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_REMAKE_ELF=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 8a8a9b0b463..369d480fd1f 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 3fc4f2f9b86..2b415b8f727 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x80000 CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_SPL=y CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index cfcb4321b1f..c7271899bdf 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y diff --git a/configs/xilinx_zynqmp_mini_nand_single_defconfig b/configs/xilinx_zynqmp_mini_nand_single_defconfig index 9af0b717ba9..bb9cd882340 100644 --- a/configs/xilinx_zynqmp_mini_nand_single_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_single_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand" CONFIG_SYS_LOAD_ADDR=0x8000000 CONFIG_XILINX_MINI=y +# CONFIG_PSCI_RESET is not set CONFIG_REMAKE_ELF=y # CONFIG_MP is not set CONFIG_FIT=y diff --git a/configs/xilinx_zynqmp_r5_defconfig b/configs/xilinx_zynqmp_r5_defconfig index d4ec2b59b71..81ea0e175ff 100644 --- a/configs/xilinx_zynqmp_r5_defconfig +++ b/configs/xilinx_zynqmp_r5_defconfig @@ -18,6 +18,7 @@ CONFIG_BOOTSTAGE=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=284 # CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_BOARD_INIT is not set CONFIG_SYS_PROMPT="ZynqMP r5> " CONFIG_SYS_MAXARGS=32 # CONFIG_CMD_SETEXPR is not set diff --git a/doc/board/nxp/imx93_frdm.rst b/doc/board/nxp/imx93_frdm.rst new file mode 100644 index 00000000000..a1f526fd4cc --- /dev/null +++ b/doc/board/nxp/imx93_frdm.rst @@ -0,0 +1,75 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx93_frdm +========== + +U-Boot for the NXP i.MX93 FRDM board + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the DDR firmware +- Get ahab-container.img +- Build U-Boot +- Boot from the SD card + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.8 + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx93 bl31 + $ cp build/imx93/release/bl31.bin $(srctree) + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin + $ chmod +x firmware-imx-8.21.bin + $ ./firmware-imx-8.21.bin + $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Get ahab-container.img +---------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin + $ chmod +x firmware-sentinel-0.11.bin + $ ./firmware-sentinel-0.11.bin + $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx93_frdm_defconfig + $ make + +Copy the flash.bin binary to the MicroSD card at offset 32KB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1k seek=32; sync + +Boot from the SD card +--------------------- + +- Configure SW1 boot switches to SD boot mode: + 0011 SW1[3:0] - ("USDHC2 4-bit SD3.0" Boot Mode) +- Insert the SD card in the SD slot (P13) of the board. +- Connect a USB Type-C cable into the P16 Debug USB Port and connect + using a terminal emulator at 115200 bps, 8n1. The console will show up + at /dev/ttyACM0. +- Power on the board by connecting a USB Type-C cable into the P1 + Power USB Port. diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index e7ec725cc04..aa7d857346d 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -15,6 +15,7 @@ NXP Semiconductors imx91_11x11_evk imx93_9x9_qsb imx93_11x11_evk + imx93_frdm imx95_evk imxrt1020-evk imxrt1050-evk diff --git a/drivers/adc/imx93-adc.c b/drivers/adc/imx93-adc.c index f593fb6447b..d671df79f68 100644 --- a/drivers/adc/imx93-adc.c +++ b/drivers/adc/imx93-adc.c @@ -221,7 +221,7 @@ static int imx93_adc_stop(struct udevice *dev) static int imx93_adc_probe(struct udevice *dev) { struct imx93_adc_priv *adc = dev_get_priv(dev); - unsigned int ret; + int ret; ret = imx93_adc_calibration(adc); if (ret < 0) @@ -238,7 +238,7 @@ static int imx93_adc_of_to_plat(struct udevice *dev) { struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); struct imx93_adc_priv *adc = dev_get_priv(dev); - unsigned int ret; + int ret; adc->regs = dev_read_addr_ptr(dev); if (adc->regs == (struct imx93_adc *)FDT_ADDR_T_NONE) { diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index ce5e61bbaa6..5365ac68f9e 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -261,17 +261,14 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp) return 0; } -int uclass_find_next_device(struct udevice **devp) +void uclass_find_next_device(struct udevice **devp) { struct udevice *dev = *devp; *devp = NULL; - if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) - return 0; - - *devp = list_entry(dev->uclass_node.next, struct udevice, uclass_node); - - return 0; + if (!list_is_last(&dev->uclass_node, &dev->uclass->dev_head)) + *devp = list_entry(dev->uclass_node.next, struct udevice, + uclass_node); } int uclass_find_device_by_namelen(enum uclass_id id, const char *name, int len, @@ -675,11 +672,8 @@ int uclass_first_device_check(enum uclass_id id, struct udevice **devp) int uclass_next_device_check(struct udevice **devp) { - int ret; + uclass_find_next_device(devp); - ret = uclass_find_next_device(devp); - if (ret) - return ret; if (!*devp) return 0; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index d18ae523b6b..e07ec3929b2 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -500,11 +500,8 @@ static int zynqmp_firmware_bind(struct udevice *dev) if (!smc_call_handler) return -EINVAL; - if ((IS_ENABLED(CONFIG_XPL_BUILD) && - IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) && - IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) || - (!IS_ENABLED(CONFIG_XPL_BUILD) && - IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) { + if (CONFIG_IS_ENABLED(POWER_DOMAIN) && + IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) { ret = device_bind_driver_to_node(dev, "zynqmp_power_domain", "zynqmp_power_domain", dev_ofnode(dev), &child); diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 3de9011ac06..e1514fc56d0 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -14,6 +14,7 @@ #include <log.h> #include <ACEX1K.h> /* ACEX device family */ #include <linux/delay.h> +#include <time.h> /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 62cb77b098c..9456ca3149a 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -15,6 +15,7 @@ config FPGA_ALTERA config FPGA_SOCFPGA bool "Enable Gen5 and Arria10 common FPGA drivers" + depends on ARCH_SOCFPGA select FPGA_ALTERA help Say Y here to enable the Gen5 and Arria10 common FPGA driver diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index f88267e01b6..2297fefd149 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -16,20 +16,6 @@ static int next_desc = FPGA_INVALID_DEVICE; static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; -/* - * fpga_no_sup - * 'no support' message function - */ -static void fpga_no_sup(char *fn, char *msg) -{ - if (fn && msg) - printf("%s: No support for %s.\n", fn, msg); - else if (msg) - printf("No support for %s.\n", msg); - else - printf("No FPGA support!\n"); -} - /* fpga_get_desc * map a device number to a descriptor */ @@ -39,8 +25,8 @@ const fpga_desc *fpga_get_desc(int devnum) if ((devnum >= 0) && (devnum < next_desc)) { desc = &desc_table[devnum]; - debug("%s: found fpga descriptor #%d @ 0x%p\n", - __func__, devnum, desc); + log_debug("found fpga descriptor #%d @ 0x%p\n", + devnum, desc); } return desc; @@ -51,15 +37,15 @@ const fpga_desc *fpga_get_desc(int devnum) * generic parameter checking code */ const fpga_desc *fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn) + size_t bsize) { const fpga_desc *desc = fpga_get_desc(devnum); if (!desc) - printf("%s: Invalid device number %d\n", fn, devnum); + log_err("Invalid device number %d\n", devnum); if (!buf) { - printf("%s: Null buffer.\n", fn); + log_err("Null buffer.\n"); return NULL; } return desc; @@ -75,40 +61,40 @@ static int fpga_dev_info(int devnum) const fpga_desc *desc = fpga_get_desc(devnum); if (desc) { - debug("%s: Device Descriptor @ 0x%p\n", - __func__, desc->devdesc); + log_info("Device Descriptor @ 0x%p\n", + desc->devdesc); switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - printf("Xilinx Device\nDescriptor @ 0x%p\n", desc); + log_info("Xilinx Device\nDescriptor @ 0x%p\n", desc); ret_val = xilinx_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) - printf("Altera Device\nDescriptor @ 0x%p\n", desc); + log_info("Altera Device\nDescriptor @ 0x%p\n", desc); ret_val = altera_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) - printf("Lattice Device\nDescriptor @ 0x%p\n", desc); + log_info("Lattice Device\nDescriptor @ 0x%p\n", desc); ret_val = lattice_info(desc->devdesc); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } else { - printf("%s: Invalid device number %d\n", __func__, devnum); + log_err("Invalid device number %d\n", devnum); } return ret_val; @@ -144,23 +130,22 @@ int fpga_add(fpga_type devtype, void *desc) int devnum = FPGA_INVALID_DEVICE; if (!desc) { - printf("%s: NULL device descriptor\n", __func__); + log_err("NULL device descriptor\n"); return devnum; } if (next_desc < 0) { - printf("%s: FPGA support not initialized!\n", __func__); + log_err("FPGA support not initialized!\n"); } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { if (next_desc < CONFIG_MAX_FPGA_DEVICES) { devnum = next_desc; desc_table[next_desc].devtype = devtype; desc_table[next_desc++].devdesc = desc; } else { - printf("%s: Exceeded Max FPGA device count\n", - __func__); + log_err("Exceeded Max FPGA device count\n"); } } else { - printf("%s: Unsupported FPGA type %d\n", __func__, devtype); + log_err("Unsupported FPGA type %d\n", devtype); } return devnum; @@ -181,7 +166,7 @@ int __weak fpga_is_partial_data(int devnum, size_t img_len) int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype) { - printf("Bitstream support not implemented for this FPGA device\n"); + log_err("Bitstream support not implemented for this FPGA device\n"); return FPGA_FAIL; } @@ -190,8 +175,7 @@ int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc *desc = fpga_validate(devnum, buf, size, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, size); if (desc) { switch (desc->devtype) { @@ -200,12 +184,12 @@ int fpga_fsload(int devnum, const void *buf, size_t size, ret_val = xilinx_loadfs(desc->devdesc, buf, size, fpga_fsinfo); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -219,8 +203,7 @@ int fpga_loads(int devnum, const void *buf, size_t size, { int ret_val = FPGA_FAIL; - const fpga_desc *desc = fpga_validate(devnum, buf, size, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, size); if (desc) { switch (desc->devtype) { @@ -229,12 +212,12 @@ int fpga_loads(int devnum, const void *buf, size_t size, ret_val = xilinx_loads(desc->devdesc, buf, size, fpga_sec_info); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -265,8 +248,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, { int ret_val = FPGA_FAIL; /* assume failure */ int ret_notify; - const fpga_desc *desc = fpga_validate(devnum, buf, bsize, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize); if (desc) { switch (desc->devtype) { @@ -275,26 +257,26 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, ret_val = xilinx_load(desc->devdesc, buf, bsize, bstype, flags); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) ret_val = altera_load(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_load(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -312,8 +294,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype, int fpga_dump(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc *desc = fpga_validate(devnum, buf, bsize, - (char *)__func__); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize); if (desc) { switch (desc->devtype) { @@ -321,26 +302,26 @@ int fpga_dump(int devnum, const void *buf, size_t bsize) #if defined(CONFIG_FPGA_XILINX) ret_val = xilinx_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Xilinx devices"); + log_err("No support for Xilinx devices.\n"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) ret_val = altera_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Altera devices"); + log_err("No support for Altera devices.\n"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup((char *)__func__, "Lattice devices"); + log_err("No support for Lattice devices.\n"); #endif break; default: - printf("%s: Invalid or unsupported device type %d\n", - __func__, desc->devtype); + log_err("Invalid or unsupported device type %d\n", + desc->devtype); } } @@ -363,7 +344,7 @@ int fpga_info(int devnum) return FPGA_SUCCESS; } else { - printf("%s: No FPGA devices available.\n", __func__); + log_err("No FPGA devices available.\n"); return FPGA_FAIL; } } diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.c index 3c9a01e5110..37d5c5ec9ec 100644 --- a/drivers/fpga/ivm_core.c +++ b/drivers/fpga/ivm_core.c @@ -33,6 +33,7 @@ #include <linux/string.h> #include <malloc.h> #include <lattice.h> +#include <vsprintf.h> #define vme_out_char(c) printf("%c", c) #define vme_out_hex(c) printf("%x", c) @@ -291,7 +292,7 @@ unsigned short g_usLVDSPairCount; */ static signed char ispVMDataCode(void); -static long int ispVMDataSize(void); +static long ispVMDataSize(void); static void ispVMData(unsigned char *Data); static signed char ispVMShift(signed char Code); static signed char ispVMAmble(signed char Code); @@ -589,7 +590,7 @@ void ispVMFreeMem(void) * */ -long int ispVMDataSize() +long ispVMDataSize(void) { /* 09/11/07 NN added local variables initialization */ long int iSize = 0; @@ -614,7 +615,7 @@ long int ispVMDataSize() * */ -signed char ispVMCode() +signed char ispVMCode(void) { /* 09/11/07 NN added local variables initialization */ unsigned short iRepeatSize = 0; @@ -1113,7 +1114,7 @@ signed char ispVMCode() * */ -signed char ispVMDataCode() +signed char ispVMDataCode(void) { /* 09/11/07 NN added local variables initialization */ signed char cDataByte = 0; @@ -2475,7 +2476,7 @@ void ispVMStateMachine(signed char cNextJTAGState) * */ -void ispVMStart() +void ispVMStart(void) { #ifdef DEBUG printf("// ISPVM EMBEDDED ADDED\n"); @@ -2504,7 +2505,7 @@ void ispVMStart() * */ -void ispVMEnd() +void ispVMEnd(void) { #ifdef DEBUG printf("// ISPVM EMBEDDED ADDED\n"); diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index 3f481e38565..29cf2f60974 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -350,8 +350,8 @@ int lattice_info(Lattice_desc *desc) printf("Unsupported interface type, %d\n", desc->iface); } - printf("Device Size: \t%d bytes\n", - desc->size); + printf("Device Size: \t%zu bytes\n", + desc->size); if (desc->iface_fns) { printf("Device Function Table @ 0x%p\n", diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 906649ea181..792e4033428 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -9,6 +9,7 @@ #include <config.h> /* core U-Boot definitions */ #include <log.h> #include <spartan2.h> /* Spartan-II device family */ +#include <time.h> /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c index 73fecd9dca5..3f984385316 100644 --- a/drivers/fpga/stratixII.c +++ b/drivers/fpga/stratixII.c @@ -5,92 +5,41 @@ */ #include <altera.h> +#include <stratixII.h> #include <linux/delay.h> -int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, - int isSerial, int isSecure); -int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize); - /****************************************************************/ /* Stratix II Generic Implementation */ -int StratixII_load (Altera_desc * desc, void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0); - break; - case fast_passive_parallel: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0); - break; - case fast_passive_parallel_security: - ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1); - break; - - /* Add new interface types here */ - default: - printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, - desc->iface); - } - return ret_val; -} - -int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize) -{ - int ret_val = FPGA_FAIL; - - switch (desc->iface) { - case passive_serial: - case fast_passive_parallel: - case fast_passive_parallel_security: - ret_val = StratixII_ps_fpp_dump (desc, buf, bsize); - break; - /* Add new interface types here */ - default: - printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, - desc->iface); - } - return ret_val; -} - -int StratixII_info (Altera_desc * desc) -{ - return FPGA_SUCCESS; -} - -int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize) +int StratixII_ps_fpp_dump(Altera_desc *desc, const void *buf, size_t bsize) { - printf ("Stratix II Fast Passive Parallel dump is not implemented\n"); + printf("Stratix II Fast Passive Parallel dump is not implemented\n"); return FPGA_FAIL; } -int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, - int isSerial, int isSecure) +int StratixII_ps_fpp_load(Altera_desc *desc, const void *buf, size_t bsize, + int isSerial, int isSecure) { altera_board_specific_func *fns; int cookie; int ret_val = FPGA_FAIL; int bytecount; - char *buff = buf; + const char *buff = buf; int i; if (!desc) { - printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__); + log_err("Altera_desc missing\n"); return FPGA_FAIL; } if (!buff) { - printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__); + log_err("buffer is missing\n"); return FPGA_FAIL; } if (!bsize) { - printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__); + log_err("size is zero\n"); return FPGA_FAIL; } if (!desc->iface_fns) { - printf - ("%s(%d) Altera_desc function interface table is missing\n", - __FUNCTION__, __LINE__); + log_err("Altera_desc function interface table is missing\n"); return FPGA_FAIL; } fns = (altera_board_specific_func *) (desc->iface_fns); @@ -99,9 +48,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, if (! (fns->config && fns->status && fns->done && fns->data && fns->abort)) { - printf - ("%s(%d) Missing some function in the function interface table\n", - __FUNCTION__, __LINE__); + log_err("Missing some function in the function interface table\n"); return FPGA_FAIL; } @@ -124,13 +71,12 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, bytecount = 0; fns->clk (0, 1, cookie); - printf ("loading to fpga "); + printf("loading to fpga "); while (bytecount < bsize) { /* 3.1 check stratix has not signaled us an error */ if (fns->status (cookie) != 1) { - printf - ("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n", - __FUNCTION__, __LINE__, bytecount); + log_err("\nStratix failed (byte transferred till failure 0x%x)\n", + bytecount); fns->abort (cookie); return FPGA_FAIL; } @@ -162,7 +108,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, /* 3.5 while clk is deasserted it is safe to print some progress indication */ if ((bytecount % (bsize / 100)) == 0) { - printf ("\b\b\b%02d\%", bytecount * 100 / bsize); + printf("\b\b\b%02zu\%%", bytecount * 100 / bsize); } } @@ -170,11 +116,11 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, fns->clk (1, 1, cookie); udelay(100); if (!fns->done (cookie)) { - printf (" error!.\n"); + printf(" error!.\n"); fns->abort (cookie); return FPGA_FAIL; } else { - printf ("\b\b\b done.\n"); + printf("\b\b\b done.\n"); } /* 5. call lower layer post configuration */ @@ -187,3 +133,47 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize, return FPGA_SUCCESS; } + +int StratixII_load(Altera_desc *desc, const void *buf, size_t size) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 1, 0); + break; + case fast_passive_parallel: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 0); + break; + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 1); + break; + + /* Add new interface types here */ + default: + log_err("Unsupported interface type, %d\n", desc->iface); + } + return ret_val; +} + +int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize) +{ + int ret_val = FPGA_FAIL; + + switch (desc->iface) { + case passive_serial: + case fast_passive_parallel: + case fast_passive_parallel_security: + ret_val = StratixII_ps_fpp_dump(desc, buf, bsize); + break; + /* Add new interface types here */ + default: + log_err("Unsupported interface type, %d\n", desc->iface); + } + return ret_val; +} + +int StratixII_info(Altera_desc *desc) +{ + return FPGA_SUCCESS; +} diff --git a/drivers/fpga/stratixv.c b/drivers/fpga/stratixv.c index 372f16d92d1..4b251994598 100644 --- a/drivers/fpga/stratixv.c +++ b/drivers/fpga/stratixv.c @@ -48,7 +48,7 @@ int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) int spi_dev; int ret = 0; - if ((u32)rbf_data & 0x3) { + if ((size_t)rbf_data & 0x3) { puts("FPGA: Unaligned data, realign to 32bit boundary.\n"); return -EINVAL; } diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index d691f135e89..624493ad838 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -6,7 +6,6 @@ #include <cpu_func.h> #include <log.h> -#include <asm/arch/sys_proto.h> #include <memalign.h> #include <versalpl.h> #include <zynqmp_firmware.h> diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 8e2c12bb58b..805cbac8082 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -19,6 +19,7 @@ #include <log.h> #include <virtex2.h> #include <linux/delay.h> +#include <time.h> /* * If the SelectMap interface can be overrun by the processor, enable @@ -301,6 +302,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) size_t bytecount = 0; unsigned char *data = (unsigned char *)buf; int cookie = desc->cookie; + unsigned long ts; ret_val = virtex2_slave_pre(fn, cookie); if (ret_val != FPGA_SUCCESS) diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index c46513226d9..28c68faba55 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -49,7 +49,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ - desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); + desc = fpga_validate(devnum, dataptr, 0); /* Assign xilinx device description */ xdesc = desc->devdesc; diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 2b62bbbe3cf..1199b249e36 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -191,8 +191,8 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, } if ((ulong)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%px)\n", - __func__, buf); + log_err("Bitstream has to be placed above 1MB (%px)\n", + buf); return FPGA_FAIL; } diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 3e86d854a01..5a37a33b0a7 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -360,8 +360,8 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, } if ((u32)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%x)\n", - __func__, (u32)buf); + log_err("Bitstream has to be placed above 1MB (%x)\n", + (u32)buf); return FPGA_FAIL; } diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 7db58c70663..ef4f33f84e9 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -184,6 +184,7 @@ static const struct zynq_platform_data zynq_gpio_def = { * pin * @bank_pin_num: an output parameter used to return pin number within a bank * for the given gpio pin + * @dev: Pointer to our device structure. * * Returns the bank number and pin offset within the bank. */ diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 966783e4b62..0f753b9dbb9 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -641,6 +641,14 @@ config ESM_K3 help Support ESM (Error Signaling Module) on TI K3 SoCs. +config K3_BIST + bool "Enable K3 BIST driver" + depends on ARCH_K3 + help + Support BIST (Built-In Self Test) module on TI K3 SoCs. This driver + supports running both PBIST (Memory BIST) and LBIST (Logic BIST) on + a region or IP in the SoC. + config MICROCHIP_FLEXCOM bool "Enable Microchip Flexcom driver" depends on MISC diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 09dfd8072db..f7422c8e95a 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o obj-$(CONFIG_MICROCHIP_FLEXCOM) += microchip_flexcom.o obj-$(CONFIG_K3_AVS0) += k3_avs.o obj-$(CONFIG_ESM_K3) += k3_esm.o +obj-$(CONFIG_K3_BIST) += k3_bist.o obj-$(CONFIG_ESM_PMIC) += esm_pmic.o obj-$(CONFIG_SL28CPLD) += sl28cpld.o obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o diff --git a/drivers/misc/k3_bist.c b/drivers/misc/k3_bist.c new file mode 100644 index 00000000000..3acb1a1ac1f --- /dev/null +++ b/drivers/misc/k3_bist.c @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * Neha Malcom Francis <n-francis@ti.com> + * + */ + +#include <dm.h> +#include <errno.h> +#include <clk.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <asm/arch/hardware.h> +#include <linux/soc/ti/ti_sci_protocol.h> +#include <remoteproc.h> +#include <power-domain.h> +#include <k3_bist.h> + +#include "k3_bist_static_data.h" + +/* PBIST Timeout Value */ +#define PBIST_MAX_TIMEOUT_VALUE 100000000 + +/** + * struct k3_bist_privdata - K3 BIST structure + * @dev: device pointer + * @pbist_base: base of register set for PBIST + * @instance: PBIST instance number + * @intr_num: corresponding interrupt ID of the PBIST instance + * @lbist_ctrl_mmr: base of CTRL MMR register set for LBIST + */ +struct k3_bist_privdata { + struct udevice *dev; + void *pbist_base; + u32 instance; + u32 intr_num; + void *lbist_ctrl_mmr; + struct pbist_inst_info *pbist_info; + struct lbist_inst_info *lbist_info; +}; + +static struct k3_bist_privdata *k3_bist_priv; + +/** + * check_post_pbist_result() - Check POST results + * + * Function to check whether HW Power-On Self Test, i.e. POST has run + * successfully on the MCU domain. + * + * Return: 0 if all went fine, else corresponding error. + */ +static int check_post_pbist_result(void) +{ + bool is_done, timed_out; + u32 mask; + u32 post_reg_val, shift; + + /* Read HW POST status register */ + post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT); + + /* Check if HW POST PBIST was performed */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT; + is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!is_done) { + /* HW POST: PBIST not completed, check if it timed out */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT; + timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!timed_out) { + printf("%s: PBIST was not performed at all on this device for this core\n", + __func__); + return -EINVAL; + } + printf("%s: PBIST was attempted but timed out for this section\n", + __func__); + return -ETIMEDOUT; + + } else { + /* HW POST: PBIST was completed on this device, check the result */ + mask = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK; + + if ((post_reg_val & mask) != 0) { + printf("%s: PBIST was completed, but the test failed\n", __func__); + return -EINVAL; + } + debug("%s: HW POST PBIST completed, test passed\n", __func__); + } + + return 0; +} + +/** + * check_post_lbist_result() - Check POST results + * + * Function to check whether HW Power-On Self Test, i.e. POST has run + * successfully on the MCU domain. + * + * Return: 0 if all went fine, else corresponding error. + */ +static int check_post_lbist_result(void) +{ + bool is_done, timed_out; + u32 post_reg_val, shift; + u32 calculated_misr, expected_misr; + + /* Read HW POST status register */ + post_reg_val = readl(WKUP_CTRL_MMR0_BASE + WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT); + + /* Check if HW POST LBIST was performed */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT; + is_done = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!is_done) { + /* HW POST: PBIST not completed, check if it timed out */ + shift = WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT; + timed_out = (((post_reg_val >> shift) & 0x1u) == 0x1u) ? (bool)true : (bool)false; + + if (!timed_out) { + printf("%s: PBIST was not performed at all on this device for this core\n", + __func__); + return -EINVAL; + } + printf("%s: PBIST was attempted but timed out for this section\n", + __func__); + return -ETIMEDOUT; + + } else { + /* Get the output MISR and the expected MISR which 0 for MCU domain */ + lbist_get_misr((void *)MCU_LBIST_BASE, &calculated_misr); + expected_misr = readl(MCU_CTRL_MMR0_CFG0_BASE + MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG); + + if (calculated_misr != expected_misr) { + /* HW POST: LBIST was completed, but the test failed for this core */ + printf("%s: calculated MISR != expected MISR\n", __func__); + debug("%s: calculated MISR = %x\n", __func__, calculated_misr); + debug("%s: expected MISR = %x\n", __func__, expected_misr); + return -EINVAL; + } + debug("%s: HW POST LBIST completed, test passed\n", __func__); + } + + return 0; +} + +/** + * pbist_self_test() - Run PBIST_TEST on specified cores + * @config: pbist_config structure for PBIST test + * + * Function to run PBIST_TEST + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_self_test(struct pbist_config *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(PBIST_TEST_MODE, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set algorithm bitmap */ + writel(config->algorithms_bit_map, base + PBIST_ALGO); + + /* Set Memory group bitmap */ + writel(config->memory_groups_bit_map, base + PBIST_RINFO); + + /* Zero out override register */ + writel(config->override, base + PBIST_OVER); + + /* Set Scramble value - 64 bit*/ + writel(config->scramble_value_lo, base + PBIST_SCR_LO); + writel(config->scramble_value_hi, base + PBIST_SCR_HI); + + /* Set DLR register for ROM based testing and Config Access */ + writel(PBIST_DLR_DLR0_ROM_MASK + | PBIST_DLR_DLR0_CAM_MASK, base + PBIST_DLR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * pbist_neg_self_test() - Run PBIST_negTEST on specified cores + * @config: pbist_config_neg structure for PBIST negative test + * + * Function to run PBIST failure insertion test + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_neg_self_test(struct pbist_config_neg *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(PBIST_PACT_PACT_MASK, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(PBIST_FAILURE_INSERTION_TEST_MODE, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set DLR register */ + writel(0x10, base + PBIST_DLR); + + /* Set Registers*/ + writel(0x00000001, base + PBIST_RF0L); + writel(0x00003123, base + PBIST_RF0U); + writel(0x0513FC02, base + PBIST_RF1L); + writel(0x00000002, base + PBIST_RF1U); + writel(0x00000003, base + PBIST_RF2L); + writel(0x00000000, base + PBIST_RF2U); + writel(0x00000004, base + PBIST_RF3L); + writel(0x00000028, base + PBIST_RF3U); + writel(0x64000044, base + PBIST_RF4L); + writel(0x00000000, base + PBIST_RF4U); + writel(0x0006A006, base + PBIST_RF5L); + writel(0x00000000, base + PBIST_RF5U); + writel(0x00000007, base + PBIST_RF6L); + writel(0x0000A0A0, base + PBIST_RF6U); + writel(0x00000008, base + PBIST_RF7L); + writel(0x00000064, base + PBIST_RF7U); + writel(0x00000009, base + PBIST_RF8L); + writel(0x0000A5A5, base + PBIST_RF8U); + writel(0x0000000A, base + PBIST_RF9L); + writel(0x00000079, base + PBIST_RF9U); + writel(0x00000000, base + PBIST_RF10L); + writel(0x00000001, base + PBIST_RF10U); + writel(0xAAAAAAAA, base + PBIST_D); + writel(0xAAAAAAAA, base + PBIST_E); + + writel(config->CA2, base + PBIST_CA2); + writel(config->CL0, base + PBIST_CL0); + writel(config->CA3, base + PBIST_CA3); + writel(config->I0, base + PBIST_I0); + writel(config->CL1, base + PBIST_CL1); + writel(config->I3, base + PBIST_I3); + writel(config->I2, base + PBIST_I2); + writel(config->CL2, base + PBIST_CL2); + writel(config->CA1, base + PBIST_CA1); + writel(config->CA0, base + PBIST_CA0); + writel(config->CL3, base + PBIST_CL3); + writel(config->I1, base + PBIST_I1); + writel(config->RAMT, base + PBIST_RAMT); + writel(config->CSR, base + PBIST_CSR); + writel(config->CMS, base + PBIST_CMS); + + writel(0x00000009, base + PBIST_STR); + + /* Start PBIST */ + writel(0x00000001, base + PBIST_STR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF) == 0) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * pbist_rom_self_test() - Run PBIST_ROM_TEST on specified cores + * @config: pbist_config_rom structure for PBIST negative test + * + * Function to run PBIST test of ROM + * + * Return: 0 if all went fine, else corresponding error. + */ +static int pbist_rom_self_test(struct pbist_config_rom *config) +{ + void *base = k3_bist_priv->pbist_base; + + /* Turns on PBIST clock in PBIST ACTivate register */ + writel(0x1, base + PBIST_PACT); + + /* Set Margin mode register for Test mode */ + writel(0xf, base + PBIST_MARGIN_MODE); + + /* Zero out Loop counter 0 */ + writel(0x0, base + PBIST_L0); + + /* Set DLR register */ + writel(0x310, base + PBIST_DLR); + + /* Set Registers*/ + writel(0x00000001, base + PBIST_RF0L); + writel(0x00003123, base + PBIST_RF0U); + writel(0x7A400183, base + PBIST_RF1L); + writel(0x00000060, base + PBIST_RF1U); + writel(0x00000184, base + PBIST_RF2L); + writel(0x00000000, base + PBIST_RF2U); + writel(0x7B600181, base + PBIST_RF3L); + writel(0x00000061, base + PBIST_RF3U); + writel(0x00000000, base + PBIST_RF4L); + writel(0x00000000, base + PBIST_RF4U); + + writel(config->D, base + PBIST_D); + writel(config->E, base + PBIST_E); + writel(config->CA2, base + PBIST_CA2); + writel(config->CL0, base + PBIST_CL0); + writel(config->CA3, base + PBIST_CA3); + writel(config->I0, base + PBIST_I0); + writel(config->CL1, base + PBIST_CL1); + writel(config->I3, base + PBIST_I3); + writel(config->I2, base + PBIST_I2); + writel(config->CL2, base + PBIST_CL2); + writel(config->CA1, base + PBIST_CA1); + writel(config->CA0, base + PBIST_CA0); + writel(config->CL3, base + PBIST_CL3); + writel(config->I1, base + PBIST_I1); + writel(config->RAMT, base + PBIST_RAMT); + writel(config->CSR, base + PBIST_CSR); + writel(config->CMS, base + PBIST_CMS); + + writel(0x00000009, base + PBIST_STR); + + /* Start PBIST */ + writel(0x00000001, base + PBIST_STR); + + /* Allow time for completion of test*/ + udelay(1000); + + if (readl(base + PBIST_FSRF)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * lbist_program_config() - Program LBIST config + * @config: lbist_config structure for LBIST test + */ +static void lbist_program_config(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + + lbist_set_clock_delay(base, config->dc_def); + lbist_set_divide_ratio(base, config->divide_ratio); + lbist_clear_load_div(base); + lbist_set_load_div(base); + lbist_set_num_stuck_at_patterns(base, config->static_pc_def); + lbist_set_num_set_patterns(base, config->set_pc_def); + lbist_set_num_reset_patterns(base, config->reset_pc_def); + lbist_set_num_chain_test_patterns(base, config->scan_pc_def); + lbist_set_seed(base, config->prpg_def_l, config->prpg_def_u); +} + +/** + * lbist_enable_isolation() - LBIST Enable Isolation + * @config: lbist_config structure for LBIST test + */ +void lbist_enable_isolation(void) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_SPARE0); + writel(reg_val | (LBIST_SPARE0_LBIST_SELFTEST_EN_MASK), base + LBIST_SPARE0); +} + +/** + * lbist_disable_isolation() - LBIST Disable Isolation + * @config: lbist_config structure for LBIST test + */ +void lbist_disable_isolation(void) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_SPARE0); + writel(reg_val & (~(LBIST_SPARE0_LBIST_SELFTEST_EN_MASK)), base + LBIST_SPARE0); +} + +/** + * lbist_enable_run_bist_mode() - LBIST Enable run BIST mode + * @config: lbist_config structure for LBIST test + */ +static void lbist_enable_run_bist_mode(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT), + base + LBIST_CTRL); +} + +/** + * lbist_start() - Start LBIST test + * @config: lbist_config structure for LBIST test + */ +static void lbist_start(struct lbist_config *config) +{ + struct udevice *dev = k3_bist_priv->dev; + void *base = k3_bist_priv->lbist_ctrl_mmr; + u32 reg_val; + u32 timeout_count = 0; + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT), + base + LBIST_CTRL); + + reg_val = readl(base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT), + base + LBIST_CTRL); + + reg_val = readl(base + LBIST_STAT); + if ((reg_val & LBIST_STAT_BIST_RUNNING_MASK) != 0) + debug("%s(dev=%p): LBIST is running\n", __func__, dev); + + while (((!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK))) && + (timeout_count++ < PBIST_MAX_TIMEOUT_VALUE)) { + } + + if (!(readl(base + LBIST_STAT) & LBIST_STAT_BIST_DONE_MASK)) + printf("%s(dev=%p): test failed\n", __func__, dev); +} + +/** + * lbist_check_result() - Check LBIST test result + * @config: lbist_config structure for LBIST test + * + * Return: 0 if all went fine, else corresponding error. + */ +static int lbist_check_result(struct lbist_config *config) +{ + void *base = k3_bist_priv->lbist_ctrl_mmr; + struct lbist_inst_info *info = k3_bist_priv->lbist_info; + u32 calculated_misr; + u32 expected_misr; + + lbist_get_misr(base, &calculated_misr); + expected_misr = info->expected_misr; + lbist_clear_run_bist_mode(base); + lbist_stop(base); + lbist_reset(base); + + if (calculated_misr != expected_misr) { + printf("calculated_misr != expected_misr\n %x %x\n", + calculated_misr, expected_misr); + return -EINVAL; + } + + return 0; +} + +static int k3_run_lbist(void) +{ + /* Check whether HW POST successfully completely LBIST on the MCU domain */ + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + + lbist_program_config(&info_lbist->lbist_conf); + lbist_enable_isolation(); + lbist_reset(&info_lbist->lbist_conf); + lbist_enable_run_bist_mode(&info_lbist->lbist_conf); + lbist_start(&info_lbist->lbist_conf); + if (lbist_check_result(&info_lbist->lbist_conf)) { + printf("%s: test failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int k3_run_lbist_post(void) +{ + if (check_post_lbist_result()) { + printf("HW POST LBIST failed to run successfully\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist_post(void) +{ + /* Check whether HW POST successfully completely PBIST on the MCU domain */ + if (check_post_pbist_result()) { + printf("HW POST failed to run successfully\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist(void) +{ + /* Run PBIST test */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + int num_runs = info->num_pbist_runs; + + for (int j = 0; j < num_runs; j++) { + if (pbist_self_test(&info->pbist_config_run[j])) { + printf("failed to run PBIST test\n"); + return -EINVAL; + } + } + + return 0; +} + +static int k3_run_pbist_neg(void) +{ + /* Run PBIST failure insertion test */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + + if (pbist_neg_self_test(&info->pbist_neg_config_run)) { + printf("failed to run PBIST negative test\n"); + return -EINVAL; + } + + return 0; +} + +static int k3_run_pbist_rom(void) +{ + /* Run PBIST test on ROM */ + struct pbist_inst_info *info = k3_bist_priv->pbist_info; + int num_runs = info->num_pbist_rom_test_runs; + + for (int j = 0; j < num_runs; j++) { + if (pbist_rom_self_test(&info->pbist_rom_test_config_run[j])) { + printf("failed to run ROM PBIST test\n"); + return -EINVAL; + } + } + + return 0; +} + +int prepare_pbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info; + struct core_under_test *cut = info_pbist->cut; + + if (proc_ops->proc_request(handle, cut[0].proc_id)) { + printf("%s: requesting primary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_request(handle, cut[1].proc_id)) { + printf("%s: requesting secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0x1)) { + printf("%s: local reset primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0x1)) { + printf("%s: local reset secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, cut[0].dev_id)) { + printf("%s: power on primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, cut[1].dev_id)) { + printf("%s: power on secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->get_device(handle, info_pbist->dev_id)) { + printf("%s: power on PBIST failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int deprepare_pbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct pbist_inst_info *info_pbist = k3_bist_priv->pbist_info; + struct core_under_test *cut = info_pbist->cut; + + if (dev_ops->put_device(handle, info_pbist->dev_id)) { + printf("%s: power off PBIST failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[1].dev_id)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[0].dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[0].dev_id, 0)) { + printf("%s: putting primary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut[1].dev_id, 0)) { + printf("%s: putting secondary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[0].dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut[1].dev_id)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut[0].proc_id)) { + printf("%s: release primary core failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut[1].proc_id)) { + printf("%s: release secondary core failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int prepare_lbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + struct core_under_test *cut = &info_lbist->cut; + + if (proc_ops->proc_request(handle, cut->proc_id)) { + printf("%s: requesting primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut->dev_id, 0x3)) { + printf("%s: module and local reset primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->idle_device(handle, cut->dev_id)) { + printf("%s: putting primary core into retention failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +int deprepare_lbist(struct ti_sci_handle *handle) +{ + struct ti_sci_proc_ops *proc_ops = &handle->ops.proc_ops; + struct ti_sci_dev_ops *dev_ops = &handle->ops.dev_ops; + struct lbist_inst_info *info_lbist = k3_bist_priv->lbist_info; + struct core_under_test *cut = &info_lbist->cut; + + if (dev_ops->put_device(handle, 0)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut->dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + lbist_disable_isolation(); + + if (dev_ops->idle_device(handle, cut->dev_id)) { + printf("%s: retention primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->idle_device(handle, 0)) { + printf("%s: retention secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, 0)) { + printf("%s: power off secondary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->put_device(handle, cut->dev_id)) { + printf("%s: power off primary core failed\n", __func__); + return -EINVAL; + } + + if (dev_ops->set_device_resets(handle, cut->dev_id, 0)) { + printf("%s: putting primary core out of local reset failed\n", __func__); + return -EINVAL; + } + + if (proc_ops->proc_release(handle, cut->proc_id)) { + printf("%s: release primary core failed\n", __func__); + return -EINVAL; + } + + return 0; +} + +/** + * k3_bist_probe() - Basic probe + * @dev: corresponding BIST device + * + * Parses BIST info from device tree, and configures the module accordingly. + * Return: 0 if all goes good, else appropriate error message. + */ +static int k3_bist_probe(struct udevice *dev) +{ + int ret = 0; + struct k3_bist_privdata *priv = dev_get_priv(dev); + struct pbist_inst_info *info; + struct lbist_inst_info *info_lbist; + void *reg; + + debug("%s(dev=%p)\n", __func__, dev); + + priv = dev_get_priv(dev); + priv->dev = dev; + + k3_bist_priv = priv; + + reg = dev_read_addr_name_ptr(dev, "cfg"); + if (!reg) { + dev_err(dev, "No reg property for BIST\n"); + return -EINVAL; + } + priv->pbist_base = reg; + + reg = dev_read_addr_name_ptr(dev, "ctrl_mmr"); + if (!reg) { + dev_err(dev, "No reg property for CTRL MMR\n"); + return -EINVAL; + } + priv->lbist_ctrl_mmr = reg; + + ret = dev_read_u32(dev, "ti,sci-dev-id", &priv->instance); + if (!priv->instance) + return -ENODEV; + + switch (priv->instance) { + case PBIST14_DEV_ID: + priv->pbist_info = &pbist14_inst_info; + priv->lbist_info = &lbist_inst_info_main_r5f2_x; + info = priv->pbist_info; + info_lbist = priv->lbist_info; + priv->intr_num = info->intr_num; + break; + default: + dev_err(dev, "%s: PBIST instance %d not supported\n", __func__, priv->instance); + return -ENODEV; + }; + + return 0; +} + +static const struct bist_ops k3_bist_ops = { + .run_lbist = k3_run_lbist, + .run_lbist_post = k3_run_lbist_post, + .run_pbist = k3_run_pbist, + .run_pbist_post = k3_run_pbist_post, + .run_pbist_neg = k3_run_pbist_neg, + .run_pbist_rom = k3_run_pbist_rom, +}; + +static const struct udevice_id k3_bist_ids[] = { + { .compatible = "ti,j784s4-bist" }, + {} +}; + +U_BOOT_DRIVER(k3_bist) = { + .name = "k3_bist", + .of_match = k3_bist_ids, + .id = UCLASS_MISC, + .ops = &k3_bist_ops, + .probe = k3_bist_probe, + .priv_auto = sizeof(struct k3_bist_privdata), +}; diff --git a/drivers/misc/k3_bist_static_data.h b/drivers/misc/k3_bist_static_data.h new file mode 100644 index 00000000000..af371d83724 --- /dev/null +++ b/drivers/misc/k3_bist_static_data.h @@ -0,0 +1,673 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Static Data for Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#ifndef __K3_BIST_STATIC_DATA_H +#define __K3_BIST_STATIC_DATA_H + +/* + * Registers and functions related to PBIST + */ + +#define PBIST_MAX_NUM_RUNS 2 +#define NUM_MAX_PBIST_TEST_ROM_RUNS 13 +#define PBIST14_DFT_PBIST_CPU_0_INTR_NUM 311 + +/* VIM Registers */ +#define VIM_STS_BASE 0x40f80404 +#define VIM_RAW_BASE 0x40f80400 + +#define VIM_STS(i) (VIM_STS_BASE + (i) / 32 * 0x20) +#define VIM_RAW(i) (VIM_RAW_BASE + (i) / 32 * 0x20) +#define VIM_RAW_MASK(i) (BIT((i) % 32)) + +/* PBIST Registers and Flags*/ +#define PBIST_RF0L 0x00000000 +#define PBIST_RF1L 0x00000004 +#define PBIST_RF2L 0x00000008 +#define PBIST_RF3L 0x0000000C +#define PBIST_RF4L 0x0000010 +#define PBIST_RF5L 0x0000014 +#define PBIST_RF6L 0x0000018 +#define PBIST_RF7L 0x000001C +#define PBIST_RF8L 0x0000020 +#define PBIST_RF9L 0x0000024 +#define PBIST_RF10L 0x0000028 +#define PBIST_RF11L 0x000002C +#define PBIST_RF12L 0x0000030 +#define PBIST_RF13L 0x0000034 +#define PBIST_RF14L 0x0000038 +#define PBIST_RF15L 0x000003C +#define PBIST_RF0U 0x0000040 +#define PBIST_RF1U 0x0000044 +#define PBIST_RF2U 0x0000048 +#define PBIST_RF3U 0x000004C +#define PBIST_RF4U 0x0000050 +#define PBIST_RF5U 0x0000054 +#define PBIST_RF6U 0x0000058 +#define PBIST_RF7U 0x000005C +#define PBIST_RF8U 0x0000060 +#define PBIST_RF9U 0x0000064 +#define PBIST_RF10U 0x0000068 +#define PBIST_RF11U 0x000006C +#define PBIST_RF12U 0x0000070 +#define PBIST_RF13U 0x0000074 +#define PBIST_RF14U 0x0000078 +#define PBIST_RF15U 0x000007C +#define PBIST_A0 0x0000100 +#define PBIST_A1 0x0000104 +#define PBIST_A2 0x0000108 +#define PBIST_A3 0x000010C +#define PBIST_L0 0x0000110 +#define PBIST_L1 0x0000114 +#define PBIST_L2 0x0000118 +#define PBIST_L3 0x000011C +#define PBIST_D 0x0000120 +#define PBIST_E 0x0000124 +#define PBIST_CA0 0x0000130 +#define PBIST_CA1 0x0000134 +#define PBIST_CA2 0x0000138 +#define PBIST_CA3 0x000013C +#define PBIST_CL0 0x0000140 +#define PBIST_CL1 0x0000144 +#define PBIST_CL2 0x0000148 +#define PBIST_CL3 0x000014C +#define PBIST_I0 0x0000150 +#define PBIST_I1 0x0000154 +#define PBIST_I2 0x0000158 +#define PBIST_I3 0x000015C +#define PBIST_RAMT 0x0000160 +#define PBIST_DLR 0x0000164 +#define PBIST_CMS 0x0000168 +#define PBIST_STR 0x000016C +#define PBIST_SCR 0x0000170 +#define PBIST_SCR_LO 0x0000170 +#define PBIST_SCR_HI 0x0000174 +#define PBIST_CSR 0x0000178 +#define PBIST_FDLY 0x000017C +#define PBIST_PACT 0x0000180 +#define PBIST_PID 0x0000184 +#define PBIST_OVER 0x0000188 +#define PBIST_FSRF 0x0000190 +#define PBIST_FSRC 0x0000198 +#define PBIST_FSRA 0x00001A0 +#define PBIST_FSRDL0 0x00001A8 +#define PBIST_FSRDL1 0x00001B0 +#define PBIST_MARGIN_MODE 0x00001B4 +#define PBIST_WRENZ 0x00001B8 +#define PBIST_PAGE_PGS 0x00001BC +#define PBIST_ROM 0x00001C0 +#define PBIST_ALGO 0x00001C4 +#define PBIST_RINFO 0x00001C8 + +#define PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK 0x00000003 +#define PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT 0x00000002 +#define PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK 0x0000000C +#define PBIST_PACT_PACT_MASK 0x00000001 +#define PBIST_DLR_DLR0_ROM_MASK 0x00000004 +#define PBIST_DLR_DLR0_CAM_MASK 0x00000010 +#define PBIST_NOT_DONE 0 +#define PBIST_DONE 1 + +/* PBIST test mode */ +#define PBIST_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \ + | (1 << PBIST_MARGIN_MODE_PBIST_DFT_READ_SHIFT)) + +/* PBIST Failure Insertion test mode */ +#define PBIST_FAILURE_INSERTION_TEST_MODE (PBIST_MARGIN_MODE_PBIST_DFT_WRITE_MASK \ + | PBIST_MARGIN_MODE_PBIST_DFT_READ_MASK) + +/** + * struct core_under_test - structure for a core under a BIST test + * @dev_id: Device ID of the core + * @proc_id: Processor ID of the core + */ +struct core_under_test { + u32 dev_id; + u32 proc_id; +}; + +/* + * struct pbist_config - Structure for different configuration used for PBIST + * @override: Override value for memory configuration + * @algorithms_bit_map: Bitmap to select algorithms to use for test + * @memory_groups_bit_map: Bitmap to select memory groups to run test on + * @scramble_value_lo: Lower scramble value to be used for test + * @scramble_value_hi: Higher scramble value to be used for test + */ +struct pbist_config { + u32 override; + u32 algorithms_bit_map; + u64 memory_groups_bit_map; + u32 scramble_value_lo; + u32 scramble_value_hi; +}; + +/* + * struct pbist_config_neg - Structure for different configuration used for PBIST + * for the failure insertion test to generate negative result + * @CA0: Failure insertion value for CA0 + * @CA1: Failure insertion value for CA1 + * @CA2: Failure insertion value for CA2 + * @CA3: Failure insertion value for CA3 + * @CL0: Failure insertion value for CL0 + * @CL1: Failure insertion value for CL1 + * @CL2: Failure insertion value for CL2 + * @CL3: Failure insertion value for CL3 + * @CMS: Failure insertion value for CMS + * @CSR: Failure insertion value for CSR + * @I0: Failure insertion value for I0 + * @I1: Failure insertion value for I1 + * @I2: Failure insertion value for I2 + * @I3: Failure insertion value for I3 + * @RAMT: Failure insertion value for RAMT + */ +struct pbist_config_neg { + u32 CA0; + u32 CA1; + u32 CA2; + u32 CA3; + u32 CL0; + u32 CL1; + u32 CL2; + u32 CL3; + u32 CMS; + u32 CSR; + u32 I0; + u32 I1; + u32 I2; + u32 I3; + u32 RAMT; +}; + +/* + * struct pbist_config_neg - Structure for different configuration used for PBIST + * test of ROM + * @D: ROM test value for D + * @E: ROM test value for E + * @CA2: ROM test value for CA2 + * @CL0: ROM test value for CL0 + * @CA3: ROM test value for CA3 + * @I0: ROM test value for I0 + * @CL1: ROM test value for CL1 + * @I3: ROM test value for I3 + * @I2: ROM test value for I2 + * @CL2: ROM test value for CL2 + * @CA1: ROM test value for CA1 + * @CA0: ROM test value for CA0 + * @CL3: ROM test value for CL3 + * @I1: ROM test value for I1 + * @RAMT: ROM test value for RAMT + * @CSR: ROM test value for CSR + * @CMS: ROM test value for CMS + */ +struct pbist_config_rom { + u32 D; + u32 E; + u32 CA2; + u32 CL0; + u32 CA3; + u32 I0; + u32 CL1; + u32 I3; + u32 I2; + u32 CL2; + u32 CA1; + u32 CA0; + u32 CL3; + u32 I1; + u32 RAMT; + u32 CSR; + u32 CMS; +}; + +/* + * struct pbist_inst_info - Structure for different configuration used for PBIST + * @num_pbist_runs: Number of runs of PBIST test + * @intr_num: Interrupt number triggered by this PBIST instance to MCU R5 VIM + * @pbist_config_run: Configuration for PBIST test + * @pbist_neg_config_run: Configuration for PBIST negative test + * @num_pbist_rom_test_runs: Number of runs of PBIST test on ROM + * @pbist_rom_test_config_run: Configuration for PBIST test on ROM + */ +struct pbist_inst_info { + u32 num_pbist_runs; + u32 intr_num; + u32 dev_id; + struct core_under_test cut[2]; + struct pbist_config pbist_config_run[PBIST_MAX_NUM_RUNS]; + struct pbist_config_neg pbist_neg_config_run; + u32 num_pbist_rom_test_runs; + struct pbist_config_rom pbist_rom_test_config_run[NUM_MAX_PBIST_TEST_ROM_RUNS]; +}; + +/* + * Registers and functions related to LBIST + */ + +#define LBIST_CTRL_DIVIDE_RATIO_MASK 0x0000001F +#define LBIST_CTRL_DIVIDE_RATIO_SHIFT 0x00000000 +#define LBIST_CTRL_DIVIDE_RATIO_MAX 0x0000001F + +#define LBIST_CTRL_LOAD_DIV_MASK 0x00000080 +#define LBIST_CTRL_LOAD_DIV_SHIFT 0x00000007 +#define LBIST_CTRL_LOAD_DIV_MAX 0x00000001 + +#define LBIST_CTRL_DC_DEF_MASK 0x00000300 +#define LBIST_CTRL_DC_DEF_SHIFT 0x00000008 +#define LBIST_CTRL_DC_DEF_MAX 0x00000003 + +#define LBIST_CTRL_RUNBIST_MODE_MASK 0x0000F000 +#define LBIST_CTRL_RUNBIST_MODE_SHIFT 0x0000000C +#define LBIST_CTRL_RUNBIST_MODE_MAX 0x0000000F + +#define LBIST_CTRL_BIST_RUN_MASK 0x0F000000 +#define LBIST_CTRL_BIST_RUN_SHIFT 0x00000018 +#define LBIST_CTRL_BIST_RUN_MAX 0x0000000F + +#define LBIST_CTRL_BIST_RESET_MASK 0x80000000 +#define LBIST_CTRL_BIST_RESET_SHIFT 0x0000001F +#define LBIST_CTRL_BIST_RESET_MAX 0x00000001 + +/* LBIST_PATCOUNT */ + +#define LBIST_PATCOUNT_SCAN_PC_DEF_MASK 0x0000000F +#define LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT 0x00000000 +#define LBIST_PATCOUNT_SCAN_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_RESET_PC_DEF_MASK 0x000000F0 +#define LBIST_PATCOUNT_RESET_PC_DEF_SHIFT 0x00000004 +#define LBIST_PATCOUNT_RESET_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_SET_PC_DEF_MASK 0x00000F00 +#define LBIST_PATCOUNT_SET_PC_DEF_SHIFT 0x00000008 +#define LBIST_PATCOUNT_SET_PC_DEF_MAX 0x0000000F + +#define LBIST_PATCOUNT_STATIC_PC_DEF_MASK 0x3FFF0000 +#define LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT 0x00000010 +#define LBIST_PATCOUNT_STATIC_PC_DEF_MAX 0x00003FFF + +/* LBIST_SEED0 */ + +#define LBIST_SEED0_PRPG_DEF_MASK 0xFFFFFFFF +#define LBIST_SEED0_PRPG_DEF_SHIFT 0x00000000 +#define LBIST_SEED0_PRPG_DEF_MAX 0xFFFFFFFF + +/* LBIST_SEED1 */ + +#define LBIST_SEED1_PRPG_DEF_MASK 0x001FFFFF +#define LBIST_SEED1_PRPG_DEF_SHIFT 0x00000000 +#define LBIST_SEED1_PRPG_DEF_MAX 0x001FFFFF + +/* LBIST_SPARE0 */ + +#define LBIST_SPARE0_LBIST_SELFTEST_EN_MASK 0x00000001 +#define LBIST_SPARE0_LBIST_SELFTEST_EN_SHIFT 0x00000000 +#define LBIST_SPARE0_LBIST_SELFTEST_EN_MAX 0x00000001 + +#define LBIST_SPARE0_PBIST_SELFTEST_EN_MASK 0x00000002 +#define LBIST_SPARE0_PBIST_SELFTEST_EN_SHIFT 0x00000001 +#define LBIST_SPARE0_PBIST_SELFTEST_EN_MAX 0x00000001 + +#define LBIST_SPARE0_SPARE0_MASK 0xFFFFFFFC +#define LBIST_SPARE0_SPARE0_SHIFT 0x00000002 +#define LBIST_SPARE0_SPARE0_MAX 0x3FFFFFFF + +/* LBIST_SPARE1 */ + +#define LBIST_SPARE1_SPARE1_MASK 0xFFFFFFFF +#define LBIST_SPARE1_SPARE1_SHIFT 0x00000000 +#define LBIST_SPARE1_SPARE1_MAX 0xFFFFFFFF + +/* LBIST_STAT */ + +#define LBIST_STAT_MISR_MUX_CTL_MASK 0x000000FF +#define LBIST_STAT_MISR_MUX_CTL_SHIFT 0x00000000 +#define LBIST_STAT_MISR_MUX_CTL_MAX 0x000000FF + +#define LBIST_STAT_OUT_MUX_CTL_MASK 0x00000300 +#define LBIST_STAT_OUT_MUX_CTL_SHIFT 0x00000008 +#define LBIST_STAT_OUT_MUX_CTL_MAX 0x00000003 + +#define LBIST_STAT_BIST_RUNNING_MASK 0x00008000 +#define LBIST_STAT_BIST_RUNNING_SHIFT 0x0000000F +#define LBIST_STAT_BIST_RUNNING_MAX 0x00000001 + +#define LBIST_STAT_BIST_DONE_MASK 0x80000000 +#define LBIST_STAT_BIST_DONE_SHIFT 0x0000001F +#define LBIST_STAT_BIST_DONE_MAX 0x00000001 + +/* LBIST_MISR */ + +#define LBIST_MISR_MISR_RESULT_MASK 0xFFFFFFFF +#define LBIST_MISR_MISR_RESULT_SHIFT 0x00000000 +#define LBIST_MISR_MISR_RESULT_MAX 0xFFFFFFFF + +#define CTRL_MMR0_CFG0_BASE 0x00100000 +#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL 0x0000C1A0 +#define MAIN_R5F2_LBIST_BASE (CTRL_MMR0_CFG0_BASE +\ + MAIN_CTRL_MMR_CFG0_MCU2_LBIST_CTRL) + +#define LBIST_CTRL 0x00000000 +#define LBIST_PATCOUNT 0x00000004 +#define LBIST_SEED0 0x00000008 +#define LBIST_SEED1 0x0000000C +#define LBIST_SPARE0 0x00000010 +#define LBIST_SPARE1 0x00000014 +#define LBIST_STAT 0x00000018 +#define LBIST_MISR 0x0000001C + +#define MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG 0x0000C2C0 +#define MAIN_R5F2_LBIST_SIG (CTRL_MMR0_CFG0_BASE +\ + MAIN_CTRL_MMR_CFG0_MCU2_LBIST_SIG) +#define MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0 284 + +/* Lbist Parameters */ +#define LBIST_DC_DEF 0x3 +#define LBIST_DIVIDE_RATIO 0x02 +#define LBIST_STATIC_PC_DEF 0x3ac0 +#define LBIST_RESET_PC_DEF 0x0f +#define LBIST_SET_PC_DEF 0x00 +#define LBIST_SCAN_PC_DEF 0x04 +#define LBIST_PRPG_DEF_L 0xFFFFFFFF +#define LBIST_PRPG_DEF_U 0x1FFFFF + +/* + * LBIST setup parameters for each core + */ + +#define LBIST_MAIN_R5_STATIC_PC_DEF LBIST_STATIC_PC_DEF +#define LBIST_C7X_STATIC_PC_DEF 0x3fc0 +#define LBIST_A72_STATIC_PC_DEF 0x3fc0 +#define LBIST_DMPAC_STATIC_PC_DEF 0x1880 +#define LBIST_VPAC_STATIC_PC_DEF 0x3fc0 +#define LBIST_A72SS_STATIC_PC_DEF 0x13c0 + +/* + * LBIST expected MISR's (using parameters above) + */ + +#define MAIN_R5_MISR_EXP_VAL 0x71d66f87 +#define A72_MISR_EXP_VAL 0x14df0200 +#define C7X_MISR_EXP_VAL 0x57b0478f +#define VPAC_MISR_EXP_VAL 0xec6abe22 +#define VPAC0_MISR_EXP_VAL 0x5c43b468 +#define DMPAC_MISR_EXP_VAL 0x53e1ef7b +#define A72SS_MISR_EXP_VAL 0x87da5a92 + +/** + * lbist_set_clock_delay() - Set seed for LBIST + * @ctrl_mmr_base: CTRL MMR base + * @clock_delay: clock delay + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_clock_delay(void *ctrl_mmr_base, u32 clock_delay) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base); + writel(reg_val & LBIST_CTRL_DC_DEF_MASK, ctrl_mmr_base); + + reg_val = readl(ctrl_mmr_base); + writel(reg_val | ((clock_delay & LBIST_CTRL_DC_DEF_MAX) + << LBIST_CTRL_DC_DEF_SHIFT), ctrl_mmr_base); +} + +/** + * lbist_set_seed() - Set seed for LBIST + * @config: lbist_config structure for LBIST test + * @seed: seed + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_seed(void *ctrl_mmr_base, u32 seed_l, u32 seed_u) +{ + writel(seed_l & LBIST_SEED0_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED0); + writel(seed_u & LBIST_SEED1_PRPG_DEF_MASK, ctrl_mmr_base + LBIST_SEED1); +} + +/** + * set_num_chain_test_patterns() - Set chain test patterns + * @ctrl_mmr_base: CTRL MMR base + * @chain_test_patterns: chain test patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_chain_test_patterns(void *ctrl_mmr_base, u32 chain_test_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_SCAN_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((chain_test_patterns & LBIST_PATCOUNT_SCAN_PC_DEF_MAX) + << LBIST_PATCOUNT_SCAN_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_reset_patterns() - Set reset patterns + * @ctrl_mmr_base: CTRL MMR base + * @reset_patterns: reset patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_reset_patterns(void *ctrl_mmr_base, u32 reset_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_RESET_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((reset_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX) + << LBIST_PATCOUNT_RESET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_set_patterns() - Set patterns + * @ctrl_mmr_base: CTRL MMR base + * @set_patterns: set patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_set_patterns(void *ctrl_mmr_base, u32 set_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_SET_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((set_patterns & LBIST_PATCOUNT_RESET_PC_DEF_MAX) + << LBIST_PATCOUNT_SET_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_num_stuck_at_patterns() - Set + * @ctrl_mmr_base: CTRL MMR base + * @stuck_at_patterns: set patterns + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_num_stuck_at_patterns(void *ctrl_mmr_base, u32 stuck_at_patterns) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val & (~(LBIST_PATCOUNT_STATIC_PC_DEF_MASK)), + ctrl_mmr_base + LBIST_PATCOUNT); + + reg_val = readl(ctrl_mmr_base + LBIST_PATCOUNT); + writel(reg_val | ((stuck_at_patterns & LBIST_PATCOUNT_STATIC_PC_DEF_MAX) + << LBIST_PATCOUNT_STATIC_PC_DEF_SHIFT), ctrl_mmr_base + LBIST_PATCOUNT); +} + +/** + * set_divide_ratio() - Set divide ratio + * @ctrl_mmr_base: CTRL MMR base + * @divide_ratio: divide ratio + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_divide_ratio(void *ctrl_mmr_base, u32 divide_ratio) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_DIVIDE_RATIO_MASK)), ctrl_mmr_base + LBIST_CTRL); + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val | (divide_ratio & LBIST_CTRL_DIVIDE_RATIO_MASK), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * clear_load_div() - Clear load div + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_clear_load_div(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_LOAD_DIV_MASK)), ctrl_mmr_base + LBIST_CTRL); +} + +/** + * set_load_div() - Set load div + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_set_load_div(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val | (LBIST_CTRL_LOAD_DIV_MASK), ctrl_mmr_base + LBIST_CTRL); +} + +/* MACRO DEFINES */ +#define LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR 0x0 + +#define LBIST_STAT_OUT_MUX_CTL_CTRLMMR_PID 0x0 +#define LBIST_STAT_OUT_MUX_CTL_CTRL_ID 0x1 +#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1 0x2 +#define LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_2 0x3 + +/** + * lbist_get_misr() - Get MISR + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_get_misr(void *ctrl_mmr_base, u32 *p_misr_val) +{ + u32 reg_val; + u32 mux_val; + + reg_val = LBIST_STAT_MISR_MUX_CTL_COMPACT_MISR; + mux_val = LBIST_STAT_OUT_MUX_CTL_MISR_VALUE_1; + reg_val |= (mux_val << LBIST_STAT_OUT_MUX_CTL_SHIFT); + writel(reg_val, ctrl_mmr_base + LBIST_STAT); + *p_misr_val = readl(ctrl_mmr_base + LBIST_MISR); +} + +/** + * lbist_clear_run_bist_mode() - Clear RUN_BIST_MODE + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_clear_run_bist_mode(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_RUNBIST_MODE_MAX << LBIST_CTRL_RUNBIST_MODE_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * lbist_stop() - Stop running LBIST + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_stop(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_BIST_RUN_MAX << LBIST_CTRL_BIST_RUN_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/** + * lbist_reset() - Reset LBIST + * @ctrl_mmr_base: CTRL MMR base + * + * Return: 0 if all went fine, else corresponding error. + */ +static void lbist_reset(void *ctrl_mmr_base) +{ + u32 reg_val; + + reg_val = readl(ctrl_mmr_base + LBIST_CTRL); + writel(reg_val & (~(LBIST_CTRL_BIST_RESET_MAX << LBIST_CTRL_BIST_RESET_SHIFT)), + ctrl_mmr_base + LBIST_CTRL); +} + +/* + * struct lbist_config - Structure containing different configuration used for LBIST + * @dc_def: Clock delay after scan_enable switching + * @divide_ratio: LBIST clock divide ratio + * @static_pc_def: Bitmap of stuck-at patterns to run + * @set_pc_def: Bitmap of set patterns to run + * @reset_pc_def: Bitmap of reset patterns to run + * @scan_pc_def: Bitmap of chain test patterns to run + * @prpg_def: Initial seed for Pseudo Random Pattern generator (PRPG) + */ +struct lbist_config { + u32 dc_def; + u32 divide_ratio; + u32 static_pc_def; + u32 set_pc_def; + u32 reset_pc_def; + u32 scan_pc_def; + u32 prpg_def_l; + u32 prpg_def_u; +}; + +/* + * struct lbist_inst_info - Structure for different configuration used for LBIST + * @lbist_signature: Pointer to LBIST signature + * @intr_num: Interrupt number triggered by this LBIST instance to MCU R5 VIM + * @expected_misr: Expected signature + * @lbist_config: Configuration for LBIST test + */ +struct lbist_inst_info { + u32 *lbist_signature; + u32 intr_num; + u32 expected_misr; + struct lbist_config lbist_conf; + struct core_under_test cut; +}; + +#if IS_ENABLED(CONFIG_SOC_K3_J784S4) + +#include "k3_j784s4_bist_static_data.h" + +#endif /* CONFIG_SOC_K3_J784S4 */ +#endif /* __K3_BIST_STATIC_DATA_H */ diff --git a/drivers/misc/k3_j784s4_bist_static_data.h b/drivers/misc/k3_j784s4_bist_static_data.h new file mode 100644 index 00000000000..7f9378e917f --- /dev/null +++ b/drivers/misc/k3_j784s4_bist_static_data.h @@ -0,0 +1,370 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Static Data for Texas Instruments' BIST logic for J784S4 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +/* Device IDs of IPs that can be tested under BIST */ +#define TISCI_DEV_MCU_R5FSS2_CORE0 343 +#define TISCI_DEV_MCU_R5FSS2_CORE1 344 +#define TISCI_DEV_RTI32 365 +#define TISCI_DEV_RTI33 366 + +/* WKUP CTRL MMR Registers */ +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT 0x0000C2C0 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_DONE_SHIFT 0x00000008 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_DONE_SHIFT 0x00000001 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_TIMEOUT_SHIFT 0x00000009 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_LBIST_TIMEOUT_SHIFT 0x00000005 +#define WKUP_CTRL_MMR_CFG0_WKUP_POST_STAT_POST_MCU_PBIST_FAIL_MASK 0x00008000 + +/* MCU CTRL MMR Register */ +#define MCU_CTRL_MMR0_CFG0_BASE 0x40f00000 +#define MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL 0x0000c000 +#define MCU_CTRL_MMR_CFG0_MCU_LBIST_SIG 0x0000c280 +#define MCU_LBIST_BASE (MCU_CTRL_MMR0_CFG0_BASE + \ + MCU_CTRL_MMR_CFG0_MCU_LBIST_CTRL) + +/* Properties of PBIST instances in: PBIST14 */ +#define PBIST14_DEV_ID 234 +#define PBIST14_NUM_TEST_VECTORS 0x1 +#define PBIST14_ALGO_BITMAP_0 0x00000003 +#define PBIST14_MEM_BITMAP_0 0x000CCCCC +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0 0x0000007F +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1 0x00000003 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2 0x00000008 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3 0x000001FF +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR 0x20000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I0 0x00000001 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I1 0x00000004 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I2 0x00000008 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_I3 0x00000000 +#define PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT 0x011D2528 + +static struct pbist_inst_info pbist14_inst_info = { + /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ + .num_pbist_runs = 1, + .intr_num = PBIST14_DFT_PBIST_CPU_0_INTR_NUM, + .dev_id = TISCI_DEV_PBIST14, + .cut = { + { + .dev_id = TISCI_DEV_R5FSS2_CORE0, + .proc_id = PROC_ID_MCU_R5FSS2_CORE0, + }, + { + .dev_id = TISCI_DEV_R5FSS2_CORE1, + .proc_id = PROC_ID_MCU_R5FSS2_CORE1, + } + }, + .pbist_config_run = { + { + .override = 0, + .algorithms_bit_map = PBIST14_ALGO_BITMAP_0, + .memory_groups_bit_map = PBIST14_MEM_BITMAP_0, + .scramble_value_lo = 0x76543210, + .scramble_value_hi = 0xFEDCBA98, + }, + { + .override = 0, + .algorithms_bit_map = 0, + .memory_groups_bit_map = 0, + .scramble_value_lo = 0, + .scramble_value_hi = 0, + }, + }, + .pbist_neg_config_run = { + .CA0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA0, + .CA1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA1, + .CA2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA2, + .CA3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CA3, + .CL0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL0, + .CL1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL1, + .CL2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL2, + .CL3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_CL3, + .CMS = PBIST14_FAIL_INSERTION_TEST_VECTOR_CMS, + .CSR = PBIST14_FAIL_INSERTION_TEST_VECTOR_CSR, + .I0 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I0, + .I1 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I1, + .I2 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I2, + .I3 = PBIST14_FAIL_INSERTION_TEST_VECTOR_I3, + .RAMT = PBIST14_FAIL_INSERTION_TEST_VECTOR_RAMT + }, + .num_pbist_rom_test_runs = 1, + .pbist_rom_test_config_run = { + { + .D = 0xF412605Eu, + .E = 0xF412605Eu, + .CA2 = 0x7FFFu, + .CL0 = 0x3FFu, + .CA3 = 0x0u, + .I0 = 0x1u, + .CL1 = 0x1Fu, + .I3 = 0x0u, + .I2 = 0xEu, + .CL2 = 0xEu, + .CA1 = 0x7FFFu, + .CA0 = 0x0u, + .CL3 = 0x7FFFu, + .I1 = 0x20u, + .RAMT = 0x08002020u, + .CSR = 0x00000001u, + .CMS = 0x01u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + { + .D = 0x0u, + .E = 0x0u, + .CA2 = 0x0u, + .CL0 = 0x0u, + .CA3 = 0x0u, + .I0 = 0x0u, + .CL1 = 0x0u, + .I3 = 0x0u, + .I2 = 0x0u, + .CL2 = 0x0u, + .CA1 = 0x0u, + .CA0 = 0x0u, + .CL3 = 0x0u, + .I1 = 0x0u, + .RAMT = 0x0u, + .CSR = 0x0u, + .CMS = 0x0u + }, + }, +}; + +static struct lbist_inst_info lbist_inst_info_main_r5f2_x = { + /* Main Pulsar 2 Instance 1 or MAIN_R52_x */ + .lbist_signature = (u32 *)(MAIN_R5F2_LBIST_SIG), + .intr_num = MCU_R5FSS0_CORE0_INTR_LBIST_BIST_DONE_0, + .expected_misr = MAIN_R5_MISR_EXP_VAL, + .lbist_conf = { + .dc_def = LBIST_DC_DEF, + .divide_ratio = LBIST_DIVIDE_RATIO, + .static_pc_def = LBIST_MAIN_R5_STATIC_PC_DEF, + .set_pc_def = LBIST_SET_PC_DEF, + .reset_pc_def = LBIST_RESET_PC_DEF, + .scan_pc_def = LBIST_SCAN_PC_DEF, + .prpg_def_l = LBIST_PRPG_DEF_L, + .prpg_def_u = LBIST_PRPG_DEF_U, + }, + .cut = { + .dev_id = TISCI_DEV_R5FSS2_CORE0, + .proc_id = PROC_ID_MCU_R5FSS2_CORE0, + }, +}; diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index c8bf89d6d35..12e37cb4b78 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -373,6 +373,12 @@ static const struct udevice_id exynos_dwmmc_ids[] = { .compatible = "samsung,exynos4412-dw-mshc", .data = (ulong)&exynos4_drv_data, }, { + .compatible = "samsung,exynos5420-dw-mshc-smu", + .data = (ulong)&exynos5_drv_data, + }, { + .compatible = "samsung,exynos5420-dw-mshc", + .data = (ulong)&exynos5_drv_data, + }, { .compatible = "samsung,exynos-dwmmc", .data = (ulong)&exynos5_drv_data, }, { diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index 90fcf2679bb..928c05872ca 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -155,6 +155,7 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, struct mmc_cmd cmd; struct mmc_data data; int timeout_ms = 1000; + int err; if ((start + blkcnt) > mmc_get_blk_desc(mmc)->lba) { printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", @@ -181,9 +182,13 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, data.blocksize = mmc->write_bl_len; data.flags = MMC_DATA_WRITE; - if (mmc_send_cmd(mmc, &cmd, &data)) { + err = mmc_send_cmd(mmc, &cmd, &data); + if (err) { printf("mmc write failed\n"); - return 0; + /* + * Don't return 0 here since the emmc will still be in data + * transfer mode continue to send the STOP_TRANSMISSION command + */ } /* SPI multiblock writes terminate using a special @@ -203,6 +208,9 @@ static ulong mmc_write_blocks(struct mmc *mmc, lbaint_t start, if (mmc_poll_for_busy(mmc, timeout_ms)) return 0; + if (err) + return 0; + return blkcnt; } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 278019f02ab..c80033d8752 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -141,14 +141,6 @@ static int do_sdhci_init(struct sdhci_host *host) } } - if (dm_gpio_is_valid(&host->cd_gpio)) { - ret = dm_gpio_get_value(&host->cd_gpio); - if (ret) { - debug("no SD card detected (%d)\n", ret); - return -ENODEV; - } - } - return s5p_sdhci_core_init(host); } @@ -183,8 +175,6 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) gpio_request_by_name_nodev(offset_to_ofnode(node), "pwr-gpios", 0, &host->pwr_gpio, GPIOD_IS_OUT); - gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios", 0, - &host->cd_gpio, GPIOD_IS_IN); return 0; } @@ -236,6 +226,7 @@ static int s5p_sdhci_bind(struct udevice *dev) static const struct udevice_id s5p_sdhci_ids[] = { { .compatible = "samsung,exynos4412-sdhci"}, + { .compatible = "samsung,exynos4210-sdhci"}, { } }; diff --git a/drivers/net/sandbox-raw-bus.c b/drivers/net/sandbox-raw-bus.c index 15670d6d24a..c698a07c784 100644 --- a/drivers/net/sandbox-raw-bus.c +++ b/drivers/net/sandbox-raw-bus.c @@ -42,7 +42,7 @@ static int eth_raw_bus_post_bind(struct udevice *dev) device_probe(child); priv = dev_get_priv(child); if (priv) { - strcpy(priv->host_ifname, i->if_name); + strlcpy(priv->host_ifname, i->if_name, IFNAMSIZ); priv->host_ifindex = i->if_index; priv->local = local; } diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c index 555651937f8..56f877c20a6 100644 --- a/drivers/net/xilinx_axi_mrmac.c +++ b/drivers/net/xilinx_axi_mrmac.c @@ -346,7 +346,7 @@ static bool isrxready(struct axi_mrmac_priv *priv) * axi_mrmac_recv - MRMAC Rx function * @dev: udevice structure * @flags: flags from network stack - * @packetp pointer to received data + * @packetp: pointer to received data * * Return: received data length on success, negative value on errors * @@ -399,7 +399,7 @@ static int axi_mrmac_recv(struct udevice *dev, int flags, uchar **packetp) * axi_mrmac_free_pkt - MRMAC free packet function * @dev: udevice structure * @packet: receive buffer pointer - * @length received data length + * @length: received data length * * Return: 0 on success, negative value on errors * diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index b44aae78e6d..a7e64971a2a 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -468,6 +468,8 @@ out_clk_disable: static int imx8m_power_domain_of_xlate(struct power_domain *power_domain, struct ofnode_phandle_args *args) { + power_domain->id = 0; + return 0; } diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 09567eb9dbb..2a59a1b79c2 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -260,13 +260,13 @@ int regulator_get_by_platname(const char *plat_name, struct udevice **devp) *devp = NULL; - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret) { - dev_dbg(dev, "ret=%d\n", ret); - continue; - } + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) { + dev_dbg(dev, "ret=%d\n", ret); + return ret; + } + for (; dev; uclass_find_next_device(&dev)) { uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata || strcmp(plat_name, uc_pdata->name)) continue; @@ -410,9 +410,12 @@ static bool regulator_name_is_unique(struct udevice *check_dev, int ret; int len; - for (ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret || dev == check_dev) + ret = uclass_find_first_device(UCLASS_REGULATOR, &dev); + if (ret) + return true; + + for (; dev; uclass_find_next_device(&dev)) { + if (dev == check_dev) continue; uc_pdata = dev_get_uclass_plat(dev); diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 3233ff80419..2dbd3a21cea 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -55,9 +55,12 @@ static int for_each_remoteproc_device(int (*fn) (struct udevice *dev, struct dm_rproc_uclass_pdata *uc_pdata; int ret; - for (ret = uclass_find_first_device(UCLASS_REMOTEPROC, &dev); dev; - ret = uclass_find_next_device(&dev)) { - if (ret || dev == skip_dev) + ret = uclass_find_first_device(UCLASS_REMOTEPROC, &dev); + if (ret) + return ret; + + for (; dev; uclass_find_next_device(&dev)) { + if (dev == skip_dev) continue; uc_pdata = dev_get_uclass_plat(dev); ret = fn(dev, uc_pdata, data); diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 6f89d3add5d..4696c09f754 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -559,9 +559,6 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, u8 opcode; if (priv->dtr) - txlen += txlen & 1; - - if (priv->dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; diff --git a/fs/exfat/exfat.h b/fs/exfat/exfat.h index ca6f22b9d58..bd2965c3942 100644 --- a/fs/exfat/exfat.h +++ b/fs/exfat/exfat.h @@ -237,8 +237,10 @@ int exfat_rename(struct exfat* ef, const char* old_path, const char* new_path); void exfat_utimes(struct exfat_node* node, const struct timespec tv[2]); void exfat_update_atime(struct exfat_node* node); void exfat_update_mtime(struct exfat_node* node); +#ifndef __UBOOT__ const char* exfat_get_label(struct exfat* ef); int exfat_set_label(struct exfat* ef, const char* label); +#endif /* __UBOOT__ */ int exfat_soil_super_block(const struct exfat* ef); int exfat_mount(struct exfat* ef, const char* spec, const char* options); diff --git a/fs/exfat/node.c b/fs/exfat/node.c index 88b1357189c..b7406fbf3ed 100644 --- a/fs/exfat/node.c +++ b/fs/exfat/node.c @@ -1188,6 +1188,7 @@ void exfat_update_mtime(struct exfat_node* node) node->is_dirty = true; } +#ifndef __UBOOT__ const char* exfat_get_label(struct exfat* ef) { return ef->label; @@ -1241,3 +1242,4 @@ int exfat_set_label(struct exfat* ef, const char* label) strcpy(ef->label, label); return 0; } +#endif /* __UBOOT__ */ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 94355cf61e4..e7db0161126 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -6,8 +6,6 @@ #ifndef __IMX93_EVK_H #define __IMX93_EVK_H -#include <linux/sizes.h> -#include <linux/stringify.h> #include <asm/arch/imx-regs.h> #define CFG_SYS_UBOOT_BASE \ diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h new file mode 100644 index 00000000000..987fcacb999 --- /dev/null +++ b/include/configs/imx93_frdm.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX93_FRDM_H +#define __IMX93_FRDM_H + +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_XPL_BUILD +#define CFG_MALLOC_F_ADDR 0x204D0000 +#endif + +/* Link Definitions */ + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif diff --git a/include/dm/uclass-internal.h b/include/dm/uclass-internal.h index 3ddcdd21439..9cb3f090271 100644 --- a/include/dm/uclass-internal.h +++ b/include/dm/uclass-internal.h @@ -149,10 +149,8 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp); * * The device is not prepared for use - this is an internal function. * The function uclass_get_device_tail() can be used to probe the device. - * - * Return: 0 if OK (found or not found), -ve on error */ -int uclass_find_next_device(struct udevice **devp); +void uclass_find_next_device(struct udevice **devp); /** * uclass_find_device_by_namelen() - Find uclass device based on ID and name diff --git a/include/fpga.h b/include/fpga.h index 4cc44164b2f..a144238e66a 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -79,7 +79,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, int fpga_dump(int devnum, const void *buf, size_t bsize); int fpga_info(int devnum); const fpga_desc *fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn); + size_t bsize); int fpga_compatible2flag(int devnum, const char *compatible); #endif /* _FPGA_H_ */ diff --git a/include/k3_bist.h b/include/k3_bist.h new file mode 100644 index 00000000000..cc650f5a8c4 --- /dev/null +++ b/include/k3_bist.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Texas Instruments' BIST (Built-In Self-Test) driver + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * Neha Malcom Francis <n-francis@ti.com> + * + */ + +#ifndef _INCLUDE_BIST_H_ +#define _INCLUDE_BIST_H_ + +#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 +#define PROC_ID_MCU_R5FSS2_CORE0 0x0A +#define PROC_ID_MCU_R5FSS2_CORE1 0x0B +#define PROC_BOOT_CTRL_FLAG_R5_LPSC 0x00000002 + +#define TISCI_DEV_PBIST14 237 +#define TISCI_DEV_R5FSS2_CORE0 343 +#define TISCI_DEV_R5FSS2_CORE1 344 + +#define TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF 0 +#define TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION 1 +#define TISCI_MSG_VALUE_DEVICE_SW_STATE_ON 2 + +#define TISCI_BIT(n) ((1) << (n)) + +struct bist_ops { + int (*run_lbist)(void); + int (*run_lbist_post)(void); + int (*run_pbist_post)(void); + int (*run_pbist_neg)(void); + int (*run_pbist_rom)(void); + int (*run_pbist)(void); +}; + +void lbist_enable_isolation(void); +void lbist_disable_isolation(void); +int prepare_pbist(struct ti_sci_handle *handle); +int deprepare_pbist(struct ti_sci_handle *handle); +int prepare_lbist(struct ti_sci_handle *handle); +int deprepare_lbist(struct ti_sci_handle *handle); + +#endif /* _INCLUDE_BIST_H_ */ diff --git a/include/stratixII.h b/include/stratixII.h index 3c06bb2955a..785cdf41cb8 100644 --- a/include/stratixII.h +++ b/include/stratixII.h @@ -6,8 +6,8 @@ #ifndef _STRATIXII_H_ #define _STRATIXII_H_ -extern int StratixII_load (Altera_desc * desc, void *image, size_t size); -extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize); -extern int StratixII_info (Altera_desc * desc); +int StratixII_load(Altera_desc *desc, const void *buf, size_t size); +int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize); +int StratixII_info(Altera_desc *desc); #endif /* _STRATIXII_H_ */ diff --git a/test/dm/core.c b/test/dm/core.c index 959b834576f..53693f4f7ed 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -167,8 +167,6 @@ static int dm_test_autobind_uclass_pdata_alloc(struct unit_test_state *uts) for (uclass_find_first_device(UCLASS_TEST, &dev); dev; uclass_find_next_device(&dev)) { - ut_assertnonnull(dev); - uc_pdata = dev_get_uclass_plat(dev); ut_assert(uc_pdata); } @@ -223,8 +221,6 @@ static int dm_test_autobind_uclass_pdata_valid(struct unit_test_state *uts) for (uclass_find_first_device(UCLASS_TEST, &dev); dev; uclass_find_next_device(&dev)) { - ut_assertnonnull(dev); - uc_pdata = dev_get_uclass_plat(dev); ut_assert(uc_pdata); ut_assert(uc_pdata->intval1 == TEST_UC_PDATA_INTVAL1); @@ -734,114 +730,90 @@ static int dm_test_device_reparent(struct unit_test_state *uts) /* Re-parent top-level children with no grandchildren. */ ut_assertok(device_reparent(top[3], top[0])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_reparent(top[4], top[0])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Re-parent top-level children with grandchildren. */ ut_assertok(device_reparent(top[2], top[0])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_reparent(top[5], top[2])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Re-parent grandchildren. */ ut_assertok(device_reparent(grandchild[0], top[1])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_reparent(grandchild[1], top[1])); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Remove re-pareneted devices. */ ut_assertok(device_remove(top[3], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(top[4], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(top[5], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(top[2], DM_REMOVE_NORMAL)); - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(grandchild[0], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(device_remove(grandchild[1], DM_REMOVE_NORMAL)); + /* try to get devices */ - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); /* Try the same with unbind */ ut_assertok(device_unbind(top[3])); @@ -1090,12 +1062,9 @@ static int dm_test_uclass_devices_find(struct unit_test_state *uts) struct udevice *dev; int ret; - for (ret = uclass_find_first_device(UCLASS_TEST, &dev); - dev; - ret = uclass_find_next_device(&dev)) { - ut_assert(!ret); - ut_assertnonnull(dev); - } + ret = uclass_find_first_device(UCLASS_TEST, &dev); + ut_assert(!ret); + ut_assertnonnull(dev); ut_assertok(uclass_find_first_device(UCLASS_TEST_DUMMY, &dev)); ut_assertnull(dev); @@ -1121,18 +1090,16 @@ static int dm_test_uclass_devices_find_by_name(struct unit_test_state *uts) * this will fail on checking condition: testdev == finddev, since the * uclass_find_device_by_name(), returns the first device by given name. */ - for (ret = uclass_find_first_device(UCLASS_TEST_FDT, &testdev); - testdev; - ret = uclass_find_next_device(&testdev)) { - ut_assertok(ret); - ut_assertnonnull(testdev); + ret = uclass_find_first_device(UCLASS_TEST_FDT, &testdev); + ut_assertok(ret); + ut_assertnonnull(testdev); + for (; testdev; uclass_find_next_device(&testdev)) { findret = uclass_find_device_by_name(UCLASS_TEST_FDT, testdev->name, &finddev); ut_assertok(findret); - ut_assert(testdev); ut_asserteq_str(testdev->name, finddev->name); ut_asserteq_ptr(testdev, finddev); } diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index ceb7a25ad4d..5b4c75f8400 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,7 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:jammy-20250404 +FROM ubuntu:jammy-20250714 LABEL org.opencontainers.image.authors="Tom Rini <trini@konsulko.com>" LABEL org.opencontainers.image.description=" This image is for building U-Boot inside a container" @@ -125,6 +125,7 @@ RUN --mount=type=cache,target=/var/cache/apt,sharing=locked \ python3-dev \ python3-pip \ python3-sphinx \ + python3-tomli \ python3-venv \ rpm2cpio \ sbsigntool \ @@ -218,13 +219,10 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ RUN git clone https://gitlab.com/qemu-project/qemu.git /tmp/qemu && \ cd /tmp/qemu && \ - git checkout v8.2.0 && \ + git checkout v10.0.2 && \ # config user.name and user.email to make 'git am' happy git config user.name u-boot && \ git config user.email u-boot@denx.de && \ - git format-patch 0c7ffc977195~..0c7ffc977195 && \ - git am 0001-hw-net-cadence_gem-Fix-MDIO_OP_xxx-values.patch && \ - git cherry-pick d3c79c3974 && \ ./configure --prefix=/opt/qemu --target-list="aarch64-softmmu,arm-softmmu,i386-softmmu,m68k-softmmu,mips-softmmu,mips64-softmmu,mips64el-softmmu,mipsel-softmmu,ppc-softmmu,riscv32-softmmu,riscv64-softmmu,sh4-softmmu,x86_64-softmmu,xtensa-softmmu" && \ make -j$(nproc) all install && \ rm -rf /tmp/qemu @@ -294,8 +292,8 @@ RUN mkdir /tmp/trace && \ rm -rf /tmp/trace # Build coreboot -RUN wget -O - https://coreboot.org/releases/coreboot-24.08.tar.xz | tar -C /tmp -xJ && \ - cd /tmp/coreboot-24.08 && \ +RUN wget -O - https://coreboot.org/releases/coreboot-25.03.tar.xz | tar -C /tmp -xJ && \ + cd /tmp/coreboot-25.03 && \ make crossgcc-i386 CPUS=$(nproc) && \ make -C payloads/coreinfo olddefconfig && \ make -C payloads/coreinfo && \ @@ -306,7 +304,7 @@ RUN wget -O - https://coreboot.org/releases/coreboot-24.08.tar.xz | tar -C /tmp make -j $(nproc) && \ sudo mkdir /opt/coreboot && \ sudo cp build/coreboot.rom build/cbfstool /opt/coreboot/ && \ - rm -rf /tmp/coreboot-24.08 + rm -rf /tmp/coreboot-25.03 # Create our user/group RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot |