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-rw-r--r--arch/arm/dts/imxrt1170-evk.dts28
-rw-r--r--arch/arm/dts/imxrt1170.dtsi13
-rw-r--r--configs/imx95_19x19_evk_defconfig1
-rw-r--r--configs/imxrt1170-evk_defconfig15
-rw-r--r--drivers/clk/imx/clk-imxrt1170.c9
-rw-r--r--drivers/net/fsl_enetc.c4
-rw-r--r--drivers/spi/nxp_fspi.c55
-rw-r--r--include/dt-bindings/clock/imxrt1170-clock.h4
8 files changed, 107 insertions, 22 deletions
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
index 0d8e7016860..354352477c7 100644
--- a/arch/arm/dts/imxrt1170-evk.dts
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -234,6 +234,34 @@
(IMX_PAD_SION | 8) /* SEMC_DQS */
>;
};
+
+ pinctrl_flexspi1: flexspi1grp {
+ fsl,pins = <
+ IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0xa
+ IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0xa
+ IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0xa
+ IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0xa
+ IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0xa
+ IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0xa
+ IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0xa
+ >;
+ };
+ };
+};
+
+&flexspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi1>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <250000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
};
};
diff --git a/arch/arm/dts/imxrt1170.dtsi b/arch/arm/dts/imxrt1170.dtsi
index 2de775f043f..08665eaf06a 100644
--- a/arch/arm/dts/imxrt1170.dtsi
+++ b/arch/arm/dts/imxrt1170.dtsi
@@ -246,6 +246,19 @@
#interrupt-cells = <2>;
};
+ flexspi1: spi@400cc000 {
+ compatible = "nxp,imxrt1170-fspi";
+ reg = <0x400cc000 0x800>, <0x30000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <130>;
+ clocks = <&clks IMXRT1170_CLK_DUMMY>,
+ <&clks IMXRT1170_CLK_FLEXSPI1>;
+ clock-names = "fspi_en", "fspi";
+ status = "disabled";
+ };
+
gpt1: gpt1@400ec000 {
compatible = "fsl,imxrt-gpt";
reg = <0x400ec000 0x4000>;
diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig
index a40d93db0df..32aee1fa90a 100644
--- a/configs/imx95_19x19_evk_defconfig
+++ b/configs/imx95_19x19_evk_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_PBSIZE=2074
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
diff --git a/configs/imxrt1170-evk_defconfig b/configs/imxrt1170-evk_defconfig
index 32107fa9d52..a57c35bf686 100644
--- a/configs/imxrt1170-evk_defconfig
+++ b/configs/imxrt1170-evk_defconfig
@@ -37,6 +37,8 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SPI=y
# CONFIG_CMD_MII is not set
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_ISO_PARTITION is not set
@@ -58,6 +60,15 @@ CONFIG_CLK_IMXRT1170=y
CONFIG_MXC_GPIO=y
# CONFIG_INPUT is not set
CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_CFI_FLASH=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMXRT=y
@@ -65,6 +76,10 @@ CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_IMXRT_SDRAM=y
CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_DIRMAP=y
+CONFIG_NXP_FSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_IMX_GPT_TIMER=y
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
index 3f55d0d0127..bfd5dd6c464 100644
--- a/drivers/clk/imx/clk-imxrt1170.c
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -105,6 +105,8 @@ static const char * const usdhc1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M",
"pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm"};
static const char * const semc_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
"pll1_div5", "pll2_sys", "pll2_pfd2", "pll3_pfd0"};
+static const char * const flexspi1_sels[] = {"rcosc48M_div2", "osc", "rcosc400M", "rcosc16M",
+"pll3_pdf0", "pll2_clk", "pll2_pfd2", "pll3_clk"};
static int imxrt1170_clk_probe(struct udevice *dev)
{
@@ -163,6 +165,13 @@ static int imxrt1170_clk_probe(struct udevice *dev)
imx_clk_divider(dev, "lpuart1", "lpuart1_sel",
base + (25 * 0x80), 0, 8));
+ clk_dm(IMXRT1170_CLK_FLEXSPI1_SEL,
+ imx_clk_mux(dev, "flexspi1_sel", base + (20 * 0x80), 8, 3,
+ flexspi1_sels, ARRAY_SIZE(flexspi1_sels)));
+ clk_dm(IMXRT1170_CLK_FLEXSPI1,
+ imx_clk_divider(dev, "flexspi1", "flexspi1_sel",
+ base + (20 * 0x80), 0, 8));
+
clk_dm(IMXRT1170_CLK_USDHC1_SEL,
imx_clk_mux(dev, "usdhc1_sel", base + (58 * 0x80), 8, 3,
usdhc1_sels, ARRAY_SIZE(usdhc1_sels)));
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 52fa820f518..97cccda4519 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -473,13 +473,15 @@ static int enetc_init_sxgmii(struct udevice *dev)
/* Apply protocol specific configuration to MAC, serdes as needed */
static void enetc_start_pcs(struct udevice *dev)
{
+ struct enetc_data *data = (struct enetc_data *)dev_get_driver_data(dev);
struct enetc_priv *priv = dev_get_priv(dev);
/* register internal MDIO for debug purposes */
if (enetc_read_pcapr_mdio(dev)) {
priv->imdio.read = enetc_mdio_read;
priv->imdio.write = enetc_mdio_write;
- priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
+ priv->imdio.priv = priv->port_regs + data->reg_offset_mac +
+ ENETC_PM_IMDIO_BASE;
strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
if (!miiphy_get_dev_by_name(priv->imdio.name))
mdio_register(&priv->imdio);
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c
index 7489c896f9d..6d97b8eefc9 100644
--- a/drivers/spi/nxp_fspi.c
+++ b/drivers/spi/nxp_fspi.c
@@ -52,13 +52,6 @@
#include <linux/bug.h>
#include <linux/err.h>
-/*
- * The driver only uses one single LUT entry, that is updated on
- * each call of exec_op(). Index 0 is preset at boot with a basic
- * read operation, so let's use the last entry (31).
- */
-#define SEQID_LUT 31
-
/* Registers used by the driver */
#define FSPI_MCR0 0x00
#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
@@ -242,9 +235,6 @@
#define FSPI_TFDR 0x180
#define FSPI_LUT_BASE 0x200
-#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
-#define FSPI_LUT_REG(idx) \
- (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
/* register map end */
@@ -316,6 +306,7 @@ struct nxp_fspi_devtype_data {
unsigned int txfifo;
unsigned int ahb_buf_size;
unsigned int quirks;
+ unsigned int lut_num;
bool little_endian;
};
@@ -324,6 +315,7 @@ static struct nxp_fspi_devtype_data lx2160a_data = {
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
.quirks = 0,
+ .lut_num = 32,
.little_endian = true, /* little-endian */
};
@@ -332,9 +324,19 @@ static struct nxp_fspi_devtype_data imx8mm_data = {
.txfifo = SZ_1K, /* (128 * 64 bits) */
.ahb_buf_size = SZ_2K, /* (256 * 64 bits) */
.quirks = 0,
+ .lut_num = 32,
.little_endian = true, /* little-endian */
};
+static struct nxp_fspi_devtype_data imxrt1170_data = {
+ .rxfifo = SZ_256,
+ .txfifo = SZ_256,
+ .ahb_buf_size = SZ_4K,
+ .quirks = 0,
+ .lut_num = 16,
+ .little_endian = true,
+};
+
struct nxp_fspi {
struct udevice *dev;
void __iomem *iobase;
@@ -486,6 +488,8 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
void __iomem *base = f->iobase;
u32 lutval[4] = {};
int lutidx = 1, i;
+ u32 lut_offset = (f->devtype_data->lut_num - 1) * 4 * 4;
+ u32 target_lut_reg;
/* cmd */
lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
@@ -530,8 +534,10 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
fspi_writel(f, FSPI_LCKER_UNLOCK, f->iobase + FSPI_LCKCR);
/* fill LUT */
- for (i = 0; i < ARRAY_SIZE(lutval); i++)
- fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
+ for (i = 0; i < ARRAY_SIZE(lutval); i++) {
+ target_lut_reg = FSPI_LUT_BASE + lut_offset + i * 4;
+ fspi_writel(f, lutval[i], base + target_lut_reg);
+ }
dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n",
op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes);
@@ -731,7 +737,7 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
void __iomem *base = f->iobase;
int seqnum = 0;
int err = 0;
- u32 reg;
+ u32 reg, seqid_lut;
reg = fspi_readl(f, base + FSPI_IPRXFCR);
/* invalid RXFIFO first */
@@ -745,8 +751,9 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
* the LUT at each exec_op() call. And also specify the DATA
* length, since it's has not been specified in the LUT.
*/
+ seqid_lut = f->devtype_data->lut_num - 1;
fspi_writel(f, op->data.nbytes |
- (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
+ (seqid_lut << FSPI_IPCR1_SEQID_SHIFT) |
(seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
base + FSPI_IPCR1);
@@ -862,7 +869,7 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
{
void __iomem *base = f->iobase;
int ret, i;
- u32 reg;
+ u32 reg, seqid_lut;
#if CONFIG_IS_ENABLED(CLK)
/* the default frequency, we will change it later if necessary. */
@@ -933,11 +940,17 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
fspi_writel(f, reg, base + FSPI_FLSHB1CR1);
fspi_writel(f, reg, base + FSPI_FLSHB2CR1);
+ /*
+ * The driver only uses one single LUT entry, that is updated on
+ * each call of exec_op(). Index 0 is preset at boot with a basic
+ * read operation, so let's use the last entry.
+ */
+ seqid_lut = f->devtype_data->lut_num - 1;
/* AHB Read - Set lut sequence ID for all CS. */
- fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
- fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
- fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
- fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
+ fspi_writel(f, seqid_lut, base + FSPI_FLSHA1CR2);
+ fspi_writel(f, seqid_lut, base + FSPI_FLSHA2CR2);
+ fspi_writel(f, seqid_lut, base + FSPI_FLSHB1CR2);
+ fspi_writel(f, seqid_lut, base + FSPI_FLSHB2CR2);
return 0;
}
@@ -1035,7 +1048,8 @@ static int nxp_fspi_of_to_plat(struct udevice *bus)
}
#endif
- dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n", iobase, ahb_addr);
+ dev_dbg(bus, "iobase=<0x%llx>, ahb_addr=<0x%llx>\n",
+ (long long)iobase, (long long)ahb_addr);
return 0;
}
@@ -1057,6 +1071,7 @@ static const struct udevice_id nxp_fspi_ids[] = {
{ .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
{ .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, },
{ .compatible = "nxp,imx8mp-fspi", .data = (ulong)&imx8mm_data, },
+ { .compatible = "nxp,imxrt1170-fspi", .data = (ulong)&imxrt1170_data, },
{ }
};
diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h
index 8ab8018a15e..d3d21cf310d 100644
--- a/include/dt-bindings/clock/imxrt1170-clock.h
+++ b/include/dt-bindings/clock/imxrt1170-clock.h
@@ -43,6 +43,8 @@
#define IMXRT1170_CLK_GPT1 33
#define IMXRT1170_CLK_SEMC_SEL 34
#define IMXRT1170_CLK_SEMC 35
-#define IMXRT1170_CLK_END 36
+#define IMXRT1170_CLK_FLEXSPI1_SEL 36
+#define IMXRT1170_CLK_FLEXSPI1 37
+#define IMXRT1170_CLK_END 38
#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 15:14:36 +0000