diff options
122 files changed, 1704 insertions, 1707 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 64f92f8b5b9..2dbe6325f33 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -40,6 +40,7 @@ stages: # qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled. # The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks - ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na + - ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py - ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname` - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname` - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then diff --git a/MAINTAINERS b/MAINTAINERS index 10f7f1fd180..c1851280e6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -671,8 +671,7 @@ F: drivers/reset/sti-reset.c F: drivers/serial/serial_sti_asc.c F: drivers/sysreset/sysreset_sti.c F: drivers/timer/arm_global_timer.c -F: drivers/usb/host/dwc3-sti-glue.c -F: include/dwc3-sti-glue.h +F: drivers/usb/host/dwc3-sti.c F: include/dt-bindings/clock/stih407-clks.h F: include/dt-bindings/clock/stih410-clks.h F: include/dt-bindings/reset/stih407-resets.h @@ -3,7 +3,7 @@ VERSION = 2025 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index 9dbdff3a4fc..85f13ccd0d2 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -9,8 +9,16 @@ #include <linux/linkage.h> #include <asm/macro.h> +.pushsection .text.armv8_switch_to_el2_prep, "ax" +WEAK(armv8_switch_to_el2_prep) + ret +ENDPROC(armv8_switch_to_el2_prep) +.popsection + .pushsection .text.armv8_switch_to_el2, "ax" ENTRY(armv8_switch_to_el2) + bl armv8_switch_to_el2_prep + nop switch_el x6, 1f, 0f, 0f 0: cmp x5, #ES_TO_AARCH64 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0bf3697bdbe..267b0179a5f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -52,9 +52,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK3036) += \ - rk3036-sdk.dtb - dtb-$(CONFIG_ROCKCHIP_RK3128) += \ rk3128-evb.dtb @@ -84,6 +81,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_TEGRA) += \ + tegra20-acer-a500-picasso.dtb \ tegra20-asus-sl101.dtb \ tegra20-asus-tf101.dtb \ tegra20-asus-tf101g.dtb \ diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-evb-u-boot.dtsi index ef7e0207c3e..f8857c736d0 100644 --- a/arch/arm/dts/rk3036-sdk-u-boot.dtsi +++ b/arch/arm/dts/rk3036-evb-u-boot.dtsi @@ -1,13 +1,13 @@ #include "rk3036-u-boot.dtsi" -&uart2 { +&grf { bootph-all; }; -&grf { +&pinctrl { bootph-all; }; -&pinctrl { +&uart2 { bootph-all; }; diff --git a/arch/arm/dts/rk3036-kylin-u-boot.dtsi b/arch/arm/dts/rk3036-kylin-u-boot.dtsi new file mode 100644 index 00000000000..f8857c736d0 --- /dev/null +++ b/arch/arm/dts/rk3036-kylin-u-boot.dtsi @@ -0,0 +1,13 @@ +#include "rk3036-u-boot.dtsi" + +&grf { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&uart2 { + bootph-all; +}; diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts deleted file mode 100644 index 3493150df92..00000000000 --- a/arch/arm/dts/rk3036-sdk.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -/dts-v1/; - -#include "rk3036.dtsi" - -/ { - model = "SDK-RK3036"; - compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; - - chosen { - stdout-path = &uart2; - }; - - vcc5v0_otg: vcc5v0-otg-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_otg"; - gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&otg_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc5v0_host: vcc5v0-host-drv { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_host"; - gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; -}; - -&i2c1 { - status = "okay"; - - hym8563: hym8563@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - }; -}; - -&usb_host { - vbus-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&usb_otg { - vbus-supply = <&vcc5v0_otg>; - status = "okay"; -}; - -&pinctrl { - usb_otg { - otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb_host { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; diff --git a/arch/arm/dts/rk3036.dtsi b/arch/arm/dts/rk3036.dtsi deleted file mode 100644 index 75588de4863..00000000000 --- a/arch/arm/dts/rk3036.dtsi +++ /dev/null @@ -1,439 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3036-cru.h> -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3036"; - - interrupt-parent = <&gic>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - i2c1 = &i2c1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - mmc0 = &emmc; - mmc1 = &sdmmc; - }; - - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "rockchip,rk3036-smp"; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - resets = <&cru SRST_CORE0>; - }; - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - }; - - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - arm,pl330-broken-no-flushp; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - uart0: serial@20060000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - }; - - uart1: serial@20064000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20064000 0x100>; - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - }; - - uart2: serial@20068000 { - compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; - reg = <0x20068000 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - }; - - pwm0: pwm@20050000 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050000 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm1: pwm@20050010 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050010 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm2: pwm@20050020 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050020 0x10>; - #pwm-cells = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - pwm3: pwm@20050030 { - compatible = "rockchip,rk2928-pwm"; - reg = <0x20050030 0x10>; - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - status = "disabled"; - }; - - sram: sram@10080000 { - compatible = "rockchip,rk3036-smp-sram", "mmio-sram"; - reg = <0x10080000 0x2000>; - }; - - gic: interrupt-controller@10139000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x10139000 0x1000>, - <0x1013a000 0x1000>, - <0x1013c000 0x2000>, - <0x1013e000 0x2000>; - interrupts = <GIC_PPI 9 0xf04>; - }; - - grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon"; - reg = <0x20008000 0x1000>; - }; - - usb_otg: usb@10180000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x10180000 0x40000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG0>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <275>; - g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; - status = "disabled"; - }; - - usb_host: usb@101c0000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x101c0000 0x40000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG1>; - clock-names = "otg"; - dr_mode = "host"; - status = "disabled"; - }; - - emmc: dwmmc@1021c000 { - compatible = "rockchip,rk3288-dw-mshc"; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - dmas = <&pdma 12>; - dma-names = "rx-tx"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x1021c000 0x4000>; - broken-cd; - bus-width = <8>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - disable-wp; - fifo-mode; - non-removable; - num-slots = <1>; - default-sample-phase = <158>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - }; - - sdmmc: dwmmc@10214000 { - compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x10214000 0x4000>; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3036-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@2007c000 { - compatible = "rockchip,gpio-bank"; - reg = <0x2007c000 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@20080000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20080000 0x100>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@20084000 { - compatible = "rockchip,gpio-bank"; - reg = <0x20084000 0x100>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - /* - * We run eMMC at max speed; bump up drive strength. - * We also have external pulls, so disable the internal ones. - */ - emmc_clk: emmc-clk { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>; - /* - <1 28 RK_FUNC_2 &pcfg_pull_up>, - <1 29 RK_FUNC_2 &pcfg_pull_up>, - <1 30 RK_FUNC_2 &pcfg_pull_up>, - <1 31 RK_FUNC_2 &pcfg_pull_up>; - */ - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; - }; - /* no rts / cts for uart1 */ - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - /* no rts / cts for uart2 */ - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; - - i2c1: i2c@20056000 { - compatible = "rockchip,rk3288-i2c"; - reg = <0x20056000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; -}; diff --git a/arch/arm/dts/stih410-b2260-u-boot.dtsi b/arch/arm/dts/stih410-b2260-u-boot.dtsi index 3b080ac7a1b..e9d7ec92281 100644 --- a/arch/arm/dts/stih410-b2260-u-boot.dtsi +++ b/arch/arm/dts/stih410-b2260-u-boot.dtsi @@ -14,20 +14,30 @@ }; }; + clk_usb: clk-usb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + ohci0: usb@9a03c00 { compatible = "generic-ohci"; + clocks = <&clk_usb>; }; ehci0: usb@9a03e00 { compatible = "generic-ehci"; + clocks = <&clk_usb>; }; ohci1: usb@9a83c00 { compatible = "generic-ohci"; + clocks = <&clk_usb>; }; ehci1: usb@9a83e00 { compatible = "generic-ehci"; + clocks = <&clk_usb>; }; }; }; diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi index 376dcdf68fb..8a629bfe703 100644 --- a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi +++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi @@ -4,16 +4,9 @@ * Written by Simon Glass <sjg@chromium.org> */ -#include "tegra-u-boot.dtsi" +#include "tegra124-u-boot.dtsi" / { - host1x@50000000 { - bootph-all; - dc@54200000 { - bootph-all; - }; - }; - spi@7000d400 { spi-deactivate-delay = <500>; spi-max-frequency = <3000000>; diff --git a/arch/arm/dts/tegra124-u-boot.dtsi b/arch/arm/dts/tegra124-u-boot.dtsi index 7c119725528..6a02714a258 100644 --- a/arch/arm/dts/tegra124-u-boot.dtsi +++ b/arch/arm/dts/tegra124-u-boot.dtsi @@ -1,3 +1,16 @@ #include <config.h> #include "tegra-u-boot.dtsi" + +/ { + host1x@50000000 { + bootph-all; + dc@54200000 { + bootph-all; + }; + + dc@54240000 { + bootph-all; + }; + }; +}; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index ffec9cae09d..cac9b112302 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -136,6 +136,38 @@ status = "disabled"; }; + dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54300000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x54540000 0x00040000>; @@ -737,6 +769,13 @@ #thermal-sensor-cells = <1>; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x700e3000 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0x70110000 0x100>, /* DFLL control */ diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts new file mode 100644 index 00000000000..0c301483180 --- /dev/null +++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra20.dtsi" + +/ { + model = "Acer Iconia Tab A500"; + compatible = "acer,picasso", "nvidia,tegra20"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb3; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp", "lm1"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lsc0", + "lsc1", "lsck", "lsda", "lspi", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "csus", "dap1", + "dap4", "dte", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", + "sdc", "sdd", "slxc", "slxd", "slxk", + "spdi", "spdo", "uac", "uad", "uda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ate { + nvidia,pins = "ate", "dap2", "dap3", + "gmd", "owc", "spia", "spib", "spic", + "spid", "spie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + conf_crtp { + nvidia,pins = "crtp", "gmb", "slxa", "spig", + "spih"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_dte { + nvidia,pins = "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", + "lvp0"; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + conf_kbca { + nvidia,pins = "kbca", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", + "uab", "uca", "ucb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + drive_ddc { + nvidia,pins = "drive_ddc", + "drive_vi1", + "drive_sdio1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + drive_dbg { + nvidia,pins = "drive_dbg", + "drive_vi2", + "drive_at1", + "drive_ao1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + clock-frequency = <216000000>; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <100000>; + + pmic: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + avdd_usb: ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + }; + }; + }; + + usb1: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb3: usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 41667>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "tps658621-out32k"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + switch-rotation-lock { + label = "Rotate-lock"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; + linux,code = <SW_ROTATE_LOCK>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + + display-timings { + timing@0 { + clock-frequency = <71200000>; + + hactive = <1280>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + + vactive = <800>; + vfront-porch = <4>; + vback-porch = <8>; + vsync-len = <3>; + }; + }; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 1177e2ab1f4..d5de1ecaf05 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -218,10 +218,29 @@ dsi@54300000 { compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; - clocks = <&tegra_car TEGRA30_CLK_DSIA>; + clocks = <&tegra_car TEGRA30_CLK_DSIA>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + dsi@54400000 { + compatible = "nvidia,tegra30-dsi"; + reg = <0x54400000 0x00040000>; + clocks = <&tegra_car TEGRA30_CLK_DSIB>, + <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + resets = <&tegra_car 84>; + reset-names = "dsi"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index dd89cd20505..e6125d6bf54 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -466,18 +466,18 @@ enum { /* GRF_GPIO4C_IOMUX */ GRF_GPIO4C0_SEL_SHIFT = 0, GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT, - GRF_UART2DGBB_SIN = 2, + GRF_UART2DBGB_SIN = 2, GRF_HDMII2C_SCL = 3, GRF_GPIO4C1_SEL_SHIFT = 2, GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT, - GRF_UART2DGBB_SOUT = 2, + GRF_UART2DBGB_SOUT = 2, GRF_HDMII2C_SDA = 3, GRF_GPIO4C2_SEL_SHIFT = 4, GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT, GRF_PWM_0 = 1, GRF_GPIO4C3_SEL_SHIFT = 6, GRF_GPIO4C3_SEL_MASK = 3 << GRF_GPIO4C3_SEL_SHIFT, - GRF_UART2DGBC_SIN = 1, + GRF_UART2DBGC_SIN = 1, GRF_GPIO4C4_SEL_SHIFT = 8, GRF_GPIO4C4_SEL_MASK = 3 << GRF_GPIO4C4_SEL_SHIFT, GRF_UART2DBGC_SOUT = 1, diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index 9f531253153..055948ec07a 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* Special for Tegra124 */ /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL2, CLOCK_ID_CGENERAL3, CLOCK_ID_MEMORY2, diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h index c6d7487e629..5c4d7fc84c4 100644 --- a/arch/arm/include/asm/arch-tegra210/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h @@ -24,6 +24,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, CLOCK_ID_DP, /* These are the base clocks (inputs to the Tegra SoC) */ @@ -37,7 +38,6 @@ enum clock_id { * These are clock IDs that are used in table clock_source[][] * but will not be assigned as a clock source for any peripheral. */ - CLOCK_ID_DISPLAY2, CLOCK_ID_CGENERAL_0, CLOCK_ID_CGENERAL_1, CLOCK_ID_CGENERAL2, diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index dbf9ab43e28..091082281c7 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -239,6 +239,22 @@ int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); /* + * armv8_switch_to_el2_prep() - prepare for switch from EL3 to EL2 for ARMv8 + * + * @args: For loading 64-bit OS, fdt address. + * For loading 32-bit OS, zero. + * @mach_nr: For loading 64-bit OS, zero. + * For loading 32-bit OS, machine nr + * @fdt_addr: For loading 64-bit OS, zero. + * For loading 32-bit OS, fdt address. + * @arg4: Input argument. + * @entry_point: kernel entry point + * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 + */ +void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr, + u64 arg4, u64 entry_point, u64 es_flag); + +/* * armv8_switch_to_el2() - switch from EL3 to EL2 for ARMv8 * * @args: For loading 64-bit OS, fdt address. diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4d3157b2edd..adac11a6b89 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -29,6 +29,7 @@ config ROCKCHIP_RK3036 select CPU_V7A select SUPPORT_SPL select SPL + imply OF_UPSTREAM imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB imply ROCKCHIP_COMMON_BOARD diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 1ce43c6f0d4..99597076d2c 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -7,6 +7,7 @@ #include <init.h> #include <log.h> #include <spl.h> +#include <spl_gpio.h> #include <syscon.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> @@ -15,7 +16,6 @@ #include <asm/arch-rockchip/gpio.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> -#include <asm/gpio.h> #include <linux/bitops.h> #include <linux/printk.h> #include <power/regulator.h> @@ -133,10 +133,31 @@ void board_debug_uart_init(void) GRF_GPIO3B7_SEL_MASK, GRF_UART3_SOUT << GRF_GPIO3B7_SEL_SHIFT); #else + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; + + if (IS_ENABLED(CONFIG_XPL_BUILD) && + (IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) || + IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) { + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running + * the SPI-Flash-based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), + GPIO_PULL_NORMAL); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), + GPIO_PULL_NORMAL); + } + /* Enable early UART2 channel C on the RK3399 */ rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + GRF_UART2DBGC_SIN << GRF_GPIO4C3_SEL_SHIFT); rk_clrsetreg(&grf->gpio4c_iomux, GRF_GPIO4C4_SEL_MASK, GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 1fb01e1c4b1..f7d32829295 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -309,6 +309,8 @@ int dram_init_banksize(void) if (ram_top > SZ_4G && top < SZ_4G) { gd->bd->bi_dram[1].start = SZ_4G; gd->bd->bi_dram[1].size = ram_top - gd->bd->bi_dram[1].start; + } else if (ram_top > SZ_4G && top == SZ_4G) { + gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start; } #else #ifdef CONFIG_SPL_OPTEE_IMAGE @@ -476,6 +478,7 @@ int dram_init(void) debug("Cannot get DRAM size: %d\n", ret); return ret; } + gd->ram_base = ram.base; gd->ram_size = ram.size; debug("SDRAM base=%lx, size=%lx\n", (unsigned long)ram.base, (unsigned long)ram.size); @@ -485,7 +488,8 @@ int dram_init(void) phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + /* Make sure U-Boot only uses the space below the 4G address boundary */ + u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 4ac0c10c597..0ea212f80e2 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -598,6 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -852,6 +854,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA124_CLK_PLL_D: case TEGRA124_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA124_CLK_PLL_D2: + case TEGRA124_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA124_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA124_CLK_PLL_E: @@ -1194,6 +1199,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; case CLOCK_ID_DP: return &clkrst->plldp; default: diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 6458827d6dc..e2735d93e28 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -33,6 +33,10 @@ config TARGET_PAZ00 bool "Paz00 board" select BOARD_LATE_INIT +config TARGET_PICASSO + bool "Acer Tegra20 Picasso board" + select BOARD_LATE_INIT + config TARGET_PLUTUX bool "Avionic Design Plutux board" select BOARD_LATE_INIT @@ -73,6 +77,7 @@ config SYS_SOC source "board/nvidia/harmony/Kconfig" source "board/avionic-design/medcom-wide/Kconfig" source "board/compal/paz00/Kconfig" +source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" source "board/nvidia/seaboard/Kconfig" source "board/avionic-design/tec/Kconfig" diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 57ff0b2a19a..04708f97144 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -668,6 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; @@ -939,6 +941,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA210_CLK_PLL_D: case TEGRA210_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA210_CLK_PLL_D2: + case TEGRA210_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA210_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA210_CLK_PLL_E: @@ -1276,6 +1281,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) case CLOCK_ID_EPCI: case CLOCK_ID_SFROM32KHZ: return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; default: return NULL; } diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig new file mode 100644 index 00000000000..73c0aa08508 --- /dev/null +++ b/board/acer/picasso/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PICASSO + +config SYS_BOARD + default "picasso" + +config SYS_VENDOR + default "acer" + +config SYS_CONFIG_NAME + default "picasso" + +endif diff --git a/board/acer/picasso/MAINTAINERS b/board/acer/picasso/MAINTAINERS new file mode 100644 index 00000000000..99f8c0b6d7f --- /dev/null +++ b/board/acer/picasso/MAINTAINERS @@ -0,0 +1,7 @@ +PICASSO BOARD +M: Svyatoslav Ryhel <clamor95@gmail.com> +S: Maintained +F: board/acer/picasso/ +F: configs/picasso_defconfig +F: doc/board/acer/picasso.rst +F: include/configs/picasso.h diff --git a/board/acer/picasso/Makefile b/board/acer/picasso/Makefile new file mode 100644 index 00000000000..675059c112d --- /dev/null +++ b/board/acer/picasso/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# (C) Copyright 2024 +# Svyatoslav Ryhel <clamor95@gmail.com> + +obj-y += picasso.o diff --git a/board/acer/picasso/picasso.c b/board/acer/picasso/picasso.c new file mode 100644 index 00000000000..d3e600cad52 --- /dev/null +++ b/board/acer/picasso/picasso.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2024 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +/* Picasso derives from Ventana board */ + +#include <dm.h> +#include <i2c.h> +#include <log.h> +#include <linux/delay.h> + +#define TPS6586X_I2C_ADDRESS 0x34 +#define TPS6586X_SUPPLYENE 0x14 +#define EXITSLREQ_BIT BIT(1) +#define SLEEP_MODE_BIT BIT(3) + +#ifdef CONFIG_CMD_POWEROFF +int do_poweroff(struct cmd_tbl *cmdtp, + int flag, int argc, char *const argv[]) +{ + struct udevice *dev; + uchar data_buffer[1]; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS6586X_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("cannot find PMIC I2C chip\n"); + return 0; + } + + ret = dm_i2c_read(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] &= ~EXITSLREQ_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + data_buffer[0] |= SLEEP_MODE_BIT; + + ret = dm_i2c_write(dev, TPS6586X_SUPPLYENE, data_buffer, 1); + if (ret) + return ret; + + // wait some time and then print error + mdelay(5000); + printf("Failed to power off!!!\n"); + return 1; +} +#endif diff --git a/board/acer/picasso/picasso.env b/board/acer/picasso/picasso.env new file mode 100644 index 00000000000..d9409b07d98 --- /dev/null +++ b/board/acer/picasso/picasso.env @@ -0,0 +1,18 @@ +#include <env/nvidia/prod_upd.env> + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} + +boot_block_size_r=0x100000 +boot_block_size=0x800 +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/board/asus/grouper/Makefile b/board/asus/grouper/Makefile index 8a8e6530c86..b83b7fced48 100644 --- a/board/asus/grouper/Makefile +++ b/board/asus/grouper/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel <clamor95@gmail.com> -obj-$(CONFIG_SPL_BUILD) += grouper-spl.o +obj-$(CONFIG_XPL_BUILD) += grouper-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += grouper.o diff --git a/board/asus/transformer-t30/Makefile b/board/asus/transformer-t30/Makefile index 22b6160f757..b8617f820cd 100644 --- a/board/asus/transformer-t30/Makefile +++ b/board/asus/transformer-t30/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2021 # Svyatoslav Ryhel <clamor95@gmail.com> -obj-$(CONFIG_SPL_BUILD) += transformer-t30-spl.o +obj-$(CONFIG_XPL_BUILD) += transformer-t30-spl.o obj-$(CONFIG_MULTI_DTB_FIT) += board-info.o obj-y += transformer-t30.o diff --git a/board/asus/transformer-t30/board-info.c b/board/asus/transformer-t30/board-info.c index a2b540c90b6..e72614164b4 100644 --- a/board/asus/transformer-t30/board-info.c +++ b/board/asus/transformer-t30/board-info.c @@ -11,14 +11,14 @@ #include <asm/arch/pinmux.h> /* - * PCB_ID[1] is kb_row5_pr5 * PCB_ID[3] is kb_col7_pq7 * PCB_ID[4] is kb_row2_pr2 * PCB_ID[5] is kb_col5_pq5 + * PCB_ID[7] is gmi_cs1_n_pj2 * * Project ID * ===================================================== - * PCB_ID[1] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project + * PCB_ID[7] PCB_ID[5] PCB_ID[4] PCB_ID[3] Project * 0 0 0 0 TF201 * 0 0 0 1 P1801 * 0 0 1 0 TF300T @@ -45,10 +45,10 @@ static const char * const project_id_to_fdt[] = { [TF600T] = "tegra30-asus-tf600t", }; -static int id_gpio_get_value(u32 pingrp, u32 pin) +static int id_gpio_get_value(u32 pingrp, u32 func, u32 pin) { /* Configure pinmux */ - pinmux_set_func(pingrp, PMUX_FUNC_KBC); + pinmux_set_func(pingrp, func); pinmux_set_pullupdown(pingrp, PMUX_PULL_DOWN); pinmux_tristate_enable(pingrp); pinmux_set_io(pingrp, PMUX_PIN_INPUT); @@ -65,19 +65,19 @@ static int id_gpio_get_value(u32 pingrp, u32 pin) static int get_project_id(void) { - u32 pcb_id1, pcb_id3, pcb_id4, pcb_id5; + u32 pcb_id3, pcb_id4, pcb_id5, pcb_id7; - pcb_id1 = id_gpio_get_value(PMUX_PINGRP_KB_ROW5_PR5, - TEGRA_GPIO(R, 5)); pcb_id3 = id_gpio_get_value(PMUX_PINGRP_KB_COL7_PQ7, - TEGRA_GPIO(Q, 7)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 7)); pcb_id4 = id_gpio_get_value(PMUX_PINGRP_KB_ROW2_PR2, - TEGRA_GPIO(R, 2)); + PMUX_FUNC_KBC, TEGRA_GPIO(R, 2)); pcb_id5 = id_gpio_get_value(PMUX_PINGRP_KB_COL5_PQ5, - TEGRA_GPIO(Q, 5)); + PMUX_FUNC_KBC, TEGRA_GPIO(Q, 5)); + pcb_id7 = id_gpio_get_value(PMUX_PINGRP_GMI_CS1_N_PJ2, + PMUX_FUNC_RSVD1, TEGRA_GPIO(J, 2)); /* Construct board ID */ - int proj_id = pcb_id1 << 3 | pcb_id5 << 2 | + int proj_id = pcb_id7 << 3 | pcb_id5 << 2 | pcb_id4 << 1 | pcb_id3; log_debug("[TRANSFORMER]: project id %d (%s)\n", proj_id, diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index a912712c9dd..8ad593cccdd 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -7,11 +7,6 @@ #include <cpu_func.h> #include <init.h> #include <asm/cache.h> -#include <asm/global_data.h> -#include <linux/usb/otg.h> -#include <dwc3-sti-glue.h> -#include <dwc3-uboot.h> -#include <usb.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,31 +38,6 @@ int board_init(void) } #ifdef CONFIG_USB_DWC3 -static struct dwc3_device dwc3_device_data = { - .maximum_speed = USB_SPEED_HIGH, - .dr_mode = USB_DR_MODE_PERIPHERAL, - .index = 0, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - int node; - const void *blob = gd->fdt_blob; - - /* find the snps,dwc3 node */ - node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3"); - - dwc3_device_data.base = fdtdec_get_addr(blob, node, "reg"); - - return dwc3_uboot_init(&dwc3_device_data); -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - dwc3_uboot_exit(index); - return 0; -} - int g_dnl_board_usb_cable_connected(void) { return 1; diff --git a/board/starfive/visionfive2/MAINTAINERS b/board/starfive/visionfive2/MAINTAINERS index d7f638f9b41..898e284ce2c 100644 --- a/board/starfive/visionfive2/MAINTAINERS +++ b/board/starfive/visionfive2/MAINTAINERS @@ -1,8 +1,7 @@ STARFIVE JH7110 VISIONFIVE2 BOARD M: Minda Chen <minda.chen@starfivetech.com> +M: Hal Feng <hal.feng@starfivetech.com> S: Maintained -F: arch/riscv/include/asm/arch-jh7110/ -F: board/starfive/visionfive2/ -F: include/configs/starfive-visionfive2.h -F: configs/starfive_visionfive2_defconfig -F: drivers/pci/pcie_starfive_jh7110.c +F: drivers/ram/starfive/ +N: jh7110 +N: visionfive2 diff --git a/boot/image-android.c b/boot/image-android.c index fa4e14ca469..1746b018900 100644 --- a/boot/image-android.c +++ b/boot/image-android.c @@ -696,7 +696,10 @@ bool android_image_get_dtb_by_index(ulong hdr_addr, ulong vendor_boot_img, ulong dtb_addr; /* address of DTB blob with specified index */ u32 i; /* index iterator */ - android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, &dtb_img_addr); + if (!android_image_get_dtb_img_addr(hdr_addr, vendor_boot_img, + &dtb_img_addr)) + return false; + /* Check if DTB area of boot image is in DTBO format */ if (android_dt_check_header(dtb_img_addr)) { return android_dt_get_fdt_by_index(dtb_img_addr, index, addr, diff --git a/boot/image-fit.c b/boot/image-fit.c index aa139da628c..41ab1f552b0 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -2175,6 +2175,7 @@ int fit_image_load(struct bootm_headers *images, ulong addr, type_ok = fit_image_check_type(fit, noffset, image_type) || fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) || fit_image_check_type(fit, noffset, IH_TYPE_TEE) || + fit_image_check_type(fit, noffset, IH_TYPE_TFA_BL31) || (image_type == IH_TYPE_KERNEL && fit_image_check_type(fit, noffset, IH_TYPE_KERNEL_NOLOAD)); diff --git a/boot/image.c b/boot/image.c index abac254e026..139c5bd035a 100644 --- a/boot/image.c +++ b/boot/image.c @@ -183,6 +183,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", }, { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" }, { IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" }, + { IH_TYPE_TFA_BL31, "tfa-bl31", "TFA BL31 Image", }, { -1, "", "", }, }; diff --git a/cmd/Kconfig b/cmd/Kconfig index 2f275bd156d..8dd42571abc 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2162,6 +2162,7 @@ config WGET_HTTPS depends on CMD_WGET depends on PROT_TCP_LWIP depends on MBEDTLS_LIB + depends on DM_RNG select SHA256 select RSA select ASYMMETRIC_KEY_TYPE diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index 3948ba227fc..cbdc219e25e 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -81,7 +81,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y -CONFIG_SPL_MISC=y CONFIG_ESM_K3=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y diff --git a/configs/am62px_evm_r5_defconfig b/configs/am62px_evm_r5_defconfig index 2438d2bb4d1..39b6a83ab42 100644 --- a/configs/am62px_evm_r5_defconfig +++ b/configs/am62px_evm_r5_defconfig @@ -86,7 +86,6 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y -CONFIG_SPL_MISC=y CONFIG_ESM_K3=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_SDHCI=y diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 9a283b81052..f5c05fd4616 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -80,7 +80,6 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_BROADCOM=y CONFIG_PHY_GIGE=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index afff2d54f2c..edb49de207c 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -44,10 +44,10 @@ CONFIG_SYS_PROMPT="antminer> " CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_ELF is not set +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 1b018ef4d7c..5b8c0d35de6 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -35,6 +35,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index 1ee0c0e6c9d..a29a04aadde 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y CONFIG_TPL=y +CONFIG_TPL_GPIO=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index ba79960495e..d215af0c046 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -11,7 +11,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-evb" CONFIG_ROCKCHIP_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK=0x10081fff @@ -23,7 +23,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set diff --git a/configs/ibex-ast2700_defconfig b/configs/ibex-ast2700_defconfig index e4b9a9a5abb..6cb2a21ed2d 100644 --- a/configs/ibex-ast2700_defconfig +++ b/configs/ibex-ast2700_defconfig @@ -27,7 +27,6 @@ CONFIG_TARGET_ASPEED_AST2700_IBEX=y # CONFIG_SPL_SMP is not set CONFIG_XIP=y CONFIG_SPL_XIP=y -# CONFIG_AVAILABLE_HARTS is not set CONFIG_STACK_SIZE_SHIFT=11 CONFIG_ENV_VARS_UBOOT_CONFIG=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index dd25fd60107..bc60bc57075 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -12,7 +12,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x60100000 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3036-kylin" CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 @@ -25,7 +25,7 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3036-kylin.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y # CONFIG_SPL_FRAMEWORK is not set diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 5ea6cc371aa..f8acaa98672 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-icicle-kit.dtb" CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig index 00e3cea5264..c6a88e7e9d3 100644 --- a/configs/mt7987_rfb_defconfig +++ b/configs/mt7987_rfb_defconfig @@ -12,7 +12,6 @@ CONFIG_SYS_LOAD_ADDR=0x48000000 CONFIG_DEBUG_UART_BASE=0x11000000 CONFIG_DEBUG_UART_CLOCK=40000000 CONFIG_DEBUG_UART=y -# CONFIG_EFI_LOADER is not set CONFIG_FIT=y # CONFIG_AUTOBOOT is not set CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb" diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig new file mode 100644 index 00000000000..994951bb81e --- /dev/null +++ b/configs/picasso_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x00110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="picasso" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra20-acer-a500-picasso" +CONFIG_SPL_STACK=0xffffc +CONFIG_SPL_TEXT_BASE=0x00108000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_TEGRA20=y +CONFIG_TARGET_PICASSO=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; poweroff" +CONFIG_SYS_PBSIZE=2085 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra20 (Picasso) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x11000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Acer" +CONFIG_USB_GADGET_VENDOR_NUM=0x0502 +CONFIG_USB_GADGET_PRODUCT_NUM=0x3325 +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +# CONFIG_VIDEO_BPP8 is not set +CONFIG_VIDEO_TEGRA20=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 763fc14468a..03028c76acc 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -74,5 +74,5 @@ CONFIG_USB_EHCI_PCI=y CONFIG_SEMIHOSTING=y CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y -CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y CONFIG_TPM_PCR_ALLOCATE=y +CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index c3f2142ae1b..1e0a99ed17b 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -75,7 +75,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y -CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_WGET=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" @@ -84,6 +84,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_LWIP=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/stih410-b2260_defconfig b/configs/stih410-b2260_defconfig index 815f7557d69..1e5190dc828 100644 --- a/configs/stih410-b2260_defconfig +++ b/configs/stih410-b2260_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_TIME=y CONFIG_CMD_TIMER=y CONFIG_CMD_EXT4_WRITE=y @@ -48,11 +49,13 @@ CONFIG_MMC_SDHCI_STI=y CONFIG_PHY=y CONFIG_STI_USB_PHY=y CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y CONFIG_STI_RESET=y CONFIG_STI_ASC_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y @@ -60,6 +63,8 @@ CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_DWC3_STI=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_MCS7830=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index e7e15c64ba2..27ff3915050 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -36,10 +36,10 @@ CONFIG_SPL_FS_LOAD_ARGS_NAME="system.dtb" CONFIG_SPL_OS_BOOT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x10000000 CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index fdf8bb36129..9196a95e88a 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -61,10 +61,10 @@ CONFIG_CMD_MEMINFO_MAP=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DFU=y +CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADFS=y CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_FPGA_LOADP=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index ad46c091c4a..1a6bd67afb8 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -70,8 +70,8 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_PWM=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 036268c79f7..e5e56babf4c 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -68,8 +68,8 @@ CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_SHA1SUM=y CONFIG_CMD_CLK=y CONFIG_CMD_DFU=y -CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOADP=y +CONFIG_CMD_FPGA_LOADBP=y CONFIG_CMD_FPGA_LOAD_SECURE=y CONFIG_CMD_GPIO=y CONFIG_CMD_PWM=y diff --git a/doc/board/acer/index.rst b/doc/board/acer/index.rst new file mode 100644 index 00000000000..3741a700ccd --- /dev/null +++ b/doc/board/acer/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +ACER +==== + +.. toctree:: + :maxdepth: 2 + + picasso diff --git a/doc/board/acer/picasso.rst b/doc/board/acer/picasso.rst new file mode 100644 index 00000000000..b1d360defd8 --- /dev/null +++ b/doc/board/acer/picasso.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Acer Iconia Tab A500 +=================================== + +``DISCLAMER!`` Moving your Acer Iconia Tab A500 to use U-Boot assumes +replacement of the vendor Acer bootloader. Vendor Android firmwares will no +longer be able to run on the device. This replacement IS reversible. + +Quick Start +----------- + +- Build U-Boot +- Process U-Boot +- Flashing U-Boot into the eMMC +- Boot +- Self Upgrading + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make picasso_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for further processing. + +Process U-Boot +-------------- + +``DISCLAMER!`` All questions related to the re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form +usable by device. This process is required only on the first installation or +to recover the device in case of a failed update. + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. + +Processing for the NV3P protocol +******************************** + +.. code-block:: bash + + $ git clone https://gitlab.com/grate-driver/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-tegra.bin here + $ ./re-crypt.py --dev a500 + +The script will produce a ``repart-block.bin`` ready to flash. + +Processing for pre-loaded U-Boot +******************************** + +The procedure is the same, but the ``--split`` argument is used with the +``re-crypt.py``. The script will produce ``bct.img`` and ``ebt.img`` ready +to flash. + +Flashing U-Boot into the eMMC +----------------------------- + +``DISCLAMER!`` All questions related to NvFlash should be asked in the proper +place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! + +Permanent installation can be performed either by using the nv3p protocol or by +pre-loading just built U-Boot into RAM. + +Flashing with the NV3P protocol +******************************* + +Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can +enter it either by pre-loading vendor bootloader into RAM with the nvflash. + +With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in +encrypted state in form, which can just be written RAW at the start of eMMC. + +.. code-block:: bash + + $ nvflash --setbct --bct picasso.bct --configfile flash.cfg --bl bootloader.bin + --sbk 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX --sync # replace with your SBK + $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + +When flashing is done, reboot the device. + +Flashing with a pre-loaded U-Boot +********************************* + +U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently +U-Boot supports bootmenu entry fastboot, which allows to write a processed copy +of U-Boot permanently into eMMC. + +While pre-loading U-Boot, hold the ``volume down`` button which will trigger +the bootmenu. There, select ``fastboot`` using the volume and power buttons. +After, on host PC, do: + +.. code-block:: bash + + $ fastboot flash 0.1 bct.img + $ fastboot flash 0.2 ebt.img + $ fastboot reboot + +Device will reboot. + +Boot +---- + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while booting, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console +and update bootloader (check the next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows +the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card +and insert it into the tablet. Enter bootmenu, choose update the bootloader +option with the Power button and U-Boot should update itself. Once the process +is completed, U-Boot will ask to press any button to reboot. diff --git a/doc/board/asus/grouper.rst b/doc/board/asus/grouper.rst index d56a9ca3921..14469582907 100644 --- a/doc/board/asus/grouper.rst +++ b/doc/board/asus/grouper.rst @@ -25,7 +25,7 @@ along with cellular one. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make grouper_defconfig # For all grouper versions and tilapia $ make @@ -79,18 +79,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/grouper.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have cellular version, +use ``tilapia.bct``. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/asus/transformer_t20.rst b/doc/board/asus/transformer_t20.rst index d4bc12d1619..4f4f893c3a8 100644 --- a/doc/board/asus/transformer_t20.rst +++ b/doc/board/asus/transformer_t20.rst @@ -25,7 +25,7 @@ defconfig. Valid fragments are ``tf101.config``, ``tf101g.config`` and .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t20_defconfig tf101.config # For TF101 $ make @@ -84,8 +84,8 @@ encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ wheelie -1 --bl bootloader.bin --bct tf101.bct --odm 0x300d8011 || break + $ nvflash --resume --rawdevicewrite 0 2048 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/asus/transformer_t30.rst b/doc/board/asus/transformer_t30.rst index bebc4b9fad3..012a38251aa 100644 --- a/doc/board/asus/transformer_t30.rst +++ b/doc/board/asus/transformer_t30.rst @@ -22,6 +22,7 @@ Build U-Boot U-Boot features ability to detect transformer device model on which it is loaded. The list of supported devices include: + - ASUS Transformer Prime TF201 - ASUS Transformer Pad (3G/LTE) TF300T/TG/TL - ASUS Transformer Infinity TF700T @@ -30,7 +31,7 @@ loaded. The list of supported devices include: .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make transformer_t30_defconfig $ make @@ -84,18 +85,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/tf201.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that you should adjust bct file +name according to your device. Flashing with a pre-loaded U-Boot ********************************* diff --git a/doc/board/htc/endeavoru.rst b/doc/board/htc/endeavoru.rst index e0edefe28ae..53df2d09a6f 100644 --- a/doc/board/htc/endeavoru.rst +++ b/doc/board/htc/endeavoru.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make endeavoru_defconfig $ make @@ -72,16 +72,15 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/endeavoru.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/board/index.rst b/doc/board/index.rst index 74c4dd1f42d..b055046e649 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -6,6 +6,7 @@ Board-specific doc .. toctree:: :maxdepth: 2 + acer/index actions/index advantech/index andestech/index diff --git a/doc/board/lg/x3_t30.rst b/doc/board/lg/x3_t30.rst index 618b00d34e3..9ff75034b72 100644 --- a/doc/board/lg/x3_t30.rst +++ b/doc/board/lg/x3_t30.rst @@ -24,7 +24,7 @@ board defconfig. Valid fragments are ``p880.config`` and ``p895.config``. .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make x3_t30_defconfig p895.config # For LG Optimus Vu $ make @@ -75,18 +75,18 @@ Flashing with the NV3P protocol ******************************* Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +enter it by pre-loading vendor bootloader with the Fusée Gelée. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --blob blob.bin - $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin + $ ./run_bootloader.sh -s T30 -t ./bct/p895.bct -b android_bootloader.bin + $ ./utiils/nvflash_v1.13.87205 --resume --rawdevicewrite 0 1024 repart-block.bin -When flashing is done, reboot the device. +When flashing is done, reboot the device. Note that if you have Optimus 4x HD, +use ``p880.bct``. Flashing with a pre-loaded U-Boot ********************************* @@ -122,7 +122,7 @@ the user to use/partition it in any way the user desires. Self Upgrading -------------- -Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC (using -ability of u-boot to mount it). Enter bootmenu, choose update bootloader option -with Power button and U-Boot should update itself. Once the process is -completed, U-Boot will ask to press any button to reboot. +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the eMMC or MicroSD +card if it is supported (using ability of u-boot to mount it). Enter bootmenu, +choose update bootloader option with Power button and U-Boot should update itself. +Once the process is completed, U-Boot will ask to press any button to reboot. diff --git a/doc/board/microsoft/surface-rt.rst b/doc/board/microsoft/surface-rt.rst index b5645e79340..2b29cce40a9 100644 --- a/doc/board/microsoft/surface-rt.rst +++ b/doc/board/microsoft/surface-rt.rst @@ -14,7 +14,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make surface-rt_defconfig $ make @@ -38,4 +38,4 @@ directory with To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on eMMC. Additionally, if the Volume Down button is pressed while loading, the device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC -as mass storage, fastboot, reboot, reboot RCM, poweroffand enter U-Boot console. +as mass storage, fastboot, reboot, reboot RCM, poweroff and enter U-Boot console. diff --git a/doc/board/wexler/qc750.rst b/doc/board/wexler/qc750.rst index b61e40176b0..169629c7e47 100644 --- a/doc/board/wexler/qc750.rst +++ b/doc/board/wexler/qc750.rst @@ -21,7 +21,7 @@ Build U-Boot .. code-block:: bash - $ export CROSS_COMPILE=arm-linux-gnueabi- + $ export CROSS_COMPILE=arm-none-eabi- $ make qc750_defconfig $ make @@ -71,16 +71,15 @@ pre-loading just built U-Boot into RAM. Flashing with the NV3P protocol ******************************* -Nv3p is a custom Nvidia protocol used to recover bricked devices. Devices can -enter it either by using ``wheelie`` with the correct ``blob.bin`` file or by -pre-loading vendor bootloader with the Fusée Gelée. +Nv3p is a custom Nvidia protocol used to recover bricked devices. Tegrarcm is +used to handle such state. With nv3p, ``repart-block.bin`` is used. It contains BCT and a bootloader in encrypted state in form, which can just be written RAW at the start of eMMC. .. code-block:: bash - $ wheelie --bct qc750.bct --bl bootloader.bin + $ tegrarcm --bct qc750.bct --bootloader android_bootloader.bin --loadaddr 0x80108000 $ nvflash --resume --rawdevicewrite 0 1024 repart-block.bin When flashing is done, reboot the device. diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 03deea2af1a..b6ad7218614 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -72,7 +72,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2025.04-rc2 was released on Mon 10 February 2025. -.. * U-Boot v2025.04-rc3 was released on Mon 24 February 2025. +* U-Boot v2025.04-rc3 was released on Mon 24 February 2025. .. * U-Boot v2025.04-rc4 was released on Mon 10 March 2025. diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index da929c33447..3d9f8b32b8d 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -1145,29 +1145,9 @@ static int gpio_request_tail(int ret, const char *nodename, ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node, &desc->dev); if (ret) { -#if CONFIG_IS_ENABLED(MAX77663_GPIO) || CONFIG_IS_ENABLED(PALMAS_GPIO) - struct udevice *pmic; - ret = uclass_get_device_by_ofnode(UCLASS_PMIC, args->node, - &pmic); - if (ret) { - log_debug("%s: PMIC device get failed, err %d\n", - __func__, ret); - goto err; - } - - device_foreach_child(desc->dev, pmic) { - if (device_get_uclass_id(desc->dev) == UCLASS_GPIO) - break; - } - - /* if loop exits without GPIO device return error */ - if (device_get_uclass_id(desc->dev) != UCLASS_GPIO) - goto err; -#else debug("%s: uclass_get_device_by_ofnode failed\n", __func__); goto err; -#endif } } ret = gpio_find_and_xlate(desc, args); diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c index 27ef890ed0a..22f61d12d38 100644 --- a/drivers/led/led-uclass.c +++ b/drivers/led/led-uclass.c @@ -273,6 +273,10 @@ static const char *led_get_function_name(struct udevice *dev) /* Now try to detect function label name */ func = dev_read_string(dev, "function"); cp = dev_read_u32(dev, "color", &color); + // prevent coverity scan error CID 541279: (TAINTED_SCALAR) + if (color < LED_COLOR_ID_WHITE || color >= LED_COLOR_ID_MAX) + cp = -EINVAL; + if (cp == 0 || func) { ret = dev_read_u32(dev, "function-enumerator", &enumerator); if (!ret) { diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 799586891af..31a72366206 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2376,7 +2376,7 @@ static int mmc_startup_v4(struct mmc *mmc) | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; capacity *= MMC_MAX_BLOCK_LEN; - if ((capacity >> 20) > 2 * 1024) + if (mmc->high_capacity) mmc->capacity_user = capacity; } diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c index 9fc8c686b88..f3a0f63003e 100644 --- a/drivers/net/dwc_eth_qos_rockchip.c +++ b/drivers/net/dwc_eth_qos_rockchip.c @@ -46,6 +46,10 @@ struct rockchip_platform_data { #define GRF_BIT(nr) (BIT(nr) | BIT((nr) + 16)) #define GRF_CLR_BIT(nr) (BIT((nr) + 16)) +#define DELAY_ENABLE(soc, tx, rx) \ + (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ + ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -85,8 +89,7 @@ static int rk3568_set_to_rgmii(struct udevice *dev, regmap_write(data->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RGMII | - RK3568_GMAC_RXCLK_DLY_ENABLE | - RK3568_GMAC_TXCLK_DLY_ENABLE); + DELAY_ENABLE(RK3568, tx_delay, rx_delay)); return 0; } @@ -131,6 +134,10 @@ static int rk3568_set_gmac_speed(struct udevice *dev) return 0; } +#define RK3588_DELAY_ENABLE(id, tx, rx) \ + (((tx) ? RK3588_GMAC_TXCLK_DLY_ENABLE(id) : RK3588_GMAC_TXCLK_DLY_DISABLE(id)) | \ + ((rx) ? RK3588_GMAC_RXCLK_DLY_ENABLE(id) : RK3588_GMAC_RXCLK_DLY_DISABLE(id))) + /* sys_grf */ #define RK3588_GRF_GMAC_CON7 0x031c #define RK3588_GRF_GMAC_CON8 0x0320 @@ -189,8 +196,7 @@ static int rk3588_set_to_rgmii(struct udevice *dev, RK3588_GMAC_CLK_RGMII_MODE(id)); regmap_write(data->grf, RK3588_GRF_GMAC_CON7, - RK3588_GMAC_RXCLK_DLY_ENABLE(id) | - RK3588_GMAC_TXCLK_DLY_ENABLE(id)); + RK3588_DELAY_ENABLE(id, tx_delay, rx_delay)); regmap_write(data->grf, offset_con, RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 47c2e923a1b..dd0dc2eff27 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -14,23 +14,68 @@ static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { { - .num = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x3 - }, { + /* gpio2_b7_sel */ .num = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7 }, { + /* gpio2_c7_sel */ .num = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x3 + }, { + /* gpio3_b1_sel */ + .num = 3, + .pin = 9, + .reg = 0x44, + .bit = 2, + .mask = 0x3 + }, { + /* gpio3_b2_sel */ + .num = 3, + .pin = 10, + .reg = 0x44, + .bit = 4, + .mask = 0x3 + }, { + /* gpio3_b3_sel */ + .num = 3, + .pin = 11, + .reg = 0x44, + .bit = 6, + .mask = 0x3 + }, { + /* gpio3_b4_sel */ + .num = 3, + .pin = 12, + .reg = 0x44, + .bit = 8, + .mask = 0x3 + }, { + /* gpio3_b5_sel */ + .num = 3, + .pin = 13, + .reg = 0x44, + .bit = 10, + .mask = 0x3 + }, { + /* gpio3_b6_sel */ + .num = 3, + .pin = 14, + .reg = 0x44, + .bit = 12, + .mask = 0x3 + }, { + /* gpio3_b7_sel */ + .num = 3, + .pin = 15, + .reg = 0x44, + .bit = 14, + .mask = 0x3 }, }; @@ -275,7 +320,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, - IOMUX_WIDTH_3BIT, + IOMUX_8WIDTH_2BIT, IOMUX_WIDTH_3BIT, 0), PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index d5171b8be23..d59b3ec7b5d 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -97,9 +97,9 @@ static int tegra_pinctrl_set_state(struct udevice *dev, struct udevice *config) * then actual pins setup (with node name prefix * conf_*) and then drive setup. */ - if (!strncmp(child->name, "conf_", 5)) + if (!strncmp(child->name, "conf", 4)) tegra_pinctrl_set_pin(child); - else if (!strncmp(child->name, "drive_", 6)) + else if (!strncmp(child->name, "drive", 5)) debug("%s: drive configuration is not supported\n", __func__); else tegra_pinctrl_set_func(child); diff --git a/drivers/power/pmic/max77663.c b/drivers/power/pmic/max77663.c index cf08b6a7e1d..c2a7cbf7e40 100644 --- a/drivers/power/pmic/max77663.c +++ b/drivers/power/pmic/max77663.c @@ -47,8 +47,9 @@ static int max77663_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_MAX77663)) { - ret = device_bind_driver(dev, MAX77663_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; @@ -56,8 +57,8 @@ static int max77663_bind(struct udevice *dev) } if (IS_ENABLED(CONFIG_MAX77663_GPIO)) { - ret = device_bind_driver(dev, MAX77663_GPIO_DRIVER, - "gpio", NULL); + ret = device_bind_driver_to_node(dev, MAX77663_GPIO_DRIVER, + "gpio", dev_ofnode(dev), NULL); if (ret) { log_err("cannot bind GPIOs (ret = %d)\n", ret); return ret; diff --git a/drivers/power/pmic/palmas.c b/drivers/power/pmic/palmas.c index f676bf64169..37d4190fabe 100644 --- a/drivers/power/pmic/palmas.c +++ b/drivers/power/pmic/palmas.c @@ -49,8 +49,9 @@ static int palmas_bind(struct udevice *dev) int children, ret; if (IS_ENABLED(CONFIG_SYSRESET_PALMAS)) { - ret = device_bind_driver(dev, PALMAS_RST_DRIVER, - "sysreset", NULL); + ret = device_bind_driver_to_node(dev, PALMAS_RST_DRIVER, + "sysreset", dev_ofnode(dev), + NULL); if (ret) { log_err("cannot bind SYSRESET (ret = %d)\n", ret); return ret; diff --git a/drivers/power/regulator/tps65941_regulator.c b/drivers/power/regulator/tps65941_regulator.c index bc4d153fd84..13f94b730d4 100644 --- a/drivers/power/regulator/tps65941_regulator.c +++ b/drivers/power/regulator/tps65941_regulator.c @@ -388,6 +388,14 @@ static int tps65941_ldo_enable(struct udevice *dev, int op, bool *enable) return 0; } +static int tps65941_ldo_volt2val(__maybe_unused int idx, int uV) +{ + if (uV > TPS65941_LDO_VOLT_MAX || uV < TPS65941_LDO_VOLT_MIN) + return -EINVAL; + + return ((uV - 600000) / 50000 + 0x4) << TPS65941_LDO_MODE_MASK; +} + static int tps65941_ldo_val2volt(__maybe_unused int idx, int val) { if (val > TPS65941_LDO_VOLT_MAX_HEX || val < TPS65941_LDO_VOLT_MIN_HEX) @@ -459,7 +467,7 @@ static int tps65224_ldo_val2volt(int idx, int val) static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { [TPS65941_LDO_CONV_OPS_IDX] = { .volt_mask = TPS65941_LDO_VOLT_MASK, - .volt2val = tps65941_buck_volt2val, + .volt2val = tps65941_ldo_volt2val, .val2volt = tps65941_ldo_val2volt, }, [TPS65224_LDO_CONV_OPS_IDX] = { @@ -472,7 +480,7 @@ static const struct tps65941_reg_conv_ops ldo_conv_ops[] = { static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) { unsigned int hex, adr; - int ret, ret_volt, idx; + int ret, ret_volt, idx, ldo_bypass; struct dm_regulator_uclass_plat *uc_pdata; const struct tps65941_reg_conv_ops *conv_ops; ulong chip_id; @@ -502,7 +510,9 @@ static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) if (ret < 0) return ret; + ldo_bypass = ret & TPS65941_LDO_BYPASS_EN; ret &= conv_ops->volt_mask; + ret = ret >> TPS65941_LDO_MODE_MASK; ret_volt = conv_ops->val2volt(idx, ret); if (ret_volt < 0) return ret_volt; @@ -531,7 +541,7 @@ static int tps65941_ldo_val(struct udevice *dev, int op, int *uV) ret &= ~TPS65224_LDO_VOLT_MASK; ret |= hex; } else { - ret = hex; + ret = hex | ldo_bypass; } ret = pmic_reg_write(dev->parent, adr, ret); diff --git a/drivers/tpm/tpm2_tis_mmio.c b/drivers/tpm/tpm2_tis_mmio.c index dee5503c055..fc62dcda9ef 100644 --- a/drivers/tpm/tpm2_tis_mmio.c +++ b/drivers/tpm/tpm2_tis_mmio.c @@ -135,7 +135,7 @@ static const struct tpm_ops tpm_tis_ops = { .cleanup = tpm_tis_cleanup, }; -static const struct tpm_tis_chip_data tpm_tis_std_chip_data = { +static struct tpm_tis_chip_data tpm_tis_std_chip_data = { .pcr_count = 24, .pcr_select_min = 3, }; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 0100723a68b..682a6910655 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -87,6 +87,14 @@ config USB_DWC3_LAYERSCAPE Host and Peripheral operation modes are supported. OTG is not supported. +config USB_DWC3_STI + bool "STi USB wrapper" + depends on DM_USB && USB_DWC3_GENERIC && SYSCON + help + Enables support for the on-chip xHCI controller on STMicroelectronics + STiH407 family SoCs. This is a driver for the dwc3 to provide the + glue logic to configure the controller. + menu "PHY Subsystem" config USB_DWC3_PHY_OMAP diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index a085c9d4628..985206eafe4 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_USB_DWC3_UNIPHIER) += dwc3-uniphier.o obj-$(CONFIG_USB_DWC3_LAYERSCAPE) += dwc3-layerscape.o obj-$(CONFIG_USB_DWC3_PHY_OMAP) += ti_usb_phy.o obj-$(CONFIG_USB_DWC3_PHY_SAMSUNG) += samsung_usb_phy.o +obj-$(CONFIG_USB_DWC3_STI) += dwc3-generic-sti.o diff --git a/drivers/usb/dwc3/dwc3-generic-sti.c b/drivers/usb/dwc3/dwc3-generic-sti.c new file mode 100644 index 00000000000..b34f5ceceac --- /dev/null +++ b/drivers/usb/dwc3/dwc3-generic-sti.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * STi specific glue layer for DWC3 + * + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_NOP + +#include <reset.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/read.h> +#include <linux/usb/otg.h> +#include "dwc3-generic.h" + +/* glue registers */ +#define CLKRST_CTRL 0x00 +#define AUX_CLK_EN BIT(0) +#define SW_PIPEW_RESET_N BIT(4) +#define EXT_CFG_RESET_N BIT(8) + +#define XHCI_REVISION BIT(12) + +#define USB2_VBUS_MNGMNT_SEL1 0x2C +#define USB2_VBUS_UTMIOTG 0x1 + +#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) +#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) +#define SEL_OVERRIDE_BVALID(n) ((n) << 8) + +/* Static DRD configuration */ +#define USB3_CONTROL_MASK 0xf77 + +#define USB3_DEVICE_NOT_HOST BIT(0) +#define USB3_FORCE_VBUSVALID BIT(1) +#define USB3_DELAY_VBUSVALID BIT(2) +#define USB3_SEL_FORCE_OPMODE BIT(4) +#define USB3_FORCE_OPMODE(n) ((n) << 5) +#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) +#define USB3_FORCE_DPPULLDOWN2 BIT(9) +#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) +#define USB3_FORCE_DMPULLDOWN2 BIT(11) + +static void dwc3_stih407_glue_configure(struct udevice *dev, int index, + enum usb_dr_mode mode) +{ + struct dwc3_glue_data *glue = dev_get_plat(dev); + struct regmap *regmap; + ulong syscfg_base; + ulong syscfg_offset; + ulong glue_base; + int ret; + + /* deassert both powerdown and softreset */ + ret = reset_deassert_bulk(&glue->resets); + if (ret) { + dev_err(dev, "reset_deassert_bulk error: %d\n", ret); + return; + } + + regmap = syscon_regmap_lookup_by_phandle(dev, "st,syscfg"); + if (IS_ERR(regmap)) { + dev_err(dev, "unable to get st,syscfg, dev %s\n", dev->name); + return; + } + + syscfg_base = regmap->ranges[0].start; + glue_base = dev_read_addr_index(dev, 0); + syscfg_offset = dev_read_addr_index(dev, 1); + + clrbits_le32(syscfg_base + syscfg_offset, USB3_CONTROL_MASK); + + /* glue drd init */ + switch (mode) { + case USB_DR_MODE_PERIPHERAL: + clrbits_le32(syscfg_base + syscfg_offset, + USB3_DELAY_VBUSVALID | USB3_SEL_FORCE_OPMODE | + USB3_FORCE_OPMODE(0x3) | USB3_SEL_FORCE_DPPULLDOWN2 | + USB3_FORCE_DPPULLDOWN2 | USB3_SEL_FORCE_DMPULLDOWN2 | + USB3_FORCE_DMPULLDOWN2); + + setbits_le32(syscfg_base + syscfg_offset, + USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID); + break; + + case USB_DR_MODE_HOST: + clrbits_le32(syscfg_base + syscfg_offset, + USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID | + USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) | + USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 | + USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); + + setbits_le32(syscfg_base + syscfg_offset, USB3_DELAY_VBUSVALID); + break; + + default: + dev_err(dev, "Unsupported mode of operation %d\n", mode); + return; + } + + /* glue init */ + setbits_le32(glue_base + CLKRST_CTRL, AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION); + clrbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); + + /* configure mux for vbus, powerpresent and bvalid signals */ + setbits_le32(glue_base + USB2_VBUS_MNGMNT_SEL1, + SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | + SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | + SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG)); + setbits_le32(glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); +}; + +struct dwc3_glue_ops stih407_ops = { + .glue_configure = dwc3_stih407_glue_configure, +}; + +static const struct udevice_id dwc3_sti_match[] = { + { .compatible = "st,stih407-dwc3", .data = (ulong)&stih407_ops}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(dwc3_sti_wrapper) = { + .name = "dwc3-sti", + .id = UCLASS_NOP, + .of_match = dwc3_sti_match, + .bind = dwc3_glue_bind, + .probe = dwc3_glue_probe, + .remove = dwc3_glue_remove, + .plat_auto = sizeof(struct dwc3_glue_data), +}; diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 55e62b35c61..21452ad1569 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -7,29 +7,17 @@ * Based on dwc3-omap.c. */ -#include <cpu_func.h> -#include <log.h> #include <dm.h> -#include <dm/device-internal.h> +#include <reset.h> +#include <asm/gpio.h> #include <dm/lists.h> -#include <dwc3-uboot.h> -#include <generic-phy.h> -#include <linux/bitops.h> #include <linux/delay.h> -#include <linux/printk.h> -#include <linux/usb/ch9.h> #include <linux/usb/gadget.h> -#include <malloc.h> #include <power/regulator.h> -#include <usb.h> -#include "core.h" -#include "gadget.h" -#include <reset.h> -#include <clk.h> #include <usb/xhci.h> -#include <asm/gpio.h> - +#include "core.h" #include "dwc3-generic.h" +#include "gadget.h" struct dwc3_generic_plat { fdt_addr_t base; diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index ffe1ae6eb73..d3fc4acb401 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -682,6 +682,7 @@ static int sleep_thread(struct fsg_common *common) k = 0; } + schedule(); dm_usb_gadget_handle_interrupts(udcdev); } common->thread_wakeup_needed = 0; diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 631969b3405..f2540eb6ded 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -207,7 +207,8 @@ void g_dnl_clear_detach(void) static int on_serialno(const char *name, const char *value, enum env_op op, int flags) { - g_dnl_set_serialnumber((char *)value); + if (value) + g_dnl_set_serialnumber((char *)value); return 0; } U_BOOT_ENV_CALLBACK(serialno, on_serialno); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index a656265890e..3dc79770eeb 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -110,15 +110,6 @@ config USB_XHCI_RCAR Choose this option to add support for USB 3.0 driver on Renesas R-Car Gen3 SoCs. -config USB_XHCI_STI - bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller" - depends on ARCH_STI - default y - help - Enables support for the on-chip xHCI controller on STMicroelectronics - STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic - to configure the controller. - config USB_XHCI_DRA7XX_INDEX int "DRA7XX xHCI USB index" range 0 1 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 301bb9fdee1..902d68d0378 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -54,7 +54,6 @@ obj-$(CONFIG_USB_XHCI_GENERIC) += xhci-generic.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o -obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o # designware diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c deleted file mode 100644 index 3e6834e38e3..00000000000 --- a/drivers/usb/host/dwc3-sti-glue.c +++ /dev/null @@ -1,253 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * STiH407 family DWC3 specific Glue layer - * - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. - */ - -#include <log.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <dm.h> -#include <errno.h> -#include <dm/lists.h> -#include <regmap.h> -#include <reset-uclass.h> -#include <syscon.h> -#include <usb.h> -#include <linux/printk.h> - -#include <linux/usb/dwc3.h> -#include <linux/usb/otg.h> -#include <dwc3-sti-glue.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * struct sti_dwc3_glue_plat - dwc3 STi glue driver private structure - * @syscfg_base: addr for the glue syscfg - * @glue_base: addr for the glue registers - * @syscfg_offset: usb syscfg control offset - * @powerdown_ctl: rest controller for powerdown signal - * @softreset_ctl: reset controller for softreset signal - * @mode: drd static host/device config - */ -struct sti_dwc3_glue_plat { - phys_addr_t syscfg_base; - phys_addr_t glue_base; - phys_addr_t syscfg_offset; - struct reset_ctl powerdown_ctl; - struct reset_ctl softreset_ctl; - enum usb_dr_mode mode; -}; - -static int sti_dwc3_glue_drd_init(struct sti_dwc3_glue_plat *plat) -{ - unsigned long val; - - val = readl(plat->syscfg_base + plat->syscfg_offset); - - val &= USB3_CONTROL_MASK; - - switch (plat->mode) { - case USB_DR_MODE_PERIPHERAL: - val &= ~(USB3_DELAY_VBUSVALID - | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) - | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 - | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); - - val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; - break; - - case USB_DR_MODE_HOST: - val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID - | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) - | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 - | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); - - val |= USB3_DELAY_VBUSVALID; - break; - - default: - pr_err("Unsupported mode of operation %d\n", plat->mode); - return -EINVAL; - } - writel(val, plat->syscfg_base + plat->syscfg_offset); - - return 0; -} - -static void sti_dwc3_glue_init(struct sti_dwc3_glue_plat *plat) -{ - unsigned long reg; - - reg = readl(plat->glue_base + CLKRST_CTRL); - - reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; - reg &= ~SW_PIPEW_RESET_N; - - writel(reg, plat->glue_base + CLKRST_CTRL); - - /* configure mux for vbus, powerpresent and bvalid signals */ - reg = readl(plat->glue_base + USB2_VBUS_MNGMNT_SEL1); - - reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | - SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | - SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); - - writel(reg, plat->glue_base + USB2_VBUS_MNGMNT_SEL1); - - setbits_le32(plat->glue_base + CLKRST_CTRL, SW_PIPEW_RESET_N); -} - -static int sti_dwc3_glue_of_to_plat(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - struct udevice *syscon; - struct regmap *regmap; - int ret; - u32 reg[4]; - - ret = ofnode_read_u32_array(dev_ofnode(dev), "reg", reg, - ARRAY_SIZE(reg)); - if (ret) { - pr_err("unable to find st,stih407-dwc3 reg property(%d)\n", ret); - return ret; - } - - plat->glue_base = reg[0]; - plat->syscfg_offset = reg[2]; - - /* get corresponding syscon phandle */ - ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "st,syscfg", - &syscon); - if (ret) { - pr_err("unable to find syscon device (%d)\n", ret); - return ret; - } - - /* get syscfg-reg base address */ - regmap = syscon_get_regmap(syscon); - if (!regmap) { - pr_err("unable to find regmap\n"); - return -ENODEV; - } - plat->syscfg_base = regmap->ranges[0].start; - - /* get powerdown reset */ - ret = reset_get_by_name(dev, "powerdown", &plat->powerdown_ctl); - if (ret) { - pr_err("can't get powerdown reset for %s (%d)", dev->name, ret); - return ret; - } - - /* get softreset reset */ - ret = reset_get_by_name(dev, "softreset", &plat->softreset_ctl); - if (ret) - pr_err("can't get soft reset for %s (%d)", dev->name, ret); - - return ret; -}; - -static int sti_dwc3_glue_bind(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - ofnode node, dwc3_node; - - /* Find snps,dwc3 node from subnode */ - ofnode_for_each_subnode(node, dev_ofnode(dev)) { - if (ofnode_device_is_compatible(node, "snps,dwc3")) - dwc3_node = node; - } - - if (!ofnode_valid(dwc3_node)) { - pr_err("Can't find dwc3 subnode for %s\n", dev->name); - return -ENODEV; - } - - /* retrieve the DWC3 dual role mode */ - plat->mode = usb_get_dr_mode(dwc3_node); - if (plat->mode == USB_DR_MODE_UNKNOWN) - /* by default set dual role mode to HOST */ - plat->mode = USB_DR_MODE_HOST; - - return dm_scan_fdt_dev(dev); -} - -static int sti_dwc3_glue_probe(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - int ret; - - /* deassert both powerdown and softreset */ - ret = reset_deassert(&plat->powerdown_ctl); - if (ret < 0) { - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - return ret; - } - - ret = reset_deassert(&plat->softreset_ctl); - if (ret < 0) { - pr_err("DWC3 soft reset deassert failed: %d", ret); - goto softreset_err; - } - - ret = sti_dwc3_glue_drd_init(plat); - if (ret) - goto init_err; - - sti_dwc3_glue_init(plat); - - return 0; - -init_err: - ret = reset_assert(&plat->softreset_ctl); - if (ret < 0) { - pr_err("DWC3 soft reset deassert failed: %d", ret); - return ret; - } - -softreset_err: - ret = reset_assert(&plat->powerdown_ctl); - if (ret < 0) - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - - return ret; -} - -static int sti_dwc3_glue_remove(struct udevice *dev) -{ - struct sti_dwc3_glue_plat *plat = dev_get_plat(dev); - int ret; - - /* assert both powerdown and softreset */ - ret = reset_assert(&plat->powerdown_ctl); - if (ret < 0) { - pr_err("DWC3 powerdown reset deassert failed: %d", ret); - return ret; - } - - ret = reset_assert(&plat->softreset_ctl); - if (ret < 0) - pr_err("DWC3 soft reset deassert failed: %d", ret); - - return ret; -} - -static const struct udevice_id sti_dwc3_glue_ids[] = { - { .compatible = "st,stih407-dwc3" }, - { } -}; - -U_BOOT_DRIVER(dwc3_sti_glue) = { - .name = "dwc3_sti_glue", - .id = UCLASS_NOP, - .of_match = sti_dwc3_glue_ids, - .of_to_plat = sti_dwc3_glue_of_to_plat, - .probe = sti_dwc3_glue_probe, - .remove = sti_dwc3_glue_remove, - .bind = sti_dwc3_glue_bind, - .plat_auto = sizeof(struct sti_dwc3_glue_plat), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts index bd6419a5c20..8311af4c868 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts +++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts @@ -74,6 +74,23 @@ vin-supply = <&vcc5v0_sys>; }; + /* + * HW revision prior to v1.2 must pull GPIO4_D6 low to access sdmmc. + * This is modeled as an always-on active low fixed regulator. + */ + vcc_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_2030>; + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + vcc5v0_sys: regulator-5v0-vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -181,6 +198,12 @@ }; }; + sdmmc { + sdmmc_2030: sdmmc-2030 { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wifi { wifi_reg_on: wifi-reg-on { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -233,7 +256,7 @@ cap-mmc-highspeed; cap-sd-highspeed; disable-wp; - vmmc-supply = <&vcc_io>; + vmmc-supply = <&vcc_sd>; status = "okay"; }; diff --git a/fs/erofs/fs.c b/fs/erofs/fs.c index 7bd2e8fcfc5..dcdc883e34c 100644 --- a/fs/erofs/fs.c +++ b/fs/erofs/fs.c @@ -59,16 +59,19 @@ struct erofs_dir_stream { static int erofs_readlink(struct erofs_inode *vi) { - size_t len = vi->i_size; + size_t alloc_size; char *target; int err; - target = malloc(len + 1); + if (__builtin_add_overflow(vi->i_size, 1, &alloc_size)) + return -EFSCORRUPTED; + + target = malloc(alloc_size); if (!target) return -ENOMEM; - target[len] = '\0'; + target[vi->i_size] = '\0'; - err = erofs_pread(vi, target, len, 0); + err = erofs_pread(vi, target, vi->i_size, 0); if (err) goto err_out; diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index b9314019b1b..8fac6c6c5a9 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -719,6 +719,7 @@ static int sqfs_read_inode_table(unsigned char **inode_table) u32 src_len, dest_offset = 0; unsigned long dest_len = 0; bool compressed; + size_t buf_size; table_size = get_unaligned_le64(&sblk->directory_table_start) - get_unaligned_le64(&sblk->inode_table_start); @@ -728,7 +729,10 @@ static int sqfs_read_inode_table(unsigned char **inode_table) sblk->directory_table_start, &table_offset); /* Allocate a proper sized buffer (itb) to store the inode table */ - itb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + itb = malloc_cache_aligned(buf_size); if (!itb) return -ENOMEM; @@ -806,6 +810,7 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) u32 src_len, dest_offset = 0; unsigned long dest_len = 0; bool compressed; + size_t buf_size; *dir_table = NULL; *pos_list = NULL; @@ -818,7 +823,10 @@ static int sqfs_read_directory_table(unsigned char **dir_table, u32 **pos_list) sblk->fragment_table_start, &table_offset); /* Allocate a proper sized buffer (dtb) to store the directory table */ - dtb = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + dtb = malloc_cache_aligned(buf_size); if (!dtb) return -ENOMEM; @@ -1369,6 +1377,7 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, unsigned long dest_len; struct fs_dirent *dent; unsigned char *ipos; + size_t buf_size; *actread = 0; @@ -1573,7 +1582,10 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, table_offset = frag_entry.start - (start * ctxt.cur_dev->blksz); n_blks = DIV_ROUND_UP(table_size + table_offset, ctxt.cur_dev->blksz); - fragment = malloc_cache_aligned(n_blks * ctxt.cur_dev->blksz); + if (__builtin_mul_overflow(n_blks, ctxt.cur_dev->blksz, &buf_size)) + return -EINVAL; + + fragment = malloc_cache_aligned(buf_size); if (!fragment) { ret = -ENOMEM; diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 5ced45b88b2..0077f6a5f95 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -26,6 +26,7 @@ "scriptaddr=0x88100000\0" \ "pxefile_addr_r=0x88200000\0" \ "ramdisk_addr_r=0x88300000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/picasso.h b/include/configs/picasso.h new file mode 100644 index 00000000000..a58c7e5f353 --- /dev/null +++ b/include/configs/picasso.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * (C) Copyright 2024 + * Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h deleted file mode 100644 index 2c0552d1a93..00000000000 --- a/include/dt-bindings/clock/rk3036-cru.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_GPLL 3 -#define ARMCLK 4 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI 65 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_NANDC 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_OTGPHY0 93 -#define SCLK_LCDC 100 -#define SCLK_HDMI 109 -#define SCLK_HEVC 111 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_VIDEO 125 -#define SCLK_MAC 151 -#define SCLK_MACREF 152 -#define SCLK_SFC 160 - -#define DCLK_LCDC 190 - -/* aclk gates */ -#define ACLK_DMAC2 194 -#define ACLK_LCDC 197 -#define ACLK_VIO 203 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_SPI 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_HDMI 360 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_WDT 368 - -/* hclk gates */ -#define HCLK_OTG0 449 -#define HCLK_OTG1 450 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_I2S 462 -#define HCLK_LCDC 465 -#define HCLK_ROM 467 -#define HCLK_VIO_BUS 472 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE0_DBG 4 -#define SRST_CORE1_DBG 5 -#define SRST_CORE0_POR 8 -#define SRST_CORE1_POR 9 -#define SRST_L2C 12 -#define SRST_TOPDBG 13 -#define SRST_STRC_SYS_A 14 -#define SRST_PD_CORE_NIU 15 - -#define SRST_TIMER2 16 -#define SRST_CPUSYS_H 17 -#define SRST_AHB2APB_H 19 -#define SRST_TIMER3 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S 24 -#define SRST_DDR_PLL 25 -#define SRST_GPU_DLL 26 -#define SRST_TIMER0 27 -#define SRST_TIMER1 28 -#define SRST_CORE_DLL 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_SFC 47 - -#define SRST_PWM0 48 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_GRF 55 -#define SRST_PERIPHSYS_A 57 -#define SRST_PERIPHSYS_H 58 -#define SRST_PERIPHSYS_P 59 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA2 64 -#define SRST_MAC 66 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_MMC0 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI0 84 -#define SRST_WDT 86 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 - -#define SRST_HDMI_P 96 -#define SRST_VIO_BUS_H 99 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_LCDC1_A 117 -#define SRST_LCDC1_H 118 -#define SRST_LCDC1_D 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 - -#define SRST_DBG_P 131 - -#endif diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h deleted file mode 100644 index 453f66718c6..00000000000 --- a/include/dt-bindings/clock/rk3288-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2014 MundoReader S.L. - * Author: Heiko Stuebner <heiko@sntech.de> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_NPLL 5 -#define ARMCLK 6 - -/* sclk gates (special clocks) */ -#define SCLK_GPU 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_SDIO1 70 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_PS2C 74 -#define SCLK_NANDC0 75 -#define SCLK_NANDC1 76 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S0 82 -#define SCLK_SPDIF 83 -#define SCLK_SPDIF8CH 84 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_TIMER6 91 -#define SCLK_HSADC 92 -#define SCLK_OTGPHY0 93 -#define SCLK_OTGPHY1 94 -#define SCLK_OTGPHY2 95 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_LCDC_PWM0 100 -#define SCLK_LCDC_PWM1 101 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_ISP_JPE 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S0_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_SDIO1_DRV 116 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_SDIO1_SAMPLE 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M_SRC 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_CRYPTO 125 -#define SCLK_MIPIDSI_24M 126 -#define SCLK_VIP_OUT 127 - -#define SCLK_MAC_PLL 150 -#define SCLK_MAC 151 -#define SCLK_MACREF_OUT 152 - -#define DCLK_VOP0 190 -#define DCLK_VOP1 191 - -/* aclk gates */ -#define ACLK_GPU 192 -#define ACLK_DMAC1 193 -#define ACLK_DMAC2 194 -#define ACLK_MMU 195 -#define ACLK_GMAC 196 -#define ACLK_VOP0 197 -#define ACLK_VOP1 198 -#define ACLK_CRYPTO 199 -#define ACLK_RGA 200 -#define ACLK_RGA_NIU 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NIU 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NIU 206 -#define ACLK_HEVC 207 -#define ACLK_VCODEC 208 -#define ACLK_CPU 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_GPIO4 324 -#define PCLK_GPIO5 325 -#define PCLK_GPIO6 326 -#define PCLK_GPIO7 327 -#define PCLK_GPIO8 328 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM 350 -#define PCLK_RKPWM 351 -#define PCLK_PS2C 352 -#define PCLK_TIMER 353 -#define PCLK_TZPC 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_DSI1 357 -#define PCLK_MIPI_CSI 358 -#define PCLK_LVDS_PHY 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO2_H2P 361 -#define PCLK_CPU 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL0 364 -#define PCLK_PUBL0 365 -#define PCLK_DDRUPCTL1 366 -#define PCLK_PUBL1 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 -#define PCLK_EFUSE1024 370 -#define PCLK_ISP_IN 371 - -/* hclk gates */ -#define HCLK_GPS 448 -#define HCLK_OTG0 449 -#define HCLK_USBHOST0 450 -#define HCLK_USBHOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_NANDC1 454 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_SDIO1 458 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S0 462 -#define HCLK_SPDIF 463 -#define HCLK_SPDIF8CH 464 -#define HCLK_VOP0 465 -#define HCLK_VOP1 466 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NIU 472 -#define HCLK_VIP 473 -#define HCLK_VIO2_H2P 474 -#define HCLK_HEVC 475 -#define HCLK_VCODEC 476 -#define HCLK_CPU 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0 0 -#define SRST_CORE1 1 -#define SRST_CORE2 2 -#define SRST_CORE3 3 -#define SRST_CORE0_PO 4 -#define SRST_CORE1_PO 5 -#define SRST_CORE2_PO 6 -#define SRST_CORE3_PO 7 -#define SRST_PDCORE_STRSYS 8 -#define SRST_PDBUS_STRSYS 9 -#define SRST_L2C 10 -#define SRST_TOPDBG 11 -#define SRST_CORE0_DBG 12 -#define SRST_CORE1_DBG 13 -#define SRST_CORE2_DBG 14 -#define SRST_CORE3_DBG 15 - -#define SRST_PDBUG_AHB_ARBITOR 16 -#define SRST_EFUSE256 17 -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_TIMER 22 -#define SRST_I2S0 23 -#define SRST_SPDIF 24 -#define SRST_TIMER0 25 -#define SRST_TIMER1 26 -#define SRST_TIMER2 27 -#define SRST_TIMER3 28 -#define SRST_TIMER4 29 -#define SRST_TIMER5 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_GPIO5 37 -#define SRST_GPIO6 38 -#define SRST_GPIO7 39 -#define SRST_GPIO8 40 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_TPIU 53 -#define SRST_PMU_APB 54 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_CCP 71 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_NANDC1 78 - -#define SRST_TZPC 80 -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIO1_NIU_AXI 103 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP 111 - -#define SRST_VCODEC_AXI 112 -#define SRST_VCODEC_AHB 113 -#define SRST_VIO_H2P 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDSI1 116 -#define SRST_MIPICSI 117 -#define SRST_LVDS_PHY 118 -#define SRST_LVDS_CON 119 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_SDIO1 130 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBHOST1_AHB 138 -#define SRST_USBHOST1_PHY 139 -#define SRST_USBHOST1_CON 140 -#define SRST_USB_ADP 141 -#define SRST_ACC_EFUSE 142 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_PD_CORE_MP_AXI 147 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_LCDC_PWM1 150 -#define SRST_VIO0_H2P_BRG 151 -#define SRST_VIO1_H2P_BRG 152 -#define SRST_RGA_H2P_BRG 153 -#define SRST_HEVC 154 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_DDRPHY0_CTRL 164 -#define SRST_DDRPHY1 165 -#define SRST_DDRPHY1_APB 166 -#define SRST_DDRCTRL1 167 -#define SRST_DDRCTRL1_APB 168 -#define SRST_DDRPHY1_CTRL 169 -#define SRST_DDRMSCH0 170 -#define SRST_DDRMSCH1 171 -#define SRST_CRYPTO 174 -#define SRST_C2C_HOST 175 - -#define SRST_LCDC1_AXI 176 -#define SRST_LCDC1_AHB 177 -#define SRST_LCDC1_DCLK 178 -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_PS2C 187 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 -#define SRST_TSP_CLKIN1 190 -#define SRST_TSP_27M 191 - -#endif diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h deleted file mode 100644 index 546ffbaf7b4..00000000000 --- a/include/dwc3-sti-glue.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. - */ - -#ifndef __DWC3_STI_UBOOT_H_ -#define __DWC3_STI_UBOOT_H_ - -/* glue registers */ -#include <linux/bitops.h> -#define CLKRST_CTRL 0x00 -#define AUX_CLK_EN BIT(0) -#define SW_PIPEW_RESET_N BIT(4) -#define EXT_CFG_RESET_N BIT(8) - -#define XHCI_REVISION BIT(12) - -#define USB2_VBUS_MNGMNT_SEL1 0x2C -#define USB2_VBUS_UTMIOTG 0x1 - -#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0) -#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4) -#define SEL_OVERRIDE_BVALID(n) ((n) << 8) - -/* Static DRD configuration */ -#define USB3_CONTROL_MASK 0xf77 - -#define USB3_DEVICE_NOT_HOST BIT(0) -#define USB3_FORCE_VBUSVALID BIT(1) -#define USB3_DELAY_VBUSVALID BIT(2) -#define USB3_SEL_FORCE_OPMODE BIT(4) -#define USB3_FORCE_OPMODE(n) ((n) << 5) -#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) -#define USB3_FORCE_DPPULLDOWN2 BIT(9) -#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) -#define USB3_FORCE_DMPULLDOWN2 BIT(11) - -int sti_dwc3_init(enum usb_dr_mode mode); - -#endif /* __DWC3_STI_UBOOT_H_ */ diff --git a/include/efi_loader.h b/include/efi_loader.h index dcae6a731a0..1d75d97ebbc 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -852,21 +852,6 @@ efi_status_t efi_get_memory_map(efi_uintn_t *memory_map_size, /* Adds a range into the EFI memory map */ efi_status_t efi_add_memory_map(u64 start, u64 size, int memory_type); -/** - * efi_add_memory_map_pg() - add pages to the memory map - * - * @start: start address, must be a multiple of - * EFI_PAGE_SIZE - * @pages: number of pages to add - * @memory_type: type of memory added - * @overlap_conventional: region may only overlap free(conventional) - * memory - * Return: status code - */ -efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, - int memory_type, - bool overlap_conventional); - /* Called by board init to initialize the EFI drivers */ efi_status_t efi_driver_init(void); /* Called when a block device is added */ @@ -1264,6 +1249,21 @@ efi_status_t efi_disk_get_device_name(const efi_handle_t handle, char *buf, int void efi_add_known_memory(void); /** + * efi_map_update_notify() - notify EFI of memory map changes + * + * @addr: start of memory area + * @size: size of memory area + * @op: type of change + * Return: 0 if change could be processed + */ +#ifdef CONFIG_EFI_LOADER +int efi_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op); +#else +#define efi_map_update_notify(addr, size, op) (0) +#endif + +/** * efi_load_option_dp_join() - join device-paths for load option * * @dp: in: binary device-path, out: joined device-path diff --git a/include/image.h b/include/image.h index 8a9f779d3ff..07912606f33 100644 --- a/include/image.h +++ b/include/image.h @@ -232,6 +232,7 @@ enum image_type_t { IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */ IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */ + IH_TYPE_TFA_BL31, /* TFA BL31 image */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/include/linux/string.h b/include/linux/string.h index 27b2beb9ddb..d943fcce690 100644 --- a/include/linux/string.h +++ b/include/linux/string.h @@ -72,6 +72,9 @@ extern char * strrchr(const char *,int); #ifndef __HAVE_ARCH_STRSTR extern char * strstr(const char *,const char *); #endif +#ifndef __HAVE_ARCH_STRNSTR +extern char *strnstr(const char *, const char *, size_t); +#endif #ifndef __HAVE_ARCH_STRLEN extern __kernel_size_t strlen(const char *); #endif diff --git a/include/lmb.h b/include/lmb.h index d9d7435a431..09297a4f530 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -32,6 +32,18 @@ #define LMB_NONOTIFY BIT(2) /** + * enum lmb_map_op - memory map operation + */ +enum lmb_map_op { + /** @LMB_MAP_OP_RESERVE: reserve memory */ + LMB_MAP_OP_RESERVE = 1, + /** @LMB_MAP_OP_FREE: free memory */ + LMB_MAP_OP_FREE, + /** @LMB_MAP_OP_ADD: add memory */ + LMB_MAP_OP_ADD, +}; + +/** * struct lmb_region - Description of one region * @base: Base address of the region * @size: Size of the region diff --git a/include/net-lwip.h b/include/net-lwip.h index 4d7f9387d1d..64e5c720560 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -10,6 +10,7 @@ enum proto_t { TFTPGET }; +void net_lwip_set_current(void); struct netif *net_lwip_new_netif(struct udevice *udev); struct netif *net_lwip_new_netif_noip(struct udevice *udev); void net_lwip_remove_netif(struct netif *netif); diff --git a/include/power/tps65941.h b/include/power/tps65941.h index cec85333f0b..a026ec56958 100644 --- a/include/power/tps65941.h +++ b/include/power/tps65941.h @@ -21,10 +21,11 @@ #define TPS65941_BUCK_VOLT_MAX 3340000 #define TPS65941_BUCK_MODE_MASK 0x1 -#define TPS65941_LDO_VOLT_MASK 0x3E +#define TPS65941_LDO_VOLT_MASK 0x7E #define TPS65941_LDO_VOLT_MAX_HEX 0x3A #define TPS65941_LDO_VOLT_MIN_HEX 0x4 #define TPS65941_LDO_VOLT_MAX 3300000 +#define TPS65941_LDO_VOLT_MIN 600000 #define TPS65941_LDO_MODE_MASK 0x1 #define TPS65941_LDO_BYPASS_EN 0x80 #define TP65941_BUCK_CONF_SLEW_MASK 0x7 diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c index d3c668dc183..070747de515 100644 --- a/lib/efi_driver/efi_block_device.c +++ b/lib/efi_driver/efi_block_device.c @@ -35,8 +35,10 @@ #include <efi_driver.h> #include <malloc.h> #include <dm/device-internal.h> +#include <dm/lists.h> #include <dm/root.h> #include <dm/tag.h> +#include <dm/uclass-internal.h> /** * struct efi_blk_plat - attributes of a block device @@ -118,13 +120,18 @@ static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, static efi_status_t efi_bl_create_block_device(efi_handle_t handle, void *interface) { - struct udevice *bdev = NULL, *parent = dm_root(); + struct udevice *bdev = NULL, *parent; efi_status_t ret; + int r; int devnum; char *name; struct efi_block_io *io = interface; struct efi_blk_plat *plat; + r = uclass_find_first_device(UCLASS_EFI_LOADER, &parent); + if (r) + return EFI_OUT_OF_RESOURCES; + devnum = blk_next_free_devnum(UCLASS_EFI_LOADER); if (devnum < 0) return EFI_OUT_OF_RESOURCES; @@ -221,6 +228,24 @@ efi_bl_init(struct efi_driver_binding_extended_protocol *this) return EFI_SUCCESS; } +/** + * efi_block_device_create() - create parent for EFI block devices + * + * Create a device that serves as parent for all block devices created via + * ConnectController(). + * + * Return: 0 for success + */ +static int efi_block_device_create(void) +{ + int ret; + struct udevice *dev; + + ret = device_bind_driver(gd->dm_root, "EFI block driver", "efi", &dev); + + return ret; +} + /* Block device driver operators */ static const struct blk_ops efi_blk_ops = { .read = efi_bl_read, @@ -249,3 +274,5 @@ U_BOOT_DRIVER(efi_block) = { .id = UCLASS_EFI_LOADER, .ops = &driver_ops, }; + +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, efi_block_device_create); diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 1f3de0a2339..5452640354e 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -531,7 +531,8 @@ static efi_status_t efi_disk_add_dev( /* Store first EFI system partition */ if (part && efi_system_partition.uclass_id == UCLASS_INVALID) { - if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) { + if (part_info && + part_info->bootable & PART_EFI_SYSTEM_PARTITION) { efi_system_partition.uclass_id = desc->uclass_id; efi_system_partition.devnum = desc->devnum; efi_system_partition.part = part; diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 1212772471e..6d00b186250 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -268,6 +268,7 @@ static s64 efi_mem_carve_out(struct efi_mem_list *map, * memory * Return: status code */ +static efi_status_t efi_add_memory_map_pg(u64 start, u64 pages, int memory_type, bool overlap_conventional) @@ -865,3 +866,30 @@ int efi_memory_init(void) return 0; } + +int efi_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op) +{ + u64 efi_addr; + u64 pages; + efi_status_t status; + + efi_addr = (uintptr_t)map_sysmem(addr, 0); + pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); + efi_addr &= ~EFI_PAGE_MASK; + + status = efi_add_memory_map_pg(efi_addr, pages, + op == LMB_MAP_OP_RESERVE ? + EFI_BOOT_SERVICES_DATA : + EFI_CONVENTIONAL_MEMORY, + false); + if (status != EFI_SUCCESS) { + log_err("LMB Map notify failure %lu\n", + status & ~EFI_ERROR_MASK); + return -1; + } + unmap_sysmem((void *)(uintptr_t)efi_addr); + + return 0; +} + diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index b265d95dd6b..31180df9e3a 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -19,6 +19,7 @@ */ static struct efi_var_file __efi_runtime_data *efi_var_buf; static struct efi_var_entry __efi_runtime_data *efi_current_var; +static const u16 __efi_runtime_rodata vtf[] = u"VarToFile"; /** * efi_var_mem_compare() - compare GUID and name with a variable @@ -331,7 +332,7 @@ efi_get_variable_mem(const u16 *variable_name, const efi_guid_t *vendor, if (timep) *timep = var->time; - if (!u16_strcmp(variable_name, u"VarToFile")) + if (!u16_strcmp(variable_name, vtf)) return efi_var_collect_mem(data, data_size, EFI_VARIABLE_NON_VOLATILE); old_size = *data_size; diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c index 0d090d051dd..6a1fa39bb6f 100644 --- a/lib/efi_loader/efi_variable_tee.c +++ b/lib/efi_loader/efi_variable_tee.c @@ -41,6 +41,7 @@ static u16 mm_sp_id; extern struct efi_var_file __efi_runtime_data *efi_var_buf; static efi_uintn_t max_buffer_size; /* comm + var + func + data */ static efi_uintn_t max_payload_size; /* func + data */ +static const u16 __efi_runtime_rodata pk[] = u"PK"; struct mm_connection { struct udevice *tee; @@ -858,7 +859,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (alt_ret != EFI_SUCCESS) goto out; - if (!u16_strcmp(variable_name, u"PK")) + if (!u16_strcmp(variable_name, pk)) alt_ret = efi_init_secure_state(); out: free(comm_buf); diff --git a/lib/lmb.c b/lib/lmb.c index 7ca44591e1d..93fc1bea07c 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -23,10 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define MAP_OP_RESERVE (u8)0x1 -#define MAP_OP_FREE (u8)0x2 -#define MAP_OP_ADD (u8)0x3 - /* * The following low level LMB functions must not access the global LMB memory * map since they are also used to manage IOVA memory maps in iommu drivers like @@ -430,42 +426,12 @@ long io_lmb_free(struct lmb *io_lmb, phys_addr_t base, phys_size_t size) static struct lmb lmb; -static bool lmb_should_notify(u32 flags) -{ - return !lmb.test && !(flags & LMB_NONOTIFY) && - CONFIG_IS_ENABLED(EFI_LOADER); -} - -static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, u8 op, - u32 flags) +static int lmb_map_update_notify(phys_addr_t addr, phys_size_t size, + enum lmb_map_op op, u32 flags) { - u64 efi_addr; - u64 pages; - efi_status_t status; - - if (op != MAP_OP_RESERVE && op != MAP_OP_FREE && op != MAP_OP_ADD) { - log_err("Invalid map update op received (%d)\n", op); - return -1; - } - - if (!lmb_should_notify(flags)) - return 0; - - efi_addr = (uintptr_t)map_sysmem(addr, 0); - pages = efi_size_in_pages(size + (efi_addr & EFI_PAGE_MASK)); - efi_addr &= ~EFI_PAGE_MASK; - - status = efi_add_memory_map_pg(efi_addr, pages, - op == MAP_OP_RESERVE ? - EFI_BOOT_SERVICES_DATA : - EFI_CONVENTIONAL_MEMORY, - false); - if (status != EFI_SUCCESS) { - log_err("%s: LMB Map notify failure %lu\n", __func__, - status & ~EFI_ERROR_MASK); - return -1; - } - unmap_sysmem((void *)(uintptr_t)efi_addr); + if (CONFIG_IS_ENABLED(EFI_LOADER) && + !lmb.test && !(flags & LMB_NONOTIFY)) + return efi_map_update_notify(addr, size, op); return 0; } @@ -642,7 +608,7 @@ long lmb_add(phys_addr_t base, phys_size_t size) if (ret) return ret; - return lmb_map_update_notify(base, size, MAP_OP_ADD, LMB_NONE); + return lmb_map_update_notify(base, size, LMB_MAP_OP_ADD, LMB_NONE); } long lmb_free_flags(phys_addr_t base, phys_size_t size, @@ -654,7 +620,7 @@ long lmb_free_flags(phys_addr_t base, phys_size_t size, if (ret < 0) return ret; - return lmb_map_update_notify(base, size, MAP_OP_FREE, flags); + return lmb_map_update_notify(base, size, LMB_MAP_OP_FREE, flags); } long lmb_free(phys_addr_t base, phys_size_t size) @@ -671,7 +637,7 @@ long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags) if (ret) return ret; - return lmb_map_update_notify(base, size, MAP_OP_RESERVE, flags); + return lmb_map_update_notify(base, size, LMB_MAP_OP_RESERVE, flags); } static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, @@ -712,7 +678,7 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, return 0; ret = lmb_map_update_notify(base, size, - MAP_OP_RESERVE, + LMB_MAP_OP_RESERVE, flags); if (ret) return ret; diff --git a/lib/lwip/lwip/src/apps/tftp/tftp.c b/lib/lwip/lwip/src/apps/tftp/tftp.c index 56aeabc4d73..63b1e0e0e20 100644 --- a/lib/lwip/lwip/src/apps/tftp/tftp.c +++ b/lib/lwip/lwip/src/apps/tftp/tftp.c @@ -264,19 +264,55 @@ static u16_t payload_size(void) return TFTP_DEFAULT_BLOCK_SIZE; } +/** + * find_option() - check if OACK message contains option + * + * @p: message buffer + * @option: option key + * Return: option value + */ static const char * find_option(struct pbuf *p, const char *option) { - int i; - u16_t optlen = strlen(option); - const char *b = p->payload; - - for (i = 0; i + optlen + 1 < p->len; i++) { - if (lwip_strnstr(b + i, option, optlen)) - return b + i + optlen + 2; - } + const char *pos = p->payload; + int rem = p->len; + + /* + * According to RFC 2347 the OACK packet has the following format: + * + * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ + * | opc | opt1 | 0 | value1 | 0 | optN | 0 | valueN | 0 | + * +-------+---~~---+---+---~~---+---+---~~---+---+---~~---+---+ + */ + + /* Skip opc */ + pos += 2; + rem -= 2; + if (rem <= 0) + return NULL; + + for (;;) { + int len; + int diff; + + len = strnlen(pos, rem) + 1; + if (rem < len) + break; + diff = strcmp(pos, option); + /* Skip option */ + pos += len; + rem -= len; + len = strnlen(pos, rem) + 1; + if (rem < len) + break; + if (!diff) + return pos; + /* Skip value */ + pos += len; + rem -= len; + } - return NULL; + return NULL; } static void diff --git a/lib/lwip/u-boot/arch/cc.h b/lib/lwip/u-boot/arch/cc.h index de138846358..6104c296f6f 100644 --- a/lib/lwip/u-boot/arch/cc.h +++ b/lib/lwip/u-boot/arch/cc.h @@ -34,7 +34,7 @@ x, __LINE__, __FILE__); } while (0) #define atoi(str) (int)dectoul(str, NULL) -#define lwip_strnstr(a, b, c) strstr(a, b) +#define lwip_strnstr(a, b, c) strnstr(a, b, c) #define LWIP_ERR_T int #define LWIP_CONST_CAST(target_type, val) ((target_type)((uintptr_t)val)) diff --git a/lib/mbedtls/external/mbedtls/framework b/lib/mbedtls/external/mbedtls/framework deleted file mode 160000 -Subproject 750634d3a51eb9d61b59fd5d801546927c94658 diff --git a/lib/string.c b/lib/string.c index 0e0900de8bf..d56f88d4a84 100644 --- a/lib/string.c +++ b/lib/string.c @@ -15,13 +15,14 @@ * reentrant and should be faster). Use only strsep() in new code, please. */ +#include <asm/sections.h> #include <config.h> +#include <limits.h> #include <linux/compiler.h> -#include <linux/types.h> -#include <linux/string.h> #include <linux/ctype.h> +#include <linux/string.h> +#include <linux/types.h> #include <malloc.h> -#include <asm/sections.h> /** * strncasecmp - Case insensitive, length-limited string comparison @@ -679,30 +680,48 @@ char *memdup(const void *src, size_t len) return p; } -#ifndef __HAVE_ARCH_STRSTR +#ifndef __HAVE_ARCH_STRNSTR /** - * strstr - Find the first substring in a %NUL terminated string - * @s1: The string to be searched - * @s2: The string to search for + * strnstr() - find the first substring occurrence in a NUL terminated string + * + * @s1: string to be searched + * @s2: string to search for + * @len: maximum number of characters in s2 to consider + * + * Return: pointer to the first occurrence or NULL */ -char * strstr(const char * s1,const char * s2) +char *strnstr(const char *s1, const char *s2, size_t len) { - int l1, l2; + size_t l1, l2; + l1 = strnlen(s1, len); l2 = strlen(s2); - if (!l2) - return (char *) s1; - l1 = strlen(s1); - while (l1 >= l2) { - l1--; - if (!memcmp(s1,s2,l2)) + + for (; l1 >= l2; --l1, ++s1) { + if (!memcmp(s1, s2, l2)) return (char *) s1; - s1++; } + return NULL; } #endif +#ifndef __HAVE_ARCH_STRSTR +/** + * strstr() - find the first substring occurrence in a NUL terminated string + * + * @s1: string to be searched + * @s2: string to search for + * @len: maximum number of characters in s2 to consider + * + * Return: pointer to the first occurrence or NULL + */ +char *strstr(const char *s1, const char *s2) +{ + return strnstr(s1, s2, SIZE_MAX); +} +#endif + #ifndef __HAVE_ARCH_MEMCHR /** * memchr - Find a character in an area of memory. diff --git a/lib/uuid.c b/lib/uuid.c index 97388f597a6..75658778044 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -120,6 +120,10 @@ static const struct { EFI_BLOCK_IO_PROTOCOL_GUID, }, { + "Disk IO", + EFI_DISK_IO_PROTOCOL_GUID, + }, + { "Simple File System", EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID, }, @@ -128,6 +132,10 @@ static const struct { EFI_LOADED_IMAGE_PROTOCOL_GUID, }, { + "Loaded Image Device Path", + EFI_LOADED_IMAGE_DEVICE_PATH_PROTOCOL_GUID, + }, + { "Graphics Output", EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID, }, @@ -140,10 +148,18 @@ static const struct { EFI_HII_DATABASE_PROTOCOL_GUID, }, { + "HII Config Access", + EFI_HII_CONFIG_ACCESS_PROTOCOL_GUID, + }, + { "HII Config Routing", EFI_HII_CONFIG_ROUTING_PROTOCOL_GUID, }, { + "Load File", + EFI_LOAD_FILE_PROTOCOL_GUID, + }, + { "Load File2", EFI_LOAD_FILE2_PROTOCOL_GUID, }, diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index e7d9147455c..3b7e4700c6e 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -115,7 +115,7 @@ int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) int ret; struct udevice *dev; - eth_set_current(); + net_lwip_set_current(); dev = eth_get_dev(); if (!dev) { diff --git a/net/lwip/dns.c b/net/lwip/dns.c index 1de63c9998b..149bdb784dc 100644 --- a/net/lwip/dns.c +++ b/net/lwip/dns.c @@ -121,7 +121,7 @@ int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (argc == 3) var = argv[2]; - eth_set_current(); + net_lwip_set_current(); return dns_loop(eth_get_dev(), name, var); } diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index b863047f598..cab1dd7d483 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -127,6 +127,20 @@ static int get_udev_ipv4_info(struct udevice *dev, ip4_addr_t *ip, return 0; } +/* Initialize the lwIP stack and the ethernet devices and set current device */ +void net_lwip_set_current(void) +{ + static bool init_done; + + if (!init_done) { + eth_init_rings(); + eth_init(); + lwip_init(); + init_done = true; + } + eth_set_current(); +} + static struct netif *new_netif(struct udevice *udev, bool with_ip) { unsigned char enetaddr[ARP_HLEN]; @@ -134,19 +148,10 @@ static struct netif *new_netif(struct udevice *udev, bool with_ip) ip4_addr_t ip, mask, gw; struct netif *netif; int ret = 0; - static bool first_call = true; if (!udev) return NULL; - if (first_call) { - eth_init_rings(); - /* Pick a valid active device, if any */ - eth_init(); - lwip_init(); - first_call = false; - } - if (eth_start_udev(udev) < 0) { log_err("Could not start %s\n", udev->name); return NULL; diff --git a/net/lwip/ping.c b/net/lwip/ping.c index aa617530749..200a702bbb5 100644 --- a/net/lwip/ping.c +++ b/net/lwip/ping.c @@ -168,7 +168,7 @@ int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (!ipaddr_aton(argv[1], &addr)) return CMD_RET_USAGE; - eth_set_current(); + net_lwip_set_current(); if (ping_loop(eth_get_dev(), &addr) < 0) return CMD_RET_FAILURE; diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c index fc4aff5f2ba..123d66b5dba 100644 --- a/net/lwip/tftp.c +++ b/net/lwip/tftp.c @@ -280,7 +280,7 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) goto out; } - eth_set_current(); + net_lwip_set_current(); if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0) ret = CMD_RET_FAILURE; diff --git a/net/lwip/wget.c b/net/lwip/wget.c index b76f6c0f1d9..14f27d42998 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -354,7 +354,7 @@ static int wget_loop(struct udevice *udev, ulong dst_addr, char *uri) int wget_do_request(ulong dst_addr, char *uri) { - eth_set_current(); + net_lwip_set_current(); if (!wget_info) wget_info = &default_wget_info; @@ -433,10 +433,15 @@ bool wget_validate_uri(char *uri) if (!strncmp(uri, "http://", strlen("http://"))) { prefix_len = strlen("http://"); - } else if (!strncmp(uri, "https://", strlen("https://"))) { - prefix_len = strlen("https://"); + } else if (CONFIG_IS_ENABLED(WGET_HTTPS)) { + if (!strncmp(uri, "https://", strlen("https://"))) { + prefix_len = strlen("https://"); + } else { + log_err("only http(s):// is supported\n"); + return false; + } } else { - log_err("only http(s):// is supported\n"); + log_err("only http:// is supported\n"); return false; } diff --git a/test/lib/string.c b/test/lib/string.c index 8d22f3fd68f..31391a387b9 100644 --- a/test/lib/string.c +++ b/test/lib/string.c @@ -11,6 +11,7 @@ #include <command.h> #include <log.h> +#include <string.h> #include <test/lib.h> #include <test/test.h> #include <test/ut.h> @@ -221,3 +222,42 @@ static int lib_memdup(struct unit_test_state *uts) return 0; } LIB_TEST(lib_memdup, 0); + +/** lib_strnstr() - unit test for strnstr() */ +static int lib_strnstr(struct unit_test_state *uts) +{ + const char *s1 = "Itsy Bitsy Teenie Weenie"; + const char *s2 = "eenie"; + const char *s3 = "eery"; + + ut_asserteq_ptr(&s1[12], strnstr(s1, s2, SIZE_MAX)); + ut_asserteq_ptr(&s1[12], strnstr(s1, s2, 17)); + ut_assertnull(strnstr(s1, s2, 16)); + ut_assertnull(strnstr(s1, s2, 0)); + ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], SIZE_MAX)); + ut_asserteq_ptr(&s1[13], strnstr(&s1[3], &s2[1], 14)); + ut_assertnull(strnstr(&s1[3], &s2[1], 13)); + ut_assertnull(strnstr(&s1[3], &s2[1], 0)); + ut_assertnull(strnstr(s1, s3, SIZE_MAX)); + ut_assertnull(strnstr(s1, s3, 0)); + + return 0; +} +LIB_TEST(lib_strnstr, 0); + +/** lib_strstr() - unit test for strstr() */ +static int lib_strstr(struct unit_test_state *uts) +{ + const char *s1 = "Itsy Bitsy Teenie Weenie"; + const char *s2 = "eenie"; + const char *s3 = "easy"; + + ut_asserteq_ptr(&s1[12], strstr(s1, s2)); + ut_asserteq_ptr(&s1[13], strstr(&s1[3], &s2[1])); + ut_assertnull(strstr(s1, s3)); + ut_asserteq_ptr(&s1[2], strstr(s1, &s3[2])); + ut_asserteq_ptr(&s1[8], strstr(&s1[5], &s3[2])); + + return 0; +} +LIB_TEST(lib_strstr, 0); diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py index 45143c1c7d9..177b982e891 100644 --- a/test/py/tests/test_event_dump.py +++ b/test/py/tests/test_event_dump.py @@ -19,6 +19,7 @@ def test_event_dump(u_boot_console): EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.* EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.* EVT_LAST_STAGE_INIT alloc_write_acpi_tables .*lib/acpi/acpi_table.c:.* +EVT_LAST_STAGE_INIT efi_block_device_create .*lib/efi_driver/efi_block_device.c:.* EVT_LAST_STAGE_INIT install_smbios_table .*lib/efi_loader/efi_smbios.c:.* EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.* EVT_TEST h_adder_simple .*test/common/event.c:''' diff --git a/tools/image-host.c b/tools/image-host.c index 05d8c898209..14e8bd52a65 100644 --- a/tools/image-host.c +++ b/tools/image-host.c @@ -364,33 +364,46 @@ static int fit_image_read_key_iv_data(const char *keydir, const char *key_iv_nam return ret; } -static int get_random_data(void *data, int size) +/** + * get_random_data() - fill buffer with random data + * + * There is no common cryptographically safe function in Linux and BSD. + * Hence directly access the /dev/urandom PRNG. + * + * @data: buffer to fill + * @size: buffer size + */ +static int get_random_data(void *data, size_t size) { - unsigned char *tmp = data; - struct timespec date; - int i, ret; - - if (!tmp) { - fprintf(stderr, "%s: pointer data is NULL\n", __func__); - ret = -1; - goto out; - } + int fd; + int ret; - ret = clock_gettime(CLOCK_MONOTONIC, &date); - if (ret) { - fprintf(stderr, "%s: clock_gettime has failed (%s)\n", __func__, - strerror(errno)); - goto out; + fd = open("/dev/urandom", O_RDONLY); + if (fd < 0) { + perror("Failed to open /dev/urandom"); + return -1; } - srandom(date.tv_nsec); + while (size) { + ssize_t count; - for (i = 0; i < size; i++) { - *tmp = random() & 0xff; - tmp++; + count = read(fd, data, size); + if (count < 0) { + if (errno == EINTR) { + continue; + } else { + perror("Failed to read from /dev/urandom"); + ret = -1; + goto out; + } + } + data += count; + size -= count; } + ret = 0; +out: + close(fd); - out: return ret; } |