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-rw-r--r--arch/arm/cpu/armv8/Kconfig30
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig2
-rw-r--r--board/freescale/ls1043ardb/Kconfig8
3 files changed, 21 insertions, 19 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 4d4469c8843..09f3f50fa22 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -90,6 +90,7 @@ config SPL_RECOVER_DATA_SECTION
config SEC_FIRMWARE_ARMV8_PSCI
bool "PSCI implementation in secure monitor firmware"
depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+ depends on ARMV8_PSCI=n
help
This config enables the ARMv8 PSCI implementation in secure monitor
firmware. This is a private PSCI implementation and different from
@@ -131,6 +132,9 @@ config PSCI_RESET
Select Y here to make use of PSCI calls for system reset
+config SYS_HAS_ARMV8_SECURE_BASE
+ bool
+
config ARMV8_PSCI
bool "Enable PSCI support" if EXPERT
help
@@ -158,23 +162,27 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
A value 0 or no definition of it works for single cluster system.
System with multi-cluster should difine their own exact value.
-config ARMV8_EA_EL3_FIRST
- bool "External aborts and SError interrupt exception are taken in EL3"
+config ARMV8_PSCI_RELOCATE
+ bool "Relocate PSCI code"
+ depends on ARMV8_PSCI
+ depends on SYS_HAS_ARMV8_SECURE_BASE
help
- Exception handling at all exception levels for External Abort and
- SError interrupt exception are taken in EL3.
-
-if SYS_HAS_ARMV8_SECURE_BASE
+ Relocate PSCI code, for example to a secure memory on the SoC. If not
+ set, the PSCI sections are placed together with the u-boot and the
+ regions will be marked as reserved before linux is started.
config ARMV8_SECURE_BASE
hex "Secure address for PSCI image"
- depends on ARMV8_PSCI
+ depends on ARMV8_PSCI_RELOCATE
+ default 0x18000000 if ARCH_LS1028A
help
Address for placing the PSCI text, data and stack sections.
- If not defined, the PSCI sections are placed together with the u-boot
- but platform can choose to place PSCI code image separately in other
- places such as some secure RAM built-in SOC etc.
-endif
+
+config ARMV8_EA_EL3_FIRST
+ bool "External aborts and SError interrupt exception are taken in EL3"
+ help
+ Exception handling at all exception levels for External Abort and
+ SError interrupt exception are taken in EL3.
endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6f8d5cb72fd..80a1642447d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -55,6 +55,7 @@ config ARCH_LS1028A
select SYS_FSL_ERRATUM_A011334
select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select RESV_RAM if GIC_V3_ITS
+ select SYS_HAS_ARMV8_SECURE_BASE
imply PANIC_HANG
config ARCH_LS1043A
@@ -90,6 +91,7 @@ config ARCH_LS1043A
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ select SYS_HAS_ARMV8_SECURE_BASE
imply CMD_PCI
imply ID_EEPROM
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index 778b8d8d5a5..d66c7804b13 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -13,14 +13,6 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1043ardb"
-config SYS_HAS_ARMV8_SECURE_BASE
- bool "Enable secure address for PSCI image"
- depends on ARMV8_PSCI
- help
- PSCI image can be re-located to secure RAM.
- If enabled, please also define the value for ARMV8_SECURE_BASE,
- for LS1043ARDB, it could be some address in OCRAM.
-
if FSL_LS_PPA
config SYS_LS_PPA_FW_ADDR
hex "PPA Firmware Addr"