diff options
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.c | 16 | ||||
| -rw-r--r-- | drivers/ddr/altera/sdram_soc64.h | 5 |
2 files changed, 20 insertions, 1 deletions
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 81cb79f35a9..f8fc92060db 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -29,6 +29,9 @@ #define PGTABLE_OFF 0x4000 +#define SINGLE_RANK_CLAMSHELL 0xc3c3 +#define DUAL_RANK_CLAMSHELL 0xa5a5 + #if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { @@ -258,8 +261,19 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); + u32 reg_ctrlcfg6_value = hmc_readl(plat, CTRLCFG6); + u32 cs_rank = CTRLCFG6_CFG_CS_CHIP(reg_ctrlcfg6_value); + u32 cs_addr_width; + + if (cs_rank == SINGLE_RANK_CLAMSHELL) + cs_addr_width = 0; + else if (cs_rank == DUAL_RANK_CLAMSHELL) + cs_addr_width = 1; + else + cs_addr_width = DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw); + phys_size_t size = (phys_size_t)1 << - (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + (cs_addr_width + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 5336ce3991c..6031cef560e 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -88,6 +88,8 @@ struct altera_sdram_plat { #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c #define CTRLCFG3 0x34 +#define CTRLCFG5 0x3c +#define CTRLCFG6 0x40 #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c #define CALTIMING1 0x80 @@ -128,6 +130,9 @@ struct altera_sdram_plat { #define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ (((x) >> 7) & 0x1) +#define CTRLCFG6_CFG_CS_CHIP(x) \ + ((x) & 0xFFFF) + #define DRAMTIMING0_CFG_TCL(x) \ ((x) & 0x7f) |