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-rw-r--r--arch/x86/dts/chromebook_coral.dts5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts
index dea35b73a0f..fe0d4dedd7c 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -516,6 +516,11 @@
20 23 22 21 18 19 16 17
/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
25 28 30 31 26 27 24 29>;
+
+ fspm,dimm0-spd-address = <0>;
+ fspm,dimm1-spd-address = <0>;
+ fspm,skip-cse-rbp = <1>;
+ fspm,enable-s3-heci2 = <0>;
};
&fsp_s {