diff options
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8m/soc.c | 25 |
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 3034d280cc3..1559bf6d218 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -31,6 +31,7 @@ #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 +#define CSU_BASE_ADDR 0x303E0000 #define SYSCNT_RD_BASE_ADDR 0x306A0000 #define SYSCNT_CMP_BASE_ADDR 0x306B0000 diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index cad9200dd1e..df865e997d3 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -561,6 +561,29 @@ static void imx8m_setup_snvs(void) writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); } +static void imx8m_setup_csu_tzasc(void) +{ + const uintptr_t tzasc_base[4] = { + 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000 + }; + int i, j; + + if (!IS_ENABLED(CONFIG_ARMV8_PSCI)) + return; + + /* CSU */ + for (i = 0; i < 64; i++) + writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i)); + + /* TZASC */ + for (j = 0; j < 4; j++) { + writel(0x77777777, (void *)(tzasc_base[j])); + writel(0x77777777, (void *)(tzasc_base[j]) + 0x4); + for (i = 0; i <= 0x10; i += 4) + writel(0, (void *)(tzasc_base[j]) + 0x40 + i); + } +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -613,6 +636,8 @@ int arch_cpu_init(void) imx8m_setup_snvs(); + imx8m_setup_csu_tzasc(); + return 0; } |