diff options
| -rw-r--r-- | configs/chromebook_coral_defconfig | 5 | ||||
| -rw-r--r-- | doc/board/google/chromebook_coral.rst | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 0fb73049738..b4f7e61ad0d 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -2,6 +2,7 @@ CONFIG_X86=y CONFIG_TEXT_BASE=0x1110000 CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x3d00 +CONFIG_BLOBLIST_SIZE_RELOC=0x30000 CONFIG_NR_DRAM_BANKS=8 CONFIG_MAX_CPUS=8 CONFIG_SPL_DM_SPI=y @@ -44,8 +45,8 @@ CONFIG_LOGF_FUNC=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BLOBLIST=y # CONFIG_TPL_BLOBLIST is not set -CONFIG_BLOBLIST_ADDR=0x100000 -CONFIG_BLOBLIST_SIZE=0x30000 +CONFIG_BLOBLIST_ADDR=0xfef10000 +CONFIG_BLOBLIST_SIZE=0x1000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_SEPARATE_BSS=y diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst index 1eda769c752..b48afb27938 100644 --- a/doc/board/google/chromebook_coral.rst +++ b/doc/board/google/chromebook_coral.rst @@ -243,7 +243,7 @@ board_init_r(), as per the rules, and DRAM is available then. SPL sets up a bloblist and passes the SPL hand-off information to U-Boot proper. This includes a pointer to the HOB list as well as DRAM information. See struct arch_spl_handoff. The bloblist address is set by CONFIG_BLOBLIST_ADDR, -normally 100000. +normally fef10000. SPL uses SPI flash to update the MRC caches in ROM. This speeds up subsequent boots. Be warned that SPL can take 30 seconds without this cache! This is a |