summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--board/freescale/p1_p2_rdb_pc/law.c1
-rw-r--r--board/freescale/p1_p2_rdb_pc/tlb.c3
-rw-r--r--include/configs/p1_p2_rdb_pc.h9
-rw-r--r--scripts/config_whitelist.txt4
4 files changed, 0 insertions, 17 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 5f4d713ca56..6bdfb356eed 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -9,7 +9,6 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 6ded38ac683..38843a96cbf 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -65,9 +65,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 10, BOOKE_PAGESZ_64K, 1),
#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 6d417c57fdb..2a24236c111 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -173,7 +173,6 @@
* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
* (early boot only)
* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
- * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
@@ -280,14 +279,6 @@
#endif
/* CPLD config size: 1Mb */
-#define CONFIG_SYS_PMC_BASE 0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index d9d63913dc3..b0d693a5826 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -418,8 +418,6 @@ CONFIG_PHY_IRAM_BASE
CONFIG_PL011_CLOCK
CONFIG_PL01x_PORTS
CONFIG_PM
-CONFIG_PMC_BR_PRELIM
-CONFIG_PMC_OR_PRELIM
CONFIG_PME_PLAT_CLK_DIV
CONFIG_POST
CONFIG_POSTBOOTMENU
@@ -1413,8 +1411,6 @@ CONFIG_SYS_PLL_FDR
CONFIG_SYS_PLL_ODR
CONFIG_SYS_PLL_SETTLING_TIME
CONFIG_SYS_PMAN
-CONFIG_SYS_PMC_BASE
-CONFIG_SYS_PMC_BASE_PHYS
CONFIG_SYS_PME_CLK
CONFIG_SYS_POST_MEMORY
CONFIG_SYS_POST_MEM_REGIONS