diff options
| -rw-r--r-- | arch/arm/dts/socfpga_agilex.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager_s10.c | 17 | ||||
| -rw-r--r-- | drivers/clk/altera/clk-mem-n5x.h | 4 |
3 files changed, 20 insertions, 5 deletions
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi index c3ead2d72b9..712304d07a4 100644 --- a/arch/arm/dts/socfpga_agilex.dtsi +++ b/arch/arm/dts/socfpga_agilex.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019, Intel Corporation + * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> */ /dts-v1/; @@ -20,7 +20,7 @@ service_reserved: svcbuffer@0 { compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x1000000>; + reg = <0x0 0x0 0x0 0x2000000>; alignment = <0x1000>; no-map; }; diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 4b4f0749dbf..45300336d52 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2023 Intel Corporation <www.intel.com> * */ @@ -399,6 +399,21 @@ unsigned int cm_get_l4_sys_free_clk_hz(void) return cm_get_l3_main_clk_hz() / 4; } +/* + * Override weak dw_spi_get_clk implementation in designware_spi.c driver + */ + +int dw_spi_get_clk(struct udevice *bus, ulong *rate) +{ + *rate = cm_get_spi_controller_clk_hz(); + if (!*rate) { + printf("SPI: clock rate is zero"); + return -EINVAL; + } + + return 0; +} + void cm_print_clock_quick_summary(void) { printf("MPU %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000)); diff --git a/drivers/clk/altera/clk-mem-n5x.h b/drivers/clk/altera/clk-mem-n5x.h index 7b687012e8f..c6bc44bb34c 100644 --- a/drivers/clk/altera/clk-mem-n5x.h +++ b/drivers/clk/altera/clk-mem-n5x.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* - * Copyright (C) 2020-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2020-2023 Intel Corporation <www.intel.com> */ #ifndef _CLK_MEM_N5X_ @@ -77,7 +77,7 @@ #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 -#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) +#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(0) #define MEMCLKMGR_EXTCNTRST_ALLCNTRST \ (MEMCLKMGR_EXTCNTRST_C0CNTRST) |