diff options
134 files changed, 371 insertions, 16258 deletions
@@ -1082,7 +1082,7 @@ expect = $(foreach cfg,$(1),y) # Show a deprecation message # Args: -# 1: List of CONFIG_DM_... to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK") +# 1: List of options to migrate to (e.g. "CONFIG_DM_MMC CONFIG_BLK") # 2: Name of component (e.g . "Ethernet drivers") # 3: Release deadline (e.g. "v202.07") # 4: Condition to require before checking (e.g. "$(CONFIG_NET)") @@ -1454,9 +1454,6 @@ u-boot-with-spl.kwb: u-boot.bin spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) $(BOARD_SIZE_CHECK) -u-boot.sha1: u-boot.bin - tools/ubsha1 u-boot.bin - u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ @@ -1531,8 +1528,7 @@ MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_TEXT_BASE) u-boot.ubl: u-boot-with-spl.bin FORCE $(call if_changed,mkimage) -MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \ - $(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \ +MKIMAGEFLAGS_u-boot-spl.ais = -s -n "/dev/null" \ -T aisimage -e $(CONFIG_SPL_TEXT_BASE) spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) @@ -1656,17 +1652,6 @@ OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE $(call if_changed,pad_cat) -# PPC4xx needs the SPL at the end of the image, since the reset vector -# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target -# and need to introduce a new build target with the full blown U-Boot -# at the start padded up to the start of the SPL image. And then concat -# the SPL image to the end. - -OBJCOPYFLAGS_u-boot-img-spl-at-end.bin := -I binary -O binary \ - --pad-to=$(CONFIG_UBOOT_PAD_TO) --gap-fill=0xff -u-boot-img-spl-at-end.bin: u-boot.img spl/u-boot-spl.bin FORCE - $(call if_changed,pad_cat) - quiet_cmd_u-boot-elf ?= LD $@ cmd_u-boot-elf ?= $(LD) u-boot-elf.o -o $@ \ $(if $(CONFIG_SYS_BIG_ENDIAN),-EB,-EL) \ @@ -2008,10 +1993,6 @@ dtbs: prepare3 scripts_dtc dtbs_install: $(Q)$(MAKE) $(dtbinst)=$(dtstree) -ifdef CONFIG_OF_EARLY_FLATTREE -all: dtbs -endif - endif # Check dtc and pylibfdt, if DTC is provided, else build them @@ -286,13 +286,6 @@ The following options need to be configured: same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. -- MIPS CPU options: - CONFIG_XWAY_SWAP_BYTES - - Enable compilation of tools/xway-swap-bytes needed for Lantiq - XWAY SoCs for booting from NOR flash. The U-Boot image needs to - be swapped if a flash programmer is used. - - ARM options: CFG_SYS_EXCEPTION_VECTORS_HIGH diff --git a/arch/arc/config.mk b/arch/arc/config.mk index b713fa3054c..b110f7deaf6 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -12,10 +12,6 @@ KBUILD_LDFLAGS += -EB PLATFORM_CPPFLAGS += -mbig-endian endif -ifdef CONFIG_ARC_MMU_VER -CONFIG_MMU = 1 -endif - PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common diff --git a/arch/arc/lib/ints_low.S b/arch/arc/lib/ints_low.S index 38c45c60a95..fb283f239ea 100644 --- a/arch/arc/lib/ints_low.S +++ b/arch/arc/lib/ints_low.S @@ -76,13 +76,8 @@ .endm .macro SAVE_EXCEPTION_SOURCE -#ifdef CONFIG_MMU - /* If MMU exists exception faulting address is loaded in EFA reg */ - lr %r0, [%efa] -#else /* Otherwise in ERET (exception return) reg */ lr %r0, [%eret] -#endif .endm ENTRY(memory_error) diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index b70822c67ab..5ac3740621c 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -7,8 +7,6 @@ extra-y = start.o obj-y += cpu.o -obj-$(CONFIG_IMX) += imx/ - # some files can only build in ARM mode ifdef CONFIG_$(SPL_)SYS_THUMB_BUILD diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index bfbd85ae64e..653eef8ad79 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -26,7 +26,6 @@ obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o obj-$(CONFIG_IPROC) += iproc-common/ -obj-$(CONFIG_KONA) += kona-common/ obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o ifneq (,$(filter s5pc1xx exynos,$(SOC))) @@ -38,7 +37,6 @@ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/ -obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_VF610) += vf610/ diff --git a/arch/arm/cpu/armv7/kona-common/Makefile b/arch/arm/cpu/armv7/kona-common/Makefile deleted file mode 100644 index 56de3d18e0e..00000000000 --- a/arch/arm/cpu/armv7/kona-common/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Broadcom Corporation. - -obj-y += s_init.o -obj-y += hwinit-common.o -obj-y += clk-stubs.o -obj-${CONFIG_KONA_RESET_S} += reset.o diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/arch/arm/cpu/armv7/kona-common/clk-stubs.c deleted file mode 100644 index 4eddaca8879..00000000000 --- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <common.h> - -/* - * These weak functions are available to kona architectures that don't - * require clock enables from the driver code. - */ -int __weak clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) -{ - return 0; -} - -int __weak clk_bsc_enable(void *base) -{ - return 0; -} - -int __weak clk_usb_otg_enable(void *base) -{ - return 0; -} diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c deleted file mode 100644 index cfc7c9fbc64..00000000000 --- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <common.h> -#include <cpu_func.h> -#include <asm/cache.h> -#include <linux/sizes.h> - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/arch/arm/cpu/armv7/kona-common/reset.S b/arch/arm/cpu/armv7/kona-common/reset.S deleted file mode 100644 index eea835b341c..00000000000 --- a/arch/arm/cpu/armv7/kona-common/reset.S +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -.globl reset_cpu -reset_cpu: - ldr r1, =0x35001f00 - ldr r2, [r1] - ldr r4, =0x80000000 - and r4, r2, r4 - ldr r3, =0xA5A500 - orr r4, r4, r3 - orr r4, r4, #0x1 - - str r4, [r1] - - ldr r1, =0x35001f04 - ldr r2, [r1] - ldr r4, =0x80000000 - and r4, r2, r4 - str r4, [r1] - -_loop_forever: - b _loop_forever diff --git a/arch/arm/cpu/armv7/kona-common/s_init.c b/arch/arm/cpu/armv7/kona-common/s_init.c deleted file mode 100644 index 778b9176fa2..00000000000 --- a/arch/arm/cpu/armv7/kona-common/s_init.c +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -/* - * Early system init. Currently empty. - */ -void s_init(void) -{ -} diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index 2e4bf9e038c..bba4f570dbb 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -39,7 +39,6 @@ obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o endif obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ -obj-$(CONFIG_S32V234) += s32v234/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ obj-$(CONFIG_ARMV8_PSCI) += psci.o obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/ diff --git a/arch/arm/lib/debug.S b/arch/arm/lib/debug.S index 5983f2c04ce..af4beb4d9d2 100644 --- a/arch/arm/lib/debug.S +++ b/arch/arm/lib/debug.S @@ -21,22 +21,10 @@ #include CONFIG_DEBUG_LL_INCLUDE #endif -#ifdef CONFIG_MMU - .macro addruart_current, rx, tmp1, tmp2 - addruart \tmp1, \tmp2, \rx - mrc p15, 0, \rx, c1, c0 - tst \rx, #1 - moveq \rx, \tmp1 - movne \rx, \tmp2 - .endm - -#else /* !CONFIG_MMU */ .macro addruart_current, rx, tmp1, tmp2 addruart \rx, \tmp1, \tmp2 .endm -#endif /* CONFIG_MMU */ - /* * Useful debugging routines */ @@ -97,15 +85,6 @@ ENTRY(printch) b 1b ENDPROC(printch) -#ifdef CONFIG_MMU -ENTRY(debug_ll_addr) - addruart r2, r3, ip - str r2, [r0] - str r3, [r1] - mov pc, lr -ENDPROC(debug_ll_addr) -#endif - #else ENTRY(printascii) diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index a23511b113b..a9f506cf2fb 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -35,10 +35,10 @@ endif extra-y += kwbimage.cfg -ifneq ($(CONFIG_ARMADA_370)$(CONFIG_ARMADA_XP),) +ifneq ($(CONFIG_ARMADA_XP),) KWB_REPLACE += CPU KWB_CFG_CPU = SHEEVA -else ifneq ($(CONFIG_ARMADA_375)$(CONFIG_ARMADA_38X)$(CONFIG_ARMADA_39X),) +else ifneq ($(CONFIG_ARMADA_375)$(CONFIG_ARMADA_38X),) KWB_REPLACE += CPU KWB_CFG_CPU = A9 endif diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 195bbeb5c88..5b86221bc25 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -7,9 +7,7 @@ obj-y = cpu_info.o obj-y += emac.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o -obj-$(CONFIG_GLOBAL_TIMER) += timer.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o -obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o diff --git a/arch/arm/mach-rmobile/cpu_info-sh73a0.c b/arch/arm/mach-rmobile/cpu_info-sh73a0.c deleted file mode 100644 index 0c7ee8acf5a..00000000000 --- a/arch/arm/mach-rmobile/cpu_info-sh73a0.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012 Renesas Solutions Corp. - */ -#include <common.h> -#include <asm/io.h> - -u32 rmobile_get_cpu_type(void) -{ - u32 id; - u32 type; - struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; - - id = readl(&hpb->cccr); - type = (id >> 8) & 0xFF; - - return type; -} - -u32 rmobile_get_cpu_rev_integer(void) -{ - u32 id; - u32 rev; - struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; - - id = readl(&hpb->cccr); - rev = ((id >> 4) & 0xF) + 1; - - return rev; -} - -u32 rmobile_get_cpu_rev_fraction(void) -{ - u32 id; - u32 rev; - struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; - - id = readl(&hpb->cccr); - rev = id & 0xF; - - return rev; -} diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index bd9e71707f5..246029ac294 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -62,7 +62,6 @@ static const struct { u16 cpu_type; u8 cpu_name[10]; } rmobile_cpuinfo[] = { - { RMOBILE_CPU_TYPE_SH73A0, "SH73A0" }, { RMOBILE_CPU_TYPE_R8A7740, "R8A7740" }, { RMOBILE_CPU_TYPE_R8A7790, "R8A7790" }, { RMOBILE_CPU_TYPE_R8A7791, "R8A7791" }, diff --git a/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h b/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h deleted file mode 100644 index ca8c5f37063..00000000000 --- a/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2013,2014 Renesas Electronics Corporation - * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - */ - -#ifndef __EHCI_RMOBILE_H__ -#define __EHCI_RMOBILE_H__ - -/* Register offset */ -#define OHCI_OFFSET 0x00 -#define OHCI_SIZE 0x1000 -#define EHCI_OFFSET 0x1000 -#define EHCI_SIZE 0x1000 - -#define EHCI_USBCMD (EHCI_OFFSET + 0x0020) - -/* USBCTR */ -#define DIRPD (1 << 8) -#define PLL_RST (1 << 2) -#define PCICLK_MASK (1 << 1) -#define USBH_RST (1 << 0) - -/* CMND_STS */ -#define SERREN (1 << 8) -#define PERREN (1 << 6) -#define MASTEREN (1 << 2) -#define MEMEN (1 << 1) - -/* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ -#define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) - -/* AHBPCI_WIN1_CTR */ -#define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) -#define AHB_CFG_AHBPCI 0x40000000 -#define AHB_CFG_HOST 0x80000000 - -/* AHBPCI_WIN2_CTR */ -#define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) - -/* PCI_INT_ENABLE */ -#define USBH_PMEEN (1 << 19) -#define USBH_INTBEN (1 << 17) -#define USBH_INTAEN (1 << 16) - -/* AHB_BUS_CTR */ -#define SMODE_READY_CTR (1 << 17) -#define SMODE_READ_BURST (1 << 16) -#define MMODE_HBUSREQ (1 << 7) -#define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) -#define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) -#define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) -#define MMODE_WR_INCR (1 << 2) -#define MMODE_BYTE_BURST (1 << 1) -#define MMODE_HTRANS (1 << 0) - -/* PCI_ARBITER_CTR */ -#define PCIBUS_PARK_TIMER 0x00FF0000 -#define PCIBUS_PARK_TIMER_SET 0x00070000 -#define PCIBP_MODE (1 << 12) -#define PCIREQ7 (1 << 7) -#define PCIREQ6 (1 << 6) -#define PCIREQ5 (1 << 5) -#define PCIREQ4 (1 << 4) -#define PCIREQ3 (1 << 3) -#define PCIREQ2 (1 << 2) -#define PCIREQ1 (1 << 1) -#define PCIREQ0 (1 << 0) - -#define SMSTPCR7 0xE615014C -#define SMSTPCR703 (1 << 3) - -/* Init AHB master and slave functions of the host logic */ -#define AHB_BUS_CTR_INIT \ - (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ - MMODE_BYTE_BURST | MMODE_HTRANS) - -#define USBCTR_WIN_SIZE_1GB 0x800 - -/* PCI Configuration Registers */ -#define PCI_CONF_OHCI_OFFSET 0x10000 -#define PCI_CONF_EHCI_OFFSET 0x10100 -struct ahb_pciconf { - u32 vid_did; - u32 cmnd_sts; - u32 rev; - u32 cache_line; - u32 basead; -}; - -/* PCI Configuration Registers for AHB-PCI Bridge Registers */ -#define PCI_CONF_AHBPCI_OFFSET 0x10000 -struct ahbconf_pci_bridge { - u32 vid_did; /* 0x00 */ - u32 cmnd_sts; - u32 revid_cc; - u32 cls_lt_ht_bist; - u32 basead; /* 0x10 */ - u32 win1_basead; - u32 win2_basead; - u32 dummy0[5]; - u32 ssvdi_ssid; /* 0x2C */ - u32 dummy1[4]; - u32 intr_line_pin; -}; - -/* AHB-PCI Bridge PCI Communication Registers */ -#define AHBPCI_OFFSET 0x10800 -struct ahbcom_pci_bridge { - u32 pciahb_win1_ctr; /* 0x00 */ - u32 pciahb_win2_ctr; - u32 pciahb_dct_ctr; - u32 dummy0; - u32 ahbpci_win1_ctr; /* 0x10 */ - u32 ahbpci_win2_ctr; - u32 dummy1; - u32 ahbpci_dct_ctr; - u32 pci_int_enable; /* 0x20 */ - u32 pci_int_status; - u32 dummy2[2]; - u32 ahb_bus_ctr; /* 0x30 */ - u32 usbctr; - u32 dummy3[2]; - u32 pci_arbiter_ctr; /* 0x40 */ - u32 dummy4; - u32 pci_unit_rev; /* 0x48 */ -}; - -struct rmobile_ehci_reg { - u32 hciversion; /* hciversion/caplength */ - u32 hcsparams; /* hcsparams */ - u32 hccparams; /* hccparams */ - u32 hcsp_portroute; /* hcsp_portroute */ - u32 usbcmd; /* usbcmd */ - u32 usbsts; /* usbsts */ - u32 usbintr; /* usbintr */ - u32 frindex; /* frindex */ - u32 ctrldssegment; /* ctrldssegment */ - u32 periodiclistbase; /* periodiclistbase */ - u32 asynclistaddr; /* asynclistaddr */ - u32 dummy[9]; - u32 configflag; /* configflag */ - u32 portsc; /* portsc */ -}; - -#endif /* __EHCI_RMOBILE_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h index 6b5e4ed4eb5..150aa46034d 100644 --- a/arch/arm/mach-rmobile/include/mach/gpio.h +++ b/arch/arm/mach-rmobile/include/mach/gpio.h @@ -1,10 +1,7 @@ #ifndef __ASM_ARCH_GPIO_H #define __ASM_ARCH_GPIO_H -#if defined(CONFIG_SH73A0) -#include "sh73a0-gpio.h" -void sh73a0_pinmux_init(void); -#elif defined(CONFIG_R8A7740) +#if defined(CONFIG_R8A7740) #include "r8a7740-gpio.h" void r8a7740_pinmux_init(void); #endif diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index dc6f87631bc..53f9a80ecfe 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -2,9 +2,7 @@ #define __ASM_ARCH_RMOBILE_H #if defined(CONFIG_ARCH_RMOBILE) -#if defined(CONFIG_SH73A0) -#include <asm/arch/sh73a0.h> -#elif defined(CONFIG_R8A7740) +#if defined(CONFIG_R8A7740) #include <asm/arch/r8a7740.h> #elif defined(CONFIG_R8A7790) #include <asm/arch/r8a7790.h> @@ -25,7 +23,6 @@ #endif /* CONFIG_ARCH_RMOBILE */ /* PRR CPU IDs */ -#define RMOBILE_CPU_TYPE_SH73A0 0x37 #define RMOBILE_CPU_TYPE_R8A7740 0x40 #define RMOBILE_CPU_TYPE_R8A7790 0x45 #define RMOBILE_CPU_TYPE_R8A7791 0x47 diff --git a/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h b/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h deleted file mode 100644 index 398e2c10913..00000000000 --- a/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h +++ /dev/null @@ -1,553 +0,0 @@ -#ifndef __ASM_SH73A0_H__ -#define __ASM_SH73A0_H__ - -/* Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function and MSEL switch - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* Hardware manual Table 25-1 (GPIO) */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, - - GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - - GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, - GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, - - GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, - GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, - - GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, - GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, - - GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, - GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, - - GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, - GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, - - GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, - GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, - - GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, - GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, - - GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, - GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, - - GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, - GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, - - GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, - - GPIO_PORT288, GPIO_PORT289, - - GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, - GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, - - GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, - GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, - - /* Table 25-1 (Function 0-7) */ - GPIO_FN_VBUS_0, - GPIO_FN_GPI0, - GPIO_FN_GPI1, - GPIO_FN_GPI2, - GPIO_FN_GPI3, - GPIO_FN_GPI4, - GPIO_FN_GPI5, - GPIO_FN_GPI6, - GPIO_FN_GPI7, - GPIO_FN_SCIFA7_RXD, - GPIO_FN_SCIFA7_CTS_, - GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, - GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, - GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ - GPIO_FN_PORT16_VIO_CKOR, - GPIO_FN_SCIFA0_TXD, - GPIO_FN_SCIFA7_TXD, - GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, - GPIO_FN_GPO0, - GPIO_FN_GPO1, - GPIO_FN_GPO2, GPIO_FN_STATUS0, - GPIO_FN_GPO3, GPIO_FN_STATUS1, - GPIO_FN_GPO4, GPIO_FN_STATUS2, - GPIO_FN_VINT, - GPIO_FN_TCKON, - GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ - GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, - GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ - GPIO_FN_PORT28_TPU1TO1, - GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, - GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, - GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, - GPIO_FN_SCIFA4_TXD, - GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, - GPIO_FN_SCIFA4_RTS_, - GPIO_FN_SCIFA4_CTS_, - GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, - GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, - GPIO_FN_FSIBOSLD, - GPIO_FN_FSIBISLD, - GPIO_FN_VACK, - GPIO_FN_XTAL1L, - GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, - GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, - GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, - GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, - GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, - GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, - GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ - GPIO_FN_FSIAOMC, - GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, - - GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, - GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, - GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ - GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, - GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ - GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, - GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, - GPIO_FN_A0, GPIO_FN_BS_, - GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, - GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, - GPIO_FN_A14, GPIO_FN_KEYOUT5, - GPIO_FN_A15, GPIO_FN_KEYOUT4, - GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, - GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, - GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, - GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, - GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, - GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, - GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, - GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, - GPIO_FN_A26, GPIO_FN_KEYIN6, - GPIO_FN_KEYIN7, - GPIO_FN_D0_NAF0, - GPIO_FN_D1_NAF1, - GPIO_FN_D2_NAF2, - GPIO_FN_D3_NAF3, - GPIO_FN_D4_NAF4, - GPIO_FN_D5_NAF5, - GPIO_FN_D6_NAF6, - GPIO_FN_D7_NAF7, - GPIO_FN_D8_NAF8, - GPIO_FN_D9_NAF9, - GPIO_FN_D10_NAF10, - GPIO_FN_D11_NAF11, - GPIO_FN_D12_NAF12, - GPIO_FN_D13_NAF13, - GPIO_FN_D14_NAF14, - GPIO_FN_D15_NAF15, - GPIO_FN_CS4_, - GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, - GPIO_FN_CS5B_, GPIO_FN_FCE1_, - GPIO_FN_CS6B_, GPIO_FN_DACK0, - GPIO_FN_FCE0_, GPIO_FN_CS6A_, - GPIO_FN_WAIT_, GPIO_FN_DREQ0, - GPIO_FN_RD__FSC, - GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, - GPIO_FN_WE1_, - GPIO_FN_FRB, - GPIO_FN_CKO, - GPIO_FN_NBRSTOUT_, - GPIO_FN_NBRST_, - GPIO_FN_BBIF2_TXD, - GPIO_FN_BBIF2_RXD, - GPIO_FN_BBIF2_SYNC, - GPIO_FN_BBIF2_SCK, - GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, - GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, - GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, - GPIO_FN_SCIFA3_TXD, - GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, - GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, - GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, - GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ - GPIO_FN_PORT115_I2C_SCL3, - GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ - GPIO_FN_PORT116_I2C_SDA3, - GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, - GPIO_FN_HSI_TX_FLAG, - GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ - GPIO_FN_LCD2D0, - - GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ - GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, - GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, - GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ - GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, - GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ - GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, - GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, - GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, - GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, - GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, - GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, - GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ - GPIO_FN_LCD2D6, - GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ - GPIO_FN_LCD2D7, - GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, - GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, - GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ - GPIO_FN_LCD2D2, - GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ - GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, - GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ - GPIO_FN_LCD2D4, - GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ - GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, - GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ - GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, - GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, - GPIO_FN_VIO_CKO, - GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ - GPIO_FN_PORT149_KEYOUT9, - GPIO_FN_MFG0_IN2, - GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, - GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, - GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, - GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, - GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, - GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, - GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, - GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, - GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, - GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, - GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, - GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ - GPIO_FN_TPU3TO0, - GPIO_FN_LCDD0, - GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, - GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, - GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, - GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, - GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ - GPIO_FN_TPU2TO1, - GPIO_FN_LCDD6, - GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, - GPIO_FN_LCDD8, GPIO_FN_D16, - GPIO_FN_LCDD9, GPIO_FN_D17, - GPIO_FN_LCDD10, GPIO_FN_D18, - GPIO_FN_LCDD11, GPIO_FN_D19, - GPIO_FN_LCDD12, GPIO_FN_D20, - GPIO_FN_LCDD13, GPIO_FN_D21, - GPIO_FN_LCDD14, GPIO_FN_D22, - GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, - GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, - GPIO_FN_LCDD17, GPIO_FN_D25, - GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, - GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, - GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, - GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, - GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, - GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, - GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, - GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ - GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, - GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ - GPIO_FN_PORT218_VIO_CKOR, - GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ - GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ - GPIO_FN_LCD2DCK_2, - GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, - GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ - GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ - GPIO_FN_PORT221_LCD2HSYN, - GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ - GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, - - GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, - GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, - GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, - GPIO_FN_SCIFA1_RXD, - GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, - GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, - GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, - GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, - GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, - GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ - GPIO_FN_LCD2D20, - GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ - GPIO_FN_LCD2D21, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, - GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, - GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, - GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, - GPIO_FN_SCIFA6_TXD, - GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ - GPIO_FN_TPU4TO0, - GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, - GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, - GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ - GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, - GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ - GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, - GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ - GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, - GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ - GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, - GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ - GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ - GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, - GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ - GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, - GPIO_FN_SDHICLK0, - GPIO_FN_SDHICD0, - GPIO_FN_SDHID0_0, - GPIO_FN_SDHID0_1, - GPIO_FN_SDHID0_2, - GPIO_FN_SDHID0_3, - GPIO_FN_SDHICMD0, - GPIO_FN_SDHIWP0, - GPIO_FN_SDHICLK1, - GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, - GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, - GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, - GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, - GPIO_FN_SDHICMD1, - GPIO_FN_SDHICLK2, - GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, - GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, - GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, - GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, - GPIO_FN_SDHICMD2, - GPIO_FN_MMCCLK0, - GPIO_FN_MMCD0_0, - GPIO_FN_MMCD0_1, - GPIO_FN_MMCD0_2, - GPIO_FN_MMCD0_3, - GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, - GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, - GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, - GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, - GPIO_FN_MMCCMD0, - GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, - GPIO_FN_MCP_WAIT__MCP_FRB, - GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, - GPIO_FN_MCP_D15_MCP_NAF15, - GPIO_FN_MCP_D14_MCP_NAF14, - GPIO_FN_MCP_D13_MCP_NAF13, - GPIO_FN_MCP_D12_MCP_NAF12, - GPIO_FN_MCP_D11_MCP_NAF11, - GPIO_FN_MCP_D10_MCP_NAF10, - GPIO_FN_MCP_D9_MCP_NAF9, - GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, - GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, - - GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, - GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, - GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, - GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, - GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, - GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, - GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, - GPIO_FN_MCP_NBRSTOUT_, - GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, - - /* MSEL2 special case */ - GPIO_FN_TSIF2_TS_XX1, - GPIO_FN_TSIF2_TS_XX2, - GPIO_FN_TSIF2_TS_XX3, - GPIO_FN_TSIF2_TS_XX4, - GPIO_FN_TSIF2_TS_XX5, - GPIO_FN_TSIF1_TS_XX1, - GPIO_FN_TSIF1_TS_XX2, - GPIO_FN_TSIF1_TS_XX3, - GPIO_FN_TSIF1_TS_XX4, - GPIO_FN_TSIF1_TS_XX5, - GPIO_FN_TSIF0_TS_XX1, - GPIO_FN_TSIF0_TS_XX2, - GPIO_FN_TSIF0_TS_XX3, - GPIO_FN_TSIF0_TS_XX4, - GPIO_FN_TSIF0_TS_XX5, - GPIO_FN_MST1_TS_XX1, - GPIO_FN_MST1_TS_XX2, - GPIO_FN_MST1_TS_XX3, - GPIO_FN_MST1_TS_XX4, - GPIO_FN_MST1_TS_XX5, - GPIO_FN_MST0_TS_XX1, - GPIO_FN_MST0_TS_XX2, - GPIO_FN_MST0_TS_XX3, - GPIO_FN_MST0_TS_XX4, - GPIO_FN_MST0_TS_XX5, - - /* MSEL3 special cases */ - GPIO_FN_SDHI0_VCCQ_MC0_ON, - GPIO_FN_SDHI0_VCCQ_MC0_OFF, - GPIO_FN_DEBUG_MON_VIO, - GPIO_FN_DEBUG_MON_LCDD, - GPIO_FN_LCDC_LCDC0, - GPIO_FN_LCDC_LCDC1, - - /* MSEL4 special cases */ - GPIO_FN_IRQ9_MEM_INT, - GPIO_FN_IRQ9_MCP_INT, - GPIO_FN_A11, - GPIO_FN_KEYOUT8, - GPIO_FN_TPU4TO3, - GPIO_FN_RESETA_N_PU_ON, - GPIO_FN_RESETA_N_PU_OFF, - GPIO_FN_EDBGREQ_PD, - GPIO_FN_EDBGREQ_PU, - - /* Functions with pull-ups */ - GPIO_FN_KEYIN0_PU, - GPIO_FN_KEYIN1_PU, - GPIO_FN_KEYIN2_PU, - GPIO_FN_KEYIN3_PU, - GPIO_FN_KEYIN4_PU, - GPIO_FN_KEYIN5_PU, - GPIO_FN_KEYIN6_PU, - GPIO_FN_KEYIN7_PU, - GPIO_FN_SDHICD0_PU, - GPIO_FN_SDHID0_0_PU, - GPIO_FN_SDHID0_1_PU, - GPIO_FN_SDHID0_2_PU, - GPIO_FN_SDHID0_3_PU, - GPIO_FN_SDHICMD0_PU, - GPIO_FN_SDHIWP0_PU, - GPIO_FN_SDHID1_0_PU, - GPIO_FN_SDHID1_1_PU, - GPIO_FN_SDHID1_2_PU, - GPIO_FN_SDHID1_3_PU, - GPIO_FN_SDHICMD1_PU, - GPIO_FN_SDHID2_0_PU, - GPIO_FN_SDHID2_1_PU, - GPIO_FN_SDHID2_2_PU, - GPIO_FN_SDHID2_3_PU, - GPIO_FN_SDHICMD2_PU, - GPIO_FN_MMCCMD0_PU, - GPIO_FN_MMCCMD1_PU, - GPIO_FN_MMCD0_0_PU, - GPIO_FN_MMCD0_1_PU, - GPIO_FN_MMCD0_2_PU, - GPIO_FN_MMCD0_3_PU, - GPIO_FN_MMCD0_4_PU, - GPIO_FN_MMCD0_5_PU, - GPIO_FN_MMCD0_6_PU, - GPIO_FN_MMCD0_7_PU, - GPIO_FN_FSIACK_PU, - GPIO_FN_FSIAILR_PU, - GPIO_FN_FSIAIBT_PU, - GPIO_FN_FSIAISLD_PU, - - /* end of GPIO */ - GPIO_NR, -}; - -/* DMA slave IDs */ -enum { - SHDMA_SLAVE_INVALID, - SHDMA_SLAVE_SCIF0_TX, - SHDMA_SLAVE_SCIF0_RX, - SHDMA_SLAVE_SCIF1_TX, - SHDMA_SLAVE_SCIF1_RX, - SHDMA_SLAVE_SCIF2_TX, - SHDMA_SLAVE_SCIF2_RX, - SHDMA_SLAVE_SCIF3_TX, - SHDMA_SLAVE_SCIF3_RX, - SHDMA_SLAVE_SCIF4_TX, - SHDMA_SLAVE_SCIF4_RX, - SHDMA_SLAVE_SCIF5_TX, - SHDMA_SLAVE_SCIF5_RX, - SHDMA_SLAVE_SCIF6_TX, - SHDMA_SLAVE_SCIF6_RX, - SHDMA_SLAVE_SCIF7_TX, - SHDMA_SLAVE_SCIF7_RX, - SHDMA_SLAVE_SCIF8_TX, - SHDMA_SLAVE_SCIF8_RX, - SHDMA_SLAVE_SDHI0_TX, - SHDMA_SLAVE_SDHI0_RX, - SHDMA_SLAVE_SDHI1_TX, - SHDMA_SLAVE_SDHI1_RX, - SHDMA_SLAVE_SDHI2_TX, - SHDMA_SLAVE_SDHI2_RX, - SHDMA_SLAVE_MMCIF_TX, - SHDMA_SLAVE_MMCIF_RX, -}; - -/* - * SH73A0 IRQ LOCATION TABLE - * - * 416 ----------------------------------------- - * IRQ0-IRQ15 - * 431 ----------------------------------------- - * ... - * 448 ----------------------------------------- - * sh73a0-intcs - * sh73a0-intca-irq-pins - * 680 ----------------------------------------- - * ... - * 700 ----------------------------------------- - * sh73a0-pint0 - * 731 ----------------------------------------- - * 732 ----------------------------------------- - * sh73a0-pint1 - * 739 ----------------------------------------- - * ... - * 800 ----------------------------------------- - * IRQ16-IRQ31 - * 815 ----------------------------------------- - * ... - * 928 ----------------------------------------- - * sh73a0-intca-irq-pins - * 943 ----------------------------------------- - */ - -/* PINT interrupts are located at Linux IRQ 700 and up */ -#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) -#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) - -#endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/sh73a0.h b/arch/arm/mach-rmobile/include/mach/sh73a0.h deleted file mode 100644 index bdbb4086421..00000000000 --- a/arch/arm/mach-rmobile/include/mach/sh73a0.h +++ /dev/null @@ -1,289 +0,0 @@ -#ifndef __ASM_ARCH_RMOBILE_SH73A0_H -#define __ASM_ARCH_RMOBILE_SH73A0_H - -/* Global Timer */ -#define GLOBAL_TIMER_BASE_ADDR (0xF0000200) -#define MERAM_BASE (0xE5580000) - -/* GIC */ -#define GIC_BASE (0xF0000100) -#define ICCICR GIC_BASE - -/* Secure control register */ -#define LIFEC_SEC_SRC (0xE6110008) - -/* RWDT */ -#define RWDT_BASE (0xE6020000) - -/* HPB Semaphore Control Registers */ -#define HPB_BASE (0xE6001010) - -/* Bus Semaphore Control Registers */ -#define HPBSCR_BASE (0xE6001600) - -/* SBSC1 */ -#define SBSC1_BASE (0xFE400000) -#define SDMRA1A (SBSC1_BASE + 0x100000) -#define SDMRA2A (SBSC1_BASE + 0x1C0000) -#define SDMRA3A (SBSC1_BASE + 0x104000) - -/* SBSC2 */ -#define SBSC2_BASE (0xFB400000) -#define SDMRA1B (SBSC2_BASE + 0x100000) -#define SDMRA2B (SBSC2_BASE + 0x1C0000) -#define SDMRA3B (SBSC2_BASE + 0x104000) - -/* CPG */ -#define CPG_BASE (0xE6150000) -#define CPG_SRCR_BASE (CPG_BASE + 0x80A0) -#define WUPCR (CPG_BASE + 0x1010) -#define SRESCR (CPG_BASE + 0x1018) -#define PCLKCR (CPG_BASE + 0x1020) - -/* SYSC */ -#define SYSC_BASE (0xE6180000) -#define RESCNT2 (SYSC_BASE + 0x8020) - -/* BSC */ -#define BSC_BASE (0xFEC10000) - -/* SCIF */ -#define SCIF0_BASE (0xE6C40000) -#define SCIF1_BASE (0xE6C50000) -#define SCIF2_BASE (0xE6C60000) -#define SCIF3_BASE (0xE6C70000) -#define SCIF4_BASE (0xE6C80000) -#define SCIF5_BASE (0xE6CB0000) -#define SCIF6_BASE (0xE6CC0000) -#define SCIF7_BASE (0xE6CD0000) - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct sh73a0_rwdt { - u16 rwtcnt0; /* 0x00 */ - u16 dummy0; /* 0x02 */ - u16 rwtcsra0; /* 0x04 */ - u16 dummy1; /* 0x06 */ - u16 rwtcsrb0; /* 0x08 */ -}; - -/* HPB Semaphore Control Registers */ -struct sh73a0_hpb { - u32 hpbctrl0; - u32 hpbctrl1; - u32 hpbctrl2; - u32 cccr; - u32 dummy0; /* 0x20 */ - u32 hpbctrl4; - u32 hpbctrl5; - u32 dummy1; /* 0x2C */ - u32 hpbctrl6; -}; - -/* Bus Semaphore Control Registers */ -struct sh73a0_hpb_bscr { - u32 mpsrc; /* 0x00 */ - u32 mpacctl; /* 0x04 */ - u32 dummy0[6]; - u32 smgpiosrc; /* 0x20 */ - u32 smgpioerr; - u32 smgpiotime; - u32 smgpiocnt; - u32 dummy1[4]; /* 0x30 .. 0x3C */ - u32 smcmt2src; - u32 smcmt2err; - u32 smcmt2time; - u32 smcmt2cnt; - u32 smcpgsrc; - u32 smcpgerr; - u32 smcpgtime; - u32 smcpgcnt; - u32 dummy2[4]; /* 0x60 - 0x6C */ - u32 smsyscsrc; - u32 smsyscerr; - u32 smsysctime; - u32 smsysccnt; -}; - -/* SBSC */ -struct sh73a0_sbsc { - u32 dummy0[2]; /* 0x00, 0x04 */ - u32 sdcr0; - u32 sdcr1; - u32 sdpcr; - u32 dummy1; /* 0x14 */ - u32 sdcr0s; - u32 sdcr1s; - u32 rtcsr; - u32 dummy2; /* 0x24 */ - u32 rtcor; - u32 rtcorh; - u32 rtcors; - u32 rtcorsh; - u32 dummy3[2]; /* 0x38, 0x3C */ - u32 sdwcrc0; - u32 sdwcrc1; - u32 sdwcr00; - u32 sdwcr01; - u32 sdwcr10; - u32 sdwcr11; - u32 sdpdcr0; - u32 dummy4; /* 0x5C */ - u32 sdwcr2; - u32 sdwcrc2; - u32 zqccr; - u32 dummy5[6]; /* 0x6C .. 0x80 */ - u32 sdmracr0; - u32 dummy6; /* 0x88 */ - u32 sdmrtmpcr; - u32 dummy7; /* 0x90 */ - u32 sdmrtmpmsk; - u32 dummy8; /* 0x98 */ - u32 sdgencnt; - u32 dphycnt0; - u32 dphycnt1; - u32 dphycnt2; - u32 dummy9[2]; /* 0xAC .. 0xB0 */ - u32 sddrvcr0; - u32 dummy10[14]; /* 0xB8 .. 0xEC */ - u32 dptdivcr0; - u32 dptdivcr1; - u32 dptdivcr2; - u32 dummy11; /* 0xFC */ - u32 sdptcr0; - u32 sdptcr1; - u32 sdptcr2; - u32 sdptcr3; /* 0x10C */ - u32 dummy12[145]; /* 0x110 .. 0x350 */ - u32 dllcnt0; /* 0x354 */ - u32 sbscmon0; -}; - -/* CPG */ -struct sh73a0_sbsc_cpg { - u32 frqcra; /* 0x00 */ - u32 frqcrb; - u32 vclkcr1; - u32 vclkcr2; - u32 zbckcr; - u32 flckcr; - u32 fsiackcr; - u32 vclkcr3; - u32 rtstbcr; - u32 systbcr; - u32 pll1cr; - u32 pll2cr; - u32 mstpsr0; - u32 dummy0; /* 0x34 */ - u32 mstpsr1; - u32 mstpsr5; - u32 mstpsr2; - u32 dummy1; /* 0x44 */ - u32 mstpsr3; - u32 mstpsr4; - u32 dummy2; /* 0x50 */ - u32 astat; - u32 dvfscr0; - u32 dvfscr1; - u32 dsitckcr; - u32 dsi0pckcr; - u32 dsi1pckcr; - u32 dsi0phycr; - u32 dsi1phycr; - u32 sd0ckcr; - u32 sd1ckcr; - u32 sd2ckcr; - u32 subckcr; - u32 spuackcr; - u32 msuckcr; - u32 hsickcr; - u32 fsibckcr; - u32 spuvckcr; - u32 mfck1cr; - u32 mfck2cr; - u32 dummy3[8]; /* 0xA0 .. 0xBC */ - u32 ckscr; - u32 dummy4; /* 0xC4 */ - u32 pll1stpcr; - u32 mpmode; - u32 pllecr; - u32 dummy5; /* 0xD4 */ - u32 pll0cr; - u32 pll3cr; - u32 dummy6; /* 0xE0 */ - u32 frqcrd; - u32 dummyi7; /* 0xE8 */ - u32 vrefcr; - u32 pll0stpcr; - u32 dummy8; /* 0xF4 */ - u32 pll2stpcr; - u32 pll3stpcr; - u32 dummy9[4]; /* 0x100 .. 0x10c */ - u32 rmstpcr0; - u32 rmstpcr1; - u32 rmstpcr2; - u32 rmstpcr3; - u32 rmstpcr4; - u32 rmstpcr5; - u32 dummy10[2]; /* 0x128 .. 0x12c */ - u32 smstpcr0; - u32 smstpcr1; - u32 smstpcr2; - u32 smstpcr3; - u32 smstpcr4; - u32 smstpcr5; - u32 dummy11[2]; /* 0x148 .. 0x14c */ - u32 cpgxxcs4; - u32 dummy12[7]; /* 0x154 .. 0x16c */ - u32 dvfscr2; - u32 dvfscr3; - u32 dvfscr4; - u32 dvfscr5; /* 0x17C */ -}; - -/* CPG SRCR part OK */ -struct sh73a0_sbsc_cpg_srcr { - u32 srcr0; - u32 dummy0; /* 0xA4 */ - u32 srcr1; - u32 dummy1; /* 0xAC */ - u32 srcr2; - u32 dummy2; /* 0xB4 */ - u32 srcr3; - u32 srcr4; - u32 dummy3; /* 0xC0 */ - u32 srcr5; -}; - -/* BSC */ -struct sh73a0_bsc { - u32 cmncr; - u32 cs0bcr; - u32 cs2bcr; - u32 dummy0; /* 0x0C */ - u32 cs4bcr; - u32 cs5abcr; - u32 cs5bbcr; - u32 cs6abcr; - u32 cs6bbcr; - u32 cs0wcr; - u32 cs2wcr; - u32 dummy1; /* 0x2C */ - u32 cs4wcr; - u32 cs5awcr; - u32 cs5bwcr; - u32 cs6awcr; - u32 cs6bwcr; - u32 rbwtcnt; - u32 busycr; - u32 dummy2; /* 0x5c */ - u32 cs7abcr; - u32 cs7awcr; - u32 dummy3[2]; /* 0x68, 0x6C */ - u32 bromtimcr; -}; -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */ diff --git a/arch/arm/mach-rmobile/pfc-sh73a0.c b/arch/arm/mach-rmobile/pfc-sh73a0.c deleted file mode 100644 index 55dab7c1389..00000000000 --- a/arch/arm/mach-rmobile/pfc-sh73a0.c +++ /dev/null @@ -1,2807 +0,0 @@ -/* - * sh73a0 processor support - PFC hardware block - * - * Copyright (C) 2010 Renesas Solutions Corp. - * Copyright (C) 2010 NISHIMOTO Hiroki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <common.h> -#include <sh_pfc.h> -#include <asm/arch/sh73a0-gpio.h> - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \ - PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \ - PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \ - PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \ - PORT_10(fn, pfx##10, sfx), \ - PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ - PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ - PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \ - PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \ - PORT_1(fn, pfx##118, sfx), \ - PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ - PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \ - PORT_10(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \ - PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \ - PORT_1(fn, pfx##164, sfx), \ - PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ - PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ - PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ - PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ - PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \ - PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \ - PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \ - PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ - PORT_1(fn, pfx##282, sfx), \ - PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ - PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx) - -enum { - PINMUX_RESERVED = 0, - - PINMUX_DATA_BEGIN, - PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */ - PINMUX_DATA_END, - - PINMUX_INPUT_BEGIN, - PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ - PINMUX_INPUT_END, - - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ - PINMUX_INPUT_PULLUP_END, - - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ - PINMUX_INPUT_PULLDOWN_END, - - PINMUX_OUTPUT_BEGIN, - PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ - PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ - PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */ - PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */ - PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */ - PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */ - PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */ - PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */ - PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */ - PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */ - - MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, - MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, - MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, - MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, - MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, - MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, - MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, - MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, - MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, - MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, - MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, - MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, - MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, - MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, - MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, - MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, - MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, - MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, - MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, - MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, - MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, - MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, - MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, - MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, - MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, - MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, - MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, - MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, - MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, - MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, - MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, - MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, - MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, - MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, - MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, - MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, - MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, - MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, - MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, - MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, - MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - /* Hardware manual Table 25-1 (Function 0-7) */ - VBUS_0_MARK, - GPI0_MARK, - GPI1_MARK, - GPI2_MARK, - GPI3_MARK, - GPI4_MARK, - GPI5_MARK, - GPI6_MARK, - GPI7_MARK, - SCIFA7_RXD_MARK, - SCIFA7_CTS__MARK, - GPO7_MARK, MFG0_OUT2_MARK, - GPO6_MARK, MFG1_OUT2_MARK, - GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK, - SCIFA0_TXD_MARK, - SCIFA7_TXD_MARK, - SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK, - GPO0_MARK, - GPO1_MARK, - GPO2_MARK, STATUS0_MARK, - GPO3_MARK, STATUS1_MARK, - GPO4_MARK, STATUS2_MARK, - VINT_MARK, - TCKON_MARK, - XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \ - MFG0_OUT1_MARK, PORT27_IROUT_MARK, - XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \ - PORT28_TPU1TO1_MARK, - SIM_RST_MARK, PORT29_TPU1TO1_MARK, - SIM_CLK_MARK, PORT30_VIO_CKOR_MARK, - SIM_D_MARK, PORT31_IROUT_MARK, - SCIFA4_TXD_MARK, - SCIFA4_RXD_MARK, XWUP_MARK, - SCIFA4_RTS__MARK, - SCIFA4_CTS__MARK, - FSIBOBT_MARK, FSIBIBT_MARK, - FSIBOLR_MARK, FSIBILR_MARK, - FSIBOSLD_MARK, - FSIBISLD_MARK, - VACK_MARK, - XTAL1L_MARK, - SCIFA0_RTS__MARK, FSICOSLDT2_MARK, - SCIFA0_RXD_MARK, - SCIFA0_CTS__MARK, FSICOSLDT1_MARK, - FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK, - FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK, - FSICOSLD_MARK, PORT47_FSICSPDIF_MARK, - FSICISLD_MARK, FSIDISLD_MARK, - FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK, - FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK, - - FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK, - FSIAOSLD_MARK, BBIF2_TXD2_MARK, - FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \ - PORT53_FSICSPDIF_MARK, - FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \ - FSICCK_MARK, FSICOMC_MARK, - FSIAISLD_MARK, TPU0TO0_MARK, - A0_MARK, BS__MARK, - A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK, - A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK, - A14_MARK, KEYOUT5_MARK, - A15_MARK, KEYOUT4_MARK, - A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK, - A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK, - A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK, - A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK, - A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK, - A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK, - A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK, - A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK, - A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK, - A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK, - A26_MARK, KEYIN6_MARK, - KEYIN7_MARK, - D0_NAF0_MARK, - D1_NAF1_MARK, - D2_NAF2_MARK, - D3_NAF3_MARK, - D4_NAF4_MARK, - D5_NAF5_MARK, - D6_NAF6_MARK, - D7_NAF7_MARK, - D8_NAF8_MARK, - D9_NAF9_MARK, - D10_NAF10_MARK, - D11_NAF11_MARK, - D12_NAF12_MARK, - D13_NAF13_MARK, - D14_NAF14_MARK, - D15_NAF15_MARK, - CS4__MARK, - CS5A__MARK, PORT91_RDWR_MARK, - CS5B__MARK, FCE1__MARK, - CS6B__MARK, DACK0_MARK, - FCE0__MARK, CS6A__MARK, - WAIT__MARK, DREQ0_MARK, - RD__FSC_MARK, - WE0__FWE_MARK, RDWR_FWE_MARK, - WE1__MARK, - FRB_MARK, - CKO_MARK, - NBRSTOUT__MARK, - NBRST__MARK, - BBIF2_TXD_MARK, - BBIF2_RXD_MARK, - BBIF2_SYNC_MARK, - BBIF2_SCK_MARK, - SCIFA3_CTS__MARK, MFG3_IN2_MARK, - SCIFA3_RXD_MARK, MFG3_IN1_MARK, - BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK, - SCIFA3_TXD_MARK, - HSI_RX_DATA_MARK, BBIF1_RXD_MARK, - HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK, - HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK, - HSI_TX_READY_MARK, BBIF1_TXD_MARK, - HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \ - PORT115_I2C_SCL3_MARK, - HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \ - PORT116_I2C_SDA3_MARK, - HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK, - HSI_TX_FLAG_MARK, - VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK, - - VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \ - VIO2_HD_MARK, LCD2D1_MARK, - VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK, - VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \ - PORT131_KEYOUT11_MARK, LCD2D11_MARK, - VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \ - PORT132_KEYOUT10_MARK, LCD2D12_MARK, - VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK, - VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK, - VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK, - VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK, - VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK, - VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK, - VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK, - VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK, - VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK, - VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK, - VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \ - VIO2_D5_MARK, LCD2D3_MARK, - VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK, - VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \ - PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK, - VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \ - LCD2D18_MARK, - VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK, - VIO_CKO_MARK, - A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK, - MFG0_IN2_MARK, - TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, - TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, - TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, - SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, - SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, - SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK, - SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK, - DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, - PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, - PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, - PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK, - PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, - PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK, - LCDD0_MARK, - LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK, - LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK, - LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK, - LCDD4_MARK, PORT196_SCIFA5_TXD_MARK, - LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK, - LCDD6_MARK, - LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, - LCDD8_MARK, D16_MARK, - LCDD9_MARK, D17_MARK, - LCDD10_MARK, D18_MARK, - LCDD11_MARK, D19_MARK, - LCDD12_MARK, D20_MARK, - LCDD13_MARK, D21_MARK, - LCDD14_MARK, D22_MARK, - LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK, - LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK, - LCDD17_MARK, D25_MARK, - LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, - LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, - LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, - LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, - LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, - LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, - LCDDCK_MARK, LCDWR__MARK, - LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \ - VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK, - LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \ - PORT218_VIO_CKOR_MARK, - LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \ - MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK, - LCDVSYN_MARK, LCDVSYN2_MARK, - LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \ - MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK, - LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \ - VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK, - - SCIFA1_TXD_MARK, OVCN2_MARK, - EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK, - SCIFA1_RTS__MARK, IDIN_MARK, - SCIFA1_RXD_MARK, - SCIFA1_CTS__MARK, MFG1_IN1_MARK, - MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, - MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK, - MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, - MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, - MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK, - MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK, - MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK, - MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK, - MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK, - MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK, - SCIFA6_TXD_MARK, - PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK, - PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, - PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, - PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \ - MSIOF2R_RXD_MARK, - PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \ - MSIOF2R_TXD_MARK, - PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \ - TPU1TO0_MARK, - PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \ - TPU3TO1_MARK, - PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \ - TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK, - PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \ - MSIOF2R_TSYNC_MARK, - SDHICLK0_MARK, - SDHICD0_MARK, - SDHID0_0_MARK, - SDHID0_1_MARK, - SDHID0_2_MARK, - SDHID0_3_MARK, - SDHICMD0_MARK, - SDHIWP0_MARK, - SDHICLK1_MARK, - SDHID1_0_MARK, TS_SPSYNC2_MARK, - SDHID1_1_MARK, TS_SDAT2_MARK, - SDHID1_2_MARK, TS_SDEN2_MARK, - SDHID1_3_MARK, TS_SCK2_MARK, - SDHICMD1_MARK, - SDHICLK2_MARK, - SDHID2_0_MARK, TS_SPSYNC4_MARK, - SDHID2_1_MARK, TS_SDAT4_MARK, - SDHID2_2_MARK, TS_SDEN4_MARK, - SDHID2_3_MARK, TS_SCK4_MARK, - SDHICMD2_MARK, - MMCCLK0_MARK, - MMCD0_0_MARK, - MMCD0_1_MARK, - MMCD0_2_MARK, - MMCD0_3_MARK, - MMCD0_4_MARK, TS_SPSYNC5_MARK, - MMCD0_5_MARK, TS_SDAT5_MARK, - MMCD0_6_MARK, TS_SDEN5_MARK, - MMCD0_7_MARK, TS_SCK5_MARK, - MMCCMD0_MARK, - RESETOUTS__MARK, EXTAL2OUT_MARK, - MCP_WAIT__MCP_FRB_MARK, - MCP_CKO_MARK, MMCCLK1_MARK, - MCP_D15_MCP_NAF15_MARK, - MCP_D14_MCP_NAF14_MARK, - MCP_D13_MCP_NAF13_MARK, - MCP_D12_MCP_NAF12_MARK, - MCP_D11_MCP_NAF11_MARK, - MCP_D10_MCP_NAF10_MARK, - MCP_D9_MCP_NAF9_MARK, - MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK, - MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK, - - MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK, - MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK, - MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK, - MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK, - MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK, - MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK, - MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK, - MCP_NBRSTOUT__MARK, - MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK, - - /* MSEL2 special cases */ - TSIF2_TS_XX1_MARK, - TSIF2_TS_XX2_MARK, - TSIF2_TS_XX3_MARK, - TSIF2_TS_XX4_MARK, - TSIF2_TS_XX5_MARK, - TSIF1_TS_XX1_MARK, - TSIF1_TS_XX2_MARK, - TSIF1_TS_XX3_MARK, - TSIF1_TS_XX4_MARK, - TSIF1_TS_XX5_MARK, - TSIF0_TS_XX1_MARK, - TSIF0_TS_XX2_MARK, - TSIF0_TS_XX3_MARK, - TSIF0_TS_XX4_MARK, - TSIF0_TS_XX5_MARK, - MST1_TS_XX1_MARK, - MST1_TS_XX2_MARK, - MST1_TS_XX3_MARK, - MST1_TS_XX4_MARK, - MST1_TS_XX5_MARK, - MST0_TS_XX1_MARK, - MST0_TS_XX2_MARK, - MST0_TS_XX3_MARK, - MST0_TS_XX4_MARK, - MST0_TS_XX5_MARK, - - /* MSEL3 special cases */ - SDHI0_VCCQ_MC0_ON_MARK, - SDHI0_VCCQ_MC0_OFF_MARK, - DEBUG_MON_VIO_MARK, - DEBUG_MON_LCDD_MARK, - LCDC_LCDC0_MARK, - LCDC_LCDC1_MARK, - - /* MSEL4 special cases */ - IRQ9_MEM_INT_MARK, - IRQ9_MCP_INT_MARK, - A11_MARK, - KEYOUT8_MARK, - TPU4TO3_MARK, - RESETA_N_PU_ON_MARK, - RESETA_N_PU_OFF_MARK, - EDBGREQ_PD_MARK, - EDBGREQ_PU_MARK, - - /* Functions with pull-ups */ - KEYIN0_PU_MARK, - KEYIN1_PU_MARK, - KEYIN2_PU_MARK, - KEYIN3_PU_MARK, - KEYIN4_PU_MARK, - KEYIN5_PU_MARK, - KEYIN6_PU_MARK, - KEYIN7_PU_MARK, - SDHICD0_PU_MARK, - SDHID0_0_PU_MARK, - SDHID0_1_PU_MARK, - SDHID0_2_PU_MARK, - SDHID0_3_PU_MARK, - SDHICMD0_PU_MARK, - SDHIWP0_PU_MARK, - SDHID1_0_PU_MARK, - SDHID1_1_PU_MARK, - SDHID1_2_PU_MARK, - SDHID1_3_PU_MARK, - SDHICMD1_PU_MARK, - SDHID2_0_PU_MARK, - SDHID2_1_PU_MARK, - SDHID2_2_PU_MARK, - SDHID2_3_PU_MARK, - SDHICMD2_PU_MARK, - MMCCMD0_PU_MARK, - MMCCMD1_PU_MARK, - MMCD0_0_PU_MARK, - MMCD0_1_PU_MARK, - MMCD0_2_PU_MARK, - MMCD0_3_PU_MARK, - MMCD0_4_PU_MARK, - MMCD0_5_PU_MARK, - MMCD0_6_PU_MARK, - MMCD0_7_PU_MARK, - FSIBISLD_PU_MARK, - FSIACK_PU_MARK, - FSIAILR_PU_MARK, - FSIAIBT_PU_MARK, - FSIAISLD_PU_MARK, - - PINMUX_MARK_END, -}; - -static unsigned short pinmux_data[] = { - /* specify valid pin states for each pin in GPIO mode */ - - /* Table 25-1 (I/O and Pull U/D) */ - PORT_DATA_I_PD(0), - PORT_DATA_I_PU(1), - PORT_DATA_I_PU(2), - PORT_DATA_I_PU(3), - PORT_DATA_I_PU(4), - PORT_DATA_I_PU(5), - PORT_DATA_I_PU(6), - PORT_DATA_I_PU(7), - PORT_DATA_I_PU(8), - PORT_DATA_I_PD(9), - PORT_DATA_I_PD(10), - PORT_DATA_I_PU_PD(11), - PORT_DATA_IO_PU_PD(12), - PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PU_PD(14), - PORT_DATA_IO_PU_PD(15), - PORT_DATA_IO_PD(16), - PORT_DATA_IO_PD(17), - PORT_DATA_IO_PU(18), - PORT_DATA_IO_PU(19), - PORT_DATA_O(20), - PORT_DATA_O(21), - PORT_DATA_O(22), - PORT_DATA_O(23), - PORT_DATA_O(24), - PORT_DATA_I_PD(25), - PORT_DATA_I_PD(26), - PORT_DATA_IO_PU(27), - PORT_DATA_IO_PU(28), - PORT_DATA_IO_PD(29), - PORT_DATA_IO_PD(30), - PORT_DATA_IO_PU(31), - PORT_DATA_IO_PD(32), - PORT_DATA_I_PU_PD(33), - PORT_DATA_IO_PD(34), - PORT_DATA_I_PU_PD(35), - PORT_DATA_IO_PD(36), - PORT_DATA_IO(37), - PORT_DATA_O(38), - PORT_DATA_I_PU(39), - PORT_DATA_I_PU_PD(40), - PORT_DATA_O(41), - PORT_DATA_IO_PD(42), - PORT_DATA_IO_PU_PD(43), - PORT_DATA_IO_PU_PD(44), - PORT_DATA_IO_PD(45), - PORT_DATA_IO_PD(46), - PORT_DATA_IO_PD(47), - PORT_DATA_I_PD(48), - PORT_DATA_IO_PU_PD(49), - PORT_DATA_IO_PD(50), - - PORT_DATA_IO_PD(51), - PORT_DATA_O(52), - PORT_DATA_IO_PU_PD(53), - PORT_DATA_IO_PU_PD(54), - PORT_DATA_IO_PD(55), - PORT_DATA_I_PU_PD(56), - PORT_DATA_IO(57), - PORT_DATA_IO(58), - PORT_DATA_IO(59), - PORT_DATA_IO(60), - PORT_DATA_IO(61), - PORT_DATA_IO_PD(62), - PORT_DATA_IO_PD(63), - PORT_DATA_IO_PU_PD(64), - PORT_DATA_IO_PD(65), - PORT_DATA_IO_PU_PD(66), - PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), - PORT_DATA_IO_PU_PD(69), - PORT_DATA_IO_PU_PD(70), - PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), - PORT_DATA_I_PU_PD(73), - PORT_DATA_IO_PU(74), - PORT_DATA_IO_PU(75), - PORT_DATA_IO_PU(76), - PORT_DATA_IO_PU(77), - PORT_DATA_IO_PU(78), - PORT_DATA_IO_PU(79), - PORT_DATA_IO_PU(80), - PORT_DATA_IO_PU(81), - PORT_DATA_IO_PU(82), - PORT_DATA_IO_PU(83), - PORT_DATA_IO_PU(84), - PORT_DATA_IO_PU(85), - PORT_DATA_IO_PU(86), - PORT_DATA_IO_PU(87), - PORT_DATA_IO_PU(88), - PORT_DATA_IO_PU(89), - PORT_DATA_O(90), - PORT_DATA_IO_PU(91), - PORT_DATA_O(92), - PORT_DATA_IO_PU(93), - PORT_DATA_O(94), - PORT_DATA_I_PU_PD(95), - PORT_DATA_IO(96), - PORT_DATA_IO(97), - PORT_DATA_IO(98), - PORT_DATA_I_PU(99), - PORT_DATA_O(100), - PORT_DATA_O(101), - PORT_DATA_I_PU(102), - PORT_DATA_IO_PD(103), - PORT_DATA_I_PU_PD(104), - PORT_DATA_I_PD(105), - PORT_DATA_I_PD(106), - PORT_DATA_I_PU_PD(107), - PORT_DATA_I_PU_PD(108), - PORT_DATA_IO_PD(109), - PORT_DATA_IO_PD(110), - PORT_DATA_IO_PU_PD(111), - PORT_DATA_IO_PU_PD(112), - PORT_DATA_IO_PU_PD(113), - PORT_DATA_IO_PD(114), - PORT_DATA_IO_PU(115), - PORT_DATA_IO_PU(116), - PORT_DATA_IO_PU_PD(117), - PORT_DATA_IO_PU_PD(118), - PORT_DATA_IO_PD(128), - - PORT_DATA_IO_PD(129), - PORT_DATA_IO_PU_PD(130), - PORT_DATA_IO_PD(131), - PORT_DATA_IO_PD(132), - PORT_DATA_IO_PD(133), - PORT_DATA_IO_PU_PD(134), - PORT_DATA_IO_PU_PD(135), - PORT_DATA_IO_PU_PD(136), - PORT_DATA_IO_PU_PD(137), - PORT_DATA_IO_PD(138), - PORT_DATA_IO_PD(139), - PORT_DATA_IO_PD(140), - PORT_DATA_IO_PD(141), - PORT_DATA_IO_PD(142), - PORT_DATA_IO_PD(143), - PORT_DATA_IO_PU_PD(144), - PORT_DATA_IO_PD(145), - PORT_DATA_IO_PU_PD(146), - PORT_DATA_IO_PU_PD(147), - PORT_DATA_IO_PU_PD(148), - PORT_DATA_IO_PU_PD(149), - PORT_DATA_I_PU_PD(150), - PORT_DATA_IO_PU_PD(151), - PORT_DATA_IO_PU_PD(152), - PORT_DATA_IO_PD(153), - PORT_DATA_IO_PD(154), - PORT_DATA_I_PU_PD(155), - PORT_DATA_IO_PU_PD(156), - PORT_DATA_I_PD(157), - PORT_DATA_IO_PD(158), - PORT_DATA_IO_PU_PD(159), - PORT_DATA_IO_PU_PD(160), - PORT_DATA_I_PU_PD(161), - PORT_DATA_I_PU_PD(162), - PORT_DATA_IO_PU_PD(163), - PORT_DATA_I_PU_PD(164), - PORT_DATA_IO_PD(192), - PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PD(194), - PORT_DATA_IO_PU_PD(195), - PORT_DATA_IO_PD(196), - PORT_DATA_IO_PD(197), - PORT_DATA_IO_PD(198), - PORT_DATA_IO_PD(199), - PORT_DATA_IO_PU_PD(200), - PORT_DATA_IO_PU_PD(201), - PORT_DATA_IO_PU_PD(202), - PORT_DATA_IO_PU_PD(203), - PORT_DATA_IO_PU_PD(204), - PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), - PORT_DATA_IO_PD(207), - PORT_DATA_IO_PD(208), - PORT_DATA_IO_PD(209), - PORT_DATA_IO_PD(210), - PORT_DATA_IO_PD(211), - PORT_DATA_IO_PD(212), - PORT_DATA_IO_PD(213), - PORT_DATA_IO_PU_PD(214), - PORT_DATA_IO_PU_PD(215), - PORT_DATA_IO_PD(216), - PORT_DATA_IO_PD(217), - PORT_DATA_O(218), - PORT_DATA_IO_PD(219), - PORT_DATA_IO_PD(220), - PORT_DATA_IO_PU_PD(221), - PORT_DATA_IO_PU_PD(222), - PORT_DATA_I_PU_PD(223), - PORT_DATA_I_PU_PD(224), - - PORT_DATA_IO_PU_PD(225), - PORT_DATA_O(226), - PORT_DATA_IO_PU_PD(227), - PORT_DATA_I_PU_PD(228), - PORT_DATA_I_PD(229), - PORT_DATA_IO(230), - PORT_DATA_IO_PU_PD(231), - PORT_DATA_IO_PU_PD(232), - PORT_DATA_I_PU_PD(233), - PORT_DATA_IO_PU_PD(234), - PORT_DATA_IO_PU_PD(235), - PORT_DATA_IO_PU_PD(236), - PORT_DATA_IO_PD(237), - PORT_DATA_IO_PU_PD(238), - PORT_DATA_IO_PU_PD(239), - PORT_DATA_IO_PU_PD(240), - PORT_DATA_O(241), - PORT_DATA_I_PD(242), - PORT_DATA_IO_PU_PD(243), - PORT_DATA_IO_PU_PD(244), - PORT_DATA_IO_PU_PD(245), - PORT_DATA_IO_PU_PD(246), - PORT_DATA_IO_PU_PD(247), - PORT_DATA_IO_PU_PD(248), - PORT_DATA_IO_PU_PD(249), - PORT_DATA_IO_PU_PD(250), - PORT_DATA_IO_PU_PD(251), - PORT_DATA_IO_PU_PD(252), - PORT_DATA_IO_PU_PD(253), - PORT_DATA_IO_PU_PD(254), - PORT_DATA_IO_PU_PD(255), - PORT_DATA_IO_PU_PD(256), - PORT_DATA_IO_PU_PD(257), - PORT_DATA_IO_PU_PD(258), - PORT_DATA_IO_PU_PD(259), - PORT_DATA_IO_PU_PD(260), - PORT_DATA_IO_PU_PD(261), - PORT_DATA_IO_PU_PD(262), - PORT_DATA_IO_PU_PD(263), - PORT_DATA_IO_PU_PD(264), - PORT_DATA_IO_PU_PD(265), - PORT_DATA_IO_PU_PD(266), - PORT_DATA_IO_PU_PD(267), - PORT_DATA_IO_PU_PD(268), - PORT_DATA_IO_PU_PD(269), - PORT_DATA_IO_PU_PD(270), - PORT_DATA_IO_PU_PD(271), - PORT_DATA_IO_PU_PD(272), - PORT_DATA_IO_PU_PD(273), - PORT_DATA_IO_PU_PD(274), - PORT_DATA_IO_PU_PD(275), - PORT_DATA_IO_PU_PD(276), - PORT_DATA_IO_PU_PD(277), - PORT_DATA_IO_PU_PD(278), - PORT_DATA_IO_PU_PD(279), - PORT_DATA_IO_PU_PD(280), - PORT_DATA_O(281), - PORT_DATA_O(282), - PORT_DATA_I_PU(288), - PORT_DATA_IO_PU_PD(289), - PORT_DATA_IO_PU_PD(290), - PORT_DATA_IO_PU_PD(291), - PORT_DATA_IO_PU_PD(292), - PORT_DATA_IO_PU_PD(293), - PORT_DATA_IO_PU_PD(294), - PORT_DATA_IO_PU_PD(295), - PORT_DATA_IO_PU_PD(296), - PORT_DATA_IO_PU_PD(297), - PORT_DATA_IO_PU_PD(298), - - PORT_DATA_IO_PU_PD(299), - PORT_DATA_IO_PU_PD(300), - PORT_DATA_IO_PU_PD(301), - PORT_DATA_IO_PU_PD(302), - PORT_DATA_IO_PU_PD(303), - PORT_DATA_IO_PU_PD(304), - PORT_DATA_IO_PU_PD(305), - PORT_DATA_O(306), - PORT_DATA_O(307), - PORT_DATA_I_PU(308), - PORT_DATA_O(309), - - /* Table 25-1 (Function 0-7) */ - PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), - PINMUX_DATA(GPI0_MARK, PORT1_FN1), - PINMUX_DATA(GPI1_MARK, PORT2_FN1), - PINMUX_DATA(GPI2_MARK, PORT3_FN1), - PINMUX_DATA(GPI3_MARK, PORT4_FN1), - PINMUX_DATA(GPI4_MARK, PORT5_FN1), - PINMUX_DATA(GPI5_MARK, PORT6_FN1), - PINMUX_DATA(GPI6_MARK, PORT7_FN1), - PINMUX_DATA(GPI7_MARK, PORT8_FN1), - PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2), - PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2), - PINMUX_DATA(GPO7_MARK, PORT14_FN1), \ - PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4), - PINMUX_DATA(GPO6_MARK, PORT15_FN1), \ - PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4), - PINMUX_DATA(GPO5_MARK, PORT16_FN1), \ - PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \ - PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \ - PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4), - PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), - PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2), - PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \ - PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), - PINMUX_DATA(GPO0_MARK, PORT20_FN1), - PINMUX_DATA(GPO1_MARK, PORT21_FN1), - PINMUX_DATA(GPO2_MARK, PORT22_FN1), \ - PINMUX_DATA(STATUS0_MARK, PORT22_FN2), - PINMUX_DATA(GPO3_MARK, PORT23_FN1), \ - PINMUX_DATA(STATUS1_MARK, PORT23_FN2), - PINMUX_DATA(GPO4_MARK, PORT24_FN1), \ - PINMUX_DATA(STATUS2_MARK, PORT24_FN2), - PINMUX_DATA(VINT_MARK, PORT25_FN1), - PINMUX_DATA(TCKON_MARK, PORT26_FN1), - PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \ - PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0, - MSEL2CR_MSEL16_1), \ - PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0, - MSEL2CR_MSEL18_1), \ - PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \ - PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7), - PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \ - PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0, - MSEL2CR_MSEL16_1), \ - PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0, - MSEL2CR_MSEL18_1), \ - PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7), - PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \ - PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4), - PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \ - PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4), - PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \ - PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4), - PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), - PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \ - PINMUX_DATA(XWUP_MARK, PORT33_FN3), - PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2), - PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2), - PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \ - PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2), - PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \ - PINMUX_DATA(FSIBILR_MARK, PORT37_FN2), - PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1), - PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1), - PINMUX_DATA(VACK_MARK, PORT40_FN1), - PINMUX_DATA(XTAL1L_MARK, PORT41_FN1), - PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \ - PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3), - PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), - PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \ - PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3), - PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \ - PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \ - PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \ - PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4), - PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \ - PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \ - PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \ - PINMUX_DATA(FSIDILR_MARK, PORT46_FN4), - PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \ - PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2), - PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \ - PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3), - PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \ - PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \ - PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \ - PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5), - PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \ - PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \ - PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \ - PINMUX_DATA(FSIAILR_MARK, PORT50_FN5), - - PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \ - PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \ - PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \ - PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5), - PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \ - PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), - PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \ - PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \ - PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \ - PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \ - PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6), - PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \ - PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \ - PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \ - PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \ - PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \ - PINMUX_DATA(FSICOMC_MARK, PORT54_FN7), - PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \ - PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), - PINMUX_DATA(A0_MARK, PORT57_FN1), \ - PINMUX_DATA(BS__MARK, PORT57_FN2), - PINMUX_DATA(A12_MARK, PORT58_FN1), \ - PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \ - PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4), - PINMUX_DATA(A13_MARK, PORT59_FN1), \ - PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \ - PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), - PINMUX_DATA(A14_MARK, PORT60_FN1), \ - PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2), - PINMUX_DATA(A15_MARK, PORT61_FN1), \ - PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2), - PINMUX_DATA(A16_MARK, PORT62_FN1), \ - PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \ - PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A17_MARK, PORT63_FN1), \ - PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \ - PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A18_MARK, PORT64_FN1), \ - PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \ - PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A19_MARK, PORT65_FN1), \ - PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \ - PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A20_MARK, PORT66_FN1), \ - PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \ - PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A21_MARK, PORT67_FN1), \ - PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \ - PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A22_MARK, PORT68_FN1), \ - PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \ - PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A23_MARK, PORT69_FN1), \ - PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \ - PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A24_MARK, PORT70_FN1), \ - PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \ - PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A25_MARK, PORT71_FN1), \ - PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \ - PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0), - PINMUX_DATA(A26_MARK, PORT72_FN1), \ - PINMUX_DATA(KEYIN6_MARK, PORT72_FN2), - PINMUX_DATA(KEYIN7_MARK, PORT73_FN2), - PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1), - PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1), - PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1), - PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1), - PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1), - PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1), - PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1), - PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1), - PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1), - PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1), - PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1), - PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1), - PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1), - PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1), - PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1), - PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1), - PINMUX_DATA(CS4__MARK, PORT90_FN1), - PINMUX_DATA(CS5A__MARK, PORT91_FN1), \ - PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2), - PINMUX_DATA(CS5B__MARK, PORT92_FN1), \ - PINMUX_DATA(FCE1__MARK, PORT92_FN2), - PINMUX_DATA(CS6B__MARK, PORT93_FN1), \ - PINMUX_DATA(DACK0_MARK, PORT93_FN4), - PINMUX_DATA(FCE0__MARK, PORT94_FN1), \ - PINMUX_DATA(CS6A__MARK, PORT94_FN2), - PINMUX_DATA(WAIT__MARK, PORT95_FN1), \ - PINMUX_DATA(DREQ0_MARK, PORT95_FN2), - PINMUX_DATA(RD__FSC_MARK, PORT96_FN1), - PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \ - PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2), - PINMUX_DATA(WE1__MARK, PORT98_FN1), - PINMUX_DATA(FRB_MARK, PORT99_FN1), - PINMUX_DATA(CKO_MARK, PORT100_FN1), - PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1), - PINMUX_DATA(NBRST__MARK, PORT102_FN1), - PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3), - PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3), - PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3), - PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3), - PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \ - PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4), - PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \ - PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4), - PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \ - PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \ - PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4), - PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3), - PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \ - PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3), - PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \ - PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3), - PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \ - PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3), - PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \ - PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3), - PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \ - PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \ - PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \ - PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1), - PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \ - PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \ - PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \ - PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1), - PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \ - PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \ - PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3), - PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1), - PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \ - PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \ - PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \ - PINMUX_DATA(LCD2D0_MARK, PORT128_FN7), - - PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \ - PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \ - PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \ - PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \ - PINMUX_DATA(LCD2D1_MARK, PORT129_FN7), - PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \ - PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0, - MSEL4CR_MSEL10_1), \ - PINMUX_DATA(LCD2D10_MARK, PORT130_FN7), - PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \ - PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \ - PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \ - PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \ - PINMUX_DATA(LCD2D11_MARK, PORT131_FN7), - PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \ - PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \ - PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \ - PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \ - PINMUX_DATA(LCD2D12_MARK, PORT132_FN7), - PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \ - PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \ - PINMUX_DATA(LCD2D13_MARK, PORT133_FN7), - PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \ - PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \ - PINMUX_DATA(LCD2D14_MARK, PORT134_FN7), - PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \ - PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \ - PINMUX_DATA(LCD2D15_MARK, PORT135_FN7), - PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \ - PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \ - PINMUX_DATA(LCD2D16_MARK, PORT136_FN7), - PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \ - PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \ - PINMUX_DATA(LCD2D17_MARK, PORT137_FN7), - PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \ - PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \ - PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \ - PINMUX_DATA(LCD2D6_MARK, PORT138_FN7), - PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \ - PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \ - PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \ - PINMUX_DATA(LCD2D7_MARK, PORT139_FN7), - PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \ - PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \ - PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \ - PINMUX_DATA(LCD2D8_MARK, PORT140_FN7), - PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \ - PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \ - PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \ - PINMUX_DATA(LCD2D9_MARK, PORT141_FN7), - PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \ - PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \ - PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \ - PINMUX_DATA(LCD2D2_MARK, PORT142_FN7), - PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \ - PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \ - PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \ - PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \ - PINMUX_DATA(LCD2D3_MARK, PORT143_FN7), - PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \ - PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \ - PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \ - PINMUX_DATA(LCD2D4_MARK, PORT144_FN7), - PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \ - PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \ - PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \ - PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \ - PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \ - PINMUX_DATA(LCD2D5_MARK, PORT145_FN7), - PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \ - PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \ - PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \ - PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \ - PINMUX_DATA(LCD2D18_MARK, PORT146_FN7), - PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \ - PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \ - PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \ - PINMUX_DATA(LCD2D19_MARK, PORT147_FN7), - PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), - PINMUX_DATA(A27_MARK, PORT149_FN1), \ - PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \ - PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \ - PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4), - PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3), - PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \ - PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5), - PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \ - PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5), - PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \ - PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \ - PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5), - PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \ - PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5), - PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \ - PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5), - PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \ - PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5), - PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \ - PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0, - MSEL4CR_MSEL10_0), - PINMUX_DATA(DINT__MARK, PORT158_FN1), \ - PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \ - PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4), - PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \ - PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \ - PINMUX_DATA(NMI_MARK, PORT159_FN3), - PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \ - PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1), - PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \ - PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1), - PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \ - PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1), - PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \ - PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \ - PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), - PINMUX_DATA(LCDD0_MARK, PORT192_FN1), - PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \ - PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_1), \ - PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5), - PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \ - PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_1), \ - PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5), - PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \ - PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_1), \ - PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5), - PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \ - PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_1), - PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \ - PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_1), \ - PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \ - PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7), - PINMUX_DATA(LCDD6_MARK, PORT198_FN1), - PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \ - PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \ - PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5), - PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \ - PINMUX_DATA(D16_MARK, PORT200_FN6), - PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \ - PINMUX_DATA(D17_MARK, PORT201_FN6), - PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \ - PINMUX_DATA(D18_MARK, PORT202_FN6), - PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \ - PINMUX_DATA(D19_MARK, PORT203_FN6), - PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \ - PINMUX_DATA(D20_MARK, PORT204_FN6), - PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \ - PINMUX_DATA(D21_MARK, PORT205_FN6), - PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \ - PINMUX_DATA(D22_MARK, PORT206_FN6), - PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \ - PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D23_MARK, PORT207_FN6), - PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \ - PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D24_MARK, PORT208_FN6), - PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \ - PINMUX_DATA(D25_MARK, PORT209_FN6), - PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \ - PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \ - PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D26_MARK, PORT210_FN6), - PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \ - PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D27_MARK, PORT211_FN6), - PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \ - PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \ - PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D28_MARK, PORT212_FN6), - PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \ - PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \ - PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D29_MARK, PORT213_FN6), - PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \ - PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \ - PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D30_MARK, PORT214_FN6), - PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \ - PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \ - PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(D31_MARK, PORT215_FN6), - PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \ - PINMUX_DATA(LCDWR__MARK, PORT216_FN2), - PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \ - PINMUX_DATA(DACK2_MARK, PORT217_FN2), \ - PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \ - PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_1), \ - PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7), - PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \ - PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \ - PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \ - PINMUX_DATA(DACK3_MARK, PORT218_FN4), \ - PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), - PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \ - PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \ - PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \ - PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \ - PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_1), \ - PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7), - PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \ - PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), - PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \ - PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \ - PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \ - PINMUX_DATA(PWEN_MARK, PORT221_FN4), \ - PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_1), \ - PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7), - PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \ - PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \ - PINMUX_DATA(DACK1_MARK, PORT222_FN3), \ - PINMUX_DATA(OVCN_MARK, PORT222_FN4), \ - PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \ - PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_1), \ - PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1), - - PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \ - PINMUX_DATA(OVCN2_MARK, PORT225_FN4), - PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \ - PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \ - PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5), - PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \ - PINMUX_DATA(IDIN_MARK, PORT227_FN4), - PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2), - PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \ - PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3), - PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \ - PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1), - PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \ - PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1), - PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \ - PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1), - PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \ - PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1), - PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \ - PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \ - PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_0), \ - PINMUX_DATA(LCD2D20_MARK, PORT234_FN7), - PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \ - PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \ - PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_0), \ - PINMUX_DATA(LCD2D21_MARK, PORT235_FN7), - PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \ - PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0, - MSEL2CR_MSEL16_0), - PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \ - PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0, - MSEL2CR_MSEL16_0), - PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \ - PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_0), \ - PINMUX_DATA(LCD2D22_MARK, PORT238_FN7), - PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \ - PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_0), \ - PINMUX_DATA(LCD2D23_MARK, PORT239_FN7), - PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), - PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \ - PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \ - PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \ - PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), - PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \ - PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3), - PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \ - PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), - PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_0), \ - PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \ - PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \ - PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1), - PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_0), \ - PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \ - PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \ - PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1), - PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_0), \ - PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \ - PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \ - PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), - PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_0), \ - PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \ - PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \ - PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), - PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0, - MSEL4CR_MSEL20_0), \ - PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \ - PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \ - PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \ - PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0, - MSEL2CR_MSEL18_0), \ - PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1), - PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \ - PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \ - PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0, - MSEL2CR_MSEL18_0), \ - PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1), - PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), - PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), - PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), - PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), - PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), - PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), - PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), - PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), - PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), - PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \ - PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), - PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \ - PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), - PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \ - PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), - PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \ - PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), - PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), - PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1), - PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \ - PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3), - PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \ - PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3), - PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \ - PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3), - PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \ - PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), - PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), - PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, - MSEL4CR_MSEL15_0), \ - PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), - PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, - MSEL4CR_MSEL15_0), \ - PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), - PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, - MSEL4CR_MSEL15_0), \ - PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), - PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, - MSEL4CR_MSEL15_0), \ - PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), - PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ - PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), - PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), - PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \ - PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1), - PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1), - PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1), - PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1), - PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1), - PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1), - PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1), - PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \ - PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \ - PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1), - - PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \ - PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \ - PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \ - PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \ - PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \ - PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \ - PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \ - PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1), - PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1), - PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \ - PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2), - - /* MSEL2 special cases */ - PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, - MSEL2CR_MSEL12_0), - PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, - MSEL2CR_MSEL12_1), - PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, - MSEL2CR_MSEL12_0), - PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, - MSEL2CR_MSEL12_1), - PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0, - MSEL2CR_MSEL12_0), - PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, - MSEL2CR_MSEL9_0), - PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, - MSEL2CR_MSEL9_1), - PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, - MSEL2CR_MSEL9_0), - PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, - MSEL2CR_MSEL9_1), - PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0, - MSEL2CR_MSEL9_0), - PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, - MSEL2CR_MSEL6_0), - PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, - MSEL2CR_MSEL6_1), - PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, - MSEL2CR_MSEL6_0), - PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, - MSEL2CR_MSEL6_1), - PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0, - MSEL2CR_MSEL6_0), - PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, - MSEL2CR_MSEL3_0), - PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, - MSEL2CR_MSEL3_1), - PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, - MSEL2CR_MSEL3_0), - PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, - MSEL2CR_MSEL3_1), - PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0, - MSEL2CR_MSEL3_0), - PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, - MSEL2CR_MSEL0_0), - PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, - MSEL2CR_MSEL0_1), - PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, - MSEL2CR_MSEL0_0), - PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, - MSEL2CR_MSEL0_1), - PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0, - MSEL2CR_MSEL0_0), - - /* MSEL3 special cases */ - PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1), - PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0), - PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0), - PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1), - PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0), - PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1), - - /* MSEL4 special cases */ - PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0), - PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1), - PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0), - PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1), - PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0), - PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0), - PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), - PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), - PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), - - /* Functions with pull-ups */ - PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), - PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), - PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), - PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), - PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), - PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), - PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), - PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), - - PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), - PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), - PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), - PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), - PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), - PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), - PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), - PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), - PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), - PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), - PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), - PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), - PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), - PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), - PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), - PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), - PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), - - PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, - MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, - MSEL4CR_MSEL15_1), - - PINMUX_DATA(MMCD0_0_PU_MARK, - PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_1_PU_MARK, - PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_2_PU_MARK, - PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_3_PU_MARK, - PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_4_PU_MARK, - PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_5_PU_MARK, - PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_6_PU_MARK, - PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), - PINMUX_DATA(MMCD0_7_PU_MARK, - PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), - - PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), - PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), - PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), - PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), - PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - GPIO_PORT_ALL(), - - /* Table 25-1 (Functions 0-7) */ - GPIO_FN(VBUS_0), - GPIO_FN(GPI0), - GPIO_FN(GPI1), - GPIO_FN(GPI2), - GPIO_FN(GPI3), - GPIO_FN(GPI4), - GPIO_FN(GPI5), - GPIO_FN(GPI6), - GPIO_FN(GPI7), - GPIO_FN(SCIFA7_RXD), - GPIO_FN(SCIFA7_CTS_), - GPIO_FN(GPO7), \ - GPIO_FN(MFG0_OUT2), - GPIO_FN(GPO6), \ - GPIO_FN(MFG1_OUT2), - GPIO_FN(GPO5), \ - GPIO_FN(SCIFA0_SCK), \ - GPIO_FN(FSICOSLDT3), \ - GPIO_FN(PORT16_VIO_CKOR), - GPIO_FN(SCIFA0_TXD), - GPIO_FN(SCIFA7_TXD), - GPIO_FN(SCIFA7_RTS_), \ - GPIO_FN(PORT19_VIO_CKO2), - GPIO_FN(GPO0), - GPIO_FN(GPO1), - GPIO_FN(GPO2), \ - GPIO_FN(STATUS0), - GPIO_FN(GPO3), \ - GPIO_FN(STATUS1), - GPIO_FN(GPO4), \ - GPIO_FN(STATUS2), - GPIO_FN(VINT), - GPIO_FN(TCKON), - GPIO_FN(XDVFS1), \ - GPIO_FN(PORT27_I2C_SCL2), \ - GPIO_FN(PORT27_I2C_SCL3), \ - GPIO_FN(MFG0_OUT1), \ - GPIO_FN(PORT27_IROUT), - GPIO_FN(XDVFS2), \ - GPIO_FN(PORT28_I2C_SDA2), \ - GPIO_FN(PORT28_I2C_SDA3), \ - GPIO_FN(PORT28_TPU1TO1), - GPIO_FN(SIM_RST), \ - GPIO_FN(PORT29_TPU1TO1), - GPIO_FN(SIM_CLK), \ - GPIO_FN(PORT30_VIO_CKOR), - GPIO_FN(SIM_D), \ - GPIO_FN(PORT31_IROUT), - GPIO_FN(SCIFA4_TXD), - GPIO_FN(SCIFA4_RXD), \ - GPIO_FN(XWUP), - GPIO_FN(SCIFA4_RTS_), - GPIO_FN(SCIFA4_CTS_), - GPIO_FN(FSIBOBT), \ - GPIO_FN(FSIBIBT), - GPIO_FN(FSIBOLR), \ - GPIO_FN(FSIBILR), - GPIO_FN(FSIBOSLD), - GPIO_FN(FSIBISLD), - GPIO_FN(VACK), - GPIO_FN(XTAL1L), - GPIO_FN(SCIFA0_RTS_), \ - GPIO_FN(FSICOSLDT2), - GPIO_FN(SCIFA0_RXD), - GPIO_FN(SCIFA0_CTS_), \ - GPIO_FN(FSICOSLDT1), - GPIO_FN(FSICOBT), \ - GPIO_FN(FSICIBT), \ - GPIO_FN(FSIDOBT), \ - GPIO_FN(FSIDIBT), - GPIO_FN(FSICOLR), \ - GPIO_FN(FSICILR), \ - GPIO_FN(FSIDOLR), \ - GPIO_FN(FSIDILR), - GPIO_FN(FSICOSLD), \ - GPIO_FN(PORT47_FSICSPDIF), - GPIO_FN(FSICISLD), \ - GPIO_FN(FSIDISLD), - GPIO_FN(FSIACK), \ - GPIO_FN(PORT49_IRDA_OUT), \ - GPIO_FN(PORT49_IROUT), \ - GPIO_FN(FSIAOMC), - GPIO_FN(FSIAOLR), \ - GPIO_FN(BBIF2_TSYNC2), \ - GPIO_FN(TPU2TO2), \ - GPIO_FN(FSIAILR), - - GPIO_FN(FSIAOBT), \ - GPIO_FN(BBIF2_TSCK2), \ - GPIO_FN(TPU2TO3), \ - GPIO_FN(FSIAIBT), - GPIO_FN(FSIAOSLD), \ - GPIO_FN(BBIF2_TXD2), - GPIO_FN(FSIASPDIF), \ - GPIO_FN(PORT53_IRDA_IN), \ - GPIO_FN(TPU3TO3), \ - GPIO_FN(FSIBSPDIF), \ - GPIO_FN(PORT53_FSICSPDIF), - GPIO_FN(FSIBCK), \ - GPIO_FN(PORT54_IRDA_FIRSEL), \ - GPIO_FN(TPU3TO2), \ - GPIO_FN(FSIBOMC), \ - GPIO_FN(FSICCK), \ - GPIO_FN(FSICOMC), - GPIO_FN(FSIAISLD), \ - GPIO_FN(TPU0TO0), - GPIO_FN(A0), \ - GPIO_FN(BS_), - GPIO_FN(A12), \ - GPIO_FN(PORT58_KEYOUT7), \ - GPIO_FN(TPU4TO2), - GPIO_FN(A13), \ - GPIO_FN(PORT59_KEYOUT6), \ - GPIO_FN(TPU0TO1), - GPIO_FN(A14), \ - GPIO_FN(KEYOUT5), - GPIO_FN(A15), \ - GPIO_FN(KEYOUT4), - GPIO_FN(A16), \ - GPIO_FN(KEYOUT3), \ - GPIO_FN(MSIOF0_SS1), - GPIO_FN(A17), \ - GPIO_FN(KEYOUT2), \ - GPIO_FN(MSIOF0_TSYNC), - GPIO_FN(A18), \ - GPIO_FN(KEYOUT1), \ - GPIO_FN(MSIOF0_TSCK), - GPIO_FN(A19), \ - GPIO_FN(KEYOUT0), \ - GPIO_FN(MSIOF0_TXD), - GPIO_FN(A20), \ - GPIO_FN(KEYIN0), \ - GPIO_FN(MSIOF0_RSCK), - GPIO_FN(A21), \ - GPIO_FN(KEYIN1), \ - GPIO_FN(MSIOF0_RSYNC), - GPIO_FN(A22), \ - GPIO_FN(KEYIN2), \ - GPIO_FN(MSIOF0_MCK0), - GPIO_FN(A23), \ - GPIO_FN(KEYIN3), \ - GPIO_FN(MSIOF0_MCK1), - GPIO_FN(A24), \ - GPIO_FN(KEYIN4), \ - GPIO_FN(MSIOF0_RXD), - GPIO_FN(A25), \ - GPIO_FN(KEYIN5), \ - GPIO_FN(MSIOF0_SS2), - GPIO_FN(A26), \ - GPIO_FN(KEYIN6), - GPIO_FN(KEYIN7), - GPIO_FN(D0_NAF0), - GPIO_FN(D1_NAF1), - GPIO_FN(D2_NAF2), - GPIO_FN(D3_NAF3), - GPIO_FN(D4_NAF4), - GPIO_FN(D5_NAF5), - GPIO_FN(D6_NAF6), - GPIO_FN(D7_NAF7), - GPIO_FN(D8_NAF8), - GPIO_FN(D9_NAF9), - GPIO_FN(D10_NAF10), - GPIO_FN(D11_NAF11), - GPIO_FN(D12_NAF12), - GPIO_FN(D13_NAF13), - GPIO_FN(D14_NAF14), - GPIO_FN(D15_NAF15), - GPIO_FN(CS4_), - GPIO_FN(CS5A_), \ - GPIO_FN(PORT91_RDWR), - GPIO_FN(CS5B_), \ - GPIO_FN(FCE1_), - GPIO_FN(CS6B_), \ - GPIO_FN(DACK0), - GPIO_FN(FCE0_), \ - GPIO_FN(CS6A_), - GPIO_FN(WAIT_), \ - GPIO_FN(DREQ0), - GPIO_FN(RD__FSC), - GPIO_FN(WE0__FWE), \ - GPIO_FN(RDWR_FWE), - GPIO_FN(WE1_), - GPIO_FN(FRB), - GPIO_FN(CKO), - GPIO_FN(NBRSTOUT_), - GPIO_FN(NBRST_), - GPIO_FN(BBIF2_TXD), - GPIO_FN(BBIF2_RXD), - GPIO_FN(BBIF2_SYNC), - GPIO_FN(BBIF2_SCK), - GPIO_FN(SCIFA3_CTS_), \ - GPIO_FN(MFG3_IN2), - GPIO_FN(SCIFA3_RXD), \ - GPIO_FN(MFG3_IN1), - GPIO_FN(BBIF1_SS2), \ - GPIO_FN(SCIFA3_RTS_), \ - GPIO_FN(MFG3_OUT1), - GPIO_FN(SCIFA3_TXD), - GPIO_FN(HSI_RX_DATA), \ - GPIO_FN(BBIF1_RXD), - GPIO_FN(HSI_TX_WAKE), \ - GPIO_FN(BBIF1_TSCK), - GPIO_FN(HSI_TX_DATA), \ - GPIO_FN(BBIF1_TSYNC), - GPIO_FN(HSI_TX_READY), \ - GPIO_FN(BBIF1_TXD), - GPIO_FN(HSI_RX_READY), \ - GPIO_FN(BBIF1_RSCK), \ - GPIO_FN(PORT115_I2C_SCL2), \ - GPIO_FN(PORT115_I2C_SCL3), - GPIO_FN(HSI_RX_WAKE), \ - GPIO_FN(BBIF1_RSYNC), \ - GPIO_FN(PORT116_I2C_SDA2), \ - GPIO_FN(PORT116_I2C_SDA3), - GPIO_FN(HSI_RX_FLAG), \ - GPIO_FN(BBIF1_SS1), \ - GPIO_FN(BBIF1_FLOW), - GPIO_FN(HSI_TX_FLAG), - GPIO_FN(VIO_VD), \ - GPIO_FN(PORT128_LCD2VSYN), \ - GPIO_FN(VIO2_VD), \ - GPIO_FN(LCD2D0), - - GPIO_FN(VIO_HD), \ - GPIO_FN(PORT129_LCD2HSYN), \ - GPIO_FN(PORT129_LCD2CS_), \ - GPIO_FN(VIO2_HD), \ - GPIO_FN(LCD2D1), - GPIO_FN(VIO_D0), \ - GPIO_FN(PORT130_MSIOF2_RXD), \ - GPIO_FN(LCD2D10), - GPIO_FN(VIO_D1), \ - GPIO_FN(PORT131_KEYOUT6), \ - GPIO_FN(PORT131_MSIOF2_SS1), \ - GPIO_FN(PORT131_KEYOUT11), \ - GPIO_FN(LCD2D11), - GPIO_FN(VIO_D2), \ - GPIO_FN(PORT132_KEYOUT7), \ - GPIO_FN(PORT132_MSIOF2_SS2), \ - GPIO_FN(PORT132_KEYOUT10), \ - GPIO_FN(LCD2D12), - GPIO_FN(VIO_D3), \ - GPIO_FN(MSIOF2_TSYNC), \ - GPIO_FN(LCD2D13), - GPIO_FN(VIO_D4), \ - GPIO_FN(MSIOF2_TXD), \ - GPIO_FN(LCD2D14), - GPIO_FN(VIO_D5), \ - GPIO_FN(MSIOF2_TSCK), \ - GPIO_FN(LCD2D15), - GPIO_FN(VIO_D6), \ - GPIO_FN(PORT136_KEYOUT8), \ - GPIO_FN(LCD2D16), - GPIO_FN(VIO_D7), \ - GPIO_FN(PORT137_KEYOUT9), \ - GPIO_FN(LCD2D17), - GPIO_FN(VIO_D8), \ - GPIO_FN(PORT138_KEYOUT8), \ - GPIO_FN(VIO2_D0), \ - GPIO_FN(LCD2D6), - GPIO_FN(VIO_D9), \ - GPIO_FN(PORT139_KEYOUT9), \ - GPIO_FN(VIO2_D1), \ - GPIO_FN(LCD2D7), - GPIO_FN(VIO_D10), \ - GPIO_FN(TPU0TO2), \ - GPIO_FN(VIO2_D2), \ - GPIO_FN(LCD2D8), - GPIO_FN(VIO_D11), \ - GPIO_FN(TPU0TO3), \ - GPIO_FN(VIO2_D3), \ - GPIO_FN(LCD2D9), - GPIO_FN(VIO_D12), \ - GPIO_FN(PORT142_KEYOUT10), \ - GPIO_FN(VIO2_D4), \ - GPIO_FN(LCD2D2), - GPIO_FN(VIO_D13), \ - GPIO_FN(PORT143_KEYOUT11), \ - GPIO_FN(PORT143_KEYOUT6), \ - GPIO_FN(VIO2_D5), \ - GPIO_FN(LCD2D3), - GPIO_FN(VIO_D14), \ - GPIO_FN(PORT144_KEYOUT7), \ - GPIO_FN(VIO2_D6), \ - GPIO_FN(LCD2D4), - GPIO_FN(VIO_D15), \ - GPIO_FN(TPU1TO3), \ - GPIO_FN(PORT145_LCD2DISP), \ - GPIO_FN(PORT145_LCD2RS), \ - GPIO_FN(VIO2_D7), \ - GPIO_FN(LCD2D5), - GPIO_FN(VIO_CLK), \ - GPIO_FN(LCD2DCK), \ - GPIO_FN(PORT146_LCD2WR_), \ - GPIO_FN(VIO2_CLK), \ - GPIO_FN(LCD2D18), - GPIO_FN(VIO_FIELD), \ - GPIO_FN(LCD2RD_), \ - GPIO_FN(VIO2_FIELD), \ - GPIO_FN(LCD2D19), - GPIO_FN(VIO_CKO), - GPIO_FN(A27), \ - GPIO_FN(PORT149_RDWR), \ - GPIO_FN(MFG0_IN1), \ - GPIO_FN(PORT149_KEYOUT9), - GPIO_FN(MFG0_IN2), - GPIO_FN(TS_SPSYNC3), \ - GPIO_FN(MSIOF2_RSCK), - GPIO_FN(TS_SDAT3), \ - GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(TPU1TO2), \ - GPIO_FN(TS_SDEN3), \ - GPIO_FN(PORT153_MSIOF2_SS1), - GPIO_FN(SCIFA2_TXD1), \ - GPIO_FN(MSIOF2_MCK0), - GPIO_FN(SCIFA2_RXD1), \ - GPIO_FN(MSIOF2_MCK1), - GPIO_FN(SCIFA2_RTS1_), \ - GPIO_FN(PORT156_MSIOF2_SS2), - GPIO_FN(SCIFA2_CTS1_), \ - GPIO_FN(PORT157_MSIOF2_RXD), - GPIO_FN(DINT_), \ - GPIO_FN(SCIFA2_SCK1), \ - GPIO_FN(TS_SCK3), - GPIO_FN(PORT159_SCIFB_SCK), \ - GPIO_FN(PORT159_SCIFA5_SCK), \ - GPIO_FN(NMI), - GPIO_FN(PORT160_SCIFB_TXD), \ - GPIO_FN(PORT160_SCIFA5_TXD), - GPIO_FN(PORT161_SCIFB_CTS_), \ - GPIO_FN(PORT161_SCIFA5_CTS_), - GPIO_FN(PORT162_SCIFB_RXD), \ - GPIO_FN(PORT162_SCIFA5_RXD), - GPIO_FN(PORT163_SCIFB_RTS_), \ - GPIO_FN(PORT163_SCIFA5_RTS_), \ - GPIO_FN(TPU3TO0), - GPIO_FN(LCDD0), - GPIO_FN(LCDD1), \ - GPIO_FN(PORT193_SCIFA5_CTS_), \ - GPIO_FN(BBIF2_TSYNC1), - GPIO_FN(LCDD2), \ - GPIO_FN(PORT194_SCIFA5_RTS_), \ - GPIO_FN(BBIF2_TSCK1), - GPIO_FN(LCDD3), \ - GPIO_FN(PORT195_SCIFA5_RXD), \ - GPIO_FN(BBIF2_TXD1), - GPIO_FN(LCDD4), \ - GPIO_FN(PORT196_SCIFA5_TXD), - GPIO_FN(LCDD5), \ - GPIO_FN(PORT197_SCIFA5_SCK), \ - GPIO_FN(MFG2_OUT2), \ - GPIO_FN(TPU2TO1), - GPIO_FN(LCDD6), - GPIO_FN(LCDD7), \ - GPIO_FN(TPU4TO1), \ - GPIO_FN(MFG4_OUT2), - GPIO_FN(LCDD8), \ - GPIO_FN(D16), - GPIO_FN(LCDD9), \ - GPIO_FN(D17), - GPIO_FN(LCDD10), \ - GPIO_FN(D18), - GPIO_FN(LCDD11), \ - GPIO_FN(D19), - GPIO_FN(LCDD12), \ - GPIO_FN(D20), - GPIO_FN(LCDD13), \ - GPIO_FN(D21), - GPIO_FN(LCDD14), \ - GPIO_FN(D22), - GPIO_FN(LCDD15), \ - GPIO_FN(PORT207_MSIOF0L_SS1), \ - GPIO_FN(D23), - GPIO_FN(LCDD16), \ - GPIO_FN(PORT208_MSIOF0L_SS2), \ - GPIO_FN(D24), - GPIO_FN(LCDD17), \ - GPIO_FN(D25), - GPIO_FN(LCDD18), \ - GPIO_FN(DREQ2), \ - GPIO_FN(PORT210_MSIOF0L_SS1), \ - GPIO_FN(D26), - GPIO_FN(LCDD19), \ - GPIO_FN(PORT211_MSIOF0L_SS2), \ - GPIO_FN(D27), - GPIO_FN(LCDD20), \ - GPIO_FN(TS_SPSYNC1), \ - GPIO_FN(MSIOF0L_MCK0), \ - GPIO_FN(D28), - GPIO_FN(LCDD21), \ - GPIO_FN(TS_SDAT1), \ - GPIO_FN(MSIOF0L_MCK1), \ - GPIO_FN(D29), - GPIO_FN(LCDD22), \ - GPIO_FN(TS_SDEN1), \ - GPIO_FN(MSIOF0L_RSCK), \ - GPIO_FN(D30), - GPIO_FN(LCDD23), \ - GPIO_FN(TS_SCK1), \ - GPIO_FN(MSIOF0L_RSYNC), \ - GPIO_FN(D31), - GPIO_FN(LCDDCK), \ - GPIO_FN(LCDWR_), - GPIO_FN(LCDRD_), \ - GPIO_FN(DACK2), \ - GPIO_FN(PORT217_LCD2RS), \ - GPIO_FN(MSIOF0L_TSYNC), \ - GPIO_FN(VIO2_FIELD3), \ - GPIO_FN(PORT217_LCD2DISP), - GPIO_FN(LCDHSYN), \ - GPIO_FN(LCDCS_), \ - GPIO_FN(LCDCS2_), \ - GPIO_FN(DACK3), \ - GPIO_FN(PORT218_VIO_CKOR), - GPIO_FN(LCDDISP), \ - GPIO_FN(LCDRS), \ - GPIO_FN(PORT219_LCD2WR_), \ - GPIO_FN(DREQ3), \ - GPIO_FN(MSIOF0L_TSCK), \ - GPIO_FN(VIO2_CLK3), \ - GPIO_FN(LCD2DCK_2), - GPIO_FN(LCDVSYN), \ - GPIO_FN(LCDVSYN2), - GPIO_FN(LCDLCLK), \ - GPIO_FN(DREQ1), \ - GPIO_FN(PORT221_LCD2CS_), \ - GPIO_FN(PWEN), \ - GPIO_FN(MSIOF0L_RXD), \ - GPIO_FN(VIO2_HD3), \ - GPIO_FN(PORT221_LCD2HSYN), - GPIO_FN(LCDDON), \ - GPIO_FN(LCDDON2), \ - GPIO_FN(DACK1), \ - GPIO_FN(OVCN), \ - GPIO_FN(MSIOF0L_TXD), \ - GPIO_FN(VIO2_VD3), \ - GPIO_FN(PORT222_LCD2VSYN), - - GPIO_FN(SCIFA1_TXD), \ - GPIO_FN(OVCN2), - GPIO_FN(EXTLP), \ - GPIO_FN(SCIFA1_SCK), \ - GPIO_FN(PORT226_VIO_CKO2), - GPIO_FN(SCIFA1_RTS_), \ - GPIO_FN(IDIN), - GPIO_FN(SCIFA1_RXD), - GPIO_FN(SCIFA1_CTS_), \ - GPIO_FN(MFG1_IN1), - GPIO_FN(MSIOF1_TXD), \ - GPIO_FN(SCIFA2_TXD2), - GPIO_FN(MSIOF1_TSYNC), \ - GPIO_FN(SCIFA2_CTS2_), - GPIO_FN(MSIOF1_TSCK), \ - GPIO_FN(SCIFA2_SCK2), - GPIO_FN(MSIOF1_RXD), \ - GPIO_FN(SCIFA2_RXD2), - GPIO_FN(MSIOF1_RSCK), \ - GPIO_FN(SCIFA2_RTS2_), \ - GPIO_FN(VIO2_CLK2), \ - GPIO_FN(LCD2D20), - GPIO_FN(MSIOF1_RSYNC), \ - GPIO_FN(MFG1_IN2), \ - GPIO_FN(VIO2_VD2), \ - GPIO_FN(LCD2D21), - GPIO_FN(MSIOF1_MCK0), \ - GPIO_FN(PORT236_I2C_SDA2), - GPIO_FN(MSIOF1_MCK1), \ - GPIO_FN(PORT237_I2C_SCL2), - GPIO_FN(MSIOF1_SS1), \ - GPIO_FN(VIO2_FIELD2), \ - GPIO_FN(LCD2D22), - GPIO_FN(MSIOF1_SS2), \ - GPIO_FN(VIO2_HD2), \ - GPIO_FN(LCD2D23), - GPIO_FN(SCIFA6_TXD), - GPIO_FN(PORT241_IRDA_OUT), \ - GPIO_FN(PORT241_IROUT), \ - GPIO_FN(MFG4_OUT1), \ - GPIO_FN(TPU4TO0), - GPIO_FN(PORT242_IRDA_IN), \ - GPIO_FN(MFG4_IN2), - GPIO_FN(PORT243_IRDA_FIRSEL), \ - GPIO_FN(PORT243_VIO_CKO2), - GPIO_FN(PORT244_SCIFA5_CTS_), \ - GPIO_FN(MFG2_IN1), \ - GPIO_FN(PORT244_SCIFB_CTS_), \ - GPIO_FN(MSIOF2R_RXD), - GPIO_FN(PORT245_SCIFA5_RTS_), \ - GPIO_FN(MFG2_IN2), \ - GPIO_FN(PORT245_SCIFB_RTS_), \ - GPIO_FN(MSIOF2R_TXD), - GPIO_FN(PORT246_SCIFA5_RXD), \ - GPIO_FN(MFG1_OUT1), \ - GPIO_FN(PORT246_SCIFB_RXD), \ - GPIO_FN(TPU1TO0), - GPIO_FN(PORT247_SCIFA5_TXD), \ - GPIO_FN(MFG3_OUT2), \ - GPIO_FN(PORT247_SCIFB_TXD), \ - GPIO_FN(TPU3TO1), - GPIO_FN(PORT248_SCIFA5_SCK), \ - GPIO_FN(MFG2_OUT1), \ - GPIO_FN(PORT248_SCIFB_SCK), \ - GPIO_FN(TPU2TO0), \ - GPIO_FN(PORT248_I2C_SCL3), \ - GPIO_FN(MSIOF2R_TSCK), - GPIO_FN(PORT249_IROUT), \ - GPIO_FN(MFG4_IN1), \ - GPIO_FN(PORT249_I2C_SDA3), \ - GPIO_FN(MSIOF2R_TSYNC), - GPIO_FN(SDHICLK0), - GPIO_FN(SDHICD0), - GPIO_FN(SDHID0_0), - GPIO_FN(SDHID0_1), - GPIO_FN(SDHID0_2), - GPIO_FN(SDHID0_3), - GPIO_FN(SDHICMD0), - GPIO_FN(SDHIWP0), - GPIO_FN(SDHICLK1), - GPIO_FN(SDHID1_0), \ - GPIO_FN(TS_SPSYNC2), - GPIO_FN(SDHID1_1), \ - GPIO_FN(TS_SDAT2), - GPIO_FN(SDHID1_2), \ - GPIO_FN(TS_SDEN2), - GPIO_FN(SDHID1_3), \ - GPIO_FN(TS_SCK2), - GPIO_FN(SDHICMD1), - GPIO_FN(SDHICLK2), - GPIO_FN(SDHID2_0), \ - GPIO_FN(TS_SPSYNC4), - GPIO_FN(SDHID2_1), \ - GPIO_FN(TS_SDAT4), - GPIO_FN(SDHID2_2), \ - GPIO_FN(TS_SDEN4), - GPIO_FN(SDHID2_3), \ - GPIO_FN(TS_SCK4), - GPIO_FN(SDHICMD2), - GPIO_FN(MMCCLK0), - GPIO_FN(MMCD0_0), - GPIO_FN(MMCD0_1), - GPIO_FN(MMCD0_2), - GPIO_FN(MMCD0_3), - GPIO_FN(MMCD0_4), \ - GPIO_FN(TS_SPSYNC5), - GPIO_FN(MMCD0_5), \ - GPIO_FN(TS_SDAT5), - GPIO_FN(MMCD0_6), \ - GPIO_FN(TS_SDEN5), - GPIO_FN(MMCD0_7), \ - GPIO_FN(TS_SCK5), - GPIO_FN(MMCCMD0), - GPIO_FN(RESETOUTS_), \ - GPIO_FN(EXTAL2OUT), - GPIO_FN(MCP_WAIT__MCP_FRB), - GPIO_FN(MCP_CKO), \ - GPIO_FN(MMCCLK1), - GPIO_FN(MCP_D15_MCP_NAF15), - GPIO_FN(MCP_D14_MCP_NAF14), - GPIO_FN(MCP_D13_MCP_NAF13), - GPIO_FN(MCP_D12_MCP_NAF12), - GPIO_FN(MCP_D11_MCP_NAF11), - GPIO_FN(MCP_D10_MCP_NAF10), - GPIO_FN(MCP_D9_MCP_NAF9), - GPIO_FN(MCP_D8_MCP_NAF8), \ - GPIO_FN(MMCCMD1), - GPIO_FN(MCP_D7_MCP_NAF7), \ - GPIO_FN(MMCD1_7), - - GPIO_FN(MCP_D6_MCP_NAF6), \ - GPIO_FN(MMCD1_6), - GPIO_FN(MCP_D5_MCP_NAF5), \ - GPIO_FN(MMCD1_5), - GPIO_FN(MCP_D4_MCP_NAF4), \ - GPIO_FN(MMCD1_4), - GPIO_FN(MCP_D3_MCP_NAF3), \ - GPIO_FN(MMCD1_3), - GPIO_FN(MCP_D2_MCP_NAF2), \ - GPIO_FN(MMCD1_2), - GPIO_FN(MCP_D1_MCP_NAF1), \ - GPIO_FN(MMCD1_1), - GPIO_FN(MCP_D0_MCP_NAF0), \ - GPIO_FN(MMCD1_0), - GPIO_FN(MCP_NBRSTOUT_), - GPIO_FN(MCP_WE0__MCP_FWE), \ - GPIO_FN(MCP_RDWR_MCP_FWE), - - /* MSEL2 special cases */ - GPIO_FN(TSIF2_TS_XX1), - GPIO_FN(TSIF2_TS_XX2), - GPIO_FN(TSIF2_TS_XX3), - GPIO_FN(TSIF2_TS_XX4), - GPIO_FN(TSIF2_TS_XX5), - GPIO_FN(TSIF1_TS_XX1), - GPIO_FN(TSIF1_TS_XX2), - GPIO_FN(TSIF1_TS_XX3), - GPIO_FN(TSIF1_TS_XX4), - GPIO_FN(TSIF1_TS_XX5), - GPIO_FN(TSIF0_TS_XX1), - GPIO_FN(TSIF0_TS_XX2), - GPIO_FN(TSIF0_TS_XX3), - GPIO_FN(TSIF0_TS_XX4), - GPIO_FN(TSIF0_TS_XX5), - GPIO_FN(MST1_TS_XX1), - GPIO_FN(MST1_TS_XX2), - GPIO_FN(MST1_TS_XX3), - GPIO_FN(MST1_TS_XX4), - GPIO_FN(MST1_TS_XX5), - GPIO_FN(MST0_TS_XX1), - GPIO_FN(MST0_TS_XX2), - GPIO_FN(MST0_TS_XX3), - GPIO_FN(MST0_TS_XX4), - GPIO_FN(MST0_TS_XX5), - - /* MSEL3 special cases */ - GPIO_FN(SDHI0_VCCQ_MC0_ON), - GPIO_FN(SDHI0_VCCQ_MC0_OFF), - GPIO_FN(DEBUG_MON_VIO), - GPIO_FN(DEBUG_MON_LCDD), - GPIO_FN(LCDC_LCDC0), - GPIO_FN(LCDC_LCDC1), - - /* MSEL4 special cases */ - GPIO_FN(IRQ9_MEM_INT), - GPIO_FN(IRQ9_MCP_INT), - GPIO_FN(A11), - GPIO_FN(KEYOUT8), - GPIO_FN(TPU4TO3), - GPIO_FN(RESETA_N_PU_ON), - GPIO_FN(RESETA_N_PU_OFF), - GPIO_FN(EDBGREQ_PD), - GPIO_FN(EDBGREQ_PU), - - /* Functions with pull-ups */ - GPIO_FN(KEYIN0_PU), - GPIO_FN(KEYIN1_PU), - GPIO_FN(KEYIN2_PU), - GPIO_FN(KEYIN3_PU), - GPIO_FN(KEYIN4_PU), - GPIO_FN(KEYIN5_PU), - GPIO_FN(KEYIN6_PU), - GPIO_FN(KEYIN7_PU), - GPIO_FN(SDHICD0_PU), - GPIO_FN(SDHID0_0_PU), - GPIO_FN(SDHID0_1_PU), - GPIO_FN(SDHID0_2_PU), - GPIO_FN(SDHID0_3_PU), - GPIO_FN(SDHICMD0_PU), - GPIO_FN(SDHIWP0_PU), - GPIO_FN(SDHID1_0_PU), - GPIO_FN(SDHID1_1_PU), - GPIO_FN(SDHID1_2_PU), - GPIO_FN(SDHID1_3_PU), - GPIO_FN(SDHICMD1_PU), - GPIO_FN(SDHID2_0_PU), - GPIO_FN(SDHID2_1_PU), - GPIO_FN(SDHID2_2_PU), - GPIO_FN(SDHID2_3_PU), - GPIO_FN(SDHICMD2_PU), - GPIO_FN(MMCCMD0_PU), - GPIO_FN(MMCCMD1_PU), - GPIO_FN(MMCD0_0_PU), - GPIO_FN(MMCD0_1_PU), - GPIO_FN(MMCD0_2_PU), - GPIO_FN(MMCD0_3_PU), - GPIO_FN(MMCD0_4_PU), - GPIO_FN(MMCD0_5_PU), - GPIO_FN(MMCD0_6_PU), - GPIO_FN(MMCD0_7_PU), - GPIO_FN(FSIACK_PU), - GPIO_FN(FSIAILR_PU), - GPIO_FN(FSIAIBT_PU), - GPIO_FN(FSIAISLD_PU), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - PORTCR(0, 0xe6050000), /* PORT0CR */ - PORTCR(1, 0xe6050001), /* PORT1CR */ - PORTCR(2, 0xe6050002), /* PORT2CR */ - PORTCR(3, 0xe6050003), /* PORT3CR */ - PORTCR(4, 0xe6050004), /* PORT4CR */ - PORTCR(5, 0xe6050005), /* PORT5CR */ - PORTCR(6, 0xe6050006), /* PORT6CR */ - PORTCR(7, 0xe6050007), /* PORT7CR */ - PORTCR(8, 0xe6050008), /* PORT8CR */ - PORTCR(9, 0xe6050009), /* PORT9CR */ - - PORTCR(10, 0xe605000a), /* PORT10CR */ - PORTCR(11, 0xe605000b), /* PORT11CR */ - PORTCR(12, 0xe605000c), /* PORT12CR */ - PORTCR(13, 0xe605000d), /* PORT13CR */ - PORTCR(14, 0xe605000e), /* PORT14CR */ - PORTCR(15, 0xe605000f), /* PORT15CR */ - PORTCR(16, 0xe6050010), /* PORT16CR */ - PORTCR(17, 0xe6050011), /* PORT17CR */ - PORTCR(18, 0xe6050012), /* PORT18CR */ - PORTCR(19, 0xe6050013), /* PORT19CR */ - - PORTCR(20, 0xe6050014), /* PORT20CR */ - PORTCR(21, 0xe6050015), /* PORT21CR */ - PORTCR(22, 0xe6050016), /* PORT22CR */ - PORTCR(23, 0xe6050017), /* PORT23CR */ - PORTCR(24, 0xe6050018), /* PORT24CR */ - PORTCR(25, 0xe6050019), /* PORT25CR */ - PORTCR(26, 0xe605001a), /* PORT26CR */ - PORTCR(27, 0xe605001b), /* PORT27CR */ - PORTCR(28, 0xe605001c), /* PORT28CR */ - PORTCR(29, 0xe605001d), /* PORT29CR */ - - PORTCR(30, 0xe605001e), /* PORT30CR */ - PORTCR(31, 0xe605001f), /* PORT31CR */ - PORTCR(32, 0xe6051020), /* PORT32CR */ - PORTCR(33, 0xe6051021), /* PORT33CR */ - PORTCR(34, 0xe6051022), /* PORT34CR */ - PORTCR(35, 0xe6051023), /* PORT35CR */ - PORTCR(36, 0xe6051024), /* PORT36CR */ - PORTCR(37, 0xe6051025), /* PORT37CR */ - PORTCR(38, 0xe6051026), /* PORT38CR */ - PORTCR(39, 0xe6051027), /* PORT39CR */ - - PORTCR(40, 0xe6051028), /* PORT40CR */ - PORTCR(41, 0xe6051029), /* PORT41CR */ - PORTCR(42, 0xe605102a), /* PORT42CR */ - PORTCR(43, 0xe605102b), /* PORT43CR */ - PORTCR(44, 0xe605102c), /* PORT44CR */ - PORTCR(45, 0xe605102d), /* PORT45CR */ - PORTCR(46, 0xe605102e), /* PORT46CR */ - PORTCR(47, 0xe605102f), /* PORT47CR */ - PORTCR(48, 0xe6051030), /* PORT48CR */ - PORTCR(49, 0xe6051031), /* PORT49CR */ - - PORTCR(50, 0xe6051032), /* PORT50CR */ - PORTCR(51, 0xe6051033), /* PORT51CR */ - PORTCR(52, 0xe6051034), /* PORT52CR */ - PORTCR(53, 0xe6051035), /* PORT53CR */ - PORTCR(54, 0xe6051036), /* PORT54CR */ - PORTCR(55, 0xe6051037), /* PORT55CR */ - PORTCR(56, 0xe6051038), /* PORT56CR */ - PORTCR(57, 0xe6051039), /* PORT57CR */ - PORTCR(58, 0xe605103a), /* PORT58CR */ - PORTCR(59, 0xe605103b), /* PORT59CR */ - - PORTCR(60, 0xe605103c), /* PORT60CR */ - PORTCR(61, 0xe605103d), /* PORT61CR */ - PORTCR(62, 0xe605103e), /* PORT62CR */ - PORTCR(63, 0xe605103f), /* PORT63CR */ - PORTCR(64, 0xe6051040), /* PORT64CR */ - PORTCR(65, 0xe6051041), /* PORT65CR */ - PORTCR(66, 0xe6051042), /* PORT66CR */ - PORTCR(67, 0xe6051043), /* PORT67CR */ - PORTCR(68, 0xe6051044), /* PORT68CR */ - PORTCR(69, 0xe6051045), /* PORT69CR */ - - PORTCR(70, 0xe6051046), /* PORT70CR */ - PORTCR(71, 0xe6051047), /* PORT71CR */ - PORTCR(72, 0xe6051048), /* PORT72CR */ - PORTCR(73, 0xe6051049), /* PORT73CR */ - PORTCR(74, 0xe605104a), /* PORT74CR */ - PORTCR(75, 0xe605104b), /* PORT75CR */ - PORTCR(76, 0xe605104c), /* PORT76CR */ - PORTCR(77, 0xe605104d), /* PORT77CR */ - PORTCR(78, 0xe605104e), /* PORT78CR */ - PORTCR(79, 0xe605104f), /* PORT79CR */ - - PORTCR(80, 0xe6051050), /* PORT80CR */ - PORTCR(81, 0xe6051051), /* PORT81CR */ - PORTCR(82, 0xe6051052), /* PORT82CR */ - PORTCR(83, 0xe6051053), /* PORT83CR */ - PORTCR(84, 0xe6051054), /* PORT84CR */ - PORTCR(85, 0xe6051055), /* PORT85CR */ - PORTCR(86, 0xe6051056), /* PORT86CR */ - PORTCR(87, 0xe6051057), /* PORT87CR */ - PORTCR(88, 0xe6051058), /* PORT88CR */ - PORTCR(89, 0xe6051059), /* PORT89CR */ - - PORTCR(90, 0xe605105a), /* PORT90CR */ - PORTCR(91, 0xe605105b), /* PORT91CR */ - PORTCR(92, 0xe605105c), /* PORT92CR */ - PORTCR(93, 0xe605105d), /* PORT93CR */ - PORTCR(94, 0xe605105e), /* PORT94CR */ - PORTCR(95, 0xe605105f), /* PORT95CR */ - PORTCR(96, 0xe6052060), /* PORT96CR */ - PORTCR(97, 0xe6052061), /* PORT97CR */ - PORTCR(98, 0xe6052062), /* PORT98CR */ - PORTCR(99, 0xe6052063), /* PORT99CR */ - - PORTCR(100, 0xe6052064), /* PORT100CR */ - PORTCR(101, 0xe6052065), /* PORT101CR */ - PORTCR(102, 0xe6052066), /* PORT102CR */ - PORTCR(103, 0xe6052067), /* PORT103CR */ - PORTCR(104, 0xe6052068), /* PORT104CR */ - PORTCR(105, 0xe6052069), /* PORT105CR */ - PORTCR(106, 0xe605206a), /* PORT106CR */ - PORTCR(107, 0xe605206b), /* PORT107CR */ - PORTCR(108, 0xe605206c), /* PORT108CR */ - PORTCR(109, 0xe605206d), /* PORT109CR */ - - PORTCR(110, 0xe605206e), /* PORT110CR */ - PORTCR(111, 0xe605206f), /* PORT111CR */ - PORTCR(112, 0xe6052070), /* PORT112CR */ - PORTCR(113, 0xe6052071), /* PORT113CR */ - PORTCR(114, 0xe6052072), /* PORT114CR */ - PORTCR(115, 0xe6052073), /* PORT115CR */ - PORTCR(116, 0xe6052074), /* PORT116CR */ - PORTCR(117, 0xe6052075), /* PORT117CR */ - PORTCR(118, 0xe6052076), /* PORT118CR */ - - PORTCR(128, 0xe6052080), /* PORT128CR */ - PORTCR(129, 0xe6052081), /* PORT129CR */ - - PORTCR(130, 0xe6052082), /* PORT130CR */ - PORTCR(131, 0xe6052083), /* PORT131CR */ - PORTCR(132, 0xe6052084), /* PORT132CR */ - PORTCR(133, 0xe6052085), /* PORT133CR */ - PORTCR(134, 0xe6052086), /* PORT134CR */ - PORTCR(135, 0xe6052087), /* PORT135CR */ - PORTCR(136, 0xe6052088), /* PORT136CR */ - PORTCR(137, 0xe6052089), /* PORT137CR */ - PORTCR(138, 0xe605208a), /* PORT138CR */ - PORTCR(139, 0xe605208b), /* PORT139CR */ - - PORTCR(140, 0xe605208c), /* PORT140CR */ - PORTCR(141, 0xe605208d), /* PORT141CR */ - PORTCR(142, 0xe605208e), /* PORT142CR */ - PORTCR(143, 0xe605208f), /* PORT143CR */ - PORTCR(144, 0xe6052090), /* PORT144CR */ - PORTCR(145, 0xe6052091), /* PORT145CR */ - PORTCR(146, 0xe6052092), /* PORT146CR */ - PORTCR(147, 0xe6052093), /* PORT147CR */ - PORTCR(148, 0xe6052094), /* PORT148CR */ - PORTCR(149, 0xe6052095), /* PORT149CR */ - - PORTCR(150, 0xe6052096), /* PORT150CR */ - PORTCR(151, 0xe6052097), /* PORT151CR */ - PORTCR(152, 0xe6052098), /* PORT152CR */ - PORTCR(153, 0xe6052099), /* PORT153CR */ - PORTCR(154, 0xe605209a), /* PORT154CR */ - PORTCR(155, 0xe605209b), /* PORT155CR */ - PORTCR(156, 0xe605209c), /* PORT156CR */ - PORTCR(157, 0xe605209d), /* PORT157CR */ - PORTCR(158, 0xe605209e), /* PORT158CR */ - PORTCR(159, 0xe605209f), /* PORT159CR */ - - PORTCR(160, 0xe60520a0), /* PORT160CR */ - PORTCR(161, 0xe60520a1), /* PORT161CR */ - PORTCR(162, 0xe60520a2), /* PORT162CR */ - PORTCR(163, 0xe60520a3), /* PORT163CR */ - PORTCR(164, 0xe60520a4), /* PORT164CR */ - - PORTCR(192, 0xe60520c0), /* PORT192CR */ - PORTCR(193, 0xe60520c1), /* PORT193CR */ - PORTCR(194, 0xe60520c2), /* PORT194CR */ - PORTCR(195, 0xe60520c3), /* PORT195CR */ - PORTCR(196, 0xe60520c4), /* PORT196CR */ - PORTCR(197, 0xe60520c5), /* PORT197CR */ - PORTCR(198, 0xe60520c6), /* PORT198CR */ - PORTCR(199, 0xe60520c7), /* PORT199CR */ - - PORTCR(200, 0xe60520c8), /* PORT200CR */ - PORTCR(201, 0xe60520c9), /* PORT201CR */ - PORTCR(202, 0xe60520ca), /* PORT202CR */ - PORTCR(203, 0xe60520cb), /* PORT203CR */ - PORTCR(204, 0xe60520cc), /* PORT204CR */ - PORTCR(205, 0xe60520cd), /* PORT205CR */ - PORTCR(206, 0xe60520ce), /* PORT206CR */ - PORTCR(207, 0xe60520cf), /* PORT207CR */ - PORTCR(208, 0xe60520d0), /* PORT208CR */ - PORTCR(209, 0xe60520d1), /* PORT209CR */ - - PORTCR(210, 0xe60520d2), /* PORT210CR */ - PORTCR(211, 0xe60520d3), /* PORT211CR */ - PORTCR(212, 0xe60520d4), /* PORT212CR */ - PORTCR(213, 0xe60520d5), /* PORT213CR */ - PORTCR(214, 0xe60520d6), /* PORT214CR */ - PORTCR(215, 0xe60520d7), /* PORT215CR */ - PORTCR(216, 0xe60520d8), /* PORT216CR */ - PORTCR(217, 0xe60520d9), /* PORT217CR */ - PORTCR(218, 0xe60520da), /* PORT218CR */ - PORTCR(219, 0xe60520db), /* PORT219CR */ - - PORTCR(220, 0xe60520dc), /* PORT220CR */ - PORTCR(221, 0xe60520dd), /* PORT221CR */ - PORTCR(222, 0xe60520de), /* PORT222CR */ - PORTCR(223, 0xe60520df), /* PORT223CR */ - PORTCR(224, 0xe60530e0), /* PORT224CR */ - PORTCR(225, 0xe60530e1), /* PORT225CR */ - PORTCR(226, 0xe60530e2), /* PORT226CR */ - PORTCR(227, 0xe60530e3), /* PORT227CR */ - PORTCR(228, 0xe60530e4), /* PORT228CR */ - PORTCR(229, 0xe60530e5), /* PORT229CR */ - - PORTCR(230, 0xe60530e6), /* PORT230CR */ - PORTCR(231, 0xe60530e7), /* PORT231CR */ - PORTCR(232, 0xe60530e8), /* PORT232CR */ - PORTCR(233, 0xe60530e9), /* PORT233CR */ - PORTCR(234, 0xe60530ea), /* PORT234CR */ - PORTCR(235, 0xe60530eb), /* PORT235CR */ - PORTCR(236, 0xe60530ec), /* PORT236CR */ - PORTCR(237, 0xe60530ed), /* PORT237CR */ - PORTCR(238, 0xe60530ee), /* PORT238CR */ - PORTCR(239, 0xe60530ef), /* PORT239CR */ - - PORTCR(240, 0xe60530f0), /* PORT240CR */ - PORTCR(241, 0xe60530f1), /* PORT241CR */ - PORTCR(242, 0xe60530f2), /* PORT242CR */ - PORTCR(243, 0xe60530f3), /* PORT243CR */ - PORTCR(244, 0xe60530f4), /* PORT244CR */ - PORTCR(245, 0xe60530f5), /* PORT245CR */ - PORTCR(246, 0xe60530f6), /* PORT246CR */ - PORTCR(247, 0xe60530f7), /* PORT247CR */ - PORTCR(248, 0xe60530f8), /* PORT248CR */ - PORTCR(249, 0xe60530f9), /* PORT249CR */ - - PORTCR(250, 0xe60530fa), /* PORT250CR */ - PORTCR(251, 0xe60530fb), /* PORT251CR */ - PORTCR(252, 0xe60530fc), /* PORT252CR */ - PORTCR(253, 0xe60530fd), /* PORT253CR */ - PORTCR(254, 0xe60530fe), /* PORT254CR */ - PORTCR(255, 0xe60530ff), /* PORT255CR */ - PORTCR(256, 0xe6053100), /* PORT256CR */ - PORTCR(257, 0xe6053101), /* PORT257CR */ - PORTCR(258, 0xe6053102), /* PORT258CR */ - PORTCR(259, 0xe6053103), /* PORT259CR */ - - PORTCR(260, 0xe6053104), /* PORT260CR */ - PORTCR(261, 0xe6053105), /* PORT261CR */ - PORTCR(262, 0xe6053106), /* PORT262CR */ - PORTCR(263, 0xe6053107), /* PORT263CR */ - PORTCR(264, 0xe6053108), /* PORT264CR */ - PORTCR(265, 0xe6053109), /* PORT265CR */ - PORTCR(266, 0xe605310a), /* PORT266CR */ - PORTCR(267, 0xe605310b), /* PORT267CR */ - PORTCR(268, 0xe605310c), /* PORT268CR */ - PORTCR(269, 0xe605310d), /* PORT269CR */ - - PORTCR(270, 0xe605310e), /* PORT270CR */ - PORTCR(271, 0xe605310f), /* PORT271CR */ - PORTCR(272, 0xe6053110), /* PORT272CR */ - PORTCR(273, 0xe6053111), /* PORT273CR */ - PORTCR(274, 0xe6053112), /* PORT274CR */ - PORTCR(275, 0xe6053113), /* PORT275CR */ - PORTCR(276, 0xe6053114), /* PORT276CR */ - PORTCR(277, 0xe6053115), /* PORT277CR */ - PORTCR(278, 0xe6053116), /* PORT278CR */ - PORTCR(279, 0xe6053117), /* PORT279CR */ - - PORTCR(280, 0xe6053118), /* PORT280CR */ - PORTCR(281, 0xe6053119), /* PORT281CR */ - PORTCR(282, 0xe605311a), /* PORT282CR */ - - PORTCR(288, 0xe6052120), /* PORT288CR */ - PORTCR(289, 0xe6052121), /* PORT289CR */ - - PORTCR(290, 0xe6052122), /* PORT290CR */ - PORTCR(291, 0xe6052123), /* PORT291CR */ - PORTCR(292, 0xe6052124), /* PORT292CR */ - PORTCR(293, 0xe6052125), /* PORT293CR */ - PORTCR(294, 0xe6052126), /* PORT294CR */ - PORTCR(295, 0xe6052127), /* PORT295CR */ - PORTCR(296, 0xe6052128), /* PORT296CR */ - PORTCR(297, 0xe6052129), /* PORT297CR */ - PORTCR(298, 0xe605212a), /* PORT298CR */ - PORTCR(299, 0xe605212b), /* PORT299CR */ - - PORTCR(300, 0xe605212c), /* PORT300CR */ - PORTCR(301, 0xe605212d), /* PORT301CR */ - PORTCR(302, 0xe605212e), /* PORT302CR */ - PORTCR(303, 0xe605212f), /* PORT303CR */ - PORTCR(304, 0xe6052130), /* PORT304CR */ - PORTCR(305, 0xe6052131), /* PORT305CR */ - PORTCR(306, 0xe6052132), /* PORT306CR */ - PORTCR(307, 0xe6052133), /* PORT307CR */ - PORTCR(308, 0xe6052134), /* PORT308CR */ - PORTCR(309, 0xe6052135), /* PORT309CR */ - - { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, - MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, - MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, - MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, - 0, 0, - MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, - MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, - MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, - MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, - MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, - MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, - MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, - MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, - MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, - MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, - MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, - MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, - MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, - MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, - MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, - } - }, - { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { - 0, 0, - 0, 0, - 0, 0, - MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, - 0, 0, - 0, 0, - 0, 0, - MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, - 0, 0, - MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, - 0, 0, - 0, 0, - MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, - 0, 0, - 0, 0, - 0, 0, - MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, - 0, 0, - 0, 0, - } - }, - { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { - 0, 0, - 0, 0, - MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, - 0, 0, - MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, - MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, - 0, 0, - 0, 0, - 0, 0, - MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, - MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, - MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, - MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, - 0, 0, - 0, 0, - 0, 0, - MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, - 0, 0, - MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, - MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, - MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, - MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, - MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, - MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, - MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, - 0, 0, - 0, 0, - MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, - 0, 0, - 0, 0, - MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, - 0, 0, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { - PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, - PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, - PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, - PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, - PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, - PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, - PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, - PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } - }, - { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { - PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, - PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, - PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, - PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, - PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, - PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, - PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, - PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } - }, - { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) { - PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, - PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, - PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, - PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, - PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, - PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, - PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, - PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } - }, - { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, - PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, - PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, - PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, - PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, - PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } - }, - { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) { - PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, - PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, - PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, - PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, - PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, - PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, - PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, - PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } - }, - { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, PORT164_DATA, - PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } - }, - { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) { - PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, - PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, - PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, - PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, - PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, - PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, - PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, - PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } - }, - { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { - PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, - PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, - PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, - PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, - PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, - PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, - PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, - PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } - }, - { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { - 0, 0, 0, 0, - 0, PORT282_DATA, PORT281_DATA, PORT280_DATA, - PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, - PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, - PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, - PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, - PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, - PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } - }, - { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, PORT309_DATA, PORT308_DATA, - PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, - PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, - PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, - PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, - PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA } - }, - { }, -}; - -#if 0 -/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ -#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) -#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) -#else -#define EXT_IRQ16L(n) (n) -#define EXT_IRQ16H(n) (n) -#endif - -static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), - PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), - PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), - PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), - PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), - PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), - PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), - PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), - PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), - PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), - PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), - PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), - PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), - PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), - PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), - PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), - PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), - PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), - PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), - PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), - PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), - PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), - PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), - PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), - PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), - PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), - PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), - PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), - PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), - PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), - PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), -}; - -static struct pinmux_info sh73a0_pinmux_info = { - .name = "sh73a0_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, - .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_FSIAISLD_PU, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), - - .gpio_irq = pinmux_irqs, - .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), -}; - -void sh73a0_pinmux_init(void) -{ - register_pinmux(&sh73a0_pinmux_info); -} diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c deleted file mode 100644 index 293c23b5e25..00000000000 --- a/arch/arm/mach-rmobile/timer.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <div64.h> -#include <init.h> -#include <time.h> -#include <asm/io.h> -#include <asm/arch-armv7/globaltimer.h> -#include <asm/arch/rmobile.h> -#include <linux/delay.h> - -static struct globaltimer *global_timer = \ - (struct globaltimer *)GLOBAL_TIMER_BASE_ADDR; - -#define CLK2MHZ(clk) (clk / 1000 / 1000) -static u64 get_cpu_global_timer(void) -{ - u32 low, high; - u64 timer; - - u32 old = readl(&global_timer->cnt_h); - while (1) { - low = readl(&global_timer->cnt_l); - high = readl(&global_timer->cnt_h); - if (old == high) - break; - else - old = high; - } - - timer = high; - return (u64)((timer << 32) | low); -} - -static u64 get_time_us(void) -{ - u64 timer = get_cpu_global_timer(); - - timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1)); - do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK)); - return timer; -} - -static ulong get_time_ms(void) -{ - u64 us = get_time_us(); - - do_div(us, 1000); - return us; -} - -int timer_init(void) -{ - writel(0x01, &global_timer->ctl); - return 0; -} - -void __udelay(unsigned long usec) -{ - u64 start, current; - u64 wait; - - start = get_cpu_global_timer(); - wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2); - do { - current = get_cpu_global_timer(); - } while ((current - start) < wait); -} - -ulong get_timer(ulong base) -{ - return get_time_ms() - base; -} - -unsigned long long get_ticks(void) -{ - return get_cpu_global_timer(); -} - -ulong get_tbclk(void) -{ - return (ulong)(CFG_SYS_CPU_CLK >> 2); -} diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 32138fa723f..e3d4a8b42e4 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,7 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) # Always include boot_mode.o, as we bypass it (i.e. turn it off) -# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way, +# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way, # we can have the preprocessor correctly recognise both 0x0 and 0 # meaning "turn it off". obj-y += boot_mode.o diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile index 63f18109a57..4a7960bbeb4 100644 --- a/arch/m68k/Makefile +++ b/arch/m68k/Makefile @@ -7,7 +7,6 @@ libs-y += arch/m68k/lib/ cpuflags-$(CONFIG_M5208) := -mcpu=5208 cpuflags-$(CONFIG_M5235) := -mcpu=5235 -fPIC -cpuflags-$(CONFIG_M52277) := -mcpu=52277 -fPIC cpuflags-$(CONFIG_M5249) := -mcpu=5249 cpuflags-$(CONFIG_M5253) := -mcpu=5253 cpuflags-$(CONFIG_M5271) := -mcpu=5271 diff --git a/arch/mips/mach-octeon/octeon_fdt.c b/arch/mips/mach-octeon/octeon_fdt.c index 0ccfe149dcc..c74fe9d9fb8 100644 --- a/arch/mips/mach-octeon/octeon_fdt.c +++ b/arch/mips/mach-octeon/octeon_fdt.c @@ -30,9 +30,6 @@ #ifdef CONFIG_PCF857X #include <pcf857x.h> #endif -#ifdef CONFIG_PCA9698 -#include <pca9698.h> -#endif #ifdef CONFIG_PCA9554 #include <pca9554.h> #endif @@ -59,13 +56,6 @@ static const char * const pca9555_gpio_list[] = { }; #endif -#ifdef CONFIG_PCA9698 -/** List of compatible strings supported by pca9698 driver */ -static const char * const pca9698_gpio_list[] = { - "nxp,pca9505", "pca9505", "nxp,pca9698", "pca9698", NULL, -}; -#endif - #ifdef CONFIG_PCA953X /** List of compatible strings supported by pca953x driver */ static const char * const pca953x_gpio_list[] = { @@ -808,19 +798,6 @@ int octeon_fdt_read_gpio(const void *fdt, int phandle, int pin) value = (value >> pin) & 1; break; #endif -#ifdef CONFIG_PCA9698 - case CVMX_GPIO_PIN_PCA9698: - node = fdt_node_offset_by_phandle(fdt, phandle); - if (octeon_fdt_get_i2c_bus_addr(fdt, node, &bus, &addr)) { - printf("%s: Could not get gpio bus and/or address\n", __func__); - return -1; - } - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(bus); - value = pca9698_get_value(addr, pin); - i2c_set_bus_num(old_bus); - break; -#endif case CVMX_GPIO_PIN_OCTEON: value = gpio_get_value(pin); break; @@ -881,18 +858,6 @@ int octeon_fdt_set_gpio(const void *fdt, int phandle, int pin, int val) } return pcf957x_set_val(bus, addr, 1 << pin, val << pin); #endif -#ifdef CONFIG_PCA9698 - case CVMX_GPIO_PIN_PCA9698: - if (octeon_fdt_get_i2c_bus_addr(fdt, node, &bus, &addr)) { - printf("%s: Could not get gpio bus and/or address\n", __func__); - return -1; - } - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(bus); - rc = pca9698_set_value(addr, pin, val); - i2c_set_bus_num(old_bus); - return rc; -#endif case CVMX_GPIO_PIN_OCTEON: return gpio_set_value(pin, val); default: @@ -951,13 +916,7 @@ int octeon_fdt_get_gpio_info(int fdt_node, enum octeon_gpio_type *type, *type = GPIO_TYPE_PCA953X; } #endif -#ifdef CONFIG_PCA9698 - if (!octeon_fdt_node_check_compatible(fdt, fdt_node, pca9698_gpio_list)) { - debug("%s: Found PCA9698 compatible GPIO", __func__); - *type = GPIO_TYPE_PCA9698; - } -#endif -#if defined(CONFIG_PCA953X) || defined(CONFIG_PCA9698) || \ +#if defined(CONFIG_PCA953X) || \ defined(CONFIG_PCA9555) || defined(CONFIG_PCA9554) if (!i2c_addr || !i2c_bus) { printf("%s: Error: i2c_addr or i2c_bus is NULL\n", __func__); diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 066d7f408e0..bb819dcbb6c 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -34,7 +34,6 @@ obj-y += ticks.o endif obj-y += reloc.o -obj-$(CONFIG_BAT_RW) += bat_rw.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o diff --git a/arch/powerpc/lib/bat_rw.c b/arch/powerpc/lib/bat_rw.c deleted file mode 100644 index 24dd30615bd..00000000000 --- a/arch/powerpc/lib/bat_rw.c +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - */ - -#include <common.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/io.h> -#include <linux/compiler.h> - -#ifdef CONFIG_ADDR_MAP -#include <addr_map.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) -{ - __maybe_unused int batn = -1; - - sync(); - - switch (bat) { - case DBAT0: - mtspr (DBAT0L, lower); - mtspr (DBAT0U, upper); - batn = 0; - break; - case IBAT0: - mtspr (IBAT0L, lower); - mtspr (IBAT0U, upper); - break; - case DBAT1: - mtspr (DBAT1L, lower); - mtspr (DBAT1U, upper); - batn = 1; - break; - case IBAT1: - mtspr (IBAT1L, lower); - mtspr (IBAT1U, upper); - break; - case DBAT2: - mtspr (DBAT2L, lower); - mtspr (DBAT2U, upper); - batn = 2; - break; - case IBAT2: - mtspr (IBAT2L, lower); - mtspr (IBAT2U, upper); - break; - case DBAT3: - mtspr (DBAT3L, lower); - mtspr (DBAT3U, upper); - batn = 3; - break; - case IBAT3: - mtspr (IBAT3L, lower); - mtspr (IBAT3U, upper); - break; -#ifdef CONFIG_HIGH_BATS - case DBAT4: - mtspr (DBAT4L, lower); - mtspr (DBAT4U, upper); - batn = 4; - break; - case IBAT4: - mtspr (IBAT4L, lower); - mtspr (IBAT4U, upper); - break; - case DBAT5: - mtspr (DBAT5L, lower); - mtspr (DBAT5U, upper); - batn = 5; - break; - case IBAT5: - mtspr (IBAT5L, lower); - mtspr (IBAT5U, upper); - break; - case DBAT6: - mtspr (DBAT6L, lower); - mtspr (DBAT6U, upper); - batn = 6; - break; - case IBAT6: - mtspr (IBAT6L, lower); - mtspr (IBAT6U, upper); - break; - case DBAT7: - mtspr (DBAT7L, lower); - mtspr (DBAT7U, upper); - batn = 7; - break; - case IBAT7: - mtspr (IBAT7L, lower); - mtspr (IBAT7U, upper); - break; -#endif - default: - return (-1); - } - -#ifdef CONFIG_ADDR_MAP - if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) { - phys_size_t size; - if (!BATU_VALID(upper)) - size = 0; - else - size = BATU_SIZE(upper); - addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), - size, batn); - } -#endif - - sync(); - isync(); - - return (0); -} - -int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) -{ - unsigned long register u; - unsigned long register l; - - switch (bat) { - case DBAT0: - l = mfspr (DBAT0L); - u = mfspr (DBAT0U); - break; - case IBAT0: - l = mfspr (IBAT0L); - u = mfspr (IBAT0U); - break; - case DBAT1: - l = mfspr (DBAT1L); - u = mfspr (DBAT1U); - break; - case IBAT1: - l = mfspr (IBAT1L); - u = mfspr (IBAT1U); - break; - case DBAT2: - l = mfspr (DBAT2L); - u = mfspr (DBAT2U); - break; - case IBAT2: - l = mfspr (IBAT2L); - u = mfspr (IBAT2U); - break; - case DBAT3: - l = mfspr (DBAT3L); - u = mfspr (DBAT3U); - break; - case IBAT3: - l = mfspr (IBAT3L); - u = mfspr (IBAT3U); - break; -#ifdef CONFIG_HIGH_BATS - case DBAT4: - l = mfspr (DBAT4L); - u = mfspr (DBAT4U); - break; - case IBAT4: - l = mfspr (IBAT4L); - u = mfspr (IBAT4U); - break; - case DBAT5: - l = mfspr (DBAT5L); - u = mfspr (DBAT5U); - break; - case IBAT5: - l = mfspr (IBAT5L); - u = mfspr (IBAT5U); - break; - case DBAT6: - l = mfspr (DBAT6L); - u = mfspr (DBAT6U); - break; - case IBAT6: - l = mfspr (IBAT6L); - u = mfspr (IBAT6U); - break; - case DBAT7: - l = mfspr (DBAT7L); - u = mfspr (DBAT7U); - break; - case IBAT7: - l = mfspr (IBAT7L); - u = mfspr (IBAT7U); - break; -#endif - default: - return (-1); - } - - *upper = u; - *lower = l; - - return (0); -} - -void print_bats(void) -{ - printf("BAT registers:\n"); - - printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L)); - printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U)); - printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L)); - printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U)); - printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L)); - printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U)); - printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L)); - printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U)); - printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L)); - printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U)); - printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L)); - printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U)); - printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L)); - printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U)); - printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L)); - printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U)); - -#ifdef CONFIG_HIGH_BATS - printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L)); - printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U)); - printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L)); - printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U)); - printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L)); - printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U)); - printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L)); - printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U)); - printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L)); - printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U)); - printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L)); - printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U)); - printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L)); - printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U)); - printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L)); - printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U)); -#endif -} diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 1284ef390b5..2d184c5f652 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -44,8 +44,6 @@ cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \ -Wl,--no-whole-archive \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections) -CONFIG_ARCH_DEVICE_TREE := sandbox - ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64)) EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds EFI_TARGET := --target=efi-app-x86_64 diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h index 5d79d0ec58e..18b95ff5cfb 100644 --- a/arch/sh/include/asm/pci.h +++ b/arch/sh/include/asm/pci.h @@ -13,8 +13,6 @@ #include <pci.h> #if defined(CONFIG_SH7751_PCI) int pci_sh7751_init(struct pci_controller *hose); -#elif defined(CONFIG_SH7780_PCI) -int pci_sh7780_init(struct pci_controller *hose); #else #error "Not support PCI." #endif diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile b/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile index 5914796628d..f73f35cd664 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile @@ -1,8 +1,4 @@ obj-y += ddr.o obj-y += lpddr4_timing_ff020008.o obj-y += lpddr4_timing_ff000110.o -ifdef CONFIG_TARGET_MCM_IMX8M_MINI -obj-y += lpddr4_timing_01061010.o -else obj-y += lpddr4_timing_01061010.1_2.o -endif diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile index 8187c8db22e..fe043d517f2 100644 --- a/board/davinci/da8xxevm/Makefile +++ b/board/davinci/da8xxevm/Makefile @@ -5,6 +5,5 @@ # # Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> -obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o obj-$(CONFIG_TARGET_OMAPL138_LCDK) += omapl138_lcdk.o diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index cc1371867d8..b4faf6f9e0a 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -29,7 +29,6 @@ endif obj-$(CONFIG_FSL_CADMUS) += cadmus.o obj-$(CONFIG_FSL_VIA) += cds_via.o obj-$(CONFIG_FMAN_ENET) += fman.o -obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o endif @@ -37,7 +36,6 @@ obj-$(I2C_COMMON) += i2c_common.o obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o obj-$(CONFIG_$(SPL_)VID) += vid.o obj-$(CONFIG_FSL_QIXIS) += qixis.o -obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o endif @@ -53,14 +51,9 @@ endif obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o -obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o -obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o -obj-$(CONFIG_P2020DS) += ics307_clk.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o -obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o -obj-$(CONFIG_ZM7300) += zm7300.o ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o endif @@ -78,7 +71,6 @@ obj-$(CONFIG_EMC2305) += emc2305.o obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ obj-$(CONFIG_TARGET_P3041DS) += p_corenet/ obj-$(CONFIG_TARGET_P4080DS) += p_corenet/ -obj-$(CONFIG_TARGET_P5020DS) += p_corenet/ obj-$(CONFIG_TARGET_P5040DS) += p_corenet/ obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c deleted file mode 100644 index 7096b107e54..00000000000 --- a/board/freescale/common/pixis.c +++ /dev/null @@ -1,470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2006,2010 Freescale Semiconductor - * Jeff Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -#include <common.h> -#include <command.h> -#include <asm/io.h> - -#define pixis_base (u8 *)PIXIS_BASE - -/* - * Simple board reset. - */ -void pixis_reset(void) -{ - out_8(pixis_base + PIXIS_RST, 0); - - while (1); -} - -/* - * Per table 27, page 58 of MPC8641HPCN spec. - */ -static int set_px_sysclk(unsigned long sysclk) -{ - u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; - - switch (sysclk) { - case 33: - sysclk_s = 0x04; - sysclk_r = 0x04; - sysclk_v = 0x07; - sysclk_aux = 0x00; - break; - case 40: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x20; - sysclk_aux = 0x01; - break; - case 50: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x2A; - sysclk_aux = 0x02; - break; - case 66: - sysclk_s = 0x01; - sysclk_r = 0x04; - sysclk_v = 0x04; - sysclk_aux = 0x03; - break; - case 83: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x04; - break; - case 100: - sysclk_s = 0x01; - sysclk_r = 0x1F; - sysclk_v = 0x5C; - sysclk_aux = 0x05; - break; - case 134: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x3B; - sysclk_aux = 0x06; - break; - case 166: - sysclk_s = 0x06; - sysclk_r = 0x1F; - sysclk_v = 0x4B; - sysclk_aux = 0x07; - break; - default: - printf("Unsupported SYSCLK frequency.\n"); - return 0; - } - - vclkh = (sysclk_s << 5) | sysclk_r; - vclkl = sysclk_v; - - out_8(pixis_base + PIXIS_VCLKH, vclkh); - out_8(pixis_base + PIXIS_VCLKL, vclkl); - - out_8(pixis_base + PIXIS_AUX, sysclk_aux); - - return 1; -} - -/* Set the CFG_SYSPLL bits - * - * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if - * read_from_px_regs() is called. - */ -static int set_px_mpxpll(unsigned long mpxpll) -{ - switch (mpxpll) { - case 2: - case 4: - case 6: - case 8: - case 10: - case 12: - case 14: - case 16: - clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll); - return 1; - } - - printf("Unsupported MPXPLL ratio.\n"); - return 0; -} - -static int set_px_corepll(unsigned long corepll) -{ - u8 val; - - switch (corepll) { - case 20: - val = 0x08; - break; - case 25: - val = 0x0C; - break; - case 30: - val = 0x10; - break; - case 35: - val = 0x1C; - break; - case 40: - val = 0x14; - break; - case 45: - val = 0x0E; - break; - default: - printf("Unsupported COREPLL ratio.\n"); - return 0; - } - - clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val); - return 1; -} - -#ifndef CFG_SYS_PIXIS_VCFGEN0_ENABLE -#define CFG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C -#endif - -/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values - * - * The PIXIS can be programmed to look at either the on-board dip switches - * or various other PIXIS registers to determine the values for COREPLL, - * MPXPLL, and SYSCLK. - * - * CFG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0 - * register that tells the pixis to use the various PIXIS register. - */ -static void read_from_px_regs(int set) -{ - u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); - - if (set) - tmp = tmp | CFG_SYS_PIXIS_VCFGEN0_ENABLE; - else - tmp = tmp & ~CFG_SYS_PIXIS_VCFGEN0_ENABLE; - - out_8(pixis_base + PIXIS_VCFGEN0, tmp); -} - -/* CFG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1 - * register that tells the pixis to use the PX_VBOOT[LBMAP] register. - */ -#ifndef CFG_SYS_PIXIS_VBOOT_ENABLE -#define CFG_SYS_PIXIS_VBOOT_ENABLE 0x04 -#endif - -/* Configure the source of the boot location - * - * The PIXIS can be programmed to look at either the on-board dip switches - * or the PX_VBOOT[LBMAP] register to determine where we should boot. - * - * If we want to boot from the alternate boot bank, we need to tell the PIXIS - * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead. - */ -static void read_from_px_regs_altbank(int set) -{ - u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); - - if (set) - tmp = tmp | CFG_SYS_PIXIS_VBOOT_ENABLE; - else - tmp = tmp & ~CFG_SYS_PIXIS_VBOOT_ENABLE; - - out_8(pixis_base + PIXIS_VCFGEN1, tmp); -} - -/* CFG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that - * tells the PIXIS what the alternate flash bank is. - * - * Note that it's not really a mask. It contains the actual LBMAP bits that - * must be set to select the alternate bank. This code assumes that the - * primary bank has these bits set to 0, and the alternate bank has these - * bits set to 1. - */ -#ifndef CFG_SYS_PIXIS_VBOOT_MASK -#define CFG_SYS_PIXIS_VBOOT_MASK (0x40) -#endif - -/* Tell the PIXIS to boot from the default flash bank - * - * Program the default flash bank into the VBOOT register. This register is - * used only if PX_VCFGEN1[FLASH]=1. - */ -static void clear_altbank(void) -{ - clrbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK); -} - -/* Tell the PIXIS to boot from the alternate flash bank - * - * Program the alternate flash bank into the VBOOT register. This register is - * used only if PX_VCFGEN1[FLASH]=1. - */ -static void set_altbank(void) -{ - setbits_8(pixis_base + PIXIS_VBOOT, CFG_SYS_PIXIS_VBOOT_MASK); -} - -/* Reset the board with watchdog disabled. - * - * This respects the altbank setting. - */ -static void set_px_go(void) -{ - /* Disable the VELA sequencer and watchdog */ - clrbits_8(pixis_base + PIXIS_VCTL, 9); - - /* Reboot by starting the VELA sequencer */ - setbits_8(pixis_base + PIXIS_VCTL, 0x1); - - while (1); -} - -/* Reset the board with watchdog enabled. - * - * This respects the altbank setting. - */ -static void set_px_go_with_watchdog(void) -{ - /* Disable the VELA sequencer */ - clrbits_8(pixis_base + PIXIS_VCTL, 1); - - /* Enable the watchdog and reboot by starting the VELA sequencer */ - setbits_8(pixis_base + PIXIS_VCTL, 0x9); - - while (1); -} - -/* Disable the watchdog - * - */ -static int pixis_disable_watchdog_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - /* Disable the VELA sequencer and the watchdog */ - clrbits_8(pixis_base + PIXIS_VCTL, 9); - - return 0; -} - -U_BOOT_CMD( - diswd, 1, 0, pixis_disable_watchdog_cmd, - "Disable watchdog timer", - "" -); - -/* - * This function takes the non-integral cpu:mpx pll ratio - * and converts it to an integer that can be used to assign - * FPGA register values. - * input: strptr i.e. argv[2] - */ -static unsigned long strfractoint(char *strptr) -{ - int i, j; - int mulconst; - int no_dec = 0; - unsigned long intval = 0, decval = 0; - char intarr[3], decarr[3]; - - /* Assign the integer part to intarr[] - * If there is no decimal point i.e. - * if the ratio is an integral value - * simply create the intarr. - */ - i = 0; - while (strptr[i] != '.') { - if (strptr[i] == 0) { - no_dec = 1; - break; - } - intarr[i] = strptr[i]; - i++; - } - - intarr[i] = '\0'; - - if (no_dec) { - /* Currently needed only for single digit corepll ratios */ - mulconst = 10; - decval = 0; - } else { - j = 0; - i++; /* Skipping the decimal point */ - while ((strptr[i] >= '0') && (strptr[i] <= '9')) { - decarr[j] = strptr[i]; - i++; - j++; - } - - decarr[j] = '\0'; - - mulconst = 1; - for (i = 0; i < j; i++) - mulconst *= 10; - decval = dectoul(decarr, NULL); - } - - intval = dectoul(intarr, NULL); - intval = intval * mulconst; - - return intval + decval; -} - -static int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned int i; - char *p_cf = NULL; - char *p_cf_sysclk = NULL; - char *p_cf_corepll = NULL; - char *p_cf_mpxpll = NULL; - char *p_altbank = NULL; - char *p_wd = NULL; - int unknown_param = 0; - - /* - * No args is a simple reset request. - */ - if (argc <= 1) { - pixis_reset(); - /* not reached */ - } - - for (i = 1; i < argc; i++) { - if (strcmp(argv[i], "cf") == 0) { - p_cf = argv[i]; - if (i + 3 >= argc) { - break; - } - p_cf_sysclk = argv[i+1]; - p_cf_corepll = argv[i+2]; - p_cf_mpxpll = argv[i+3]; - i += 3; - continue; - } - - if (strcmp(argv[i], "altbank") == 0) { - p_altbank = argv[i]; - continue; - } - - if (strcmp(argv[i], "wd") == 0) { - p_wd = argv[i]; - continue; - } - - unknown_param = 1; - } - - /* - * Check that cf has all required parms - */ - if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll)) - || unknown_param) { -#ifdef CONFIG_SYS_LONGHELP - puts(cmdtp->help); - putc('\n'); -#endif - return 1; - } - - /* - * PIXIS seems to be sensitive to the ordering of - * the registers that are touched. - */ - read_from_px_regs(0); - - if (p_altbank) - read_from_px_regs_altbank(0); - - clear_altbank(); - - /* - * Clock configuration specified. - */ - if (p_cf) { - unsigned long sysclk; - unsigned long corepll; - unsigned long mpxpll; - - sysclk = dectoul(p_cf_sysclk, NULL); - corepll = strfractoint(p_cf_corepll); - mpxpll = dectoul(p_cf_mpxpll, NULL); - - if (!(set_px_sysclk(sysclk) - && set_px_corepll(corepll) - && set_px_mpxpll(mpxpll))) { -#ifdef CONFIG_SYS_LONGHELP - puts(cmdtp->help); - putc('\n'); -#endif - return 1; - } - read_from_px_regs(1); - } - - /* - * Altbank specified - * - * NOTE CHANGE IN BEHAVIOR: previous code would default - * to enabling watchdog if altbank is specified. - * Now the watchdog must be enabled explicitly using 'wd'. - */ - if (p_altbank) { - set_altbank(); - read_from_px_regs_altbank(1); - } - - /* - * Reset with watchdog specified. - */ - if (p_wd) - set_px_go_with_watchdog(); - else - set_px_go(); - - /* - * Shouldn't be reached. - */ - return 0; -} - - -U_BOOT_CMD( - pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, - "Reset the board using the FPGA sequencer", - " pixis_reset\n" - " pixis_reset [altbank]\n" - " pixis_reset altbank wd\n" - " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n" - " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>" -); diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h deleted file mode 100644 index f19e85cb1c9..00000000000 --- a/board/freescale/common/pixis.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - */ -#ifndef __PIXIS_H_ -#define __PIXIS_H_ 1 - -/* PIXIS register set. */ -#if defined(CONFIG_TARGET_MPC8536DS) -typedef struct pixis { - u8 id; - u8 ver; - u8 pver; - u8 csr; - u8 rst; - u8 rst2; - u8 aux1; - u8 spd; - u8 aux2; - u8 csr2; - u8 watch; - u8 led; - u8 pwr; - u8 res[3]; - u8 vctl; - u8 vstat; - u8 vcfgen0; - u8 vcfgen1; - u8 vcore0; - u8 res1; - u8 vboot; - u8 vspeed[3]; - u8 sclk[3]; - u8 dclk[3]; - u8 i2cdacr; - u8 vcoreacc[4]; - u8 vcorecnt[3]; - u8 vcoremax[2]; - u8 vplatacc[4]; - u8 vplatcnt[3]; - u8 vplatmax[2]; - u8 vtempacc[4]; - u8 vtempcnt[3]; - u8 vtempmax[2]; - u8 res2[4]; -} __attribute__ ((packed)) pixis_t; -#else -#error Need to define pixis_t for this board -#endif - -/* Pointer to the PIXIS register set */ -#define pixis ((pixis_t *)PIXIS_BASE) - -#endif /* __PIXIS_H_ */ diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c deleted file mode 100644 index 162c8a954f0..00000000000 --- a/board/freescale/common/pq-mds-pib.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * Tony Li <tony.li@freescale.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation; - */ - -#include <common.h> -#include <i2c.h> -#include <asm/io.h> - -#include "pq-mds-pib.h" - -int pib_init(void) -{ - u8 val8; - u8 orig_i2c_bus; - - /* Switch temporarily to I2C bus #2 */ - orig_i2c_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - val8 = 0; -#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE) - /* Assign PIB PMC slot to desired PCI bus */ - i2c_write(0x23, 0x6, 1, &val8, 1); - i2c_write(0x23, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x23, 0x2, 1, &val8, 1); - i2c_write(0x23, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x26, 0x6, 1, &val8, 1); - val8 = 0x34; - i2c_write(0x26, 0x7, 1, &val8, 1); - val8 = 0xf3; /* PMC1, PMC2, PMC3 slot to PCI bus */ - i2c_write(0x26, 0x2, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x26, 0x3, 1, &val8, 1); - - val8 = 0; - i2c_write(0x27, 0x6, 1, &val8, 1); - i2c_write(0x27, 0x7, 1, &val8, 1); - val8 = 0xff; - i2c_write(0x27, 0x2, 1, &val8, 1); - val8 = 0xef; - i2c_write(0x27, 0x3, 1, &val8, 1); - - eieio(); - - printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n"); -#endif - - /* Reset to original I2C bus */ - i2c_set_bus_num(orig_i2c_bus); - return 0; -} diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h deleted file mode 100644 index 67066fd118d..00000000000 --- a/board/freescale/common/pq-mds-pib.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation; - */ - -extern int pib_init(void); diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c deleted file mode 100644 index c51f3c5aca2..00000000000 --- a/board/freescale/common/vsc3316_3308.c +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include "vsc3316_3308.h" -#include <log.h> - -#define REVISION_ID_REG 0x7E -#define INTERFACE_MODE_REG 0x79 -#define CURRENT_PAGE_REGISTER 0x7F -#define CONNECTION_CONFIG_PAGE 0x00 -#define INPUT_STATE_REG 0x13 -#define GLOBAL_INPUT_ISE1 0x51 -#define GLOBAL_INPUT_ISE2 0x52 -#define GLOBAL_INPUT_GAIN 0x53 -#define GLOBAL_INPUT_LOS 0x55 -#define GLOBAL_OUTPUT_PE1 0x56 -#define GLOBAL_OUTPUT_PE2 0x57 -#define GLOBAL_OUTPUT_LEVEL 0x58 -#define GLOBAL_OUTPUT_TERMINATION 0x5A -#define GLOBAL_CORE_CNTRL 0x5D -#define OUTPUT_MODE_PAGE 0x23 -#define CORE_CONTROL_PAGE 0x25 -#define CORE_CONFIG_REG 0x75 - -int vsc_if_enable(unsigned int vsc_addr) -{ - u8 data; - - debug("VSC:Configuring VSC at I2C address 0x%2x" - " for 2-wire interface\n", vsc_addr); - - /* enable 2-wire Serial InterFace (I2C) */ - data = 0x02; -#if CONFIG_IS_ENABLED(DM_I2C) - int ret, bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - return dm_i2c_write(dev, INTERFACE_MODE_REG, &data, 1); -#else - return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); -#endif -} - -int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3316 at I2C address 0x%2x" - " for Tx\n", vsc_addr); - -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Configuring the required input of the switch */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 0x80); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); - -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Configuring the required input of the switch */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 0x80); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - - vsc_wp_config(vsc_addr); - - return 0; -} - -#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR -int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n", - vsc_addr); - -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Configure Global Input ISE */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0); - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0); - - /* Configure Tx/Rx Global Output PE1 */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE1, 0); - - /* Configure Tx/Rx Global Output PE2 */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_PE2, 0); - - /* Configure Tx/Rx Global Input GAIN */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_GAIN, 0x3F); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0xE0); - - /* Setting Global output termination */ - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_TERMINATION, 0); - - /* Configure Tx/Rx Global Output level */ - if (vsc_addr == VSC3308_TX_ADDRESS) - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 4); - else - dm_i2c_reg_write(dev, GLOBAL_OUTPUT_LEVEL, 2); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning off all the required input of the switch */ - for (i = 0; i < num_con; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - dm_i2c_reg_write(dev, 2, 0); - dm_i2c_reg_write(dev, 3, 0); - } else { - dm_i2c_reg_write(dev, 0, 0); - dm_i2c_reg_write(dev, 1, 0); - } - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn off the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - dm_i2c_reg_write(dev, 0, 0); - dm_i2c_reg_write(dev, 1, 0); - } else { - dm_i2c_reg_write(dev, 3, 0); - dm_i2c_reg_write(dev, 4, 0); - } - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Configure Global Input ISE */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0); - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0); - - /* Configure Tx/Rx Global Output PE1 */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0); - - /* Configure Tx/Rx Global Output PE2 */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0); - - /* Configure Tx/Rx Global Input GAIN */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0); - - /* Setting Global output termination */ - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0); - - /* Configure Tx/Rx Global Output level */ - if (vsc_addr == VSC3308_TX_ADDRESS) - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4); - else - i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning off all the required input of the switch */ - for (i = 0; i < num_con; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - i2c_reg_write(vsc_addr, 2, 0); - i2c_reg_write(vsc_addr, 3, 0); - } else { - i2c_reg_write(vsc_addr, 0, 0); - i2c_reg_write(vsc_addr, 1, 0); - } - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn off the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 1); - - /* only turn on specific Tx/Rx requested by the XFI erratum */ - if (vsc_addr == VSC3308_TX_ADDRESS) { - i2c_reg_write(vsc_addr, 0, 0); - i2c_reg_write(vsc_addr, 1, 0); - } else { - i2c_reg_write(vsc_addr, 3, 0); - i2c_reg_write(vsc_addr, 4, 0); - } - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - vsc_wp_config(vsc_addr); - - return 0; -} -#endif - -int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], - unsigned int num_con) -{ - unsigned int i; - u8 rev_id = 0; - int ret; - - debug("VSC:Initializing VSC3308 at I2C address 0x%x" - " for Tx\n", vsc_addr); -#if CONFIG_IS_ENABLED(DM_I2C) - int bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, REVISION_ID_REG, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output - */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], con_arr[i][0]); - - /*Configure Global Input ISE and gain */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE1, 0x12); - dm_i2c_reg_write(dev, GLOBAL_INPUT_ISE2, 0x12); - - /* input state - page 0x13 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning ON the required input of the switch */ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][0], 0); - - /* Setting Global Input LOS threshold value */ - dm_i2c_reg_write(dev, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - dm_i2c_reg_write(dev, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - dm_i2c_reg_write(dev, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - dm_i2c_reg_write(dev, GLOBAL_CORE_CNTRL, 0); -#else - ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1); - if (ret < 0) { - printf("VSC:0x%x could not read REV_ID from device.\n", - vsc_addr); - return ret; - } - - if (rev_id != 0xab) { - printf("VSC: device at address 0x%x is not VSC3316/3308.\n", - vsc_addr); - return -ENODEV; - } - - ret = vsc_if_enable(vsc_addr); - if (ret) { - printf("VSC:0x%x could not configured for 2-wire I/F.\n", - vsc_addr); - return ret; - } - - /* config connections - page 0x00 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE); - - /* Making crosspoint connections, by connecting required - * input to output */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]); - - /*Configure Global Input ISE and gain */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12); - i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12); - - /* input state - page 0x13 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG); - /* Turning ON the required input of the switch */ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][0], 0); - - /* Setting Global Input LOS threshold value */ - i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60); - - /* config output mode - page 0x23 */ - i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE); - /* Turn ON the Output driver correspond to required output*/ - for (i = 0; i < num_con ; i++) - i2c_reg_write(vsc_addr, con_arr[i][1], 0); - - /* configure global core control register, Turn on Global core power */ - i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0); -#endif - vsc_wp_config(vsc_addr); - - return 0; -} - -void vsc_wp_config(unsigned int vsc_addr) -{ - debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr); - - /* For new crosspoint configuration to occur, WP bit of - * CORE_CONFIG_REG should be set 1 and then reset to 0 */ -#if CONFIG_IS_ENABLED(DM_I2C) - int ret, bus_num = 0; - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, vsc_addr, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; - } - - dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x01); - dm_i2c_reg_write(dev, CORE_CONFIG_REG, 0x0); -#else - i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01); - i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0); -#endif -} diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c deleted file mode 100644 index e8c2fc85c84..00000000000 --- a/board/freescale/common/zm7300.c +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* Power-One ZM7300 DPM */ -#include "zm7300.h" -#include <log.h> - -#define DPM_WP 0x96 -#define WRP_OPCODE 0x01 -#define WRM_OPCODE 0x02 -#define RRP_OPCODE 0x11 - -#define DPM_SUCCESS 0x01 -#define DPM_EXEC_FAIL 0x00 - -static const uint16_t hex_to_1_10mv[] = { - 5000, - 5125, - 5250, - 5375, - 5500, - 5625, - 5750, - 5875, - 6000, - 6125, - 6250, - 6375, - 6500, - 6625, - 6750, - 6875, - 7000, - 7125, - 7250, - 7375, - 7500, - 7625, - 7750, - 7875, - 8000, - 8125, - 8250, - 8375, - 8500, - 8625, - 8750, - 8875, - 9000, - 9125, - 9250, - 9375, - 9500, /* 0.95mV */ - 9625, - 9750, - 9875, - 10000, /* 1.0V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 11125, - 11250, - 11375, - 11500, - 11625, - 11750, - 11875, - 12000, - 12125, - 12250, - 12375, - 0, /* reserved */ -}; - - -/* Read Data d from Register r of POL p */ -u8 dpm_rrp(uchar r) -{ - u8 ret[5]; - - ret[0] = RRP_OPCODE; - /* POL is 0 */ - ret[1] = 0; - ret[2] = r; - i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2); - if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */ - debug("RRP_OPCODE returned success data is %x\n", ret[0]); - return ret[0]; - } else { - return -1; - } -} - -/* Write Data d into DPM register r (RAM) */ -int dpm_wrm(u8 r, u8 d) -{ - u8 ret[5]; - - ret[0] = WRM_OPCODE; - ret[1] = r; - ret[2] = d; - i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1); - if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ - debug("WRM_OPCODE returned success data is %x\n", ret[0]); - return ret[0]; - } else { - return -1; - } -} - -/* Write Data d into Register r of POL(s) a */ -int dpm_wrp(u8 r, u8 d) -{ - u8 ret[7]; - - ret[0] = WRP_OPCODE; - /* only POL0 is present */ - ret[1] = 0x01; - ret[2] = 0x00; - ret[3] = 0x00; - ret[4] = 0x00; - ret[5] = r; - ret[6] = d; - i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1); - if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ - debug("WRP_OPCODE returned success data is %x\n", ret[0]); - return 0; - } else { - return -1; - } -} - -/* Uses the DPM command RRP */ -u8 zm_read(uchar reg) -{ - return dpm_rrp(reg); -} - -/* ZM_write -- - Steps: - a. Write data to the register - b. Read data from register and compare to written value - c. Return return_code & voltage_read -*/ -u8 zm_write(u8 reg, u8 data) -{ - u8 d; - - /* write data to register */ - dpm_wrp(reg, data); - - /* read register and compare to written value */ - d = dpm_rrp(reg); - if (d != data) { - printf("zm_write : Comparison register data failed\n"); - return -1; - } - - return d; -} - -/* zm_write_out_voltage - * voltage in 1/10 mV - */ -int zm_write_voltage(int voltage) -{ - u8 reg = 0x7, vid; - uint16_t voltage_read; - u8 ret; - - vid = (voltage - 5000) / ZM_STEP; - - ret = zm_write(reg, vid); - if (ret != -1) { - voltage_read = hex_to_1_10mv[ret]; - debug("voltage set to %dmV\n", voltage_read/10); - return voltage_read; - } - return -1; -} - -/* zm_read_out_voltage - * voltage in 1/10 mV - */ -int zm_read_voltage(void) -{ - u8 reg = 0x7; - u8 ret; - int voltage; - - ret = zm_read(reg); - if (ret != -1) { - voltage = hex_to_1_10mv[ret]; - debug("Voltage read is %dmV\n", voltage/10); - return voltage; - } else { - return -1; - } -} - -int zm_disable_wp() -{ - u8 new_wp_value; - - /* Disable using Write-Protect register 0x96 */ - new_wp_value = 0x8; - if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) { - printf("Disable Write-Protect register failed\n"); - return -1; - } - return 0; -} - -int zm_enable_wp() -{ - u8 orig_wp_value; - orig_wp_value = 0x0; - - /* Enable using Write-Protect register 0x96 */ - if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) { - printf("Enable Write-Protect register failed\n"); - return -1; - } - return 0; -} diff --git a/board/freescale/common/zm7300.h b/board/freescale/common/zm7300.h deleted file mode 100644 index 9ce24afc178..00000000000 --- a/board/freescale/common/zm7300.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __ZM7300_H_ -#define __ZM7300_H 1_ - -#include <common.h> -#include <i2c.h> -#include <errno.h> -#include <asm/io.h> - -#define ZM_STEP 125 -int zm7300_set_voltage(int voltage_1_10mv); -int zm_write_voltage(int voltage); -int zm_read_voltage(void); -int zm_disable_wp(void); -int zm_enable_wp(void); - -#endif /* __ZM7300_H_ */ diff --git a/board/freescale/mx7ulp_evk/Makefile b/board/freescale/mx7ulp_evk/Makefile index 686763d6744..9f33c61f03b 100644 --- a/board/freescale/mx7ulp_evk/Makefile +++ b/board/freescale/mx7ulp_evk/Makefile @@ -2,7 +2,3 @@ # (C) Copyright 2016 Freescale Semiconductor, Inc. obj-y := mx7ulp_evk.o - -extra-$(CONFIG_USE_PLUGIN) := plugin.bin -$(obj)/plugin.bin: $(obj)/plugin.o - $(OBJCOPY) -O binary --gap-fill 0xff $< $@ diff --git a/board/gdsys/a38x/hre.c b/board/gdsys/a38x/hre.c index 2f16a4d3e11..d16233ed78e 100644 --- a/board/gdsys/a38x/hre.c +++ b/board/gdsys/a38x/hre.c @@ -15,7 +15,6 @@ #include <u-boot/sha1.h> #include <asm/byteorder.h> #include <asm/unaligned.h> -#include <pca9698.h> #include "hre.h" diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index dd6d5e69de5..94cbf3c5cc1 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -3,9 +3,8 @@ # (C) Copyright 2007 # Stefan Roese, DENX Software Engineering, sr@denx.de. -obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o -obj-$(CONFIG_CONTROLCENTERD) += dp501.o +obj-$(CONFIG_TARGET_CONTROLCENTERDC) += dp501.o obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o ifdef CONFIG_OSD diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c deleted file mode 100644 index 5ba6613ed56..00000000000 --- a/board/gdsys/common/fpga.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifdef CONFIG_GDSYS_LEGACY_DRIVERS - -#include <common.h> -#include <gdsys_fpga.h> - -#include <asm/io.h> - -int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) -{ - out_le16(reg, data); - - return 0; -} - -int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) -{ - *data = in_le16(reg); - - return 0; -} - -#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 002821916c4..b00accca1be 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -7,4 +7,3 @@ obj-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o obj-$(CONFIG_ARCH_P2020) += fsl_8xxx_clk.o obj-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o obj-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o -obj-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c deleted file mode 100644 index 2d8a57576a6..00000000000 --- a/board/xes/common/actl_nand.c +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * - * This driver support NAND devices which have address lines - * connected as ALE and CLE inputs. - */ - -#include <common.h> -#include <nand.h> -#include <linux/mtd/rawnand.h> -#include <asm/io.h> - -/* - * Hardware specific access to control-lines - */ -static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE | - CONFIG_SYS_NAND_ACTL_ALE | - CONFIG_SYS_NAND_ACTL_NCE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE; - if (ctrl & NAND_NCE) - IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE; - - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = nand_addr_hwcontrol; - nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY; - - return 0; -} diff --git a/cmd/Kconfig b/cmd/Kconfig index b50e14f70a0..c7344ee1f66 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2021,6 +2021,13 @@ config CMD_LED with led on/off/togle/blink. Any LED drivers can be controlled with this command, e.g. led_gpio. +config CMD_INI + bool "ini" + help + Enable the 'ini' command which allows a .ini file to be parsed and + placed into environment variables. Please check the source code for + this as there is no documentation. + config CMD_DATE bool "date" default y if DM_RTC diff --git a/cmd/Makefile b/cmd/Makefile index b03d68d5f9b..36d2daf22a1 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -47,7 +47,6 @@ obj-$(CONFIG_CMD_CONFIG) += config.o obj-$(CONFIG_CMD_CONITRACE) += conitrace.o obj-$(CONFIG_CMD_CONSOLE) += console.o obj-$(CONFIG_CMD_CPU) += cpu.o -obj-$(CONFIG_DATAFLASH_MMC_SELECT) += dataflash_mmc_mux.o obj-$(CONFIG_CMD_DATE) += date.o obj-$(CONFIG_CMD_DEMO) += demo.o obj-$(CONFIG_CMD_DM) += dm.o @@ -108,7 +107,6 @@ obj-$(CONFIG_ID_EEPROM) += mac.o obj-$(CONFIG_CMD_MD5SUM) += md5sum.o obj-$(CONFIG_CMD_MEMORY) += mem.o obj-$(CONFIG_CMD_IO) += io.o -obj-$(CONFIG_CMD_MFSL) += mfsl.o obj-$(CONFIG_CMD_MII) += mii.o obj-$(CONFIG_CMD_MISC) += misc.o obj-$(CONFIG_CMD_MDIO) += mdio.o diff --git a/cmd/dataflash_mmc_mux.c b/cmd/dataflash_mmc_mux.c deleted file mode 100644 index 73876e9464a..00000000000 --- a/cmd/dataflash_mmc_mux.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <command.h> - -static int mmc_nspi (const char *); - -int do_dataflash_mmc_mux(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - switch (argc) { - case 2: /* on / off */ - switch (mmc_nspi (argv[1])) { - case 0: AT91F_SelectSPI (); - break; - case 1: AT91F_SelectMMC (); - break; - } - case 1: /* get status */ - printf ("Mux is configured to be %s\n", - AT91F_GetMuxStatus () ? "MMC" : "SPI"); - return 0; - default: - return CMD_RET_USAGE; - } - return 0; -} - -static int mmc_nspi (const char *s) -{ - if (strcmp (s, "mmc") == 0) { - return 1; - } else if (strcmp (s, "spi") == 0) { - return 0; - } - return -1; -} - -U_BOOT_CMD( - dataflash_mmc_mux, 2, 1, do_dataflash_mmc_mux, - "enable or disable MMC or SPI\n", - "[mmc, spi]\n" - " - enable or disable MMC or SPI" -); diff --git a/cmd/mfsl.c b/cmd/mfsl.c deleted file mode 100644 index 0c78720ec46..00000000000 --- a/cmd/mfsl.c +++ /dev/null @@ -1,387 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK <monstr@monstr.eu> - */ - -/* - * Microblaze FSL support - */ - -#include <common.h> -#include <config.h> -#include <command.h> -#include <asm/asm.h> - -int do_frd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int fslnum; - unsigned int num; - unsigned int blocking; - - if (argc < 2) - return CMD_RET_USAGE; - - fslnum = (unsigned int)hextoul(argv[1], NULL); - blocking = (unsigned int)hextoul(argv[2], NULL); - if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) { - puts ("Bad number of FSL\n"); - return CMD_RET_USAGE; - } - - switch (fslnum) { -#if (XILINX_FSL_NUMBER > 0) - case 0: - switch (blocking) { - case 0: NGET (num, 0); - break; - case 1: NCGET (num, 0); - break; - case 2: GET (num, 0); - break; - case 3: CGET (num, 0); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 1) - case 1: - switch (blocking) { - case 0: NGET (num, 1); - break; - case 1: NCGET (num, 1); - break; - case 2: GET (num, 1); - break; - case 3: CGET (num, 1); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 2) - case 2: - switch (blocking) { - case 0: NGET (num, 2); - break; - case 1: NCGET (num, 2); - break; - case 2: GET (num, 2); - break; - case 3: CGET (num, 2); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 3) - case 3: - switch (blocking) { - case 0: NGET (num, 3); - break; - case 1: NCGET (num, 3); - break; - case 2: GET (num, 3); - break; - case 3: CGET (num, 3); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 4) - case 4: - switch (blocking) { - case 0: NGET (num, 4); - break; - case 1: NCGET (num, 4); - break; - case 2: GET (num, 4); - break; - case 3: CGET (num, 4); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 5) - case 5: - switch (blocking) { - case 0: NGET (num, 5); - break; - case 1: NCGET (num, 5); - break; - case 2: GET (num, 5); - break; - case 3: CGET (num, 5); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 6) - case 6: - switch (blocking) { - case 0: NGET (num, 6); - break; - case 1: NCGET (num, 6); - break; - case 2: GET (num, 6); - break; - case 3: CGET (num, 6); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 7) - case 7: - switch (blocking) { - case 0: NGET (num, 7); - break; - case 1: NCGET (num, 7); - break; - case 2: GET (num, 7); - break; - case 3: CGET (num, 7); - break; - default: - return 2; - } - break; -#endif - default: - return 1; - } - - printf ("%01x: 0x%08x - %s %s read\n", fslnum, num, - blocking < 2 ? "non blocking" : "blocking", - ((blocking == 1) || (blocking == 3)) ? "control" : "data" ); - return 0; -} - -int do_fwr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int fslnum; - unsigned int num; - unsigned int blocking; - - if (argc < 3) - return CMD_RET_USAGE; - - fslnum = (unsigned int)hextoul(argv[1], NULL); - num = (unsigned int)hextoul(argv[2], NULL); - blocking = (unsigned int)hextoul(argv[3], NULL); - if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) - return CMD_RET_USAGE; - - switch (fslnum) { -#if (XILINX_FSL_NUMBER > 0) - case 0: - switch (blocking) { - case 0: NPUT (num, 0); - break; - case 1: NCPUT (num, 0); - break; - case 2: PUT (num, 0); - break; - case 3: CPUT (num, 0); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 1) - case 1: - switch (blocking) { - case 0: NPUT (num, 1); - break; - case 1: NCPUT (num, 1); - break; - case 2: PUT (num, 1); - break; - case 3: CPUT (num, 1); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 2) - case 2: - switch (blocking) { - case 0: NPUT (num, 2); - break; - case 1: NCPUT (num, 2); - break; - case 2: PUT (num, 2); - break; - case 3: CPUT (num, 2); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 3) - case 3: - switch (blocking) { - case 0: NPUT (num, 3); - break; - case 1: NCPUT (num, 3); - break; - case 2: PUT (num, 3); - break; - case 3: CPUT (num, 3); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 4) - case 4: - switch (blocking) { - case 0: NPUT (num, 4); - break; - case 1: NCPUT (num, 4); - break; - case 2: PUT (num, 4); - break; - case 3: CPUT (num, 4); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 5) - case 5: - switch (blocking) { - case 0: NPUT (num, 5); - break; - case 1: NCPUT (num, 5); - break; - case 2: PUT (num, 5); - break; - case 3: CPUT (num, 5); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 6) - case 6: - switch (blocking) { - case 0: NPUT (num, 6); - break; - case 1: NCPUT (num, 6); - break; - case 2: PUT (num, 6); - break; - case 3: CPUT (num, 6); - break; - default: - return 2; - } - break; -#endif -#if (XILINX_FSL_NUMBER > 7) - case 7: - switch (blocking) { - case 0: NPUT (num, 7); - break; - case 1: NCPUT (num, 7); - break; - case 2: PUT (num, 7); - break; - case 3: CPUT (num, 7); - break; - default: - return 2; - } - break; -#endif - default: - return 1; - } - - printf ("%01x: 0x%08x - %s %s write\n", fslnum, num, - blocking < 2 ? "non blocking" : "blocking", - ((blocking == 1) || (blocking == 3)) ? "control" : "data" ); - return 0; - -} - -int do_rspr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int reg = 0; - unsigned int val = 0; - - if (argc < 2) - return CMD_RET_USAGE; - - reg = (unsigned int)hextoul(argv[1], NULL); - val = (unsigned int)hextoul(argv[2], NULL); - switch (reg) { - case 0x1: - if (argc > 2) { - MTS (val, rmsr); - NOP; - MFS (val, rmsr); - } else { - MFS (val, rmsr); - } - puts ("MSR"); - break; - case 0x3: - MFS (val, rear); - puts ("EAR"); - break; - case 0x5: - MFS (val, resr); - puts ("ESR"); - break; - default: - puts ("Unsupported register\n"); - return 1; - } - printf (": 0x%08x\n", val); - return 0; -} - -/***************************************************/ - -U_BOOT_CMD (frd, 3, 1, do_frd, - "read data from FSL", - "- [fslnum [0|1|2|3]]\n" - " 0 - non blocking data read\n" - " 1 - non blocking control read\n" - " 2 - blocking data read\n" - " 3 - blocking control read"); - -U_BOOT_CMD (fwr, 4, 1, do_fwr, - "write data to FSL", - "- [fslnum [0|1|2|3]]\n" - " 0 - non blocking data write\n" - " 1 - non blocking control write\n" - " 2 - blocking data write\n" - " 3 - blocking control write"); - -U_BOOT_CMD (rspr, 3, 1, do_rspr, - "read/write special purpose register", - "- reg_num [write value] read/write special purpose register\n" - " 1 - MSR - Machine status register\n" - " 3 - EAR - Exception address register\n" - " 5 - ESR - Exception status register"); diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 53e6b57b60e..e2a5f0089e9 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -51,7 +51,6 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_ENV_IS_IN_NAND) || \ defined(CONFIG_ENV_IS_IN_NVRAM) || \ defined(CONFIG_ENV_IS_IN_ONENAND) || \ - defined(CONFIG_ENV_IS_IN_SATA) || \ defined(CONFIG_ENV_IS_IN_SPI_FLASH) || \ defined(CONFIG_ENV_IS_IN_REMOTE) || \ defined(CONFIG_ENV_IS_IN_UBI) diff --git a/common/usb_hub.c b/common/usb_hub.c index f7fd12c0450..85c0822d8b7 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -507,11 +507,6 @@ static int usb_scan_port(struct usb_device_scan *usb_scan) debug("port %d enable change, status %x\n", i + 1, portstatus); usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_C_ENABLE); /* - * The following hack causes a ghost device problem - * to Faraday EHCI - */ -#ifndef CONFIG_USB_EHCI_FARADAY - /* * EM interference sometimes causes bad shielded USB * devices to be shutdown by the hub, this hack enables * them again. Works at least with mouse driver @@ -523,7 +518,6 @@ static int usb_scan_port(struct usb_device_scan *usb_scan) i + 1); usb_hub_port_connect_change(dev, i); } -#endif } if (portstatus & USB_PORT_STAT_SUSPEND) { diff --git a/drivers/Makefile b/drivers/Makefile index 83b14ef1fd3..15d19d0c8a3 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -59,7 +59,6 @@ obj-$(CONFIG_SPL_USB_GADGET) += usb/common/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/ obj-$(CONFIG_SPL_WATCHDOG) += watchdog/ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ -obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 4113de230cd..61490d6d8de 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -21,6 +21,12 @@ config FPGA_SOCFPGA This provides common functionality for Gen5 and Arria10 devices. +config FPGA_STRATIX_II + bool "Enable Stratix II FPGA drivers" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Stratix II FPGA-specific driver. + config FPGA_STRATIX_V bool "Enable Stratix V FPGA drivers" depends on FPGA_ALTERA @@ -54,6 +60,12 @@ config FPGA_INTEL_SDM_MAILBOX Enable FPGA driver for writing full bitstream into Intel FPGA devices through SDM (Secure Device Manager) Mailbox. +config FPGA_LATTICE + bool "Enable Lattice FPGA driver" + help + This is used for the lattice FPGAs. Please check the source code as + there is no documentation for this at present. + config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 7235714fcc0..fcd136367ac 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -23,13 +23,11 @@ obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o -obj-$(CONFIG_PCA9698) += pca9698.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o @@ -38,16 +36,13 @@ obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o sandbox_test.o obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o -obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o -obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o obj-$(CONFIG_MPC83XX_SPISEL_BOOT) += mpc83xx_spisel_boot.o obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o -obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o diff --git a/drivers/gpio/adi_gpio2.c b/drivers/gpio/adi_gpio2.c deleted file mode 100644 index d0849c85c3b..00000000000 --- a/drivers/gpio/adi_gpio2.c +++ /dev/null @@ -1,425 +0,0 @@ -/* - * ADI GPIO2 Abstraction Layer - * Support BF54x, BF60x and future processors. - * - * Copyright 2008-2013 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include <common.h> -#include <malloc.h> -#include <linux/bug.h> -#include <linux/errno.h> -#include <asm/gpio.h> - -#define RESOURCE_LABEL_SIZE 16 - -static struct str_ident { - char name[RESOURCE_LABEL_SIZE]; -} str_ident[MAX_RESOURCES]; - -static void gpio_error(unsigned gpio) -{ - printf("adi_gpio2: GPIO %d wasn't requested!\n", gpio); -} - -static void set_label(unsigned short ident, const char *label) -{ - if (label) { - strncpy(str_ident[ident].name, label, - RESOURCE_LABEL_SIZE); - str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; - } -} - -static char *get_label(unsigned short ident) -{ - return *str_ident[ident].name ? str_ident[ident].name : "UNKNOWN"; -} - -static int cmp_label(unsigned short ident, const char *label) -{ - if (label == NULL) - printf("adi_gpio2: please provide none-null label\n"); - - if (label) - return strcmp(str_ident[ident].name, label); - else - return -EINVAL; -} - -#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)] -#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i)) -#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i)) -#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i)) -#define DECLARE_RESERVED_MAP(m, c) unsigned short reserved_##m##_map[c] - -static DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM); -static DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES)); - -inline int check_gpio(unsigned gpio) -{ -#if defined(CONFIG_BF54x) - if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 || - gpio == GPIO_PH14 || gpio == GPIO_PH15 || - gpio == GPIO_PJ14 || gpio == GPIO_PJ15) - return -EINVAL; -#endif - if (gpio >= MAX_GPIOS) - return -EINVAL; - return 0; -} - -static void port_setup(unsigned gpio, unsigned short usage) -{ -#if defined(CONFIG_BF54x) - if (usage == GPIO_USAGE) - gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); - else - gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); -#else - if (usage == GPIO_USAGE) - gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio); - else - gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio); -#endif -} - -inline void portmux_setup(unsigned short per) -{ - u32 pmux; - u16 ident = P_IDENT(per); - u16 function = P_FUNCT2MUX(per); - - pmux = gpio_array[gpio_bank(ident)]->port_mux; - - pmux &= ~(0x3 << (2 * gpio_sub_n(ident))); - pmux |= (function & 0x3) << (2 * gpio_sub_n(ident)); - - gpio_array[gpio_bank(ident)]->port_mux = pmux; -} - -inline u16 get_portmux(unsigned short per) -{ - u32 pmux; - u16 ident = P_IDENT(per); - - pmux = gpio_array[gpio_bank(ident)]->port_mux; - - return pmux >> (2 * gpio_sub_n(ident)) & 0x3; -} - -unsigned short get_gpio_dir(unsigned gpio) -{ - return 0x01 & - (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)); -} - -/*********************************************************** -* -* FUNCTIONS: Peripheral Resource Allocation -* and PortMux Setup -* -* INPUTS/OUTPUTS: -* per Peripheral Identifier -* label String -* -* DESCRIPTION: Peripheral Resource Allocation and Setup API -**************************************************************/ - -int peripheral_request(unsigned short per, const char *label) -{ - unsigned short ident = P_IDENT(per); - - /* - * Don't cares are pins with only one dedicated function - */ - - if (per & P_DONTCARE) - return 0; - - if (!(per & P_DEFINED)) - return -EINVAL; - - BUG_ON(ident >= MAX_RESOURCES); - - /* If a pin can be muxed as either GPIO or peripheral, make - * sure it is not already a GPIO pin when we request it. - */ - if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) { - printf("%s: Peripheral %d is already reserved as GPIO by %s!\n", - __func__, ident, get_label(ident)); - return -EBUSY; - } - - if (unlikely(is_reserved(peri, ident, 1))) { - /* - * Pin functions like AMC address strobes my - * be requested and used by several drivers - */ - - if (!((per & P_MAYSHARE) && - get_portmux(per) == P_FUNCT2MUX(per))) { - /* - * Allow that the identical pin function can - * be requested from the same driver twice - */ - - if (cmp_label(ident, label) == 0) - goto anyway; - - printf("%s: Peripheral %d function %d is already " - "reserved by %s!\n", __func__, ident, - P_FUNCT2MUX(per), get_label(ident)); - return -EBUSY; - } - } - - anyway: - reserve(peri, ident); - - portmux_setup(per); - port_setup(ident, PERIPHERAL_USAGE); - - set_label(ident, label); - - return 0; -} - -int peripheral_request_list(const unsigned short per[], const char *label) -{ - u16 cnt; - int ret; - - for (cnt = 0; per[cnt] != 0; cnt++) { - ret = peripheral_request(per[cnt], label); - - if (ret < 0) { - for (; cnt > 0; cnt--) - peripheral_free(per[cnt - 1]); - - return ret; - } - } - - return 0; -} - -void peripheral_free(unsigned short per) -{ - unsigned short ident = P_IDENT(per); - - if (per & P_DONTCARE) - return; - - if (!(per & P_DEFINED)) - return; - - if (unlikely(!is_reserved(peri, ident, 0))) - return; - - if (!(per & P_MAYSHARE)) - port_setup(ident, GPIO_USAGE); - - unreserve(peri, ident); - - set_label(ident, "free"); -} - -void peripheral_free_list(const unsigned short per[]) -{ - u16 cnt; - for (cnt = 0; per[cnt] != 0; cnt++) - peripheral_free(per[cnt]); -} - -/*********************************************************** -* -* FUNCTIONS: GPIO Driver -* -* INPUTS/OUTPUTS: -* gpio PIO Number between 0 and MAX_GPIOS -* label String -* -* DESCRIPTION: GPIO Driver API -**************************************************************/ - -int gpio_request(unsigned gpio, const char *label) -{ - if (check_gpio(gpio) < 0) - return -EINVAL; - - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) - return 0; - - if (unlikely(is_reserved(gpio, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved by %s!\n", - gpio, get_label(gpio)); - return -EBUSY; - } - if (unlikely(is_reserved(peri, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved as Peripheral " - "by %s!\n", gpio, get_label(gpio)); - return -EBUSY; - } - - reserve(gpio, gpio); - set_label(gpio, label); - - port_setup(gpio, GPIO_USAGE); - - return 0; -} - -int gpio_free(unsigned gpio) -{ - if (check_gpio(gpio) < 0) - return -1; - - if (unlikely(!is_reserved(gpio, gpio, 0))) { - gpio_error(gpio); - return -1; - } - - unreserve(gpio, gpio); - - set_label(gpio, "free"); - - return 0; -} - -#ifdef ADI_SPECIAL_GPIO_BANKS -static DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES)); - -int special_gpio_request(unsigned gpio, const char *label) -{ - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) - return 0; - - if (unlikely(is_reserved(special_gpio, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved by %s!\n", - gpio, get_label(gpio)); - return -EBUSY; - } - if (unlikely(is_reserved(peri, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved as Peripheral " - "by %s!\n", gpio, get_label(gpio)); - - return -EBUSY; - } - - reserve(special_gpio, gpio); - reserve(peri, gpio); - - set_label(gpio, label); - port_setup(gpio, GPIO_USAGE); - - return 0; -} - -void special_gpio_free(unsigned gpio) -{ - if (unlikely(!is_reserved(special_gpio, gpio, 0))) { - gpio_error(gpio); - return; - } - - unreserve(special_gpio, gpio); - unreserve(peri, gpio); - set_label(gpio, "free"); -} -#endif - -static inline void __gpio_direction_input(unsigned gpio) -{ - gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); -#if defined(CONFIG_BF54x) - gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); -#else - gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio); -#endif -} - -int gpio_direction_input(unsigned gpio) -{ - unsigned long flags; - - if (!is_reserved(gpio, gpio, 0)) { - gpio_error(gpio); - return -EINVAL; - } - - local_irq_save(flags); - __gpio_direction_input(gpio); - local_irq_restore(flags); - - return 0; -} - -int gpio_set_value(unsigned gpio, int arg) -{ - if (arg) - gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); - else - gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio); - - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - unsigned long flags; - - if (!is_reserved(gpio, gpio, 0)) { - gpio_error(gpio); - return -EINVAL; - } - - local_irq_save(flags); - -#if defined(CONFIG_BF54x) - gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); -#else - gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio); -#endif - gpio_set_value(gpio, value); - gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); - - local_irq_restore(flags); - - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - return 1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)); -} - -void gpio_labels(void) -{ - int c, gpio; - - for (c = 0; c < MAX_RESOURCES; c++) { - gpio = is_reserved(gpio, c, 1); - if (!check_gpio(c) && gpio) - printf("GPIO_%d:\t%s\tGPIO %s\n", c, get_label(c), - get_gpio_dir(c) ? "OUTPUT" : "INPUT"); - else if (is_reserved(peri, c, 1)) - printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c)); - else - continue; - } -} diff --git a/drivers/gpio/kona_gpio.c b/drivers/gpio/kona_gpio.c deleted file mode 100644 index 29791882a34..00000000000 --- a/drivers/gpio/kona_gpio.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/arch/sysmap.h> - -#define GPIO_BASE (void *)GPIO2_BASE_ADDR - -#define GPIO_PASSWD 0x00a5a501 -#define GPIO_PER_BANK 32 -#define GPIO_MAX_BANK_NUM 8 - -#define GPIO_BANK(gpio) ((gpio) >> 5) -#define GPIO_BITMASK(gpio) \ - (1UL << ((gpio) & (GPIO_PER_BANK - 1))) - -#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) -#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) -#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) -#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) -#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) -#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) -#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) -#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) -#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) - -#define GPIO_GPPWR_OFFSET 0x00000520 - -#define GPIO_GPCTR0_DBR_SHIFT 5 -#define GPIO_GPCTR0_DBR_MASK 0x000001e0 - -#define GPIO_GPCTR0_ITR_SHIFT 3 -#define GPIO_GPCTR0_ITR_MASK 0x00000018 -#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 -#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 -#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 - -#define GPIO_GPCTR0_IOTR_MASK 0x00000001 -#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 -#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 - -int gpio_request(unsigned gpio, const char *label) -{ - unsigned int value, off; - - writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); - off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); - value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); - writel(value, GPIO_BASE + off); - - return 0; -} - -int gpio_free(unsigned gpio) -{ - unsigned int value, off; - - writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); - off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); - value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); - writel(value, GPIO_BASE + off); - - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - u32 val; - - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= ~GPIO_GPCTR0_IOTR_MASK; - val |= GPIO_GPCTR0_IOTR_CMD_INPUT; - writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); - - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - int bank_id = GPIO_BANK(gpio); - int bitmask = GPIO_BITMASK(gpio); - u32 val, off; - - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= ~GPIO_GPCTR0_IOTR_MASK; - val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; - writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); - off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); - - val = readl(GPIO_BASE + off); - val |= bitmask; - writel(val, GPIO_BASE + off); - - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - int bank_id = GPIO_BANK(gpio); - int bitmask = GPIO_BITMASK(gpio); - u32 val, off; - - /* determine the GPIO pin direction */ - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= GPIO_GPCTR0_IOTR_MASK; - - /* read the GPIO bank status */ - off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? - GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); - val = readl(GPIO_BASE + off); - - /* return the specified bit status */ - return !!(val & bitmask); -} - -void gpio_set_value(unsigned gpio, int value) -{ - int bank_id = GPIO_BANK(gpio); - int bitmask = GPIO_BITMASK(gpio); - u32 val, off; - - /* determine the GPIO pin direction */ - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= GPIO_GPCTR0_IOTR_MASK; - - /* this function only applies to output pin */ - if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) { - printf("%s: Cannot set an input pin %d\n", __func__, gpio); - return; - } - - off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); - - val = readl(GPIO_BASE + off); - val |= bitmask; - writel(val, GPIO_BASE + off); -} diff --git a/drivers/gpio/mpc83xx_gpio.c b/drivers/gpio/mpc83xx_gpio.c deleted file mode 100644 index bf693c8d457..00000000000 --- a/drivers/gpio/mpc83xx_gpio.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MPC83xx GPIO handling. - */ - -#include <common.h> -#include <malloc.h> -#include <mpc83xx.h> -#include <asm/gpio.h> -#include <asm/io.h> - -#ifndef CFG_MPC83XX_GPIO_0_INIT_DIRECTION -#define CFG_MPC83XX_GPIO_0_INIT_DIRECTION 0 -#endif -#ifndef CFG_MPC83XX_GPIO_1_INIT_DIRECTION -#define CFG_MPC83XX_GPIO_1_INIT_DIRECTION 0 -#endif -#ifndef CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN -#define CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0 -#endif -#ifndef CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN -#define CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0 -#endif -#ifndef CFG_MPC83XX_GPIO_0_INIT_VALUE -#define CFG_MPC83XX_GPIO_0_INIT_VALUE 0 -#endif -#ifndef CFG_MPC83XX_GPIO_1_INIT_VALUE -#define CFG_MPC83XX_GPIO_1_INIT_VALUE 0 -#endif - -static unsigned int gpio_output_value[MPC83XX_GPIO_CTRLRS]; - -/* - * Generic_GPIO primitives. - */ - -int gpio_request(unsigned gpio, const char *label) -{ - if (gpio >= MAX_NUM_GPIOS) - return -1; - - return 0; -} - -int gpio_free(unsigned gpio) -{ - /* Do not set to input */ - return 0; -} - -/* set GPIO pin 'gpio' as an input */ -int gpio_direction_input(unsigned gpio) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - clrbits_be32(&im->gpio[ctrlr].dir, line_mask); - - return 0; -} - -/* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int gpio_direction_output(unsigned gpio, int value) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - if (value != 0 && value != 1) { - printf("Error: Value parameter must be 0 or 1.\n"); - return -1; - } - - gpio_set_value(gpio, value); - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - /* Make the line output */ - setbits_be32(&im->gpio[ctrlr].dir, line_mask); - - return 0; -} - -/* read GPIO IN value of pin 'gpio' */ -int gpio_get_value(unsigned gpio) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - /* Read the value and mask off the bit */ - return (in_be32(&im->gpio[ctrlr].dat) & line_mask) != 0; -} - -/* write GPIO OUT value to pin 'gpio' */ -int gpio_set_value(unsigned gpio, int value) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - if (value != 0 && value != 1) { - printf("Error: Value parameter must be 0 or 1.\n"); - return -1; - } - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - /* Update the local output buffer soft copy */ - gpio_output_value[ctrlr] = - (gpio_output_value[ctrlr] & ~line_mask) | \ - (value ? line_mask : 0); - - /* Write the output */ - out_be32(&im->gpio[ctrlr].dat, gpio_output_value[ctrlr]); - - return 0; -} - -/* Configure GPIO registers early */ -void mpc83xx_gpio_init_f(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - -#if MPC83XX_GPIO_CTRLRS >= 1 - out_be32(&im->gpio[0].dir, CFG_MPC83XX_GPIO_0_INIT_DIRECTION); - out_be32(&im->gpio[0].odr, CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN); - out_be32(&im->gpio[0].dat, CFG_MPC83XX_GPIO_0_INIT_VALUE); - out_be32(&im->gpio[0].ier, 0xFFFFFFFF); /* Clear all events */ - out_be32(&im->gpio[0].imr, 0); - out_be32(&im->gpio[0].icr, 0); -#endif - -#if MPC83XX_GPIO_CTRLRS >= 2 - out_be32(&im->gpio[1].dir, CFG_MPC83XX_GPIO_1_INIT_DIRECTION); - out_be32(&im->gpio[1].odr, CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN); - out_be32(&im->gpio[1].dat, CFG_MPC83XX_GPIO_1_INIT_VALUE); - out_be32(&im->gpio[1].ier, 0xFFFFFFFF); /* Clear all events */ - out_be32(&im->gpio[1].imr, 0); - out_be32(&im->gpio[1].icr, 0); -#endif -} - -/* Initialize GPIO soft-copies */ -void mpc83xx_gpio_init_r(void) -{ -#if MPC83XX_GPIO_CTRLRS >= 1 - gpio_output_value[0] = CFG_MPC83XX_GPIO_0_INIT_VALUE; -#endif - -#if MPC83XX_GPIO_CTRLRS >= 2 - gpio_output_value[1] = CFG_MPC83XX_GPIO_1_INIT_VALUE; -#endif -} diff --git a/drivers/gpio/pca9698.c b/drivers/gpio/pca9698.c deleted file mode 100644 index 11274c78101..00000000000 --- a/drivers/gpio/pca9698.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -/* - * Driver for NXP's pca9698 40 bit I2C gpio expander - */ - -#include <common.h> -#include <i2c.h> -#include <malloc.h> -#include <linux/errno.h> -#include <pca9698.h> - -/* - * The pca9698 registers - */ - -#define PCA9698_REG_INPUT 0x00 -#define PCA9698_REG_OUTPUT 0x08 -#define PCA9698_REG_POLARITY 0x10 -#define PCA9698_REG_CONFIG 0x18 - -#define PCA9698_BUFFER_SIZE 5 -#define PCA9698_GPIO_COUNT 40 - -static int pca9698_read40(u8 addr, u8 offset, u8 *buffer) -{ - u8 command = offset | 0x80; /* autoincrement */ - - return i2c_read(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); -} - -static int pca9698_write40(u8 addr, u8 offset, u8 *buffer) -{ - u8 command = offset | 0x80; /* autoincrement */ - - return i2c_write(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); -} - -static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value) -{ - unsigned byte = gpio / 8; - unsigned bit = gpio % 8; - - if (value) - buffer[byte] |= (1 << bit); - else - buffer[byte] &= ~(1 << bit); -} - -int pca9698_request(unsigned gpio, const char *label) -{ - if (gpio >= PCA9698_GPIO_COUNT) - return -EINVAL; - - return 0; -} - -void pca9698_free(unsigned gpio) -{ -} - -int pca9698_direction_input(u8 addr, unsigned gpio) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, 1); - - return pca9698_write40(addr, PCA9698_REG_CONFIG, data); -} - -int pca9698_direction_output(u8 addr, unsigned gpio, int value) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_set_value(addr, gpio, value); - if (res) - return res; - - res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, 0); - - return pca9698_write40(addr, PCA9698_REG_CONFIG, data); -} - -int pca9698_get_value(u8 addr, unsigned gpio) -{ - unsigned config_byte = gpio / 8; - unsigned config_bit = gpio % 8; - unsigned value; - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_INPUT, data); - if (res) - return -1; - - value = data[config_byte] & (1 << config_bit); - - return !!value; -} - -int pca9698_set_value(u8 addr, unsigned gpio, int value) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_OUTPUT, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, value); - - return pca9698_write40(addr, PCA9698_REG_OUTPUT, data); -} diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 920aafb91c5..cde0597290c 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -25,7 +25,6 @@ obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o -obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c deleted file mode 100644 index b9b0ff1c39e..00000000000 --- a/drivers/i2c/kona_i2c.c +++ /dev/null @@ -1,728 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.rst for instructions. - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include <i2c.h> - -/* Hardware register offsets and field defintions */ -#define CS_OFFSET 0x00000020 -#define CS_ACK_SHIFT 3 -#define CS_ACK_MASK 0x00000008 -#define CS_ACK_CMD_GEN_START 0x00000000 -#define CS_ACK_CMD_GEN_RESTART 0x00000001 -#define CS_CMD_SHIFT 1 -#define CS_CMD_CMD_NO_ACTION 0x00000000 -#define CS_CMD_CMD_START_RESTART 0x00000001 -#define CS_CMD_CMD_STOP 0x00000002 -#define CS_EN_SHIFT 0 -#define CS_EN_CMD_ENABLE_BSC 0x00000001 - -#define TIM_OFFSET 0x00000024 -#define TIM_PRESCALE_SHIFT 6 -#define TIM_P_SHIFT 3 -#define TIM_NO_DIV_SHIFT 2 -#define TIM_DIV_SHIFT 0 - -#define DAT_OFFSET 0x00000028 - -#define TOUT_OFFSET 0x0000002c - -#define TXFCR_OFFSET 0x0000003c -#define TXFCR_FIFO_FLUSH_MASK 0x00000080 -#define TXFCR_FIFO_EN_MASK 0x00000040 - -#define IER_OFFSET 0x00000044 -#define IER_READ_COMPLETE_INT_MASK 0x00000010 -#define IER_I2C_INT_EN_MASK 0x00000008 -#define IER_FIFO_INT_EN_MASK 0x00000002 -#define IER_NOACK_EN_MASK 0x00000001 - -#define ISR_OFFSET 0x00000048 -#define ISR_RESERVED_MASK 0xffffff60 -#define ISR_CMDBUSY_MASK 0x00000080 -#define ISR_READ_COMPLETE_MASK 0x00000010 -#define ISR_SES_DONE_MASK 0x00000008 -#define ISR_ERR_MASK 0x00000004 -#define ISR_TXFIFOEMPTY_MASK 0x00000002 -#define ISR_NOACK_MASK 0x00000001 - -#define CLKEN_OFFSET 0x0000004c -#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 -#define CLKEN_M_SHIFT 4 -#define CLKEN_N_SHIFT 1 -#define CLKEN_CLKEN_MASK 0x00000001 - -#define FIFO_STATUS_OFFSET 0x00000054 -#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 -#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 - -#define HSTIM_OFFSET 0x00000058 -#define HSTIM_HS_MODE_MASK 0x00008000 -#define HSTIM_HS_HOLD_SHIFT 10 -#define HSTIM_HS_HIGH_PHASE_SHIFT 5 -#define HSTIM_HS_SETUP_SHIFT 0 - -#define PADCTL_OFFSET 0x0000005c -#define PADCTL_PAD_OUT_EN_MASK 0x00000004 - -#define RXFCR_OFFSET 0x00000068 -#define RXFCR_NACK_EN_SHIFT 7 -#define RXFCR_READ_COUNT_SHIFT 0 -#define RXFIFORDOUT_OFFSET 0x0000006c - -/* Locally used constants */ -#define MAX_RX_FIFO_SIZE 64U /* bytes */ -#define MAX_TX_FIFO_SIZE 64U /* bytes */ - -#define I2C_TIMEOUT 100000 /* usecs */ - -#define WAIT_INT_CHK 100 /* usecs */ -#if I2C_TIMEOUT % WAIT_INT_CHK -#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK -#endif - -/* Operations that can be commanded to the controller */ -enum bcm_kona_cmd_t { - BCM_CMD_NOACTION = 0, - BCM_CMD_START, - BCM_CMD_RESTART, - BCM_CMD_STOP, -}; - -/* Internal divider settings for standard mode, fast mode and fast mode plus */ -struct bus_speed_cfg { - uint8_t time_m; /* Number of cycles for setup time */ - uint8_t time_n; /* Number of cycles for hold time */ - uint8_t prescale; /* Prescale divider */ - uint8_t time_p; /* Timing coefficient */ - uint8_t no_div; /* Disable clock divider */ - uint8_t time_div; /* Post-prescale divider */ -}; - -static const struct bus_speed_cfg std_cfg_table[] = { - [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, - [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, - [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, -}; - -struct bcm_kona_i2c_dev { - void *base; - uint speed; - const struct bus_speed_cfg *std_cfg; -}; - -/* Keep these two defines in sync */ -#define DEF_SPD I2C_SPEED_STANDARD_RATE -#define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD - -#define DEF_DEVICE(num) \ -{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} - -static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = { -#ifdef CONFIG_SYS_I2C_BASE0 - DEF_DEVICE(0), -#endif -#ifdef CONFIG_SYS_I2C_BASE1 - DEF_DEVICE(1), -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - DEF_DEVICE(2), -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - DEF_DEVICE(3), -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - DEF_DEVICE(4), -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - DEF_DEVICE(5), -#endif -}; - -#define I2C_M_TEN 0x0010 /* ten bit address */ -#define I2C_M_RD 0x0001 /* read data */ -#define I2C_M_NOSTART 0x4000 /* no restart between msgs */ - -struct kona_i2c_msg { - uint16_t addr; - uint16_t flags; - uint16_t len; - uint8_t *buf; -}; - -static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, - enum bcm_kona_cmd_t cmd) -{ - debug("%s, %d\n", __func__, cmd); - - switch (cmd) { - case BCM_CMD_NOACTION: - writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_START: - writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | - (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_RESTART: - writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | - (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_STOP: - writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - default: - printf("Unknown command %d\n", cmd); - } -} - -static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, - dev->base + CLKEN_OFFSET); -} - -static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, - dev->base + CLKEN_OFFSET); -} - -/* Wait until at least one of the mask bit(s) are set */ -static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev, - unsigned long time_left, - uint32_t mask) -{ - uint32_t status; - - while (time_left) { - status = readl(dev->base + ISR_OFFSET); - - if ((status & ~ISR_RESERVED_MASK) == 0) { - debug("Bogus I2C interrupt 0x%x\n", status); - continue; - } - - /* Must flush the TX FIFO when NAK detected */ - if (status & ISR_NOACK_MASK) - writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, - dev->base + TXFCR_OFFSET); - - writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); - - if (status & mask) { - /* We are done since one of the mask bits are set */ - return time_left; - } - udelay(WAIT_INT_CHK); - time_left -= WAIT_INT_CHK; - } - return 0; -} - -/* Send command to I2C bus */ -static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, - enum bcm_kona_cmd_t cmd) -{ - int rc = 0; - unsigned long time_left = I2C_TIMEOUT; - - /* Send the command */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); - - /* Wait for transaction to finish or timeout */ - time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); - - if (!time_left) { - printf("controller timed out\n"); - rc = -ETIMEDOUT; - } - - /* Clear command */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); - - return rc; -} - -/* Read a single RX FIFO worth of data from the i2c bus */ -static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, - uint8_t *buf, unsigned int len, - unsigned int last_byte_nak) -{ - unsigned long time_left = I2C_TIMEOUT; - - /* Start the RX FIFO */ - writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | - (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET); - - /* Wait for FIFO read to complete */ - time_left = - wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK); - - if (!time_left) { - printf("RX FIFO time out\n"); - return -EREMOTEIO; - } - - /* Read data from FIFO */ - for (; len > 0; len--, buf++) - *buf = readl(dev->base + RXFIFORDOUT_OFFSET); - - return 0; -} - -/* Read any amount of data using the RX FIFO from the i2c bus */ -static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; - unsigned int last_byte_nak = 0; - unsigned int bytes_read = 0; - int rc; - - uint8_t *tmp_buf = msg->buf; - - while (bytes_read < msg->len) { - if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { - last_byte_nak = 1; /* NAK last byte of transfer */ - bytes_to_read = msg->len - bytes_read; - } - - rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, - last_byte_nak); - if (rc < 0) - return -EREMOTEIO; - - bytes_read += bytes_to_read; - tmp_buf += bytes_to_read; - } - - return 0; -} - -/* Write a single byte of data to the i2c bus */ -static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, - unsigned int nak_expected) -{ - unsigned long time_left = I2C_TIMEOUT; - unsigned int nak_received; - - /* Clear pending session done interrupt */ - writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); - - /* Send one byte of data */ - writel(data, dev->base + DAT_OFFSET); - - time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); - - if (!time_left) { - debug("controller timed out\n"); - return -ETIMEDOUT; - } - - nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; - - if (nak_received ^ nak_expected) { - debug("unexpected NAK/ACK\n"); - return -EREMOTEIO; - } - - return 0; -} - -/* Write a single TX FIFO worth of data to the i2c bus */ -static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, - uint8_t *buf, unsigned int len) -{ - int k; - unsigned long time_left = I2C_TIMEOUT; - unsigned int fifo_status; - - /* Write data into FIFO */ - for (k = 0; k < len; k++) - writel(buf[k], (dev->base + DAT_OFFSET)); - - /* Wait for FIFO to empty */ - do { - time_left = - wait_for_int_timeout(dev, time_left, - (IER_FIFO_INT_EN_MASK | - IER_NOACK_EN_MASK)); - fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); - } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); - - /* Check if there was a NAK */ - if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { - printf("unexpected NAK\n"); - return -EREMOTEIO; - } - - /* Check if a timeout occurred */ - if (!time_left) { - printf("completion timed out\n"); - return -EREMOTEIO; - } - - return 0; -} - -/* Write any amount of data using TX FIFO to the i2c bus */ -static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; - unsigned int bytes_written = 0; - int rc; - - uint8_t *tmp_buf = msg->buf; - - while (bytes_written < msg->len) { - if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) - bytes_to_write = msg->len - bytes_written; - - rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, - bytes_to_write); - if (rc < 0) - return -EREMOTEIO; - - bytes_written += bytes_to_write; - tmp_buf += bytes_to_write; - } - - return 0; -} - -/* Send i2c address */ -static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned char addr; - - if (msg->flags & I2C_M_TEN) { - /* First byte is 11110XX0 where XX is upper 2 bits */ - addr = 0xf0 | ((msg->addr & 0x300) >> 7); - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - - /* Second byte is the remaining 8 bits */ - addr = msg->addr & 0xff; - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - - if (msg->flags & I2C_M_RD) { - /* For read, send restart command */ - if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) - return -EREMOTEIO; - - /* Then re-send the first byte with the read bit set */ - addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01; - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - } - } else { - addr = msg->addr << 1; - - if (msg->flags & I2C_M_RD) - addr |= 1; - - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - } - - return 0; -} - -static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, - dev->base + CLKEN_OFFSET); -} - -static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, - dev->base + HSTIM_OFFSET); - - writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | - (dev->std_cfg->time_p << TIM_P_SHIFT) | - (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | - (dev->std_cfg->time_div << TIM_DIV_SHIFT), - dev->base + TIM_OFFSET); - - writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | - (dev->std_cfg->time_n << CLKEN_N_SHIFT) | - CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET); -} - -/* Master transfer function */ -static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg msgs[], int num) -{ - struct kona_i2c_msg *pmsg; - int rc = 0; - int i; - - /* Enable pad output */ - writel(0, dev->base + PADCTL_OFFSET); - - /* Enable internal clocks */ - bcm_kona_i2c_enable_clock(dev); - - /* Send start command */ - rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); - if (rc < 0) { - printf("Start command failed rc = %d\n", rc); - goto xfer_disable_pad; - } - - /* Loop through all messages */ - for (i = 0; i < num; i++) { - pmsg = &msgs[i]; - - /* Send restart for subsequent messages */ - if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { - rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); - if (rc < 0) { - printf("restart cmd failed rc = %d\n", rc); - goto xfer_send_stop; - } - } - - /* Send slave address */ - if (!(pmsg->flags & I2C_M_NOSTART)) { - rc = bcm_kona_i2c_do_addr(dev, pmsg); - if (rc < 0) { - debug("NAK from addr %2.2x msg#%d rc = %d\n", - pmsg->addr, i, rc); - goto xfer_send_stop; - } - } - - /* Perform data transfer */ - if (pmsg->flags & I2C_M_RD) { - rc = bcm_kona_i2c_read_fifo(dev, pmsg); - if (rc < 0) { - printf("read failure\n"); - goto xfer_send_stop; - } - } else { - rc = bcm_kona_i2c_write_fifo(dev, pmsg); - if (rc < 0) { - printf("write failure"); - goto xfer_send_stop; - } - } - } - - rc = num; - -xfer_send_stop: - /* Send a STOP command */ - bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); - -xfer_disable_pad: - /* Disable pad output */ - writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); - - /* Stop internal clock */ - bcm_kona_i2c_disable_clock(dev); - - return rc; -} - -static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev, - uint speed) -{ - switch (speed) { - case I2C_SPEED_STANDARD_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD]; - break; - case I2C_SPEED_FAST_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST]; - break; - case I2C_SPEED_FAST_PLUS_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS]; - break; - default: - printf("%d hz bus speed not supported\n", speed); - return -EINVAL; - } - dev->speed = speed; - return 0; -} - -static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev) -{ - /* Parse bus speed */ - bcm_kona_i2c_assign_bus_speed(dev, dev->speed); - - /* Enable internal clocks */ - bcm_kona_i2c_enable_clock(dev); - - /* Configure internal dividers */ - bcm_kona_i2c_config_timing(dev); - - /* Disable timeout */ - writel(0, dev->base + TOUT_OFFSET); - - /* Enable autosense */ - bcm_kona_i2c_enable_autosense(dev); - - /* Enable TX FIFO */ - writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, - dev->base + TXFCR_OFFSET); - - /* Mask all interrupts */ - writel(0, dev->base + IER_OFFSET); - - /* Clear all pending interrupts */ - writel(ISR_CMDBUSY_MASK | - ISR_READ_COMPLETE_MASK | - ISR_SES_DONE_MASK | - ISR_ERR_MASK | - ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET); - - /* Enable the controller but leave it idle */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); - - /* Disable pad output */ - writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); -} - -/* - * uboot layer - */ -struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap) -{ - return &g_i2c_devs[adap->hwadapnr]; -} - -static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - if (clk_bsc_enable(dev->base)) - return; - - bcm_kona_i2c_init(dev); -} - -static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - /* msg[0] writes the addr, msg[1] reads the data */ - struct kona_i2c_msg msg[2]; - unsigned char msgbuf0[64]; - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - msg[0].addr = chip; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */ - - msg[1].addr = chip; - msg[1].flags = I2C_M_RD; - /* msg[1].buf dest ptr increments each read */ - - msgbuf0[0] = (unsigned char)addr; - msg[1].buf = buffer; - msg[1].len = len; - if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) { - /* Sending 2 i2c messages */ - kona_i2c_init(adap, adap->speed, adap->slaveaddr); - debug("I2C read: I/O error\n"); - return -EIO; - } - return 0; -} - -static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - struct kona_i2c_msg msg[1]; - unsigned char msgbuf0[64]; - unsigned int i; - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - msg[0].addr = chip; - msg[0].flags = 0; - msg[0].len = 2; /* addr byte plus data */ - msg[0].buf = msgbuf0; - - for (i = 0; i < len; i++) { - msgbuf0[0] = addr++; - msgbuf0[1] = buffer[i]; - if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) { - kona_i2c_init(adap, adap->speed, adap->slaveaddr); - debug("I2C write: I/O error\n"); - return -EIO; - } - } - return 0; -} - -static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip) -{ - uchar tmp; - - /* - * read addr 0x0 of the given chip. - */ - return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1); -} - -static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) -{ - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - return bcm_kona_i2c_assign_bus_speed(dev, speed); -} - -/* - * Register kona i2c adapters. Keep the order below so - * that the bus number matches the adapter number. - */ -#define DEF_ADAPTER(num) \ -U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \ - kona_i2c_read, kona_i2c_write, \ - kona_i2c_set_bus_speed, DEF_SPD, 0x00, num) - -#ifdef CONFIG_SYS_I2C_BASE0 - DEF_ADAPTER(0) -#endif -#ifdef CONFIG_SYS_I2C_BASE1 - DEF_ADAPTER(1) -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - DEF_ADAPTER(2) -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - DEF_ADAPTER(3) -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - DEF_ADAPTER(4) -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - DEF_ADAPTER(5) -#endif diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 6cecec41450..3335d9482a2 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -172,14 +172,9 @@ static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr) { int ret = -1; -#if defined(CONFIG_SH73A0) - if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) - goto exit0; -#else if (sh_i2c_set_addr(dev, chip, addr, 1) != 0) goto exit0; udelay(100); -#endif writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); sh_irq_dte(dev); diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index d494639cd95..3b792f2a14c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,7 +29,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += spltest_sandbox.o endif endif -obj-$(CONFIG_ALI152X) += ali512x.o obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o @@ -37,7 +36,6 @@ obj-$(CONFIG_DS4510) += ds4510.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_IIM) += fsl_iim.o -obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o obj-$(CONFIG_GATEWORKS_SC) += gsc.o diff --git a/drivers/misc/ali512x.c b/drivers/misc/ali512x.c deleted file mode 100644 index e714e28bdc3..00000000000 --- a/drivers/misc/ali512x.c +++ /dev/null @@ -1,401 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. - */ - -/* - * Based on sc520cdp.c from rolo 1.6: - *---------------------------------------------------------------------- - * (C) Copyright 2000 - * Sysgo Real-Time Solutions GmbH - * Klein-Winternheim, Germany - *---------------------------------------------------------------------- - */ - -#include <config.h> - -#include <common.h> -#include <asm/io.h> -#include <ali512x.h> - - -/* ALI M5123 Logical device numbers: - * 0 FDC - * 1 unused? - * 2 unused? - * 3 lpt - * 4 UART1 - * 5 UART2 - * 6 RTC - * 7 mouse/kbd - * 8 CIO - */ - -/* - ************************************************************ - * Some access primitives for the ALi chip: * - ************************************************************ - */ - -static void ali_write(u8 index, u8 value) -{ - /* write an arbirary register */ - outb(index, ALI_INDEX); - outb(value, ALI_DATA); -} - -#if 0 -static int ali_read(u8 index) -{ - outb(index, ALI_INDEX); - return inb(ALI_DATA); -} -#endif - -#define ALI_OPEN() \ - outb(0x51, ALI_INDEX); \ - outb(0x23, ALI_INDEX) - - -#define ALI_CLOSE() \ - outb(0xbb, ALI_INDEX) - -/* Select a logical device */ -#define ALI_SELDEV(dev) \ - ali_write(0x07, dev) - - -void ali512x_init(void) -{ - ALI_OPEN(); - - ali_write(0x02, 0x01); /* soft reset */ - ali_write(0x03, 0x03); /* disable access to CIOs */ - ali_write(0x22, 0x00); /* disable direct powerdown */ - ali_write(0x23, 0x00); /* disable auto powerdown */ - ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */ - - ALI_CLOSE(); -} - -void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel) -{ - ALI_OPEN(); - ALI_SELDEV(0); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - ali_write(0x74, dma_channel); - - /* AT mode, no drive swap */ - ali_write(0xf0, 0x08); - ali_write(0xf1, 0x00); - ali_write(0xf2, 0xff); - ali_write(0xf4, 0x00); - } - ALI_CLOSE(); -} - - -void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel) -{ - ALI_OPEN(); - ALI_SELDEV(3); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - ali_write(0x74, dma_channel); - - /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */ - ali_write(0xf0, 0xbc); - /* 12 MHz, Burst DMA in ECP */ - ali_write(0xf1, 0x05); - } - ALI_CLOSE(); - -} - -void ali512x_set_uart(int enabled, int index, u16 io, u8 irq) -{ - ALI_OPEN(); - ALI_SELDEV(index?5:4); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - - ali_write(0xf0, 0x00); - ali_write(0xf1, 0x00); - - /* huh? write 0xf2 twice - a typo in rolo - * or some secret ali errata? Who knows? - */ - if (index) { - ali_write(0xf2, 0x00); - } - ali_write(0xf2, 0x0c); - } - ALI_CLOSE(); - -} - -void ali512x_set_uart2_irda(int enabled) -{ - ALI_OPEN(); - ALI_SELDEV(5); - - ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */ - ALI_CLOSE(); - -} - -void ali512x_set_rtc(int enabled, u16 io, u8 irq) -{ - ALI_OPEN(); - ALI_SELDEV(6); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - - ali_write(0xf0, 0x00); - } - ALI_CLOSE(); -} - -void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) -{ - ALI_OPEN(); - ALI_SELDEV(7); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x70, kbc_irq); - ali_write(0x72, mouse_irq); - - ali_write(0xf0, 0x00); - } - ALI_CLOSE(); -} - - -/* Common I/O - * - * (This descripotsion is base on several incompete sources - * since I have not been able to obtain any datasheet for the device - * there may be some mis-understandings burried in here. - * -- Daniel daniel@omicron.se) - * - * There are 22 CIO pins numbered - * 10-17 - * 20-25 - * 30-37 - * - * 20-24 are dedicated CIO pins, the other 17 are muliplexed with - * other functions. - * - * Secondary - * CIO Pin Function Decription - * ======================================================= - * CIO10 IRQIN1 Interrupt input 1? - * CIO11 IRQIN2 Interrupt input 2? - * CIO12 IRRX IrDa Receive - * CIO13 IRTX IrDa Transmit - * CIO14 P21 KBC P21 fucntion - * CIO15 P20 KBC P21 fucntion - * CIO16 I2C_CLK I2C Clock - * CIO17 I2C_DAT I2C Data - * - * CIO20 - - * CIO21 - - * CIO22 - - * CIO23 - - * CIO24 - - * CIO25 LOCK Keylock - * - * CIO30 KBC_CLK Keybaord Clock - * CIO31 CS0J General Chip Select decoder CS0J - * CIO32 CS1J General Chip Select decoder CS1J - * CIO33 ALT_KCLK Alternative Keyboard Clock - * CIO34 ALT_KDAT Alternative Keyboard Data - * CIO35 ALT_MCLK Alternative Mouse Clock - * CIO36 ALT_MDAT Alternative Mouse Data - * CIO37 ALT_KBC Alternative KBC select - * - * The CIO use an indirect address scheme. - * - * Reigster 3 in the SIO is used to select the index and data - * port addresses where the CIO I/O registers show up. - * The function selection registers are accessible under - * function SIO 8. - * - * SIO reigster 3 (CIO Address Selection) bit definitions: - * bit 7 CIO index and data registers enabled - * bit 1-0 CIO indirect registers port address select - * 0 index = 0xE0 data = 0xE1 - * 1 index = 0xE2 data = 0xE3 - * 2 index = 0xE4 data = 0xE5 - * 3 index = 0xEA data = 0xEB - * - * There are three CIO I/O register accessed via CIO index port and CIO data port - * 0x01 CIO 10-17 data - * 0x02 CIO 20-25 data (bits 7-6 unused) - * 0x03 CIO 30-37 data - * - * - * The pin function is accessed through normal - * SIO registers, each register have the same format: - * - * Bit Function Value - * 0 Input/output 1=input - * 1 Polarity of signal 1=inverted - * 2 Unused ?? - * 3 Function (normal or special) 1=special - * 7-4 Unused - * - * SIO REG - * 0xe0 CIO 10 Config - * 0xe1 CIO 11 Config - * 0xe2 CIO 12 Config - * 0xe3 CIO 13 Config - * 0xe4 CIO 14 Config - * 0xe5 CIO 15 Config - * 0xe6 CIO 16 Config - * 0xe7 CIO 16 Config - * - * 0xe8 CIO 20 Config - * 0xe9 CIO 21 Config - * 0xea CIO 22 Config - * 0xeb CIO 23 Config - * 0xec CIO 24 Config - * 0xed CIO 25 Config - * - * 0xf5 CIO 30 Config - * 0xf6 CIO 31 Config - * 0xf7 CIO 32 Config - * 0xf8 CIO 33 Config - * 0xf9 CIO 34 Config - * 0xfa CIO 35 Config - * 0xfb CIO 36 Config - * 0xfc CIO 37 Config - * - */ - -#define ALI_CIO_PORT_SEL 0x83 -#define ALI_CIO_INDEX 0xea -#define ALI_CIO_DATA 0xeb - -void ali512x_set_cio(int enabled) -{ - int i; - - ALI_OPEN(); - - if (enabled) { - ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */ - } else { - ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80); - } - - ALI_SELDEV(8); - - ali_write(0x30, enabled?1:0); - - /* set all pins to input to start with */ - for (i=0xe0;i<0xee;i++) { - ali_write(i, 1); - } - - for (i=0xf5;i<0xfe;i++) { - ali_write(i, 1); - } - - ALI_CLOSE(); -} - - -void ali512x_cio_function(int pin, int special, int inv, int input) -{ - u8 data; - u8 addr; - - /* valid pins are 10-17, 20-25 and 30-37 */ - if (pin >= 10 && pin <= 17) { - addr = 0xe0+(pin&7); - } else if (pin >= 20 && pin <= 25) { - addr = 0xe8+(pin&7); - } else if (pin >= 30 && pin <= 37) { - addr = 0xf5+(pin&7); - } else { - return; - } - - ALI_OPEN(); - - ALI_SELDEV(8); - - - data=0xf4; - if (special) { - data |= 0x08; - } else { - if (inv) { - data |= 0x02; - } - if (input) { - data |= 0x01; - } - } - - ali_write(addr, data); - - ALI_CLOSE(); -} - -void ali512x_cio_out(int pin, int value) -{ - u8 reg; - u8 data; - u8 bit; - - reg = pin/10; - bit = 1 << (pin%10); - - - outb(reg, ALI_CIO_INDEX); /* select I/O register */ - data = inb(ALI_CIO_DATA); - if (value) { - data |= bit; - } else { - data &= ~bit; - } - outb(data, ALI_CIO_DATA); -} - -int ali512x_cio_in(int pin) -{ - u8 reg; - u8 data; - u8 bit; - - /* valid pins are 10-17, 20-25 and 30-37 */ - reg = pin/10; - bit = 1 << (pin%10); - - - outb(reg, ALI_CIO_INDEX); /* select I/O register */ - data = inb(ALI_CIO_DATA); - - return data & bit; -} diff --git a/drivers/misc/mc9sdz60.c b/drivers/misc/mc9sdz60.c deleted file mode 100644 index e68a056a559..00000000000 --- a/drivers/misc/mc9sdz60.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 Stefano Babic <sbabic@denx.de> - */ - - -#include <config.h> -#include <common.h> -#include <linux/errno.h> -#include <linux/types.h> -#include <i2c.h> -#include <mc9sdz60.h> - -#ifndef CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR -#error "You have to configure I2C address for MC9SDZ60" -#endif - - -u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg) -{ - u8 val; - - if (i2c_read(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1)) { - puts("Error reading MC9SDZ60 register\n"); - return -1; - } - - return val; -} - -void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val) -{ - i2c_write(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1); -} diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 7320d581e2f..666323e2219 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,8 +56,6 @@ obj-$(CONFIG_NAND_DENALI) += denali.o obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o -obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o -obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o @@ -70,11 +68,9 @@ obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o -obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o -obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_MXIC) += mxic_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c deleted file mode 100644 index 91cc1339537..00000000000 --- a/drivers/mtd/nand/raw/fsl_upm.c +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * FSL UPM NAND driver - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/fsl_upm.h> -#include <nand.h> - -static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) -{ - clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); - (void)in_be32(upm->mxmr); -} - -static void fsl_upm_end_pattern(struct fsl_upm *upm) -{ - clrbits_be32(upm->mxmr, MxMR_OP_RUNP); - - while (in_be32(upm->mxmr) & MxMR_OP_RUNP) - eieio(); -} - -static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, - void __iomem *io_addr, u32 mar) -{ - out_be32(upm->mar, mar); - (void)in_be32(upm->mar); - switch (width) { - case 8: - out_8(io_addr, 0x0); - break; - case 16: - out_be16(io_addr, 0x0); - break; - case 32: - out_be32(io_addr, 0x0); - break; - } -} - -static void fun_wait(struct fsl_upm_nand *fun) -{ - if (fun->dev_ready) { - while (!fun->dev_ready(fun->chip_nr)) - debug("unexpected busy state\n"); - } else { - /* - * If the R/B pin is not connected, - * a short delay is necessary. - */ - udelay(1); - } -} - -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 -static void fun_select_chip(struct mtd_info *mtd, int chip_nr) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - if (chip_nr >= 0) { - fun->chip_nr = chip_nr; - chip->IO_ADDR_R = chip->IO_ADDR_W = - fun->upm.io_addr + fun->chip_offset * chip_nr; - } else if (chip_nr == -1) { - chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); - } -} -#endif - -static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - void __iomem *io_addr; - u32 mar; - - if (!(ctrl & fun->last_ctrl)) { - fsl_upm_end_pattern(&fun->upm); - - if (cmd == NAND_CMD_NONE) - return; - - fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); - } - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_ALE) - fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); - else if (ctrl & NAND_CLE) - fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); - } - - mar = cmd << (32 - fun->width); - io_addr = fun->upm.io_addr; -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 - if (fun->chip_nr > 0) { - io_addr += fun->chip_offset * fun->chip_nr; - if (fun->upm_mar_chip_offset) - mar |= fun->upm_mar_chip_offset * fun->chip_nr; - } -#endif - fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); - - /* - * Some boards/chips needs this. At least the MPC8360E-RDK - * needs it. Probably weird chip, because I don't see any - * need for this on MPC8555E + Samsung K9F1G08U0A. Usually - * here are 0-2 unexpected busy states per block read. - */ - if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) - fun_wait(fun); -} - -static u8 upm_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - return in_8(chip->IO_ADDR_R); -} - -static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - for (i = 0; i < len; i++) { - out_8(chip->IO_ADDR_W, buf[i]); - if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE) - fun_wait(fun); - } - - if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER) - fun_wait(fun); -} - -static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd_to_nand(mtd); - - for (i = 0; i < len; i++) - buf[i] = in_8(chip->IO_ADDR_R); -} - -static int nand_dev_ready(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - return fun->dev_ready(fun->chip_nr); -} - -int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) -{ - if (fun->width != 8 && fun->width != 16 && fun->width != 32) - return -ENOSYS; - - fun->last_ctrl = NAND_CLE; - - nand_set_controller_data(chip, fun); - chip->chip_delay = fun->chip_delay; - chip->ecc.mode = NAND_ECC_SOFT; - chip->cmd_ctrl = fun_cmd_ctrl; -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 - chip->select_chip = fun_select_chip; -#endif - chip->read_byte = upm_nand_read_byte; - chip->read_buf = upm_nand_read_buf; - chip->write_buf = upm_nand_write_buf; - if (fun->dev_ready) - chip->dev_ready = nand_dev_ready; - - return 0; -} diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c deleted file mode 100644 index d795864949c..00000000000 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ /dev/null @@ -1,470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. - * - * (C) Copyright 2012 - * Amit Virdi, STMicroelectronics, amit.virdi@st.com. - */ - -#include <common.h> -#include <nand.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <linux/err.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/fsmc_nand.h> -#include <asm/arch/hardware.h> - -static u32 fsmc_version; -static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *) - CONFIG_SYS_FSMC_BASE; - -/* - * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of - * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can - * correct 1 bit in 512 bytes - */ - -static struct nand_ecclayout fsmc_ecc4_lp_layout = { - .eccbytes = 104, - .eccpos = { 2, 3, 4, 5, 6, 7, 8, - 9, 10, 11, 12, 13, 14, - 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, - 34, 35, 36, 37, 38, 39, 40, - 41, 42, 43, 44, 45, 46, - 50, 51, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, - 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, - 82, 83, 84, 85, 86, 87, 88, - 89, 90, 91, 92, 93, 94, - 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, - 114, 115, 116, 117, 118, 119, 120, - 121, 122, 123, 124, 125, 126 - }, - .oobfree = { - {.offset = 15, .length = 3}, - {.offset = 31, .length = 3}, - {.offset = 47, .length = 3}, - {.offset = 63, .length = 3}, - {.offset = 79, .length = 3}, - {.offset = 95, .length = 3}, - {.offset = 111, .length = 3}, - {.offset = 127, .length = 1} - } -}; - -/* - * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes - * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118 - * bytes are free for use. - */ -static struct nand_ecclayout fsmc_ecc4_224_layout = { - .eccbytes = 104, - .eccpos = { 2, 3, 4, 5, 6, 7, 8, - 9, 10, 11, 12, 13, 14, - 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, - 34, 35, 36, 37, 38, 39, 40, - 41, 42, 43, 44, 45, 46, - 50, 51, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, - 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, - 82, 83, 84, 85, 86, 87, 88, - 89, 90, 91, 92, 93, 94, - 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, - 114, 115, 116, 117, 118, 119, 120, - 121, 122, 123, 124, 125, 126 - }, - .oobfree = { - {.offset = 15, .length = 3}, - {.offset = 31, .length = 3}, - {.offset = 47, .length = 3}, - {.offset = 63, .length = 3}, - {.offset = 79, .length = 3}, - {.offset = 95, .length = 3}, - {.offset = 111, .length = 3}, - {.offset = 127, .length = 97} - } -}; - -/* - * ECC placement definitions in oobfree type format - * There are 13 bytes of ecc for every 512 byte block and it has to be read - * consecutively and immediately after the 512 byte data block for hardware to - * generate the error bit offsets in 512 byte data - * Managing the ecc bytes in the following way makes it easier for software to - * read ecc bytes consecutive to data bytes. This way is similar to - * oobfree structure maintained already in u-boot nand driver - */ -static struct fsmc_eccplace fsmc_eccpl_lp = { - .eccplace = { - {.offset = 2, .length = 13}, - {.offset = 18, .length = 13}, - {.offset = 34, .length = 13}, - {.offset = 50, .length = 13}, - {.offset = 66, .length = 13}, - {.offset = 82, .length = 13}, - {.offset = 98, .length = 13}, - {.offset = 114, .length = 13} - } -}; - -static struct nand_ecclayout fsmc_ecc4_sp_layout = { - .eccbytes = 13, - .eccpos = { 0, 1, 2, 3, 6, 7, 8, - 9, 10, 11, 12, 13, 14 - }, - .oobfree = { - {.offset = 15, .length = 1}, - } -}; - -static struct fsmc_eccplace fsmc_eccpl_sp = { - .eccplace = { - {.offset = 0, .length = 4}, - {.offset = 6, .length = 9} - } -}; - -static struct nand_ecclayout fsmc_ecc1_layout = { - .eccbytes = 24, - .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, - 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, - .oobfree = { - {.offset = 8, .length = 8}, - {.offset = 24, .length = 8}, - {.offset = 40, .length = 8}, - {.offset = 56, .length = 8}, - {.offset = 72, .length = 8}, - {.offset = 88, .length = 8}, - {.offset = 104, .length = 8}, - {.offset = 120, .length = 8} - } -}; - -/* Count the number of 0's in buff upto a max of max_bits */ -static int count_written_bits(uint8_t *buff, int size, int max_bits) -{ - int k, written_bits = 0; - - for (k = 0; k < size; k++) { - written_bits += hweight8(~buff[k]); - if (written_bits > max_bits) - break; - } - - return written_bits; -} - -static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ALE; - - if (ctrl & NAND_NCE) { - writel(readl(&fsmc_regs_p->pc) | - FSMC_ENABLE, &fsmc_regs_p->pc); - } else { - writel(readl(&fsmc_regs_p->pc) & - ~FSMC_ENABLE, &fsmc_regs_p->pc); - } - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - /* The calculated ecc is actually the correction index in data */ - u32 err_idx[8]; - u32 num_err, i; - u32 ecc1, ecc2, ecc3, ecc4; - - num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF; - - if (likely(num_err == 0)) - return 0; - - if (unlikely(num_err > 8)) { - /* - * This is a temporary erase check. A newly erased page read - * would result in an ecc error because the oob data is also - * erased to FF and the calculated ecc for an FF data is not - * FF..FF. - * This is a workaround to skip performing correction in case - * data is FF..FF - * - * Logic: - * For every page, each bit written as 0 is counted until these - * number of bits are greater than 8 (the maximum correction - * capability of FSMC for each 512 + 13 bytes) - */ - - int bits_ecc = count_written_bits(read_ecc, 13, 8); - int bits_data = count_written_bits(dat, 512, 8); - - if ((bits_ecc + bits_data) <= 8) { - if (bits_data) - memset(dat, 0xff, 512); - return bits_data + bits_ecc; - } - - return -EBADMSG; - } - - ecc1 = readl(&fsmc_regs_p->ecc1); - ecc2 = readl(&fsmc_regs_p->ecc2); - ecc3 = readl(&fsmc_regs_p->ecc3); - ecc4 = readl(&fsmc_regs_p->sts); - - err_idx[0] = (ecc1 >> 0) & 0x1FFF; - err_idx[1] = (ecc1 >> 13) & 0x1FFF; - err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); - err_idx[3] = (ecc2 >> 7) & 0x1FFF; - err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); - err_idx[5] = (ecc3 >> 1) & 0x1FFF; - err_idx[6] = (ecc3 >> 14) & 0x1FFF; - err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); - - i = 0; - while (i < num_err) { - err_idx[i] ^= 3; - - if (err_idx[i] < 512 * 8) - __change_bit(err_idx[i], dat); - - i++; - } - - return num_err; -} - -static int fsmc_read_hwecc(struct mtd_info *mtd, - const u_char *data, u_char *ecc) -{ - u_int ecc_tmp; - int timeout = CONFIG_SYS_HZ; - ulong start; - - switch (fsmc_version) { - case FSMC_VER8: - start = get_timer(0); - while (get_timer(start) < timeout) { - /* - * Busy waiting for ecc computation - * to finish for 512 bytes - */ - if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY) - break; - } - - ecc_tmp = readl(&fsmc_regs_p->ecc1); - ecc[0] = (u_char) (ecc_tmp >> 0); - ecc[1] = (u_char) (ecc_tmp >> 8); - ecc[2] = (u_char) (ecc_tmp >> 16); - ecc[3] = (u_char) (ecc_tmp >> 24); - - ecc_tmp = readl(&fsmc_regs_p->ecc2); - ecc[4] = (u_char) (ecc_tmp >> 0); - ecc[5] = (u_char) (ecc_tmp >> 8); - ecc[6] = (u_char) (ecc_tmp >> 16); - ecc[7] = (u_char) (ecc_tmp >> 24); - - ecc_tmp = readl(&fsmc_regs_p->ecc3); - ecc[8] = (u_char) (ecc_tmp >> 0); - ecc[9] = (u_char) (ecc_tmp >> 8); - ecc[10] = (u_char) (ecc_tmp >> 16); - ecc[11] = (u_char) (ecc_tmp >> 24); - - ecc_tmp = readl(&fsmc_regs_p->sts); - ecc[12] = (u_char) (ecc_tmp >> 16); - break; - - default: - ecc_tmp = readl(&fsmc_regs_p->ecc1); - ecc[0] = (u_char) (ecc_tmp >> 0); - ecc[1] = (u_char) (ecc_tmp >> 8); - ecc[2] = (u_char) (ecc_tmp >> 16); - break; - } - - return 0; -} - -void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) -{ - writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256, - &fsmc_regs_p->pc); - writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN, - &fsmc_regs_p->pc); - writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN, - &fsmc_regs_p->pc); -} - -/* - * fsmc_read_page_hwecc - * @mtd: mtd info structure - * @chip: nand chip info structure - * @buf: buffer to store read data - * @oob_required: caller expects OOB data read to chip->oob_poi - * @page: page number to read - * - * This routine is needed for fsmc verison 8 as reading from NAND chip has to be - * performed in a strict sequence as follows: - * data(512 byte) -> ecc(13 byte) - * After this read, fsmc hardware generates and reports error data bits(upto a - * max of 8 bits) - */ -static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf, int oob_required, int page) -{ - struct fsmc_eccplace *fsmc_eccpl; - int i, j, s, stat, eccsize = chip->ecc.size; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_calc = chip->buffers->ecccalc; - uint8_t *ecc_code = chip->buffers->ecccode; - int off, len, group = 0; - uint8_t oob[13] __attribute__ ((aligned (2))); - - /* Differentiate between small and large page ecc place definitions */ - if (mtd->writesize == 512) - fsmc_eccpl = &fsmc_eccpl_sp; - else - fsmc_eccpl = &fsmc_eccpl_lp; - - for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { - - chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); - chip->ecc.hwctl(mtd, NAND_ECC_READ); - chip->read_buf(mtd, p, eccsize); - - for (j = 0; j < eccbytes;) { - off = fsmc_eccpl->eccplace[group].offset; - len = fsmc_eccpl->eccplace[group].length; - group++; - - /* - * length is intentionally kept a higher multiple of 2 - * to read at least 13 bytes even in case of 16 bit NAND - * devices - */ - if (chip->options & NAND_BUSWIDTH_16) - len = roundup(len, 2); - chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); - chip->read_buf(mtd, oob + j, len); - j += len; - } - - memcpy(&ecc_code[i], oob, 13); - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - - stat = chip->ecc.correct(mtd, p, &ecc_code[i], - &ecc_calc[i]); - if (stat < 0) - mtd->ecc_stats.failed++; - else - mtd->ecc_stats.corrected += stat; - } - - return 0; -} - -int fsmc_nand_init(struct nand_chip *nand) -{ - static int chip_nr; - struct mtd_info *mtd; - u32 peripid2 = readl(&fsmc_regs_p->peripid2); - - fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) & - FSMC_REVISION_MSK; - - writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl); - -#if defined(CONFIG_SYS_FSMC_NAND_16BIT) - writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->pc); -#elif defined(CONFIG_SYS_FSMC_NAND_8BIT) - writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->pc); -#else -#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT -#endif - writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1, - &fsmc_regs_p->pc); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->comm); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->attrib); - - nand->options = 0; -#if defined(CONFIG_SYS_FSMC_NAND_16BIT) - nand->options |= NAND_BUSWIDTH_16; -#endif - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = 512; - nand->ecc.calculate = fsmc_read_hwecc; - nand->ecc.hwctl = fsmc_enable_hwecc; - nand->cmd_ctrl = fsmc_nand_hwcontrol; - nand->IO_ADDR_R = nand->IO_ADDR_W = - (void __iomem *)CFG_SYS_NAND_BASE; - nand->badblockbits = 7; - - mtd = nand_to_mtd(nand); - - switch (fsmc_version) { - case FSMC_VER8: - nand->ecc.bytes = 13; - nand->ecc.strength = 8; - nand->ecc.correct = fsmc_bch8_correct_data; - nand->ecc.read_page = fsmc_read_page_hwecc; - if (mtd->writesize == 512) - nand->ecc.layout = &fsmc_ecc4_sp_layout; - else { - if (mtd->oobsize == 224) - nand->ecc.layout = &fsmc_ecc4_224_layout; - else - nand->ecc.layout = &fsmc_ecc4_lp_layout; - } - - break; - default: - nand->ecc.bytes = 3; - nand->ecc.strength = 1; - nand->ecc.layout = &fsmc_ecc1_layout; - nand->ecc.correct = nand_correct_data; - break; - } - - /* Detect NAND chips */ - if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) - return -ENXIO; - - if (nand_scan_tail(mtd)) - return -ENXIO; - - if (nand_register(chip_nr++, mtd)) - return -ENXIO; - - return 0; -} diff --git a/drivers/mtd/nand/raw/nand_plat.c b/drivers/mtd/nand/raw/nand_plat.c deleted file mode 100644 index 81e7aa218d5..00000000000 --- a/drivers/mtd/nand/raw/nand_plat.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Genericish driver for memory mapped NAND devices - * - * Copyright (c) 2006-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* Your board must implement the following macros: - * NAND_PLAT_WRITE_CMD(chip, cmd) - * NAND_PLAT_WRITE_ADR(chip, cmd) - * NAND_PLAT_INIT() - * - * It may also implement the following: - * NAND_PLAT_DEV_READY(chip) - */ - -#include <common.h> -#include <linux/mtd/rawnand.h> -#include <asm/io.h> -#ifdef NAND_PLAT_GPIO_DEV_READY -# include <asm/gpio.h> -# define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY) -#endif - -#include <nand.h> - -static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - NAND_PLAT_WRITE_CMD(this, cmd); - else - NAND_PLAT_WRITE_ADR(this, cmd); -} - -#ifdef NAND_PLAT_DEV_READY -static int plat_dev_ready(struct mtd_info *mtd) -{ - return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd)); -} -#else -# define plat_dev_ready NULL -#endif - -int board_nand_init(struct nand_chip *nand) -{ -#ifdef NAND_PLAT_GPIO_DEV_READY - gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat"); - gpio_direction_input(NAND_PLAT_GPIO_DEV_READY); -#endif - -#ifdef NAND_PLAT_INIT - NAND_PLAT_INIT(); -#endif - - nand->cmd_ctrl = plat_cmd_ctrl; - nand->dev_ready = plat_dev_ready; - nand->ecc.mode = NAND_ECC_SOFT; - - return 0; -} diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index d393f1ba031..49506e7ba59 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o -obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_PCIE_IPROC) += pcie_iproc.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c deleted file mode 100644 index 7533286c015..00000000000 --- a/drivers/pci/pci_sh7780.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SH7780 PCI Controller (PCIC) for U-Boot. - * (C) Dustin McIntire (dustin@sensoria.com) - * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - */ - -#include <common.h> -#include <linux/delay.h> - -#include <pci.h> -#include <asm/processor.h> -#include <asm/pci.h> -#include <asm/io.h> - -#define SH7780_VENDOR_ID 0x1912 -#define SH7780_DEVICE_ID 0x0002 -#define SH7780_PCICR_PREFIX 0xA5000000 -#define SH7780_PCICR_PFCS 0x00000800 -#define SH7780_PCICR_FTO 0x00000400 -#define SH7780_PCICR_PFE 0x00000200 -#define SH7780_PCICR_TBS 0x00000100 -#define SH7780_PCICR_ARBM 0x00000040 -#define SH7780_PCICR_IOCS 0x00000004 -#define SH7780_PCICR_PRST 0x00000002 -#define SH7780_PCICR_CFIN 0x00000001 - -#define p4_in(addr) (*(vu_long *)addr) -#define p4_out(data, addr) (*(vu_long *)addr) = (data) -#define p4_inw(addr) (*(vu_short *)addr) -#define p4_outw(data, addr) (*(vu_short *)addr) = (data) - -int pci_sh4_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 *value) -{ - u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - - p4_out(par_data, SH7780_PCIPAR); - *value = p4_in(SH7780_PCIPDR); - - return 0; -} - -int pci_sh4_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - - p4_out(par_data, SH7780_PCIPAR); - p4_out(value, SH7780_PCIPDR); - return 0; -} - -int pci_sh7780_init(struct pci_controller *hose) -{ - p4_out(0x01, SH7780_PCIECR); - - if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID - && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) { - printf("PCI: Unknown PCI host bridge.\n"); - return -1; - } - printf("PCI: SH7780 PCI host bridge found.\n"); - - /* Toggle PCI reset pin */ - p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR); - udelay(100000); - p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR); - p4_outw(0x0047, SH7780_PCICMD); - - p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0); - p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0); - p4_out(0x00000000, SH7780_PCILSR1); - p4_out(0, SH7780_PCILAR1); - p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0); - p4_out(0x00000000, SH7780_PCIMBAR1); - - p4_out(0xFD000000, SH7780_PCIMBR0); - p4_out(0x00FC0000, SH7780_PCIMBMR0); - - /* if use Operand Cache then enable PCICSCR Soonp bits. */ - p4_out(0x08000000, SH7780_PCICSAR0); - p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */ - - p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM - | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE), - SH7780_PCICR); - - pci_sh4_init(hose); - return 0; -} diff --git a/drivers/power/Makefile b/drivers/power/Makefile index f805027784d..ba64b2c5938 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -4,10 +4,7 @@ # Tom Rix <Tom.Rix at windriver.com> obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ -obj-y += battery/ obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ -obj-y += fuel_gauge/ -obj-y += mfd/ obj-y += pmic/ obj-y += regulator/ @@ -18,7 +15,6 @@ obj-$(CONFIG_AXP305_POWER) += axp305.o obj-$(CONFIG_AXP809_POWER) += axp809.o obj-$(CONFIG_AXP818_POWER) += axp818.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o -obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o obj-$(CONFIG_SY8106A_POWER) += sy8106a.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o diff --git a/drivers/power/battery/Makefile b/drivers/power/battery/Makefile deleted file mode 100644 index 370923a6ed9..00000000000 --- a/drivers/power/battery/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> - -obj-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o -obj-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o diff --git a/drivers/power/battery/bat_trats.c b/drivers/power/battery/bat_trats.c deleted file mode 100644 index 54b2bf91e5c..00000000000 --- a/drivers/power/battery/bat_trats.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <common.h> -#include <console.h> -#include <log.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <power/battery.h> -#include <power/max8997_pmic.h> -#include <errno.h> - -static struct battery battery_trats; - -static int power_battery_charge(struct pmic *bat) -{ - struct power_battery *p_bat = bat->pbat; - struct battery *battery = p_bat->bat; - int k; - - if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) - return -1; - - for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) && - bat->chrg->chrg_type(p_bat->muic) && - battery->state_of_chrg < 100; k++) { - udelay(2000000); - if (!(k % 5)) - puts("."); - bat->fg->fg_battery_update(p_bat->fg, bat); - - if (k == 200) { - debug(" %d [V]", battery->voltage_uV); - puts("\n"); - k = 0; - } - - if (ctrlc()) { - printf("\nCharging disabled on request.\n"); - goto exit; - } - } - exit: - bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0); - - return 0; -} - -static int power_battery_init_trats(struct pmic *bat_, - struct pmic *fg_, - struct pmic *chrg_, - struct pmic *muic_) -{ - bat_->pbat->fg = fg_; - bat_->pbat->chrg = chrg_; - bat_->pbat->muic = muic_; - - bat_->fg = fg_->fg; - bat_->chrg = chrg_->chrg; - bat_->chrg->chrg_type = muic_->chrg->chrg_type; - return 0; -} - -static struct power_battery power_bat_trats = { - .bat = &battery_trats, - .battery_init = power_battery_init_trats, - .battery_charge = power_battery_charge, -}; - -int power_bat_init(unsigned char bus) -{ - static const char name[] = "BAT_TRATS"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board BAT init\n"); - - p->interface = PMIC_NONE; - p->name = name; - p->bus = bus; - - p->pbat = &power_bat_trats; - return 0; -} diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c deleted file mode 100644 index 1172970d1e0..00000000000 --- a/drivers/power/battery/bat_trats2.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/battery.h> -#include <power/max77693_pmic.h> -#include <errno.h> - -static struct battery battery_trats; - -static int power_battery_charge(struct pmic *bat) -{ - struct power_battery *p_bat = bat->pbat; - - if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) - return -EINVAL; - - return 0; -} - -static int power_battery_init_trats2(struct pmic *bat_, - struct pmic *fg_, - struct pmic *chrg_, - struct pmic *muic_) -{ - bat_->pbat->fg = fg_; - bat_->pbat->chrg = chrg_; - bat_->pbat->muic = muic_; - - bat_->fg = fg_->fg; - bat_->chrg = chrg_->chrg; - bat_->chrg->chrg_type = muic_->chrg->chrg_type; - return 0; -} - -static struct power_battery power_bat_trats2 = { - .bat = &battery_trats, - .battery_init = power_battery_init_trats2, - .battery_charge = power_battery_charge, -}; - -int power_bat_init(unsigned char bus) -{ - static const char name[] = "BAT_TRATS2"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board BAT init\n"); - - p->interface = PMIC_NONE; - p->name = name; - p->bus = bus; - - p->pbat = &power_bat_trats2; - return 0; -} diff --git a/drivers/power/ftpmu010.c b/drivers/power/ftpmu010.c deleted file mode 100644 index 9a48b36554d..00000000000 --- a/drivers/power/ftpmu010.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * Copyright (C) 2010 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <faraday/ftpmu010.h> - -/* OSCC: OSC Control Register */ -void ftpmu010_32768osc_enable(void) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int oscc; - - /* enable the 32768Hz oscillator */ - oscc = readl(&pmu->OSCC); - oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); - writel(oscc, &pmu->OSCC); - - /* wait until ready */ - while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) - ; - - /* select 32768Hz oscillator */ - oscc = readl(&pmu->OSCC); - oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; - writel(oscc, &pmu->OSCC); -} - -/* MFPSR: Multi-Function Port Setting Register */ -void ftpmu010_mfpsr_select_dev(unsigned int dev) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int mfpsr; - - mfpsr = readl(&pmu->MFPSR); - mfpsr |= dev; - writel(mfpsr, &pmu->MFPSR); -} - -void ftpmu010_mfpsr_diselect_dev(unsigned int dev) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int mfpsr; - - mfpsr = readl(&pmu->MFPSR); - mfpsr &= ~dev; - writel(mfpsr, &pmu->MFPSR); -} - -/* PDLLCR0: PLL/DLL Control Register 0 */ -void ftpmu010_dlldis_disable(void) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int pdllcr0; - - pdllcr0 = readl(&pmu->PDLLCR0); - pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS; - writel(pdllcr0, &pmu->PDLLCR0); -} - -void ftpmu010_sdram_clk_disable(unsigned int cr0) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int pdllcr0; - - pdllcr0 = readl(&pmu->PDLLCR0); - pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); - writel(pdllcr0, &pmu->PDLLCR0); -} - -/* SDRAMHTC: SDRAM Signal Hold Time Control */ -void ftpmu010_sdramhtc_set(unsigned int val) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int sdramhtc; - - sdramhtc = readl(&pmu->SDRAMHTC); - sdramhtc |= val; - writel(sdramhtc, &pmu->SDRAMHTC); -} diff --git a/drivers/power/fuel_gauge/Makefile b/drivers/power/fuel_gauge/Makefile deleted file mode 100644 index ca2df947585..00000000000 --- a/drivers/power/fuel_gauge/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> - -obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o diff --git a/drivers/power/fuel_gauge/fg_max17042.c b/drivers/power/fuel_gauge/fg_max17042.c deleted file mode 100644 index a395d587a86..00000000000 --- a/drivers/power/fuel_gauge/fg_max17042.c +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <power/max17042_fg.h> -#include <i2c.h> -#include <power/max8997_pmic.h> -#include <power/power_chrg.h> -#include <power/battery.h> -#include <power/fg_battery_cell_params.h> -#include <errno.h> - -static int fg_write_regs(struct pmic *p, u8 addr, u16 *data, int num) -{ - int ret = 0; - int i; - - for (i = 0; i < num; i++, addr++) { - ret = pmic_reg_write(p, addr, *(data + i)); - if (ret) - return ret; - } - - return 0; -} - -static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num) -{ - unsigned int dat; - int ret = 0; - int i; - - for (i = 0; i < num; i++, addr++) { - ret = pmic_reg_read(p, addr, &dat); - if (ret) - return ret; - - *(data + i) = (u16)dat; - } - - return 0; -} - -static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) -{ - unsigned int val = data; - int ret = 0; - - ret |= pmic_reg_write(p, addr, val); - ret |= pmic_reg_read(p, addr, &val); - - if (ret) - return ret; - - if (((u16) val) == data) - return 0; - - return -1; -} - -static void por_fuelgauge_init(struct pmic *p) -{ - u16 r_data0[16], r_data1[16], r_data2[16]; - u32 rewrite_count = 5; - u32 check_count; - u32 lock_count; - u32 i = 0; - u32 val; - s32 ret = 0; - char *status_msg; - - /* Delay 500 ms */ - mdelay(500); - /* Initilize Configuration */ - pmic_reg_write(p, MAX17042_CONFIG, 0x2310); - -rewrite_model: - check_count = 5; - lock_count = 5; - - if (!rewrite_count--) { - status_msg = "init failed!"; - goto error; - } - - /* Unlock Model Access */ - pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1); - pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2); - - /* Write/Read/Verify the Custom Model */ - ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0, - ARRAY_SIZE(cell_character0)); - if (ret) - goto rewrite_model; - - ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1, - ARRAY_SIZE(cell_character1)); - if (ret) - goto rewrite_model; - - ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2, - ARRAY_SIZE(cell_character2)); - if (ret) - goto rewrite_model; - -check_model: - if (!check_count--) { - if (rewrite_count) - goto rewrite_model; - else - status_msg = "check failed!"; - - goto error; - } - - ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - if (ret) - goto check_model; - - ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - if (ret) - goto check_model; - - ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); - if (ret) - goto check_model; - - for (i = 0; i < 16; i++) { - if ((cell_character0[i] != r_data0[i]) - || (cell_character1[i] != r_data1[i]) - || (cell_character2[i] != r_data2[i])) - goto rewrite_model; - } - -lock_model: - if (!lock_count--) { - if (rewrite_count) - goto rewrite_model; - else - status_msg = "lock failed!"; - - goto error; - } - - /* Lock model access */ - pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1); - pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2); - - /* Verify the model access is locked */ - ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - if (ret) - goto lock_model; - - ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - if (ret) - goto lock_model; - - ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); - if (ret) - goto lock_model; - - for (i = 0; i < ARRAY_SIZE(r_data0); i++) { - /* Check if model locked */ - if (r_data0[i] || r_data1[i] || r_data2[i]) - goto lock_model; - } - - /* Write Custom Parameters */ - fg_write_and_verify(p, MAX17042_RCOMP0, RCOMP0); - fg_write_and_verify(p, MAX17042_TEMPCO, TempCo); - - /* Delay at least 350mS */ - mdelay(350); - - /* Initialization Complete */ - pmic_reg_read(p, MAX17042_STATUS, &val); - /* Write and Verify Status with POR bit Cleared */ - fg_write_and_verify(p, MAX17042_STATUS, val & ~MAX17042_POR); - - /* Delay at least 350 ms */ - mdelay(350); - - status_msg = "OK!"; -error: - debug("%s: model init status: %s\n", p->name, status_msg); - return; -} - -static int power_update_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - unsigned int val; - int ret = 0; - - if (pmic_probe(p)) { - puts("Can't find max17042 fuel gauge\n"); - return -ENODEV; - } - - ret |= pmic_reg_read(p, MAX17042_VFSOC, &val); - pb->bat->state_of_chrg = (val >> 8); - - pmic_reg_read(p, MAX17042_VCELL, &val); - debug("vfsoc: 0x%x\n", val); - pb->bat->voltage_uV = ((val & 0xFFUL) >> 3) + ((val & 0xFF00) >> 3); - pb->bat->voltage_uV = (pb->bat->voltage_uV * 625); - - pmic_reg_read(p, 0x05, &val); - pb->bat->capacity = val >> 2; - - return ret; -} - -static int power_check_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - unsigned int val; - int ret = 0; - - if (pmic_probe(p)) { - puts("Can't find max17042 fuel gauge\n"); - return -ENODEV; - } - - ret |= pmic_reg_read(p, MAX17042_STATUS, &val); - debug("fg status: 0x%x\n", val); - - if (val & MAX17042_POR) - por_fuelgauge_init(p); - - ret |= pmic_reg_read(p, MAX17042_VERSION, &val); - pb->bat->version = val; - - power_update_battery(p, bat); - debug("fg ver: 0x%x\n", pb->bat->version); - printf("BAT: state_of_charge(SOC):%d%%\n", - pb->bat->state_of_chrg); - - printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n", - pb->bat->voltage_uV / 1000000, - pb->bat->voltage_uV % 1000000, - pb->bat->capacity); - - if (pb->bat->voltage_uV > 3850000) - pb->bat->state = EXT_SOURCE; - else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5) - pb->bat->state = CHARGE; - else - pb->bat->state = NORMAL; - - return ret; -} - -static struct power_fg power_fg_ops = { - .fg_battery_check = power_check_battery, - .fg_battery_update = power_update_battery, -}; - -int power_fg_init(unsigned char bus) -{ - static const char name[] = "MAX17042_FG"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Fuel Gauge init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = FG_NUM_OF_REGS; - p->hw.i2c.addr = MAX17042_I2C_ADDR; - p->hw.i2c.tx_num = 2; - p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG; - p->bus = bus; - - p->fg = &power_fg_ops; - return 0; -} diff --git a/drivers/power/mfd/Makefile b/drivers/power/mfd/Makefile deleted file mode 100644 index a8eb7f81e72..00000000000 --- a/drivers/power/mfd/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2013 Samsung Electronics -# Piotr Wilczek <p.wilczek@samsung.com> - -obj-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o -obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o -obj-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o diff --git a/drivers/power/mfd/fg_max77693.c b/drivers/power/mfd/fg_max77693.c deleted file mode 100644 index 983a6d4a2bd..00000000000 --- a/drivers/power/mfd/fg_max77693.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/max77693_fg.h> -#include <i2c.h> -#include <power/power_chrg.h> -#include <power/battery.h> -#include <power/fg_battery_cell_params.h> -#include <errno.h> - -static int max77693_get_vcell(u32 *vcell) -{ - u16 value; - u8 ret; - - ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VCELL, 1, - (u8 *)&value, 2); - if (ret) - return ret; - - *vcell = (u32)(value >> 3); - *vcell = *vcell * 625; - - return 0; -} - -static int max77693_get_soc(u32 *soc) -{ - u16 value; - u8 ret; - - ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VFSOC, 1, - (u8 *)&value, 2); - if (ret) - return ret; - - *soc = (u32)(value >> 8); - - return 0; -} - -static int power_update_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - int ret; - - if (pmic_probe(p)) { - puts("Can't find max77693 fuel gauge\n"); - return -ENODEV; - } - - ret = max77693_get_soc(&pb->bat->state_of_chrg); - if (ret) - return ret; - - max77693_get_vcell(&pb->bat->voltage_uV); - - return 0; -} - -static int power_check_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - unsigned int val; - int ret = 0; - - if (pmic_probe(p)) { - puts("Can't find max77693 fuel gauge\n"); - return -ENODEV; - } - - ret = pmic_reg_read(p, MAX77693_STATUS, &val); - if (ret) - return ret; - debug("fg status: 0x%x\n", val); - - ret = pmic_reg_read(p, MAX77693_VERSION, &pb->bat->version); - if (ret) - return ret; - - ret = power_update_battery(p, bat); - if (ret) - return ret; - debug("fg ver: 0x%x\n", pb->bat->version); - printf("BAT: state_of_charge(SOC):%d%%\n", - pb->bat->state_of_chrg); - - printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n", - pb->bat->voltage_uV / 1000000, - pb->bat->voltage_uV % 1000000, - pb->bat->capacity); - - if (pb->bat->voltage_uV > 3850000) - pb->bat->state = EXT_SOURCE; - else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5) - pb->bat->state = CHARGE; - else - pb->bat->state = NORMAL; - - return 0; -} - -static struct power_fg power_fg_ops = { - .fg_battery_check = power_check_battery, - .fg_battery_update = power_update_battery, -}; - -int power_fg_init(unsigned char bus) -{ - static const char name[] = "MAX77693_FG"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Fuel Gauge init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = FG_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_FUEL_I2C_ADDR; - p->hw.i2c.tx_num = 2; - p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG; - p->bus = bus; - - p->fg = &power_fg_ops; - - return 0; -} diff --git a/drivers/power/mfd/muic_max77693.c b/drivers/power/mfd/muic_max77693.c deleted file mode 100644 index 36ee44b9a2c..00000000000 --- a/drivers/power/mfd/muic_max77693.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/power_chrg.h> -#include <power/max77693_muic.h> -#include <i2c.h> -#include <errno.h> - -static int power_chrg_get_type(struct pmic *p) -{ - unsigned int val; - unsigned int charge_type, charger; - - /* if probe failed, return cable none */ - if (pmic_probe(p)) - return CHARGER_NO; - - pmic_reg_read(p, MAX77693_MUIC_STATUS2, &val); - - charge_type = val & MAX77693_MUIC_CHG_MASK; - - switch (charge_type) { - case MAX77693_MUIC_CHG_NO: - charger = CHARGER_NO; - break; - case MAX77693_MUIC_CHG_USB: - case MAX77693_MUIC_CHG_USB_D: - charger = CHARGER_USB; - break; - case MAX77693_MUIC_CHG_TA: - case MAX77693_MUIC_CHG_TA_1A: - charger = CHARGER_TA; - break; - case MAX77693_MUIC_CHG_TA_500: - charger = CHARGER_TA_500; - break; - default: - charger = CHARGER_UNKNOWN; - break; - } - - return charger; -} - -static struct power_chrg power_chrg_muic_ops = { - .chrg_type = power_chrg_get_type, -}; - -int power_muic_init(unsigned int bus) -{ - static const char name[] = "MAX77693_MUIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Micro USB Interface Controller init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = MUIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_MUIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_muic_ops; - - return 0; -} diff --git a/drivers/power/mfd/pmic_max77693.c b/drivers/power/mfd/pmic_max77693.c deleted file mode 100644 index e32a9722a40..00000000000 --- a/drivers/power/mfd/pmic_max77693.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/max77693_pmic.h> -#include <i2c.h> -#include <errno.h> - -static int max77693_charger_state(struct pmic *p, int state, int current) -{ - unsigned int val; - - if (pmic_probe(p)) - return -ENODEV; - - /* unlock write capability */ - val = MAX77693_CHG_UNLOCK; - pmic_reg_write(p, MAX77693_CHG_CNFG_06, val); - - if (state == PMIC_CHARGER_DISABLE) { - puts("Disable the charger.\n"); - pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val); - val &= ~0x01; - pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); - return -ENOTSUPP; - } - - if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) { - printf("%s: Wrong charge current: %d [mA]\n", - __func__, current); - return -EINVAL; - } - - /* set charging current */ - pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); - val &= ~MAX77693_CHG_CC; - val |= current * 10 / 333; /* 0.1A/3 steps */ - pmic_reg_write(p, MAX77693_CHG_CNFG_02, val); - - /* enable charging */ - val = MAX77693_CHG_MODE_ON; - pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); - - /* check charging current */ - pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); - val &= 0x3f; - printf("Enable the charger @ %d [mA]\n", val * 333 / 10); - - return 0; -} - -static int max77693_charger_bat_present(struct pmic *p) -{ - unsigned int val; - - if (pmic_probe(p)) - return -ENODEV; - - pmic_reg_read(p, MAX77693_CHG_INT_OK, &val); - - return !(val & MAX77693_CHG_DETBAT); -} - -static struct power_chrg power_chrg_pmic_ops = { - .chrg_bat_present = max77693_charger_bat_present, - .chrg_state = max77693_charger_state, -}; - -int pmic_init_max77693(unsigned char bus) -{ - static const char name[] = "MAX77693_PMIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board PMIC init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = PMIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_PMIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_pmic_ops; - - return 0; -} diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index c3180c58208..0b3b3d62d0e 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -37,7 +37,6 @@ obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o -obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o diff --git a/drivers/power/pmic/muic_max8997.c b/drivers/power/pmic/muic_max8997.c deleted file mode 100644 index 969ce902395..00000000000 --- a/drivers/power/pmic/muic_max8997.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/power_chrg.h> -#include <power/max8997_muic.h> -#include <i2c.h> -#include <errno.h> - -static int power_chrg_get_type(struct pmic *p) -{ - unsigned int val; - unsigned char charge_type, charger; - - if (pmic_probe(p)) - return CHARGER_NO; - - pmic_reg_read(p, MAX8997_MUIC_STATUS2, &val); - charge_type = val & MAX8997_MUIC_CHG_MASK; - - switch (charge_type) { - case MAX8997_MUIC_CHG_NO: - charger = CHARGER_NO; - break; - case MAX8997_MUIC_CHG_USB: - case MAX8997_MUIC_CHG_USB_D: - charger = CHARGER_USB; - break; - case MAX8997_MUIC_CHG_TA: - case MAX8997_MUIC_CHG_TA_1A: - charger = CHARGER_TA; - break; - case MAX8997_MUIC_CHG_TA_500: - charger = CHARGER_TA_500; - break; - default: - charger = CHARGER_UNKNOWN; - break; - } - - return charger; -} - -static struct power_chrg power_chrg_muic_ops = { - .chrg_type = power_chrg_get_type, -}; - -int power_muic_init(unsigned int bus) -{ - static const char name[] = "MAX8997_MUIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Micro USB Interface Controller init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = MUIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX8997_MUIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_muic_ops; - return 0; -} diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index acfd130bbc9..447551e15aa 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -6,49 +6,35 @@ obj-$(CONFIG_$(SPL_TPL_)DM_RTC) += rtc-uclass.o -obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o -obj-$(CONFIG_RTC_DS1302) += ds1302.o -obj-$(CONFIG_RTC_DS1306) += ds1306.o obj-$(CONFIG_RTC_DS1307) += ds1307.o obj-$(CONFIG_RTC_DS1338) += ds1307.o -obj-$(CONFIG_RTC_DS1339) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o -obj-$(CONFIG_RTC_DS1388) += ds1337.o obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o -obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o obj-$(CONFIG_RTC_HT1380) += ht1380.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o -obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o obj-$(CONFIG_RTC_M41T62) += m41t62.o -obj-$(CONFIG_RTC_MAX6900) += max6900.o obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o obj-$(CONFIG_RTC_MC146818) += mc146818.o -obj-$(CONFIG_RTC_MCP79411) += ds1307.o obj-$(CONFIG_MCFRTC) += mcfrtc.o -obj-$(CONFIG_RTC_MK48T59) += mk48t59.o obj-$(CONFIG_RTC_MV) += mvrtc.o -obj-$(CONFIG_RTC_MX27) += mx27rtc.o obj-$(CONFIG_RTC_MXS) += mxsrtc.o obj-$(CONFIG_RTC_PCF8563) += pcf8563.o obj-$(CONFIG_RTC_PCF2127) += pcf2127.o obj-$(CONFIG_RTC_PL031) += pl031.o obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o -obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o obj-$(CONFIG_RTC_RV3028) += rv3028.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RV8803) += rv8803.o obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o -obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o obj-$(CONFIG_RTC_S35392A) += s35392a.o obj-$(CONFIG_RTC_STM32) += stm32_rtc.o obj-$(CONFIG_SANDBOX) += sandbox_rtc.o -obj-$(CONFIG_RTC_X1205) += x1205.o obj-$(CONFIG_RTC_ABX80X) += abx80x.o obj-$(CONFIG_RTC_ZYNQMP) += zynqmp_rtc.o diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c deleted file mode 100644 index 6f92660ef1d..00000000000 --- a/drivers/rtc/at91sam9_rtt.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - */ - -/* - * Date & Time support for the internal Real-time Timer - * of AT91SAM9260 and compatibles. - * Compatible with the LinuX rtc driver workaround: - * The RTT cannot be written to, but only reset. - * The actual time is the sum of RTT and one of - * the four GPBR registers. - * - * The at91sam9260 has 4 GPBR (0-3). - * For their typical use see at91_gpbr.h ! - * - * make sure u-boot and kernel use the same GPBR ! - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_rtt.h> -#include <asm/arch/at91_gpbr.h> - -int rtc_get (struct rtc_time *tmp) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - ulong tim; - ulong tim2; - ulong off; - - do { - tim = readl(&rtt->vr); - tim2 = readl(&rtt->vr); - } while (tim!=tim2); - off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* off==0 means time is invalid, but we ignore that */ - rtc_to_tm(tim+off, tmp); - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - ulong tim; - - tim = rtc_mktime(tmp); - - /* clear alarm, set prescaler to 32768, clear counter */ - writel(32768+AT91_RTT_RTTRST, &rtt->mr); - writel(~0, &rtt->ar); - writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* wait for counter clear to happen, takes less than a 1/32768th second */ - while (readl(&rtt->vr) != 0) - ; - return 0; -} - -void rtc_reset (void) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - - /* clear alarm, set prescaler to 32768, clear counter */ - writel(32768+AT91_RTT_RTTRST, &rtt->mr); - writel(~0, &rtt->ar); - writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* wait for counter clear to happen, takes less than a 1/32768th second */ - while (readl(&rtt->vr) != 0) - ; -} diff --git a/drivers/rtc/ds1302.c b/drivers/rtc/ds1302.c deleted file mode 100644 index 189607c3e02..00000000000 --- a/drivers/rtc/ds1302.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip - * - * Rex G. Feany <rfeany@zumanetworks.com> - * - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <linux/delay.h> - -/* GPP Pins */ -#define DATA 0x200 -#define SCLK 0x400 -#define RST 0x800 - -/* Happy Fun Defines(tm) */ -#define RESET rtc_go_low(RST), rtc_go_low(SCLK) -#define N_RESET rtc_go_high(RST), rtc_go_low(SCLK) - -#define CLOCK_HIGH rtc_go_high(SCLK) -#define CLOCK_LOW rtc_go_low(SCLK) - -#define DATA_HIGH rtc_go_high(DATA) -#define DATA_LOW rtc_go_low(DATA) -#define DATA_READ (GTREGREAD(GPP_VALUE) & DATA) - -#undef RTC_DEBUG - -#ifdef RTC_DEBUG -# define DPRINTF(x,args...) printf("ds1302: " x , ##args) -static inline void DUMP(const char *ptr, int num) -{ - while (num--) printf("%x ", *ptr++); - printf("]\n"); -} -#else -# define DPRINTF(x,args...) -# define DUMP(ptr, num) -#endif - -/* time data format for DS1302 */ -struct ds1302_st -{ - unsigned char CH:1; /* clock halt 1=stop 0=start */ - unsigned char sec10:3; - unsigned char sec:4; - - unsigned char zero0:1; - unsigned char min10:3; - unsigned char min:4; - - unsigned char fmt:1; /* 1=12 hour 0=24 hour */ - unsigned char zero1:1; - unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */ - unsigned char hr:4; - - unsigned char zero2:2; - unsigned char date10:2; - unsigned char date:4; - - unsigned char zero3:3; - unsigned char month10:1; - unsigned char month:4; - - unsigned char zero4:5; - unsigned char day:3; /* day of week */ - - unsigned char year10:4; - unsigned char year:4; - - unsigned char WP:1; /* write protect 1=protect 0=unprot */ - unsigned char zero5:7; -}; - -static int ds1302_initted=0; - -/* Pin control */ -static inline void -rtc_go_high(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_VALUE) | mask; - - GT_REG_WRITE(GPP_VALUE, f); -} - -static inline void -rtc_go_low(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_VALUE) & ~mask; - - GT_REG_WRITE(GPP_VALUE, f); -} - -static inline void -rtc_go_input(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_IO_CONTROL) & ~mask; - - GT_REG_WRITE(GPP_IO_CONTROL, f); -} - -static inline void -rtc_go_output(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask; - - GT_REG_WRITE(GPP_IO_CONTROL, f); -} - -/* Access data in RTC */ - -static void -write_byte(unsigned char b) -{ - int i; - unsigned char mask=1; - - for(i=0;i<8;i++) { - CLOCK_LOW; /* Lower clock */ - (b&mask)?DATA_HIGH:DATA_LOW; /* set data */ - udelay(1); - CLOCK_HIGH; /* latch data with rising clock */ - udelay(1); - mask=mask<<1; - } -} - -static unsigned char -read_byte(void) -{ - int i; - unsigned char mask=1; - unsigned char b=0; - - for(i=0;i<8;i++) { - CLOCK_LOW; - udelay(1); - if (DATA_READ) b|=mask; /* if this bit is high, set in b */ - CLOCK_HIGH; /* clock out next bit */ - udelay(1); - mask=mask<<1; - } - return b; -} - -static void -read_ser_drv(unsigned char addr, unsigned char *buf, int count) -{ - int i; -#ifdef RTC_DEBUG - char *foo = buf; -#endif - - DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr); - - addr|=1; /* READ */ - N_RESET; - udelay(4); - write_byte(addr); - rtc_go_input(DATA); /* Put gpp pin into input mode */ - udelay(1); - for(i=0;i<count;i++) *(buf++)=read_byte(); - RESET; - rtc_go_output(DATA);/* Reset gpp for output */ - udelay(4); - - DUMP(foo, count); -} - -static void -write_ser_drv(unsigned char addr, unsigned char *buf, int count) -{ - int i; - - DPRINTF("WRITE 0x%x bytes @ 0x%x [ ", count, addr); - DUMP(buf, count); - - addr&=~1; /* WRITE */ - N_RESET; - udelay(4); - write_byte(addr); - for(i=0;i<count;i++) write_byte(*(buf++)); - RESET; - udelay(4); - -} - -void -rtc_init(void) -{ - struct ds1302_st bbclk; - unsigned char b; - int mod; - - DPRINTF("init\n"); - - rtc_go_output(DATA|SCLK|RST); - - /* disable write protect */ - b = 0; - write_ser_drv(0x8e,&b,1); - - /* enable trickle */ - b = 0xa5; /* 1010.0101 */ - write_ser_drv(0x90,&b,1); - - /* read burst */ - read_ser_drv(0xbe, (unsigned char *)&bbclk, 8); - - /* Sanity checks */ - mod = 0; - if (bbclk.CH) { - printf("ds1302: Clock was halted, starting clock\n"); - bbclk.CH=0; - mod=1; - } - - if (bbclk.fmt) { - printf("ds1302: Clock was in 12 hour mode, fixing\n"); - bbclk.fmt=0; - mod=1; - } - - if (bbclk.year>9) { - printf("ds1302: Year was corrupted, fixing\n"); - bbclk.year10=100/10; /* 2000 - why not? ;) */ - bbclk.year=0; - mod=1; - } - - /* Write out the changes if needed */ - if (mod) { - /* enable write protect */ - bbclk.WP = 1; - write_ser_drv(0xbe,(unsigned char *)&bbclk,8); - } else { - /* Else just turn write protect on */ - b = 0x80; - write_ser_drv(0x8e,&b,1); - } - DPRINTF("init done\n"); - - ds1302_initted=1; -} - -void -rtc_reset(void) -{ - if(!ds1302_initted) rtc_init(); - /* TODO */ -} - -int -rtc_get(struct rtc_time *tmp) -{ - int rel = 0; - struct ds1302_st bbclk; - - if(!ds1302_initted) rtc_init(); - - read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* read burst */ - - if (bbclk.CH) { - printf("ds1302: rtc_get: Clock was halted, clock probably " - "corrupt\n"); - rel = -1; - } - - tmp->tm_sec=10*bbclk.sec10+bbclk.sec; - tmp->tm_min=10*bbclk.min10+bbclk.min; - tmp->tm_hour=10*bbclk.hr10+bbclk.hr; - tmp->tm_wday=bbclk.day; - tmp->tm_mday=10*bbclk.date10+bbclk.date; - tmp->tm_mon=10*bbclk.month10+bbclk.month; - tmp->tm_year=10*bbclk.year10+bbclk.year + 1900; - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); - - return rel; -} - -int rtc_set(struct rtc_time *tmp) -{ - struct ds1302_st bbclk; - unsigned char b=0; - - if(!ds1302_initted) rtc_init(); - - DPRINTF("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - memset(&bbclk,0,sizeof(bbclk)); - bbclk.CH=0; /* dont halt */ - bbclk.WP=1; /* write protect when we're done */ - - bbclk.sec10=tmp->tm_sec/10; - bbclk.sec=tmp->tm_sec%10; - - bbclk.min10=tmp->tm_min/10; - bbclk.min=tmp->tm_min%10; - - bbclk.hr10=tmp->tm_hour/10; - bbclk.hr=tmp->tm_hour%10; - - bbclk.day=tmp->tm_wday; - - bbclk.date10=tmp->tm_mday/10; - bbclk.date=tmp->tm_mday%10; - - bbclk.month10=tmp->tm_mon/10; - bbclk.month=tmp->tm_mon%10; - - tmp->tm_year -= 1900; - bbclk.year10=tmp->tm_year/10; - bbclk.year=tmp->tm_year%10; - - write_ser_drv(0x8e,&b,1); /* disable write protect */ - write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* write burst */ - - return 0; -} diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c deleted file mode 100644 index 36d615812b2..00000000000 --- a/drivers/rtc/ds1306.c +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 SIXNET, dge@sixnetio.com. - * - * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - */ - -/* - * Date & Time support for DS1306 RTC using SPI: - * - * - SXNI855T: it uses its own soft SPI here in this file - * - all other: use the external spi_xfer() function - * (see include/spi.h) - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <spi.h> -#include <linux/delay.h> - -#define RTC_SECONDS 0x00 -#define RTC_MINUTES 0x01 -#define RTC_HOURS 0x02 -#define RTC_DAY_OF_WEEK 0x03 -#define RTC_DATE_OF_MONTH 0x04 -#define RTC_MONTH 0x05 -#define RTC_YEAR 0x06 - -#define RTC_SECONDS_ALARM0 0x07 -#define RTC_MINUTES_ALARM0 0x08 -#define RTC_HOURS_ALARM0 0x09 -#define RTC_DAY_OF_WEEK_ALARM0 0x0a - -#define RTC_SECONDS_ALARM1 0x0b -#define RTC_MINUTES_ALARM1 0x0c -#define RTC_HOURS_ALARM1 0x0d -#define RTC_DAY_OF_WEEK_ALARM1 0x0e - -#define RTC_CONTROL 0x0f -#define RTC_STATUS 0x10 -#define RTC_TRICKLE_CHARGER 0x11 - -#define RTC_USER_RAM_BASE 0x20 - -/* ************************************************************************* */ -#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ - -static void soft_spi_send (unsigned char n); -static unsigned char soft_spi_read (void); -static void init_spi (void); - -/*----------------------------------------------------------------------- - * Definitions - */ - -#define PB_SPISCK 0x00000002 /* PB 30 */ -#define PB_SPIMOSI 0x00000004 /* PB 29 */ -#define PB_SPIMISO 0x00000008 /* PB 28 */ -#define PB_SPI_CE 0x00010000 /* PB 15 */ - -/* ------------------------------------------------------------------------- */ - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char spi_byte; /* Data Byte */ - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); - - /* Shift out the address (0) of the time in the Clock Chip */ - soft_spi_send (0); - - /* Put the clock readings into the rtc_time structure */ - tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */ - tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */ - - /* Hours are trickier */ - spi_byte = soft_spi_read (); /* Read Hours into temporary value */ - if (spi_byte & 0x40) { - /* 12 hour mode bit is set (time is in 1-12 format) */ - if (spi_byte & 0x20) { - /* since PM we add 11 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11; - } else { - /* since AM we subtract 1 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1; - } - } else { - /* Otherwise, 0-23 hour format */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x3F)); - } - - soft_spi_read (); /* Read and discard Day of week */ - tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */ - tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */ - - /* Read Year and convert to this century */ - tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000; - - /* Now we can disable the DS1306 RTC */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - rtc_calc_weekday(tmp); /* Determine the day of week */ - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time in DS1306 RTC and in MPC8xx RTC */ -int rtc_set (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First disable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x00); /* send control register contents */ - - /* Now disable the DS1306 to terminate the write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; - udelay(10); - - /* Now enable the DS1306 to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); - - /* Next, send the address of the clock time write registers */ - soft_spi_send (0x80); /* send address of the first time register */ - - /* Use Burst Mode to send all of the time data to the clock */ - bin2bcd (tmp->tm_sec); - soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */ - soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */ - soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */ - soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */ - soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */ - soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */ - soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */ - - /* Now we can disable the Clock chip to terminate the burst write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Now we can enable the Clock chip to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First we Enable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x40); /* send out Control Register contents */ - - /* Now disable the DS1306 */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Set standard MPC8xx clock to the same time so Linux will - * see the time even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - - tim = rtc_mktime(tmp); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Initialize Port B for software SPI */ -static void init_spi (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Force output pins to begin at logic 0 */ - immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); - - /* Set these 3 signals as outputs */ - immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); - - immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ - udelay(10); -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ -static void soft_spi_send (unsigned char n) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to send, start with most significant bit */ - bitpos = 0x80; - - /* Send 8 bits to software SPI */ - for (i = 0; i < 8; i++) { /* Loop for 8 bits */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - - if (n & bitpos) - immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ - else - immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ - udelay(10); - - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); - - bitpos >>= 1; /* Shift for next bit position */ - } -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ -static unsigned char soft_spi_read (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - unsigned char spi_byte = 0; /* Return value, assume success */ - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to receive, start with most significant bit */ - bitpos = 0x80; - - /* Read 8 bits here */ - for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - udelay(10); - if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ - spi_byte |= bitpos; /* Set data accordingly */ - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); - bitpos >>= 1; /* Shift for next bit position */ - } - - return spi_byte; /* Return the byte read */ -} - -/* ------------------------------------------------------------------------- */ - -void rtc_reset (void) -{ - return; /* nothing to do */ -} - -#else /* not CONFIG_SXNI855T */ -/* ************************************************************************* */ - -static unsigned char rtc_read (unsigned char reg); -static void rtc_write (unsigned char reg, unsigned char val); - -static struct spi_slave *slave; - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - unsigned char sec, min, hour, mday, wday, mon, year; - - /* - * Assuming Vcc = 2.0V (lowest speed) - * - * REVISIT: If we add an rtc_init() function we can do this - * step just once. - */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DATE_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); - - spi_release_bus(slave); - - debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); - debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM0), - rtc_read (RTC_HOURS_ALARM0), - rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0)); - debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM1), - rtc_read (RTC_HOURS_ALARM1), - rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1)); - - tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */ - tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */ - - /* convert Hours */ - tmp->tm_hour = (hour & 0x40) - ? ((hour & 0x20) /* 12 hour mode */ - ? bcd2bin (hour & 0x1F) + 11 /* PM */ - : bcd2bin (hour & 0x1F) - 1 /* AM */ - ) - : bcd2bin (hour & 0x3F); /* 24 hour mode */ - - tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */ - tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */ - tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */ - tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */ - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time from *tmp in DS1306 RTC */ -int rtc_set (struct rtc_time *tmp) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); - rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); - rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); - rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -/* reset the DS1306 */ -void rtc_reset (void) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - /* clear the control register */ - rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ - rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ - - /* reset all alarms */ - rtc_write (RTC_SECONDS_ALARM0, 0x00); - rtc_write (RTC_SECONDS_ALARM1, 0x00); - rtc_write (RTC_MINUTES_ALARM0, 0x00); - rtc_write (RTC_MINUTES_ALARM1, 0x00); - rtc_write (RTC_HOURS_ALARM0, 0x00); - rtc_write (RTC_HOURS_ALARM1, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned char rtc_read (unsigned char reg) -{ - int ret; - - ret = spi_w8r8(slave, reg); - return ret < 0 ? 0 : ret; -} - -/* ------------------------------------------------------------------------- */ - -static void rtc_write (unsigned char reg, unsigned char val) -{ - unsigned char dout[2]; /* SPI Output Data Bytes */ - unsigned char din[2]; /* SPI Input Data Bytes */ - - dout[0] = 0x80 | reg; - dout[1] = val; - - spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); -} - -#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c deleted file mode 100644 index e384922f473..00000000000 --- a/drivers/rtc/ftrtc010.c +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday FTRTC010 Real Time Clock - * - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <rtc.h> -#include <asm/io.h> - -struct ftrtc010 { - unsigned int sec; /* 0x00 */ - unsigned int min; /* 0x04 */ - unsigned int hour; /* 0x08 */ - unsigned int day; /* 0x0c */ - unsigned int alarm_sec; /* 0x10 */ - unsigned int alarm_min; /* 0x14 */ - unsigned int alarm_hour; /* 0x18 */ - unsigned int record; /* 0x1c */ - unsigned int cr; /* 0x20 */ - unsigned int wsec; /* 0x24 */ - unsigned int wmin; /* 0x28 */ - unsigned int whour; /* 0x2c */ - unsigned int wday; /* 0x30 */ - unsigned int intr; /* 0x34 */ - unsigned int div; /* 0x38 */ - unsigned int rev; /* 0x3c */ -}; - -/* - * RTC Control Register - */ -#define FTRTC010_CR_ENABLE (1 << 0) -#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ -#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ -#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ -#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ - -static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; - -static void ftrtc010_enable(void) -{ - writel(FTRTC010_CR_ENABLE, &rtc->cr); -} - -/* - * return current time in seconds - */ -static unsigned long ftrtc010_time(void) -{ - unsigned long day; - unsigned long hour; - unsigned long minute; - unsigned long second; - unsigned long second2; - - do { - second = readl(&rtc->sec); - day = readl(&rtc->day); - hour = readl(&rtc->hour); - minute = readl(&rtc->min); - second2 = readl(&rtc->sec); - } while (second != second2); - - return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; -} - -/* - * Get the current time from the RTC - */ - -int rtc_get(struct rtc_time *tmp) -{ - unsigned long now; - - debug("%s(): record register: %x\n", - __func__, readl(&rtc->record)); - -#ifdef CFG_FTRTC010_PCLK - now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT; -#else /* CFG_FTRTC010_EXTCLK */ - now = ftrtc010_time() + readl(&rtc->record); -#endif - - rtc_to_tm(now, tmp); - - return 0; -} - -/* - * Set the RTC - */ -int rtc_set(struct rtc_time *tmp) -{ - unsigned long new; - unsigned long now; - - debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - __func__, - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - new = rtc_mktime(tmp); - - now = ftrtc010_time(); - - debug("%s(): write %lx to record register\n", __func__, new - now); - - writel(new - now, &rtc->record); - - return 0; -} - -void rtc_reset(void) -{ - debug("%s()\n", __func__); - ftrtc010_enable(); -} diff --git a/drivers/rtc/imxdi.c b/drivers/rtc/imxdi.c deleted file mode 100644 index e3a1393266c..00000000000 --- a/drivers/rtc/imxdi.c +++ /dev/null @@ -1,223 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009-2012 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on the Linux rtc-imxdi.c driver, which is: - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2010 Orex Computed Radiography - */ - -/* - * Date & Time support for Freescale i.MX DryIce RTC - */ - -#include <common.h> -#include <command.h> -#include <linux/compat.h> -#include <rtc.h> -#include <linux/delay.h> - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -/* DryIce Register Definitions */ - -struct imxdi_regs { - u32 dtcmr; /* Time Counter MSB Reg */ - u32 dtclr; /* Time Counter LSB Reg */ - u32 dcamr; /* Clock Alarm MSB Reg */ - u32 dcalr; /* Clock Alarm LSB Reg */ - u32 dcr; /* Control Reg */ - u32 dsr; /* Status Reg */ - u32 dier; /* Interrupt Enable Reg */ -}; - -#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ - -#define DCR_TCE (1 << 3) /* Time Counter Enable */ - -#define DSR_WBF (1 << 10) /* Write Busy Flag */ -#define DSR_WNF (1 << 9) /* Write Next Flag */ -#define DSR_WCF (1 << 8) /* Write Complete Flag */ -#define DSR_WEF (1 << 7) /* Write Error Flag */ -#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ -#define DSR_NVF (1 << 1) /* Non-Valid Flag */ -#define DSR_SVF (1 << 0) /* Security Violation Flag */ - -#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ -#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ -#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ -#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ - -/* Driver Private Data */ - -struct imxdi_data { - struct imxdi_regs __iomem *regs; - int init_done; -}; - -static struct imxdi_data data; - -/* - * This function attempts to clear the dryice write-error flag. - * - * A dryice write error is similar to a bus fault and should not occur in - * normal operation. Clearing the flag requires another write, so the root - * cause of the problem may need to be fixed before the flag can be cleared. - */ -static void clear_write_error(void) -{ - int cnt; - - puts("### Warning: RTC - Register write error!\n"); - - /* clear the write error flag */ - __raw_writel(DSR_WEF, &data.regs->dsr); - - /* wait for it to take effect */ - for (cnt = 0; cnt < 1000; cnt++) { - if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) - return; - udelay(10); - } - puts("### Error: RTC - Cannot clear write-error flag!\n"); -} - -/* - * Write a dryice register and wait until it completes. - * - * Use interrupt flags to determine when the write has completed. - */ -#define DI_WRITE_WAIT(val, reg) \ -( \ - /* do the register write */ \ - __raw_writel((val), &data.regs->reg), \ - \ - di_write_wait((val), #reg) \ -) -static int di_write_wait(u32 val, const char *reg) -{ - int cnt; - int ret = 0; - int rc = 0; - - /* wait for the write to finish */ - for (cnt = 0; cnt < 100; cnt++) { - if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { - ret = 1; - break; - } - udelay(10); - } - if (ret == 0) - printf("### Warning: RTC - Write-wait timeout " - "val = 0x%.8x reg = %s\n", val, reg); - - /* check for write error */ - if (__raw_readl(&data.regs->dsr) & DSR_WEF) { - clear_write_error(); - rc = -1; - } - - return rc; -} - -/* - * Initialize dryice hardware - */ -static int di_init(void) -{ - int rc = 0; - - data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE; - - /* mask all interrupts */ - __raw_writel(0, &data.regs->dier); - - /* put dryice into valid state */ - if (__raw_readl(&data.regs->dsr) & DSR_NVF) { - rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr); - if (rc) - goto err; - } - - /* initialize alarm */ - rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr); - if (rc) - goto err; - rc = DI_WRITE_WAIT(0, dcalr); - if (rc) - goto err; - - /* clear alarm flag */ - if (__raw_readl(&data.regs->dsr) & DSR_CAF) { - rc = DI_WRITE_WAIT(DSR_CAF, dsr); - if (rc) - goto err; - } - - /* the timer won't count if it has never been written to */ - if (__raw_readl(&data.regs->dtcmr) == 0) { - rc = DI_WRITE_WAIT(0, dtcmr); - if (rc) - goto err; - } - - /* start keeping time */ - if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { - rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); - if (rc) - goto err; - } - - data.init_done = 1; - return 0; - -err: - return rc; -} - -int rtc_get(struct rtc_time *tmp) -{ - unsigned long now; - int rc = 0; - - if (!data.init_done) { - rc = di_init(); - if (rc) - goto err; - } - - now = __raw_readl(&data.regs->dtcmr); - rtc_to_tm(now, tmp); - -err: - return rc; -} - -int rtc_set(struct rtc_time *tmp) -{ - unsigned long now; - int rc; - - if (!data.init_done) { - rc = di_init(); - if (rc) - goto err; - } - - now = rtc_mktime(tmp); - /* zero the fractional part first */ - rc = DI_WRITE_WAIT(0, dtclr); - if (rc == 0) - rc = DI_WRITE_WAIT(now, dtcmr); - -err: - return rc; -} - -void rtc_reset(void) -{ - di_init(); -} diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c deleted file mode 100644 index e03a87f94da..00000000000 --- a/drivers/rtc/max6900.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * Date & Time support for MAXIM MAX6900 RTC - */ - -/* #define DEBUG */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <i2c.h> -#include <linux/delay.h> - -#ifndef CFG_SYS_I2C_RTC_ADDR -#define CFG_SYS_I2C_RTC_ADDR 0x50 -#endif - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read (uchar reg) -{ - return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); -} - -static void rtc_write (uchar reg, uchar val) -{ - i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); - udelay(2500); -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar sec, min, hour, mday, wday, mon, cent, year; - int retry = 1; - - do { - sec = rtc_read (0x80); - min = rtc_read (0x82); - hour = rtc_read (0x84); - mday = rtc_read (0x86); - mon = rtc_read (0x88); - wday = rtc_read (0x8a); - year = rtc_read (0x8c); - cent = rtc_read (0x92); - /* - * Check for seconds rollover - */ - if ((sec != 59) || (rtc_read(0x80) == sec)){ - retry = 0; - } - } while (retry); - - debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, cent, mday, wday, - hour, min, sec ); - - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100; - tmp->tm_wday = bcd2bin (wday & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - - debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (0x9E, 0x00); - rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */ - rtc_write (0x92, bin2bcd(tmp->tm_year / 100)); - rtc_write (0x8c, bin2bcd(tmp->tm_year % 100)); - rtc_write (0x8a, bin2bcd(tmp->tm_wday)); - rtc_write (0x88, bin2bcd(tmp->tm_mon)); - rtc_write (0x86, bin2bcd(tmp->tm_mday)); - rtc_write (0x84, bin2bcd(tmp->tm_hour)); - rtc_write (0x82, bin2bcd(tmp->tm_min )); - rtc_write (0x80, bin2bcd(tmp->tm_sec )); - - return 0; -} - -void rtc_reset (void) -{ -} diff --git a/drivers/rtc/mk48t59.c b/drivers/rtc/mk48t59.c deleted file mode 100644 index 8c90a704076..00000000000 --- a/drivers/rtc/mk48t59.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - */ - -/* - * Date & Time support for the MK48T59 RTC - */ - -#undef RTC_DEBUG - -#include <common.h> -#include <command.h> -#include <config.h> -#include <rtc.h> -#include <mk48t59.h> - -#if defined(CONFIG_BAB7xx) - -static uchar rtc_read (short reg) -{ - out8(RTC_PORT_ADDR0, reg & 0xFF); - out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); - return in8(RTC_PORT_DATA); -} - -static void rtc_write (short reg, uchar val) -{ - out8(RTC_PORT_ADDR0, reg & 0xFF); - out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); - out8(RTC_PORT_DATA, val); -} - -#elif defined(CONFIG_EVAL5200) - -static uchar rtc_read (short reg) -{ - return in8(RTC(reg)); -} - -static void rtc_write (short reg, uchar val) -{ - out8(RTC(reg),val); -} - -#else -# error Board specific rtc access functions should be supplied -#endif - -/* ------------------------------------------------------------------------- */ - -void *nvram_read(void *dest, const short src, size_t count) -{ - uchar *d = (uchar *) dest; - short s = src; - - while (count--) - *d++ = rtc_read(s++); - - return dest; -} - -void nvram_write(short dest, const void *src, size_t count) -{ - short d = dest; - uchar *s = (uchar *) src; - - while (count--) - rtc_write(d++, *s++); -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar save_ctrl_a; - uchar sec, min, hour, mday, wday, mon, year; - - /* Simple: freeze the clock, read it and allow updates again */ - save_ctrl_a = rtc_read(RTC_CONTROLA); - - /* Set the register to read the value. */ - save_ctrl_a |= RTC_CA_READ; - rtc_write(RTC_CONTROLA, save_ctrl_a); - - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DAY_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); - - /* re-enable update */ - save_ctrl_a &= ~RTC_CA_READ; - rtc_write(RTC_CONTROLA, save_ctrl_a); - -#ifdef RTC_DEBUG - printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year); - tmp->tm_wday = bcd2bin (wday & 0x07); - if(tmp->tm_year<70) - tmp->tm_year+=2000; - else - tmp->tm_year+=1900; - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - uchar save_ctrl_a; - -#ifdef RTC_DEBUG - printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - save_ctrl_a = rtc_read(RTC_CONTROLA); - - save_ctrl_a |= RTC_CA_WRITE; - rtc_write(RTC_CONTROLA, save_ctrl_a); /* disables the RTC to update the regs */ - - rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100)); - rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon)); - - rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); - rtc_write (RTC_DAY_OF_MONTH, bin2bcd(tmp->tm_mday)); - rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour)); - rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min )); - rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec )); - - save_ctrl_a &= ~RTC_CA_WRITE; - rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */ - - return 0; -} - -void rtc_reset (void) -{ - uchar control_b; - - /* - * Start oscillator here. - */ - control_b = rtc_read(RTC_CONTROLB); - - control_b &= ~RTC_CB_STOP; - rtc_write(RTC_CONTROLB, control_b); -} - -void rtc_set_watchdog(short multi, short res) -{ - uchar wd_value; - - wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3); - rtc_write(RTC_WATCHDOG, wd_value); -} diff --git a/drivers/rtc/mx27rtc.c b/drivers/rtc/mx27rtc.c deleted file mode 100644 index 563e8a4a361..00000000000 --- a/drivers/rtc/mx27rtc.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale i.MX27 RTC Driver - * - * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr> - */ - -#include <common.h> -#include <rtc.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -#define HOUR_SHIFT 8 -#define HOUR_MASK 0x1f -#define MIN_SHIFT 0 -#define MIN_MASK 0x3f - -int rtc_get(struct rtc_time *time) -{ - struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE; - uint32_t day, hour, min, sec; - - day = readl(&rtc_regs->dayr); - hour = readl(&rtc_regs->hourmin); - sec = readl(&rtc_regs->seconds); - - min = (hour >> MIN_SHIFT) & MIN_MASK; - hour = (hour >> HOUR_SHIFT) & HOUR_MASK; - - sec += min * 60 + hour * 3600 + day * 24 * 3600; - - rtc_to_tm(sec, time); - - return 0; -} - -int rtc_set(struct rtc_time *time) -{ - struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE; - uint32_t day, hour, min, sec; - - sec = rtc_mktime(time); - - day = sec / (24 * 3600); - sec = sec % (24 * 3600); - hour = sec / 3600; - sec = sec % 3600; - min = sec / 60; - sec = sec % 60; - - hour = (hour & HOUR_MASK) << HOUR_SHIFT; - hour |= (min & MIN_MASK) << MIN_SHIFT; - - writel(day, &rtc_regs->dayr); - writel(hour, &rtc_regs->hourmin); - writel(sec, &rtc_regs->seconds); - - return 0; -} - -void rtc_reset(void) -{ - /* nothing to do */ -} diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c deleted file mode 100644 index 6b1c23ca5db..00000000000 --- a/drivers/rtc/rs5c372.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * rs5c372.c - * - * Device driver for Ricoh's Real Time Controller RS5C372A. - * - * Copyright (C) 2004 Gary Jennejohn garyj@denx.de - * - * Based in part in ds1307.c - - * (C) Copyright 2001, 2002, 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com` - * Steven Scholz, steven.scholz@imc-berlin.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <i2c.h> - -/* - * Reads are always done starting with register 15, which requires some - * jumping-through-hoops to access the data correctly. - * - * Writes are always done starting with register 0. - */ - -#define DEBUG 0 - -#if DEBUG -static unsigned int rtc_debug = DEBUG; -#else -#define rtc_debug 0 /* gcc will remove all the debug code for us */ -#endif - -#ifndef CFG_SYS_I2C_RTC_ADDR -#define CFG_SYS_I2C_RTC_ADDR 0x32 -#endif - -#define RS5C372_RAM_SIZE 0x10 -#define RATE_32000HZ 0x80 /* Rate Select 32.000KHz */ -#define RATE_32768HZ 0x00 /* Rate Select 32.768KHz */ - -#define STATUS_XPT 0x10 /* data invalid because voltage was 0 */ - -#define USE_24HOUR_MODE 0x20 -#define TWELVE_HOUR_MODE(n) ((((n) >> 5) & 1) == 0) -#define HOURS_AP(n) (((n) >> 5) & 1) -#define HOURS_12(n) bcd2bin((n) & 0x1F) -#define HOURS_24(n) bcd2bin((n) & 0x3F) - - -static int setup_done = 0; - -static int -rs5c372_readram(unsigned char *buf, int len) -{ - int ret; - - ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); - if (ret != 0) { - printf("%s: failed to read\n", __FUNCTION__); - return ret; - } - - if (buf[0] & STATUS_XPT) - printf("### Warning: RTC lost power\n"); - - return ret; -} - -static void -rs5c372_enable(void) -{ - unsigned char buf[RS5C372_RAM_SIZE + 1]; - int ret; - - /* note that this returns reg. 15 in buf[1] */ - ret = rs5c372_readram(&buf[1], RS5C372_RAM_SIZE); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return; - } - - buf[0] = 0; - /* we want to start writing at register 0 so we have to copy the */ - /* register contents up one slot */ - for (ret = 2; ret < 9; ret++) - buf[ret - 1] = buf[ret]; - /* registers 0 to 6 (time values) are not touched */ - buf[8] = RATE_32768HZ; /* reg. 7 */ - buf[9] = 0; /* reg. 8 */ - buf[10] = 0; /* reg. 9 */ - buf[11] = 0; /* reg. 10 */ - buf[12] = 0; /* reg. 11 */ - buf[13] = 0; /* reg. 12 */ - buf[14] = 0; /* reg. 13 */ - buf[15] = 0; /* reg. 14 */ - buf[16] = USE_24HOUR_MODE; /* reg. 15 */ - ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return; - } - setup_done = 1; - - return; -} - -static void -rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf) -{ - /* buf[0] is register 15 */ - dt->tm_sec = bcd2bin(buf[1]); - dt->tm_min = bcd2bin(buf[2]); - - if (TWELVE_HOUR_MODE(buf[0])) { - dt->tm_hour = HOURS_12(buf[3]); - if (HOURS_AP(buf[3])) /* PM */ - dt->tm_hour += 12; - } else /* 24-hour-mode */ - dt->tm_hour = HOURS_24(buf[3]); - - dt->tm_mday = bcd2bin(buf[5]); - dt->tm_mon = bcd2bin(buf[6]); - dt->tm_year = bcd2bin(buf[7]); - if (dt->tm_year >= 70) - dt->tm_year += 1900; - else - dt->tm_year += 2000; - /* 0 is Sunday */ - dt->tm_wday = bcd2bin(buf[4] & 0x07); - dt->tm_yday = 0; - dt->tm_isdst= 0; - - if(rtc_debug > 2) { - printf("rs5c372_convert_to_time: year = %d\n", dt->tm_year); - printf("rs5c372_convert_to_time: mon = %d\n", dt->tm_mon); - printf("rs5c372_convert_to_time: mday = %d\n", dt->tm_mday); - printf("rs5c372_convert_to_time: hour = %d\n", dt->tm_hour); - printf("rs5c372_convert_to_time: min = %d\n", dt->tm_min); - printf("rs5c372_convert_to_time: sec = %d\n", dt->tm_sec); - } -} - -/* - * Get the current time from the RTC - */ -int -rtc_get (struct rtc_time *tmp) -{ - unsigned char buf[RS5C372_RAM_SIZE]; - int ret; - - if (!setup_done) - rs5c372_enable(); - - if (!setup_done) - return -1; - - memset(buf, 0, sizeof(buf)); - - /* note that this returns reg. 15 in buf[0] */ - ret = rs5c372_readram(buf, RS5C372_RAM_SIZE); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return -1; - } - - rs5c372_convert_to_time(tmp, buf); - - return 0; -} - -/* - * Set the RTC - */ -int rtc_set (struct rtc_time *tmp) -{ - unsigned char buf[8], reg15; - int ret; - - if (!setup_done) - rs5c372_enable(); - - if (!setup_done) - return -1; - - if(rtc_debug > 2) { - printf("rtc_set: tm_year = %d\n", tmp->tm_year); - printf("rtc_set: tm_mon = %d\n", tmp->tm_mon); - printf("rtc_set: tm_mday = %d\n", tmp->tm_mday); - printf("rtc_set: tm_hour = %d\n", tmp->tm_hour); - printf("rtc_set: tm_min = %d\n", tmp->tm_min); - printf("rtc_set: tm_sec = %d\n", tmp->tm_sec); - } - - memset(buf, 0, sizeof(buf)); - - /* only read register 15 */ - ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); - - if (ret == 0) { - /* need to save register 15 */ - reg15 = buf[0]; - buf[0] = 0; /* register address on RS5C372 */ - buf[1] = bin2bcd(tmp->tm_sec); - buf[2] = bin2bcd(tmp->tm_min); - /* need to handle 12 hour mode */ - if (TWELVE_HOUR_MODE(reg15)) { - if (tmp->tm_hour >= 12) { /* PM */ - /* 12 PM is a special case */ - if (tmp->tm_hour == 12) - buf[3] = bin2bcd(tmp->tm_hour); - else - buf[3] = bin2bcd(tmp->tm_hour - 12); - buf[3] |= 0x20; - } - } else { - buf[3] = bin2bcd(tmp->tm_hour); - } - - buf[4] = bin2bcd(tmp->tm_wday); - buf[5] = bin2bcd(tmp->tm_mday); - buf[6] = bin2bcd(tmp->tm_mon); - if (tmp->tm_year < 1970 || tmp->tm_year > 2069) - printf("WARNING: year should be between 1970 and 2069!\n"); - buf[7] = bin2bcd(tmp->tm_year % 100); - - ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); - if (ret != 0) { - printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); - return -1; - } - } else { - return -1; - } - - return 0; -} - -/* - * Reset the RTC. - */ -void -rtc_reset (void) -{ - if (!setup_done) - rs5c372_enable(); -} diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c deleted file mode 100644 index 96ea3cf878e..00000000000 --- a/drivers/rtc/s3c24x0_rtc.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - */ - -/* - * Date & Time support for the built-in Samsung S3C24X0 RTC - */ - -#include <common.h> -#include <command.h> - -#include <asm/arch/s3c24x0_cpu.h> - -#include <rtc.h> -#include <asm/io.h> -#include <linux/compiler.h> - -typedef enum { - RTC_ENABLE, - RTC_DISABLE -} RTC_ACCESS; - - -static inline void SetRTC_Access(RTC_ACCESS a) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - - switch (a) { - case RTC_ENABLE: - writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); - break; - - case RTC_DISABLE: - writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); - break; - } -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get(struct rtc_time *tmp) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - uchar sec, min, hour, mday, wday, mon, year; - __maybe_unused uchar a_sec, a_min, a_hour, a_date, - a_mon, a_year, a_armed; - - /* enable access to RTC registers */ - SetRTC_Access(RTC_ENABLE); - - /* read RTC registers */ - do { - sec = readb(&rtc->bcdsec); - min = readb(&rtc->bcdmin); - hour = readb(&rtc->bcdhour); - mday = readb(&rtc->bcddate); - wday = readb(&rtc->bcdday); - mon = readb(&rtc->bcdmon); - year = readb(&rtc->bcdyear); - } while (sec != readb(&rtc->bcdsec)); - - /* read ALARM registers */ - a_sec = readb(&rtc->almsec); - a_min = readb(&rtc->almmin); - a_hour = readb(&rtc->almhour); - a_date = readb(&rtc->almdate); - a_mon = readb(&rtc->almmon); - a_year = readb(&rtc->almyear); - a_armed = readb(&rtc->rtcalm); - - /* disable access to RTC registers */ - SetRTC_Access(RTC_DISABLE); - -#ifdef RTC_DEBUG - printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); - printf("Alarms: %02x: year: %02x month: %02x date: %02x hour: " - "%02x min: %02x sec: %02x\n", - a_armed, a_year, a_mon, a_date, a_hour, a_min, a_sec); -#endif - - tmp->tm_sec = bcd2bin(sec & 0x7F); - tmp->tm_min = bcd2bin(min & 0x7F); - tmp->tm_hour = bcd2bin(hour & 0x3F); - tmp->tm_mday = bcd2bin(mday & 0x3F); - tmp->tm_mon = bcd2bin(mon & 0x1F); - tmp->tm_year = bcd2bin(year); - tmp->tm_wday = bcd2bin(wday & 0x07); - if (tmp->tm_year < 70) - tmp->tm_year += 2000; - else - tmp->tm_year += 1900; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; -#ifdef RTC_DEBUG - printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set(struct rtc_time *tmp) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - uchar sec, min, hour, mday, wday, mon, year; - -#ifdef RTC_DEBUG - printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - year = bin2bcd(tmp->tm_year % 100); - mon = bin2bcd(tmp->tm_mon); - wday = bin2bcd(tmp->tm_wday); - mday = bin2bcd(tmp->tm_mday); - hour = bin2bcd(tmp->tm_hour); - min = bin2bcd(tmp->tm_min); - sec = bin2bcd(tmp->tm_sec); - - /* enable access to RTC registers */ - SetRTC_Access(RTC_ENABLE); - - /* write RTC registers */ - writeb(sec, &rtc->bcdsec); - writeb(min, &rtc->bcdmin); - writeb(hour, &rtc->bcdhour); - writeb(mday, &rtc->bcddate); - writeb(wday, &rtc->bcdday); - writeb(mon, &rtc->bcdmon); - writeb(year, &rtc->bcdyear); - - /* disable access to RTC registers */ - SetRTC_Access(RTC_DISABLE); - - return 0; -} - -void rtc_reset(void) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - - writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); - writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); -} diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c deleted file mode 100644 index 4a8d1c5903f..00000000000 --- a/drivers/rtc/x1205.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * based on a the Linux rtc-x1207.c driver which is: - * Copyright 2004 Karen Spearel - * Copyright 2005 Alessandro Zummo - * - * Information and datasheet: - * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html - */ - -/* - * Date & Time support for Xicor/Intersil X1205 RTC - */ - -/* #define DEBUG */ - -#include <common.h> -#include <command.h> -#include <log.h> -#include <rtc.h> -#include <i2c.h> - -#define CCR_SEC 0 -#define CCR_MIN 1 -#define CCR_HOUR 2 -#define CCR_MDAY 3 -#define CCR_MONTH 4 -#define CCR_YEAR 5 -#define CCR_WDAY 6 -#define CCR_Y2K 7 - -#define X1205_REG_SR 0x3F /* status register */ -#define X1205_REG_Y2K 0x37 -#define X1205_REG_DW 0x36 -#define X1205_REG_YR 0x35 -#define X1205_REG_MO 0x34 -#define X1205_REG_DT 0x33 -#define X1205_REG_HR 0x32 -#define X1205_REG_MN 0x31 -#define X1205_REG_SC 0x30 -#define X1205_REG_DTR 0x13 -#define X1205_REG_ATR 0x12 -#define X1205_REG_INT 0x11 -#define X1205_REG_0 0x10 -#define X1205_REG_Y2K1 0x0F -#define X1205_REG_DWA1 0x0E -#define X1205_REG_YRA1 0x0D -#define X1205_REG_MOA1 0x0C -#define X1205_REG_DTA1 0x0B -#define X1205_REG_HRA1 0x0A -#define X1205_REG_MNA1 0x09 -#define X1205_REG_SCA1 0x08 -#define X1205_REG_Y2K0 0x07 -#define X1205_REG_DWA0 0x06 -#define X1205_REG_YRA0 0x05 -#define X1205_REG_MOA0 0x04 -#define X1205_REG_DTA0 0x03 -#define X1205_REG_HRA0 0x02 -#define X1205_REG_MNA0 0x01 -#define X1205_REG_SCA0 0x00 - -#define X1205_CCR_BASE 0x30 /* Base address of CCR */ -#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ - -#define X1205_SR_RTCF 0x01 /* Clock failure */ -#define X1205_SR_WEL 0x02 /* Write Enable Latch */ -#define X1205_SR_RWEL 0x04 /* Register Write Enable */ - -#define X1205_DTR_DTR0 0x01 -#define X1205_DTR_DTR1 0x02 -#define X1205_DTR_DTR2 0x04 - -#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ - -static void rtc_write(int reg, u8 val) -{ - i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); -} - -/* - * In the routines that deal directly with the x1205 hardware, we use - * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch - * Epoch is initialized as 2000. Time is set to UTC. - */ -int rtc_get(struct rtc_time *tm) -{ - u8 buf[8]; - - i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); - - debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " - "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", - __FUNCTION__, - buf[0], buf[1], buf[2], buf[3], - buf[4], buf[5], buf[6], buf[7]); - - tm->tm_sec = bcd2bin(buf[CCR_SEC]); - tm->tm_min = bcd2bin(buf[CCR_MIN]); - tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ - tm->tm_mday = bcd2bin(buf[CCR_MDAY]); - tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */ - tm->tm_year = bcd2bin(buf[CCR_YEAR]) - + (bcd2bin(buf[CCR_Y2K]) * 100); - tm->tm_wday = buf[CCR_WDAY]; - - debug("%s: tm is secs=%d, mins=%d, hours=%d, " - "mday=%d, mon=%d, year=%d, wday=%d\n", - __FUNCTION__, - tm->tm_sec, tm->tm_min, tm->tm_hour, - tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); - - return 0; -} - -int rtc_set(struct rtc_time *tm) -{ - int i; - u8 buf[8]; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, - tm->tm_hour, tm->tm_min, tm->tm_sec); - - buf[CCR_SEC] = bin2bcd(tm->tm_sec); - buf[CCR_MIN] = bin2bcd(tm->tm_min); - - /* set hour and 24hr bit */ - buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL; - - buf[CCR_MDAY] = bin2bcd(tm->tm_mday); - - /* month, 1 - 12 */ - buf[CCR_MONTH] = bin2bcd(tm->tm_mon); - - /* year, since the rtc epoch*/ - buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100); - buf[CCR_WDAY] = tm->tm_wday & 0x07; - buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100); - - /* this sequence is required to unlock the chip */ - rtc_write(X1205_REG_SR, X1205_SR_WEL); - rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL); - - /* write register's data */ - for (i = 0; i < 8; i++) - rtc_write(X1205_CCR_BASE + i, buf[i]); - - rtc_write(X1205_REG_SR, 0); - - return 0; -} - -void rtc_reset(void) -{ - /* - * Nothing to do - */ -} diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index e6ab6f1b9b7..660aaab6638 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -13,7 +13,6 @@ struct uart_port { }; #if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ # define PORT_PTCR 0xA405011EUL @@ -149,7 +148,6 @@ struct uart_port { #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ #if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) # define SCIF_ORER 0x0200 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) @@ -197,7 +195,6 @@ struct uart_port { (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) #if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) @@ -278,8 +275,7 @@ static inline void sci_##name##_out(struct uart_port *port,\ SCI_OUT(sci_size, sci_offset, value);\ } -#if defined(CONFIG_SH73A0) || \ - defined(CONFIG_R8A7740) +#if defined(CONFIG_R8A7740) #if defined(CONFIG_CPU_SH7721) || \ defined(CONFIG_SH73A0) #define SCIF_FNS(name, scif_offset, scif_size) \ @@ -323,8 +319,7 @@ static inline void sci_##name##_out(struct uart_port *port,\ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #endif -#if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) +#if defined(CONFIG_CPU_SH7721) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) @@ -477,7 +472,6 @@ static inline int sci_rxd_in(struct uart_port *port) #if defined(CONFIG_CPU_SH7780) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SH7723) diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 0ed3bbf356a..40c876764af 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -20,6 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o -obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 9c04403da30..b04b6bcd779 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -19,8 +19,7 @@ obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o -obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o -obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o +0obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c deleted file mode 100644 index af43433d88d..00000000000 --- a/drivers/usb/gadget/fotg210.c +++ /dev/null @@ -1,964 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday USB 2.0 OTG Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#include <common.h> -#include <command.h> -#include <config.h> -#include <cpu_func.h> -#include <log.h> -#include <net.h> -#include <malloc.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/types.h> -#include <linux/usb/ch9.h> -#include <linux/usb/gadget.h> - -#include <usb/fotg210.h> - -#define CFG_NUM_ENDPOINTS 4 -#define CFG_EP0_MAX_PACKET_SIZE 64 -#define CFG_EPX_MAX_PACKET_SIZE 512 - -#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */ - -struct fotg210_chip; - -struct fotg210_ep { - struct usb_ep ep; - - uint maxpacket; - uint id; - uint stopped; - - struct list_head queue; - struct fotg210_chip *chip; - const struct usb_endpoint_descriptor *desc; -}; - -struct fotg210_request { - struct usb_request req; - struct list_head queue; - struct fotg210_ep *ep; -}; - -struct fotg210_chip { - struct usb_gadget gadget; - struct usb_gadget_driver *driver; - struct fotg210_regs *regs; - uint8_t irq; - uint16_t addr; - int pullup; - enum usb_device_state state; - struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS]; -}; - -static struct usb_endpoint_descriptor ep0_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_DIR_IN, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static inline int fifo_to_ep(struct fotg210_chip *chip, int id, int in) -{ - return (id < 0) ? 0 : ((id & 0x03) + 1); -} - -static inline int ep_to_fifo(struct fotg210_chip *chip, int id) -{ - return (id <= 0) ? -1 : ((id - 1) & 0x03); -} - -static inline int ep_reset(struct fotg210_chip *chip, uint8_t ep_addr) -{ - int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK; - struct fotg210_regs *regs = chip->regs; - - if (ep_addr & USB_DIR_IN) { - /* reset endpoint */ - setbits_le32(®s->iep[ep - 1], IEP_RESET); - mdelay(1); - clrbits_le32(®s->iep[ep - 1], IEP_RESET); - /* clear endpoint stall */ - clrbits_le32(®s->iep[ep - 1], IEP_STALL); - } else { - /* reset endpoint */ - setbits_le32(®s->oep[ep - 1], OEP_RESET); - mdelay(1); - clrbits_le32(®s->oep[ep - 1], OEP_RESET); - /* clear endpoint stall */ - clrbits_le32(®s->oep[ep - 1], OEP_STALL); - } - - return 0; -} - -static int fotg210_reset(struct fotg210_chip *chip) -{ - struct fotg210_regs *regs = chip->regs; - uint32_t i; - - chip->state = USB_STATE_POWERED; - - /* chip enable */ - writel(DEVCTRL_EN, ®s->dev_ctrl); - - /* device address reset */ - chip->addr = 0; - writel(0, ®s->dev_addr); - - /* set idle counter to 7ms */ - writel(7, ®s->idle); - - /* disable all interrupts */ - writel(IMR_MASK, ®s->imr); - writel(GIMR_MASK, ®s->gimr); - writel(GIMR0_MASK, ®s->gimr0); - writel(GIMR1_MASK, ®s->gimr1); - writel(GIMR2_MASK, ®s->gimr2); - - /* clear interrupts */ - writel(ISR_MASK, ®s->isr); - writel(0, ®s->gisr); - writel(0, ®s->gisr0); - writel(0, ®s->gisr1); - writel(0, ®s->gisr2); - - /* chip reset */ - setbits_le32(®s->dev_ctrl, DEVCTRL_RESET); - mdelay(10); - if (readl(®s->dev_ctrl) & DEVCTRL_RESET) { - printf("fotg210: chip reset failed\n"); - return -1; - } - - /* CX FIFO reset */ - setbits_le32(®s->cxfifo, CXFIFO_CXFIFOCLR); - mdelay(10); - if (readl(®s->cxfifo) & CXFIFO_CXFIFOCLR) { - printf("fotg210: ep0 fifo reset failed\n"); - return -1; - } - - /* create static ep-fifo map (EP1 <-> FIFO0, EP2 <-> FIFO1 ...) */ - writel(EPMAP14_DEFAULT, ®s->epmap14); - writel(EPMAP58_DEFAULT, ®s->epmap58); - writel(FIFOMAP_DEFAULT, ®s->fifomap); - writel(0, ®s->fifocfg); - for (i = 0; i < 8; ++i) { - writel(CFG_EPX_MAX_PACKET_SIZE, ®s->iep[i]); - writel(CFG_EPX_MAX_PACKET_SIZE, ®s->oep[i]); - } - - /* FIFO reset */ - for (i = 0; i < 4; ++i) { - writel(FIFOCSR_RESET, ®s->fifocsr[i]); - mdelay(10); - if (readl(®s->fifocsr[i]) & FIFOCSR_RESET) { - printf("fotg210: fifo%d reset failed\n", i); - return -1; - } - } - - /* enable only device interrupt and triggered at level-high */ - writel(IMR_IRQLH | IMR_HOST | IMR_OTG, ®s->imr); - writel(ISR_MASK, ®s->isr); - /* disable EP0 IN/OUT interrupt */ - writel(GIMR0_CXOUT | GIMR0_CXIN, ®s->gimr0); - /* disable EPX IN+SPK+OUT interrupts */ - writel(GIMR1_MASK, ®s->gimr1); - /* disable wakeup+idle+dma+zlp interrupts */ - writel(GIMR2_WAKEUP | GIMR2_IDLE | GIMR2_DMAERR | GIMR2_DMAFIN - | GIMR2_ZLPRX | GIMR2_ZLPTX, ®s->gimr2); - /* enable all group interrupt */ - writel(0, ®s->gimr); - - /* suspend delay = 3 ms */ - writel(3, ®s->idle); - - /* turn-on device interrupts */ - setbits_le32(®s->dev_ctrl, DEVCTRL_GIRQ_EN); - - return 0; -} - -static inline int fotg210_cxwait(struct fotg210_chip *chip, uint32_t mask) -{ - struct fotg210_regs *regs = chip->regs; - int ret = -1; - ulong ts; - - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { - if ((readl(®s->cxfifo) & mask) != mask) - continue; - ret = 0; - break; - } - - if (ret) - printf("fotg210: cx/ep0 timeout\n"); - - return ret; -} - -static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req) -{ - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - uint32_t tmp, ts; - uint8_t *buf = req->req.buf + req->req.actual; - uint32_t len = req->req.length - req->req.actual; - int fifo = ep_to_fifo(chip, ep->id); - int ret = -EBUSY; - - /* 1. init dma buffer */ - if (len > ep->maxpacket) - len = ep->maxpacket; - - /* 2. wait for dma ready (hardware) */ - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { - if (!(readl(®s->dma_ctrl) & DMACTRL_START)) { - ret = 0; - break; - } - } - if (ret) { - printf("fotg210: dma busy\n"); - req->req.status = ret; - return ret; - } - - /* 3. DMA target setup */ - if (ep->desc->bEndpointAddress & USB_DIR_IN) - flush_dcache_range((ulong)buf, (ulong)buf + len); - else - invalidate_dcache_range((ulong)buf, (ulong)buf + len); - - writel(virt_to_phys(buf), ®s->dma_addr); - - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - if (ep->id == 0) { - /* Wait until cx/ep0 fifo empty */ - fotg210_cxwait(chip, CXFIFO_CXFIFOE); - udelay(1); - writel(DMAFIFO_CX, ®s->dma_fifo); - } else { - /* Wait until epx fifo empty */ - fotg210_cxwait(chip, CXFIFO_FIFOE(fifo)); - writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo); - } - writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, ®s->dma_ctrl); - } else { - uint32_t blen; - - if (ep->id == 0) { - writel(DMAFIFO_CX, ®s->dma_fifo); - do { - blen = CXFIFO_BYTES(readl(®s->cxfifo)); - } while (blen < len); - } else { - writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo); - blen = FIFOCSR_BYTES(readl(®s->fifocsr[fifo])); - } - len = (len < blen) ? len : blen; - writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, ®s->dma_ctrl); - } - - /* 4. DMA start */ - setbits_le32(®s->dma_ctrl, DMACTRL_START); - - /* 5. DMA wait */ - ret = -EBUSY; - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { - tmp = readl(®s->gisr2); - /* DMA complete */ - if (tmp & GISR2_DMAFIN) { - ret = 0; - break; - } - /* DMA error */ - if (tmp & GISR2_DMAERR) { - printf("fotg210: dma error\n"); - break; - } - /* resume, suspend, reset */ - if (tmp & (GISR2_RESUME | GISR2_SUSPEND | GISR2_RESET)) { - printf("fotg210: dma reset by host\n"); - break; - } - } - - /* 7. DMA target reset */ - if (ret) - writel(DMACTRL_ABORT | DMACTRL_CLRFF, ®s->dma_ctrl); - - writel(0, ®s->gisr2); - writel(0, ®s->dma_fifo); - - req->req.status = ret; - if (!ret) - req->req.actual += len; - else - printf("fotg210: ep%d dma error(code=%d)\n", ep->id, ret); - - return len; -} - -/* - * result of setup packet - */ -#define CX_IDLE 0 -#define CX_FINISH 1 -#define CX_STALL 2 - -static void fotg210_setup(struct fotg210_chip *chip) -{ - int id, ret = CX_IDLE; - uint32_t tmp[2]; - struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)tmp; - struct fotg210_regs *regs = chip->regs; - - /* - * If this is the first Cx 8 byte command, - * we can now query USB mode (high/full speed; USB 2.0/USB 1.0) - */ - if (chip->state == USB_STATE_POWERED) { - chip->state = USB_STATE_DEFAULT; - if (readl(®s->otgcsr) & OTGCSR_DEV_B) { - /* Mini-B */ - if (readl(®s->dev_ctrl) & DEVCTRL_HS) { - puts("fotg210: HS\n"); - chip->gadget.speed = USB_SPEED_HIGH; - /* SOF mask timer = 1100 ticks */ - writel(SOFMTR_TMR(1100), ®s->sof_mtr); - } else { - puts("fotg210: FS\n"); - chip->gadget.speed = USB_SPEED_FULL; - /* SOF mask timer = 10000 ticks */ - writel(SOFMTR_TMR(10000), ®s->sof_mtr); - } - } else { - printf("fotg210: mini-A?\n"); - } - } - - /* switch data port to ep0 */ - writel(DMAFIFO_CX, ®s->dma_fifo); - /* fetch 8 bytes setup packet */ - tmp[0] = readl(®s->ep0_data); - tmp[1] = readl(®s->ep0_data); - /* release data port */ - writel(0, ®s->dma_fifo); - - if (req->bRequestType & USB_DIR_IN) - ep0_desc.bEndpointAddress = USB_DIR_IN; - else - ep0_desc.bEndpointAddress = USB_DIR_OUT; - - ret = CX_IDLE; - - if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { - switch (req->bRequest) { - case USB_REQ_SET_CONFIGURATION: - debug("fotg210: set_cfg(%d)\n", req->wValue & 0x00FF); - if (!(req->wValue & 0x00FF)) { - chip->state = USB_STATE_ADDRESS; - writel(chip->addr, ®s->dev_addr); - } else { - chip->state = USB_STATE_CONFIGURED; - writel(chip->addr | DEVADDR_CONF, - ®s->dev_addr); - } - ret = CX_IDLE; - break; - - case USB_REQ_SET_ADDRESS: - debug("fotg210: set_addr(0x%04X)\n", req->wValue); - chip->state = USB_STATE_ADDRESS; - chip->addr = req->wValue & DEVADDR_ADDR_MASK; - ret = CX_FINISH; - writel(chip->addr, ®s->dev_addr); - break; - - case USB_REQ_CLEAR_FEATURE: - debug("fotg210: clr_feature(%d, %d)\n", - req->bRequestType & 0x03, req->wValue); - switch (req->wValue) { - case 0: /* [Endpoint] halt */ - ep_reset(chip, req->wIndex); - ret = CX_FINISH; - break; - case 1: /* [Device] remote wake-up */ - case 2: /* [Device] test mode */ - default: - ret = CX_STALL; - break; - } - break; - - case USB_REQ_SET_FEATURE: - debug("fotg210: set_feature(%d, %d)\n", - req->wValue, req->wIndex & 0xf); - switch (req->wValue) { - case 0: /* Endpoint Halt */ - id = req->wIndex & 0xf; - setbits_le32(®s->iep[id - 1], IEP_STALL); - setbits_le32(®s->oep[id - 1], OEP_STALL); - ret = CX_FINISH; - break; - case 1: /* Remote Wakeup */ - case 2: /* Test Mode */ - default: - ret = CX_STALL; - break; - } - break; - - case USB_REQ_GET_STATUS: - debug("fotg210: get_status\n"); - ret = CX_STALL; - break; - - case USB_REQ_SET_DESCRIPTOR: - debug("fotg210: set_descriptor\n"); - ret = CX_STALL; - break; - - case USB_REQ_SYNCH_FRAME: - debug("fotg210: sync frame\n"); - ret = CX_STALL; - break; - } - } /* if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) */ - - if (ret == CX_IDLE && chip->driver->setup) { - if (chip->driver->setup(&chip->gadget, req) < 0) - ret = CX_STALL; - else - ret = CX_FINISH; - } - - switch (ret) { - case CX_FINISH: - setbits_le32(®s->cxfifo, CXFIFO_CXFIN); - break; - - case CX_STALL: - setbits_le32(®s->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN); - printf("fotg210: cx_stall!\n"); - break; - - case CX_IDLE: - debug("fotg210: cx_idle?\n"); - default: - break; - } -} - -/* - * fifo - FIFO id - * zlp - zero length packet - */ -static void fotg210_recv(struct fotg210_chip *chip, int ep_id) -{ - struct fotg210_regs *regs = chip->regs; - struct fotg210_ep *ep = chip->ep + ep_id; - struct fotg210_request *req; - int len; - - if (ep->stopped || (ep->desc->bEndpointAddress & USB_DIR_IN)) { - printf("fotg210: ep%d recv, invalid!\n", ep->id); - return; - } - - if (list_empty(&ep->queue)) { - printf("fotg210: ep%d recv, drop!\n", ep->id); - return; - } - - req = list_first_entry(&ep->queue, struct fotg210_request, queue); - len = fotg210_dma(ep, req); - if (len < ep->ep.maxpacket || req->req.length <= req->req.actual) { - list_del_init(&req->queue); - if (req->req.complete) - req->req.complete(&ep->ep, &req->req); - } - - if (ep->id > 0 && list_empty(&ep->queue)) { - setbits_le32(®s->gimr1, - GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id))); - } -} - -/* - * USB Gadget Layer - */ -static int fotg210_ep_enable( - struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - int id = ep_to_fifo(chip, ep->id); - int in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0; - - if (!_ep || !desc - || desc->bDescriptorType != USB_DT_ENDPOINT - || le16_to_cpu(desc->wMaxPacketSize) == 0) { - printf("fotg210: bad ep or descriptor\n"); - return -EINVAL; - } - - ep->desc = desc; - ep->stopped = 0; - - if (in) - setbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_IN)); - - switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { - case USB_ENDPOINT_XFER_CONTROL: - return -EINVAL; - - case USB_ENDPOINT_XFER_ISOC: - setbits_le32(®s->fifocfg, - FIFOCFG(id, FIFOCFG_EN | FIFOCFG_ISOC)); - break; - - case USB_ENDPOINT_XFER_BULK: - setbits_le32(®s->fifocfg, - FIFOCFG(id, FIFOCFG_EN | FIFOCFG_BULK)); - break; - - case USB_ENDPOINT_XFER_INT: - setbits_le32(®s->fifocfg, - FIFOCFG(id, FIFOCFG_EN | FIFOCFG_INTR)); - break; - } - - return 0; -} - -static int fotg210_ep_disable(struct usb_ep *_ep) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - int id = ep_to_fifo(chip, ep->id); - - ep->desc = NULL; - ep->stopped = 1; - - clrbits_le32(®s->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK)); - clrbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK)); - - return 0; -} - -static struct usb_request *fotg210_ep_alloc_request( - struct usb_ep *_ep, gfp_t gfp_flags) -{ - struct fotg210_request *req = malloc(sizeof(*req)); - - if (req) { - memset(req, 0, sizeof(*req)); - INIT_LIST_HEAD(&req->queue); - } - return &req->req; -} - -static void fotg210_ep_free_request( - struct usb_ep *_ep, struct usb_request *_req) -{ - struct fotg210_request *req; - - req = container_of(_req, struct fotg210_request, req); - free(req); -} - -static int fotg210_ep_queue( - struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - struct fotg210_request *req; - - req = container_of(_req, struct fotg210_request, req); - if (!_req || !_req->complete || !_req->buf - || !list_empty(&req->queue)) { - printf("fotg210: invalid request to ep%d\n", ep->id); - return -EINVAL; - } - - if (!chip || chip->state == USB_STATE_SUSPENDED) { - printf("fotg210: request while chip suspended\n"); - return -EINVAL; - } - - req->req.actual = 0; - req->req.status = -EINPROGRESS; - - if (req->req.length == 0) { - req->req.status = 0; - if (req->req.complete) - req->req.complete(&ep->ep, &req->req); - return 0; - } - - if (ep->id == 0) { - do { - int len = fotg210_dma(ep, req); - if (len < ep->ep.maxpacket) - break; - if (ep->desc->bEndpointAddress & USB_DIR_IN) - udelay(100); - } while (req->req.length > req->req.actual); - } else { - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - do { - int len = fotg210_dma(ep, req); - if (len < ep->ep.maxpacket) - break; - } while (req->req.length > req->req.actual); - } else { - list_add_tail(&req->queue, &ep->queue); - clrbits_le32(®s->gimr1, - GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id))); - } - } - - if (ep->id == 0 || (ep->desc->bEndpointAddress & USB_DIR_IN)) { - if (req->req.complete) - req->req.complete(&ep->ep, &req->req); - } - - return 0; -} - -static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_request *req; - - /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; - } - if (&req->req != _req) - return -EINVAL; - - /* remove the request */ - list_del_init(&req->queue); - - /* update status & invoke complete callback */ - if (req->req.status == -EINPROGRESS) { - req->req.status = -ECONNRESET; - if (req->req.complete) - req->req.complete(_ep, &req->req); - } - - return 0; -} - -static int fotg210_ep_halt(struct usb_ep *_ep, int halt) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - int ret = -1; - - debug("fotg210: ep%d halt=%d\n", ep->id, halt); - - /* Endpoint STALL */ - if (ep->id > 0 && ep->id <= CFG_NUM_ENDPOINTS) { - if (halt) { - /* wait until all ep fifo empty */ - fotg210_cxwait(chip, 0xf00); - /* stall */ - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - setbits_le32(®s->iep[ep->id - 1], - IEP_STALL); - } else { - setbits_le32(®s->oep[ep->id - 1], - OEP_STALL); - } - } else { - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - clrbits_le32(®s->iep[ep->id - 1], - IEP_STALL); - } else { - clrbits_le32(®s->oep[ep->id - 1], - OEP_STALL); - } - } - ret = 0; - } - - return ret; -} - -/* - * activate/deactivate link with host. - */ -static void pullup(struct fotg210_chip *chip, int is_on) -{ - struct fotg210_regs *regs = chip->regs; - - if (is_on) { - if (!chip->pullup) { - chip->state = USB_STATE_POWERED; - chip->pullup = 1; - /* enable the chip */ - setbits_le32(®s->dev_ctrl, DEVCTRL_EN); - /* clear unplug bit (BIT0) */ - clrbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG); - } - } else { - chip->state = USB_STATE_NOTATTACHED; - chip->pullup = 0; - chip->addr = 0; - writel(chip->addr, ®s->dev_addr); - /* set unplug bit (BIT0) */ - setbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG); - /* disable the chip */ - clrbits_le32(®s->dev_ctrl, DEVCTRL_EN); - } -} - -static int fotg210_pullup(struct usb_gadget *_gadget, int is_on) -{ - struct fotg210_chip *chip; - - chip = container_of(_gadget, struct fotg210_chip, gadget); - - debug("fotg210: pullup=%d\n", is_on); - - pullup(chip, is_on); - - return 0; -} - -static int fotg210_get_frame(struct usb_gadget *_gadget) -{ - struct fotg210_chip *chip; - struct fotg210_regs *regs; - - chip = container_of(_gadget, struct fotg210_chip, gadget); - regs = chip->regs; - - return SOFFNR_FNR(readl(®s->sof_fnr)); -} - -static struct usb_gadget_ops fotg210_gadget_ops = { - .get_frame = fotg210_get_frame, - .pullup = fotg210_pullup, -}; - -static struct usb_ep_ops fotg210_ep_ops = { - .enable = fotg210_ep_enable, - .disable = fotg210_ep_disable, - .queue = fotg210_ep_queue, - .dequeue = fotg210_ep_dequeue, - .set_halt = fotg210_ep_halt, - .alloc_request = fotg210_ep_alloc_request, - .free_request = fotg210_ep_free_request, -}; - -static struct fotg210_chip controller = { - .regs = (void __iomem *)CONFIG_FOTG210_BASE, - .gadget = { - .name = "fotg210_udc", - .ops = &fotg210_gadget_ops, - .ep0 = &controller.ep[0].ep, - .speed = USB_SPEED_UNKNOWN, - .is_dualspeed = 1, - .is_otg = 0, - .is_a_peripheral = 0, - .b_hnp_enable = 0, - .a_hnp_support = 0, - .a_alt_hnp_support = 0, - }, - .ep[0] = { - .id = 0, - .ep = { - .name = "ep0", - .ops = &fotg210_ep_ops, - }, - .desc = &ep0_desc, - .chip = &controller, - .maxpacket = CFG_EP0_MAX_PACKET_SIZE, - }, - .ep[1] = { - .id = 1, - .ep = { - .name = "ep1", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, - .ep[2] = { - .id = 2, - .ep = { - .name = "ep2", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, - .ep[3] = { - .id = 3, - .ep = { - .name = "ep3", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, - .ep[4] = { - .id = 4, - .ep = { - .name = "ep4", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, -}; - -int usb_gadget_handle_interrupts(int index) -{ - struct fotg210_chip *chip = &controller; - struct fotg210_regs *regs = chip->regs; - uint32_t id, st, isr, gisr; - - isr = readl(®s->isr) & (~readl(®s->imr)); - gisr = readl(®s->gisr) & (~readl(®s->gimr)); - if (!(isr & ISR_DEV) || !gisr) - return 0; - - writel(ISR_DEV, ®s->isr); - - /* CX interrupts */ - if (gisr & GISR_GRP0) { - st = readl(®s->gisr0); - /* - * Write 1 and then 0 works for both W1C & RW. - * - * HW v1.11.0+: It's a W1C register (write 1 clear) - * HW v1.10.0-: It's a R/W register (write 0 clear) - */ - writel(st & GISR0_CXABORT, ®s->gisr0); - writel(0, ®s->gisr0); - - if (st & GISR0_CXERR) - printf("fotg210: cmd error\n"); - - if (st & GISR0_CXABORT) - printf("fotg210: cmd abort\n"); - - if (st & GISR0_CXSETUP) /* setup */ - fotg210_setup(chip); - else if (st & GISR0_CXEND) /* command finish */ - setbits_le32(®s->cxfifo, CXFIFO_CXFIN); - } - - /* FIFO interrupts */ - if (gisr & GISR_GRP1) { - st = readl(®s->gisr1); - for (id = 0; id < 4; ++id) { - if (st & GISR1_RX_FIFO(id)) - fotg210_recv(chip, fifo_to_ep(chip, id, 0)); - } - } - - /* Device Status Interrupts */ - if (gisr & GISR_GRP2) { - st = readl(®s->gisr2); - /* - * Write 1 and then 0 works for both W1C & RW. - * - * HW v1.11.0+: It's a W1C register (write 1 clear) - * HW v1.10.0-: It's a R/W register (write 0 clear) - */ - writel(st, ®s->gisr2); - writel(0, ®s->gisr2); - - if (st & GISR2_RESET) - printf("fotg210: reset by host\n"); - else if (st & GISR2_SUSPEND) - printf("fotg210: suspend/removed\n"); - else if (st & GISR2_RESUME) - printf("fotg210: resume\n"); - - /* Errors */ - if (st & GISR2_ISOCERR) - printf("fotg210: iso error\n"); - if (st & GISR2_ISOCABT) - printf("fotg210: iso abort\n"); - if (st & GISR2_DMAERR) - printf("fotg210: dma error\n"); - } - - return 0; -} - -int usb_gadget_register_driver(struct usb_gadget_driver *driver) -{ - int i, ret = 0; - struct fotg210_chip *chip = &controller; - - if (!driver || !driver->bind || !driver->setup) { - puts("fotg210: bad parameter.\n"); - return -EINVAL; - } - - INIT_LIST_HEAD(&chip->gadget.ep_list); - for (i = 0; i < CFG_NUM_ENDPOINTS + 1; ++i) { - struct fotg210_ep *ep = chip->ep + i; - - ep->ep.maxpacket = ep->maxpacket; - INIT_LIST_HEAD(&ep->queue); - - if (ep->id == 0) { - ep->stopped = 0; - } else { - ep->stopped = 1; - list_add_tail(&ep->ep.ep_list, &chip->gadget.ep_list); - } - } - - if (fotg210_reset(chip)) { - puts("fotg210: reset failed.\n"); - return -EINVAL; - } - - ret = driver->bind(&chip->gadget); - if (ret) { - debug("fotg210: driver->bind() returned %d\n", ret); - return ret; - } - chip->driver = driver; - - return ret; -} - -int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -{ - struct fotg210_chip *chip = &controller; - - driver->unbind(&chip->gadget); - chip->driver = NULL; - - pullup(chip, 0); - - return 0; -} diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index abc6dc7f89f..98156c312d2 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -117,12 +117,6 @@ #define gadget_is_ci(g) 0 #endif -#ifdef CONFIG_USB_GADGET_FOTG210 -#define gadget_is_fotg210(g) (!strcmp("fotg210_udc", (g)->name)) -#else -#define gadget_is_fotg210(g) 0 -#endif - #ifdef CONFIG_USB_DWC3_GADGET #define gadget_is_dwc3(g) (!strcmp("dwc3-gadget", (g)->name)) #else @@ -202,8 +196,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x20; else if (gadget_is_ci(gadget)) return 0x21; - else if (gadget_is_fotg210(gadget)) - return 0x22; else if (gadget_is_dwc3(gadget)) return 0x23; else if (gadget_is_cdns3(gadget)) diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index ddc36632069..8dad36f9369 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -17,7 +17,6 @@ obj-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o obj-$(CONFIG_USB_ATMEL) += ohci-at91.o obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o -obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o @@ -25,10 +24,8 @@ obj-$(CONFIG_USB_OHCI_NPCM) += ohci-npcm.o # echi obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o -obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o -obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o @@ -41,9 +38,7 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o -obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o -obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c deleted file mode 100644 index 2ce9f27b862..00000000000 --- a/drivers/usb/host/ehci-armada100.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact@8051projects.net> - * - * This driver is based on Kirkwood echi driver - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <usb.h> -#include "ehci.h" -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> -#include <asm/arch/utmi-armada100.h> - -/* - * EHCI host controller init - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - if (utmi_init() < 0) - return -1; - - *hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - return 0; -} - -/* - * EHCI host controller stop - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c deleted file mode 100644 index 85a35269601..00000000000 --- a/drivers/usb/host/ehci-faraday.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <usb.h> -#include <linux/delay.h> -#include <usb/fusbh200.h> -#include <usb/fotg210.h> - -#include "ehci.h" - -#ifndef CFG_USB_EHCI_BASE_LIST -#define CFG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE } -#endif - -union ehci_faraday_regs { - struct fusbh200_regs usb; - struct fotg210_regs otg; -}; - -static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs) -{ - return !readl(®s->usb.easstr); -} - -void faraday_ehci_set_usbmode(struct ehci_ctrl *ctrl) -{ - /* nothing needs to be done */ -} - -int faraday_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) -{ - int spd, ret = PORTSC_PSPD_HS; - union ehci_faraday_regs *regs; - - ret = (void __iomem *)((ulong)ctrl->hcor - 0x10); - if (ehci_is_fotg2xx(regs)) - spd = OTGCSR_SPD(readl(®s->otg.otgcsr)); - else - spd = BMCSR_SPD(readl(®s->usb.bmcsr)); - - switch (spd) { - case 0: /* full speed */ - ret = PORTSC_PSPD_FS; - break; - case 1: /* low speed */ - ret = PORTSC_PSPD_LS; - break; - case 2: /* high speed */ - ret = PORTSC_PSPD_HS; - break; - default: - printf("ehci-faraday: invalid device speed\n"); - break; - } - - return ret; -} - -uint32_t *faraday_ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) -{ - /* Faraday EHCI has one and only one portsc register */ - if (port) { - /* Printing the message would cause a scan failure! */ - debug("The request port(%d) is not configured\n", port); - return NULL; - } - - /* Faraday EHCI PORTSC register offset is 0x20 from hcor */ - return (uint32_t *)((uint8_t *)ctrl->hcor + 0x20); -} - -static const struct ehci_ops faraday_ehci_ops = { - .set_usb_mode = faraday_ehci_set_usbmode, - .get_port_speed = faraday_ehci_get_port_speed, - .get_portsc_register = faraday_ehci_get_portsc_register, -}; - -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) -{ - struct ehci_hccr *hccr; - struct ehci_hcor *hcor; - union ehci_faraday_regs *regs; - uint32_t base_list[] = CFG_USB_EHCI_BASE_LIST; - - if (index < 0 || index >= ARRAY_SIZE(base_list)) - return -1; - ehci_set_controller_priv(index, NULL, &faraday_ehci_ops); - regs = (void __iomem *)base_list[index]; - hccr = (struct ehci_hccr *)®s->usb.hccr; - hcor = (struct ehci_hcor *)®s->usb.hcor; - - if (ehci_is_fotg2xx(regs)) { - /* A-device bus reset */ - /* ... Power off A-device */ - setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP); - /* ... Drop vbus and bus traffic */ - clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ); - mdelay(1); - /* ... Power on A-device */ - clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP); - /* ... Drive vbus and bus traffic */ - setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ); - mdelay(1); - /* Disable OTG & DEV interrupts, triggered at level-high */ - writel(IMR_IRQLH | IMR_OTG | IMR_DEV, ®s->otg.imr); - /* Clear all interrupt status */ - writel(ISR_HOST | ISR_OTG | ISR_DEV, ®s->otg.isr); - } else { - /* Interrupt=level-high */ - setbits_le32(®s->usb.bmcsr, BMCSR_IRQLH); - /* VBUS on */ - clrbits_le32(®s->usb.bmcsr, BMCSR_VBUS_OFF); - /* Disable all interrupts */ - writel(0x00, ®s->usb.bmier); - writel(0x1f, ®s->usb.bmisr); - } - - *ret_hccr = hccr; - *ret_hcor = hcor; - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 9139d61dd0c..9839aa17492 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -705,12 +705,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken); } else { dev->act_len = 0; -#ifndef CONFIG_USB_EHCI_FARADAY debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), ehci_readl(&ctrl->hcor->or_portsc[0]), ehci_readl(&ctrl->hcor->or_portsc[1])); -#endif } free(qtd); @@ -1190,9 +1188,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) if (rc) return rc; #endif -#ifdef CONFIG_USB_EHCI_FARADAY - tweaks |= EHCI_TWEAK_NO_INIT_CF; -#endif rc = ehci_common_init(ctrl, tweaks); if (rc) return rc; diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c deleted file mode 100644 index 60525f22867..00000000000 --- a/drivers/usb/host/ehci-rmobile.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * EHCI HCD (Host Controller Driver) for USB. - * - * Copyright (C) 2013,2014 Renesas Electronics Corporation - * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/ehci-rmobile.h> -#include <linux/delay.h> -#include "ehci.h" - -#if defined(CONFIG_R8A7740) -static u32 usb_base_address[] = { - 0xC6700000 -}; -#elif defined(CONFIG_R8A7790) -static u32 usb_base_address[] = { - 0xEE080000, /* USB0 (EHCI) */ - 0xEE0A0000, /* USB1 */ - 0xEE0C0000, /* USB2 */ -}; -#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) -static u32 usb_base_address[] = { - 0xEE080000, /* USB0 (EHCI) */ - 0xEE0C0000, /* USB1 */ -}; -#else -#error rmobile EHCI USB driver not supported on this platform -#endif - -int ehci_hcd_stop(int index) -{ - int i; - u32 base; - struct ahbcom_pci_bridge *ahbcom_pci; - - base = usb_base_address[index]; - ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); - writel(0, &ahbcom_pci->ahb_bus_ctr); - - /* reset ehci */ - setbits_le32(base + EHCI_USBCMD, CMD_RESET); - for (i = 100; i > 0; i--) { - if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) - break; - udelay(100); - } - - if (!i) - printf("error : ehci(%d) reset failed.\n", index); - - if (index == (ARRAY_SIZE(usb_base_address) - 1)) - setbits_le32(SMSTPCR7, SMSTPCR703); - - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - u32 base; - u32 phys_base; - struct rmobile_ehci_reg *rehci; - struct ahbcom_pci_bridge *ahbcom_pci; - struct ahbconf_pci_bridge *ahbconf_pci; - struct ahb_pciconf *ahb_pciconf_ohci; - struct ahb_pciconf *ahb_pciconf_ehci; - uint32_t cap_base; - - base = usb_base_address[index]; - phys_base = base; - if (index == 0) - clrbits_le32(SMSTPCR7, SMSTPCR703); - - rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); - ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); - ahbconf_pci = - (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); - ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); - ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); - - /* Clock & Reset & Direct Power Down */ - clrsetbits_le32(&ahbcom_pci->usbctr, - (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); - clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); - - /* AHB-PCI Bridge Communication Registers */ - writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); - writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, - &ahbcom_pci->pciahb_win1_ctr); - writel(0xf0000000 | PCIAHB_WIN_PREFETCH, - &ahbcom_pci->pciahb_win2_ctr); - writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); - - setbits_le32(&ahbcom_pci->pci_arbiter_ctr, - PCIBP_MODE | PCIREQ1 | PCIREQ0); - - /* PCI Configuration Registers for AHBPCI */ - writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, - &ahbcom_pci->ahbpci_win1_ctr); - writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); - writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); - writel(0xf0000000, &ahbconf_pci->win2_basead); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahbconf_pci->cmnd_sts); - - /* PCI Configuration Registers for EHCI */ - writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); - writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); - writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahb_pciconf_ohci->cmnd_sts); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahb_pciconf_ehci->cmnd_sts); - - /* Enable PCI interrupt */ - setbits_le32(&ahbcom_pci->pci_int_enable, - USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); - - *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); - cap_base = ehci_readl(&(*hccr)->cr_capbase); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); - - return 0; -} diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c deleted file mode 100644 index 7167f82b481..00000000000 --- a/drivers/usb/host/ehci-vct.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#include <common.h> -#include <usb.h> - -#include "ehci.h" - -int vct_ehci_hcd_init(u32 *hccr, u32 *hcor); - -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - int ret; - u32 vct_hccr; - u32 vct_hcor; - - /* - * Init VCT specific stuff - */ - ret = vct_ehci_hcd_init(&vct_hccr, &vct_hcor); - if (ret) - return ret; - - *hccr = (struct ehci_hccr *)vct_hccr; - *hcor = (struct ehci_hcor *)vct_hcor; - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c deleted file mode 100644 index 7c823f241a8..00000000000 --- a/drivers/usb/host/sl811-hcd.c +++ /dev/null @@ -1,714 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This code is based on linux driver for sl811hs chip, source at - * drivers/usb/host/sl811.c: - * - * SL811 Host Controller Interface driver for USB. - * - * Copyright (c) 2003/06, Courage Co., Ltd. - * - * Based on: - * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap, - * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, - * Adam Richter, Gregory P. Smith; - * 2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com> - * 3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn> - */ - -#include <common.h> -#include <mpc8xx.h> -#include <usb.h> -#include <linux/delay.h> -#include "sl811.h" - -#include "../../../board/kup/common/kup.h" - -#ifdef __PPC__ -# define EIEIO __asm__ volatile ("eieio") -#else -# define EIEIO /* nothing */ -#endif - -#define SL811_ADR (0x50000000) -#define SL811_DAT (0x50000001) - -#ifdef SL811_DEBUG -static int debug = 9; -#endif - -static int root_hub_devnum = 0; -static struct usb_port_status rh_status = { 0 };/* root hub port status */ - -static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, - void *data, int buf_len, struct devrequest *cmd); - -static void sl811_write (__u8 index, __u8 data) -{ - *(volatile unsigned char *) (SL811_ADR) = index; - EIEIO; - *(volatile unsigned char *) (SL811_DAT) = data; - EIEIO; -} - -static __u8 sl811_read (__u8 index) -{ - __u8 data; - - *(volatile unsigned char *) (SL811_ADR) = index; - EIEIO; - data = *(volatile unsigned char *) (SL811_DAT); - EIEIO; - return (data); -} - -/* - * Read consecutive bytes of data from the SL811H/SL11H buffer - */ -static void inline sl811_read_buf(__u8 offset, __u8 *buf, __u8 size) -{ - *(volatile unsigned char *) (SL811_ADR) = offset; - EIEIO; - while (size--) { - *buf++ = *(volatile unsigned char *) (SL811_DAT); - EIEIO; - } -} - -/* - * Write consecutive bytes of data to the SL811H/SL11H buffer - */ -static void inline sl811_write_buf(__u8 offset, __u8 *buf, __u8 size) -{ - *(volatile unsigned char *) (SL811_ADR) = offset; - EIEIO; - while (size--) { - *(volatile unsigned char *) (SL811_DAT) = *buf++; - EIEIO; - } -} - -int usb_init_kup4x (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int i; - unsigned char tmp; - - memctl = &immap->im_memctl; - memctl->memc_or7 = 0xFFFF8726; - memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ - /* BP 14 low = USB ON */ - immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC); - /* PB 14 nomal port */ - immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC); - /* output */ - immap->im_cpm.cp_pbdir |= (BP_USB_VCC); - - puts ("USB: "); - - for (i = 0x10; i < 0xff; i++) { - sl811_write(i, i); - tmp = (sl811_read(i)); - if (tmp != i) { - printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp); - return (-1); - } - } - printf ("SL811 ready\n"); - return (0); -} - -/* - * This function resets SL811HS controller and detects the speed of - * the connecting device - * - * Return: 0 = no device attached; 1 = USB device attached - */ -static int sl811_hc_reset(void) -{ - int status ; - - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - - mdelay(20); - - /* Disable hardware SOF generation, clear all irq status. */ - sl811_write(SL811_CTRL1, 0); - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - status = sl811_read(SL811_INTRSTS); - - if (status & SL811_INTR_NOTPRESENT) { - /* Device is not present */ - PDEBUG(0, "Device not present\n"); - rh_status.wPortStatus &= ~(USB_PORT_STAT_CONNECTION | USB_PORT_STAT_ENABLE); - rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; - sl811_write(SL811_INTR, SL811_INTR_INSRMV); - return 0; - } - - /* Send SOF to address 0, endpoint 0. */ - sl811_write(SL811_LEN_B, 0); - sl811_write(SL811_PIDEP_B, PIDEP(USB_PID_SOF, 0)); - sl811_write(SL811_DEV_B, 0x00); - sl811_write(SL811_SOFLOW, SL811_12M_LOW); - - if (status & SL811_INTR_SPEED_FULL) { - /* full speed device connect directly to root hub */ - PDEBUG (0, "Full speed Device attached\n"); - - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - mdelay(20); - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_SOF); - - /* start the SOF or EOP */ - sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); - rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION; - rh_status.wPortStatus &= ~USB_PORT_STAT_LOW_SPEED; - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - } else { - /* slow speed device connect directly to root-hub */ - PDEBUG(0, "Low speed Device attached\n"); - - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - mdelay(20); - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_CTL2_DSWAP | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_SPEED_LOW | SL811_CTRL1_SOF); - - /* start the SOF or EOP */ - sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); - rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION | USB_PORT_STAT_LOW_SPEED; - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - } - - rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; - sl811_write(SL811_INTR, /*SL811_INTR_INSRMV*/SL811_INTR_DONE_A); - - return 1; -} - -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - root_hub_devnum = 0; - sl811_hc_reset(); - return 0; -} - -int usb_lowlevel_stop(int index) -{ - sl811_hc_reset(); - return 0; -} - -static int calc_needed_buswidth(int bytes, int need_preamble) -{ - return !need_preamble ? bytes * 8 + 256 : 8 * 8 * bytes + 2048; -} - -static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *buffer, int len) -{ - __u8 ctrl = SL811_USB_CTRL_ARM | SL811_USB_CTRL_ENABLE; - __u16 status = 0; - int err = 0, time_start = get_timer(0); - int need_preamble = !(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && - (dev->speed == USB_SPEED_LOW); - - if (len > 239) - return -1; - - if (usb_pipeout(pipe)) - ctrl |= SL811_USB_CTRL_DIR_OUT; - if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) - ctrl |= SL811_USB_CTRL_TOGGLE_1; - if (need_preamble) - ctrl |= SL811_USB_CTRL_PREAMBLE; - - sl811_write(SL811_INTRSTS, 0xff); - - while (err < 3) { - sl811_write(SL811_ADDR_A, 0x10); - sl811_write(SL811_LEN_A, len); - if (usb_pipeout(pipe) && len) - sl811_write_buf(0x10, buffer, len); - - if (!(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && - sl811_read(SL811_SOFCNTDIV)*64 < calc_needed_buswidth(len, need_preamble)) - ctrl |= SL811_USB_CTRL_SOF; - else - ctrl &= ~SL811_USB_CTRL_SOF; - - sl811_write(SL811_CTRL_A, ctrl); - while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) { - if (5*CONFIG_SYS_HZ < get_timer(time_start)) { - printf("USB transmit timed out\n"); - return -USB_ST_CRC_ERR; - } - } - - sl811_write(SL811_INTRSTS, 0xff); - status = sl811_read(SL811_STS_A); - - if (status & SL811_USB_STS_ACK) { - int remainder = sl811_read(SL811_CNT_A); - if (remainder) { - PDEBUG(0, "usb transfer remainder = %d\n", remainder); - len -= remainder; - } - if (usb_pipein(pipe) && len) - sl811_read_buf(0x10, buffer, len); - return len; - } - - if ((status & SL811_USB_STS_NAK) == SL811_USB_STS_NAK) - continue; - - PDEBUG(0, "usb transfer error %#x\n", (int)status); - err++; - } - - err = 0; - - if (status & SL811_USB_STS_ERROR) - err |= USB_ST_BUF_ERR; - if (status & SL811_USB_STS_TIMEOUT) - err |= USB_ST_CRC_ERR; - if (status & SL811_USB_STS_STALL) - err |= USB_ST_STALLED; - - return -err; -} - -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len) -{ - int dir_out = usb_pipeout(pipe); - int ep = usb_pipeendpoint(pipe); - int max = usb_maxpacket(dev, pipe); - int done = 0; - - PDEBUG(7, "dev = %ld pipe = %ld buf = %p size = %d dir_out = %d\n", - usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out); - - dev->status = 0; - - sl811_write(SL811_DEV_A, usb_pipedevice(pipe)); - sl811_write(SL811_PIDEP_A, PIDEP(!dir_out ? USB_PID_IN : USB_PID_OUT, ep)); - while (done < len) { - int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, - max > len - done ? len - done : max); - if (res < 0) { - dev->status = -res; - return res; - } - - if (!dir_out && res < max) /* short packet */ - break; - - done += res; - usb_dotoggle(dev, ep, dir_out); - } - - dev->act_len = done; - - return 0; -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len,struct devrequest *setup) -{ - int done = 0; - int devnum = usb_pipedevice(pipe); - int ep = usb_pipeendpoint(pipe); - - dev->status = 0; - - if (devnum == root_hub_devnum) - return sl811_rh_submit_urb(dev, pipe, buffer, len, setup); - - PDEBUG(7, "dev = %d pipe = %ld buf = %p size = %d rt = %#x req = %#x bus = %i\n", - devnum, ep, buffer, len, (int)setup->requesttype, - (int)setup->request, sl811_read(SL811_SOFCNTDIV)*64); - - sl811_write(SL811_DEV_A, devnum); - sl811_write(SL811_PIDEP_A, PIDEP(USB_PID_SETUP, ep)); - /* setup phase */ - usb_settoggle(dev, ep, 1, 0); - if (sl811_send_packet(dev, usb_sndctrlpipe(dev, ep), - (__u8*)setup, sizeof(*setup)) == sizeof(*setup)) { - int dir_in = usb_pipein(pipe); - int max = usb_maxpacket(dev, pipe); - - /* data phase */ - sl811_write(SL811_PIDEP_A, - PIDEP(dir_in ? USB_PID_IN : USB_PID_OUT, ep)); - usb_settoggle(dev, ep, usb_pipeout(pipe), 1); - while (done < len) { - int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, - max > len - done ? len - done : max); - if (res < 0) { - PDEBUG(0, "status data failed!\n"); - dev->status = -res; - return 0; - } - done += res; - usb_dotoggle(dev, ep, usb_pipeout(pipe)); - if (dir_in && res < max) /* short packet */ - break; - } - - /* status phase */ - sl811_write(SL811_PIDEP_A, - PIDEP(!dir_in ? USB_PID_IN : USB_PID_OUT, ep)); - usb_settoggle(dev, ep, !usb_pipeout(pipe), 1); - if (sl811_send_packet(dev, - !dir_in ? usb_rcvctrlpipe(dev, ep) : - usb_sndctrlpipe(dev, ep), - 0, 0) < 0) { - PDEBUG(0, "status phase failed!\n"); - dev->status = -1; - } - } else { - PDEBUG(0, "setup phase failed!\n"); - dev->status = -1; - } - - dev->act_len = done; - - return done; -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len, int interval, bool nonblock) -{ - PDEBUG(0, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe, - buffer, len, interval); - return -1; -} - -/* - * SL811 Virtual Root Hub - */ - -/* Device descriptor */ -static __u8 sl811_rh_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x02, /* __u8 iProduct; */ - 0x01, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 sl811_rh_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, - 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -/* root hub class descriptor*/ -static __u8 sl811_rh_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x01, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x50, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0xfc, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -/* - * helper routine for returning string descriptors in UTF-16LE - * input can actually be ISO-8859-1; ASCII is its 7-bit subset - */ -static int ascii2utf (char *s, u8 *utf, int utfmax) -{ - int retval; - - for (retval = 0; *s && utfmax > 1; utfmax -= 2, retval += 2) { - *utf++ = *s++; - *utf++ = 0; - } - return retval; -} - -/* - * root_hub_string is used by each host controller's root hub code, - * so that they're identified consistently throughout the system. - */ -static int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len) -{ - char buf [30]; - - /* assert (len > (2 * (sizeof (buf) + 1))); - assert (strlen (type) <= 8);*/ - - /* language ids */ - if (id == 0) { - *data++ = 4; *data++ = 3; /* 4 bytes data */ - *data++ = 0; *data++ = 0; /* some language id */ - return 4; - - /* serial number */ - } else if (id == 1) { - sprintf (buf, "%#x", serial); - - /* product description */ - } else if (id == 2) { - sprintf (buf, "USB %s Root Hub", type); - - /* id 3 == vendor description */ - - /* unsupported IDs --> "stall" */ - } else - return 0; - - ascii2utf (buf, data + 2, len - 2); - data [0] = 2 + strlen(buf) * 2; - data [1] = 3; - return data [0]; -} - -/* helper macro */ -#define OK(x) len = (x); break - -/* - * This function handles all USB request to the the virtual root hub - */ -static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, - void *data, int buf_len, struct devrequest *cmd) -{ - __u8 data_buf[16]; - __u8 *bufp = data_buf; - int len = 0; - int status = 0; - __u16 bmRType_bReq; - __u16 wValue = le16_to_cpu (cmd->value); - __u16 wLength = le16_to_cpu (cmd->length); -#ifdef SL811_DEBUG - __u16 wIndex = le16_to_cpu (cmd->index); -#endif - - if (usb_pipeint(pipe)) { - PDEBUG(0, "interrupt transfer unimplemented!\n"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - - PDEBUG(5, "submit rh urb, req = %d(%x) val = %#x index = %#x len=%d\n", - bmRType_bReq, bmRType_bReq, wValue, wIndex, wLength); - - /* Request Destination: - without flags: Device, - USB_RECIP_INTERFACE: interface, - USB_RECIP_ENDPOINT: endpoint, - USB_TYPE_CLASS means HUB here, - USB_RECIP_OTHER | USB_TYPE_CLASS almost ever means HUB_PORT here - */ - switch (bmRType_bReq) { - case RH_GET_STATUS: - *(__u16 *)bufp = cpu_to_le16(1); - OK(2); - - case RH_GET_STATUS | USB_RECIP_INTERFACE: - *(__u16 *)bufp = cpu_to_le16(0); - OK(2); - - case RH_GET_STATUS | USB_RECIP_ENDPOINT: - *(__u16 *)bufp = cpu_to_le16(0); - OK(2); - - case RH_GET_STATUS | USB_TYPE_CLASS: - *(__u32 *)bufp = cpu_to_le32(0); - OK(4); - - case RH_GET_STATUS | USB_RECIP_OTHER | USB_TYPE_CLASS: - *(__u32 *)bufp = cpu_to_le32(rh_status.wPortChange<<16 | rh_status.wPortStatus); - OK(4); - - case RH_CLEAR_FEATURE | USB_RECIP_ENDPOINT: - switch (wValue) { - case 1: - OK(0); - } - break; - - case RH_CLEAR_FEATURE | USB_TYPE_CLASS: - switch (wValue) { - case C_HUB_LOCAL_POWER: - OK(0); - - case C_HUB_OVER_CURRENT: - OK(0); - } - break; - - case RH_CLEAR_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: - switch (wValue) { - case USB_PORT_FEAT_ENABLE: - rh_status.wPortStatus &= ~USB_PORT_STAT_ENABLE; - OK(0); - - case USB_PORT_FEAT_SUSPEND: - rh_status.wPortStatus &= ~USB_PORT_STAT_SUSPEND; - OK(0); - - case USB_PORT_FEAT_POWER: - rh_status.wPortStatus &= ~USB_PORT_STAT_POWER; - OK(0); - - case USB_PORT_FEAT_C_CONNECTION: - rh_status.wPortChange &= ~USB_PORT_STAT_C_CONNECTION; - OK(0); - - case USB_PORT_FEAT_C_ENABLE: - rh_status.wPortChange &= ~USB_PORT_STAT_C_ENABLE; - OK(0); - - case USB_PORT_FEAT_C_SUSPEND: - rh_status.wPortChange &= ~USB_PORT_STAT_C_SUSPEND; - OK(0); - - case USB_PORT_FEAT_C_OVER_CURRENT: - rh_status.wPortChange &= ~USB_PORT_STAT_C_OVERCURRENT; - OK(0); - - case USB_PORT_FEAT_C_RESET: - rh_status.wPortChange &= ~USB_PORT_STAT_C_RESET; - OK(0); - } - break; - - case RH_SET_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: - switch (wValue) { - case USB_PORT_FEAT_SUSPEND: - rh_status.wPortStatus |= USB_PORT_STAT_SUSPEND; - OK(0); - - case USB_PORT_FEAT_RESET: - rh_status.wPortStatus |= USB_PORT_STAT_RESET; - rh_status.wPortChange = 0; - rh_status.wPortChange |= USB_PORT_STAT_C_RESET; - rh_status.wPortStatus &= ~USB_PORT_STAT_RESET; - rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; - OK(0); - - case USB_PORT_FEAT_POWER: - rh_status.wPortStatus |= USB_PORT_STAT_POWER; - OK(0); - - case USB_PORT_FEAT_ENABLE: - rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; - OK(0); - } - break; - - case RH_SET_ADDRESS: - root_hub_devnum = wValue; - OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case USB_DT_DEVICE: - len = sizeof(sl811_rh_dev_des); - bufp = sl811_rh_dev_des; - OK(len); - - case USB_DT_CONFIG: - len = sizeof(sl811_rh_config_des); - bufp = sl811_rh_config_des; - OK(len); - - case USB_DT_STRING: - len = usb_root_hub_string(wValue & 0xff, (int)(long)0, "SL811HS", data, wLength); - if (len > 0) { - bufp = data; - OK(len); - } - - default: - status = -32; - } - break; - - case RH_GET_DESCRIPTOR | USB_TYPE_CLASS: - len = sizeof(sl811_rh_hub_des); - bufp = sl811_rh_hub_des; - OK(len); - - case RH_GET_CONFIGURATION: - bufp[0] = 0x01; - OK(1); - - case RH_SET_CONFIGURATION: - OK(0); - - default: - PDEBUG(1, "unsupported root hub command\n"); - status = -32; - } - - len = min(len, buf_len); - if (data != bufp) - memcpy(data, bufp, len); - - PDEBUG(5, "len = %d, status = %d\n", len, status); - - usb_dev->status = status; - usb_dev->act_len = len; - - return status == 0 ? len : status; -} diff --git a/drivers/usb/host/sl811.h b/drivers/usb/host/sl811.h deleted file mode 100644 index c1f9f013bd1..00000000000 --- a/drivers/usb/host/sl811.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __UBOOT_SL811_H -#define __UBOOT_SL811_H - -#undef SL811_DEBUG - -#ifdef SL811_DEBUG - #define PDEBUG(level, fmt, args...) \ - if (debug >= (level)) printf("[%s:%d] " fmt, \ - __PRETTY_FUNCTION__, __LINE__ , ## args) -#else - #define PDEBUG(level, fmt, args...) do {} while(0) -#endif - -/* Sl811 host control register */ -#define SL811_CTRL_A 0x00 -#define SL811_ADDR_A 0x01 -#define SL811_LEN_A 0x02 -#define SL811_STS_A 0x03 /* read */ -#define SL811_PIDEP_A 0x03 /* write */ -#define SL811_CNT_A 0x04 /* read */ -#define SL811_DEV_A 0x04 /* write */ -#define SL811_CTRL1 0x05 -#define SL811_INTR 0x06 -#define SL811_CTRL_B 0x08 -#define SL811_ADDR_B 0x09 -#define SL811_LEN_B 0x0A -#define SL811_STS_B 0x0B /* read */ -#define SL811_PIDEP_B 0x0B /* write */ -#define SL811_CNT_B 0x0C /* read */ -#define SL811_DEV_B 0x0C /* write */ -#define SL811_INTRSTS 0x0D /* write clears bitwise */ -#define SL811_HWREV 0x0E /* read */ -#define SL811_SOFLOW 0x0E /* write */ -#define SL811_SOFCNTDIV 0x0F /* read */ -#define SL811_CTRL2 0x0F /* write */ - -/* USB control register bits (addr 0x00 and addr 0x08) */ -#define SL811_USB_CTRL_ARM 0x01 -#define SL811_USB_CTRL_ENABLE 0x02 -#define SL811_USB_CTRL_DIR_OUT 0x04 -#define SL811_USB_CTRL_ISO 0x10 -#define SL811_USB_CTRL_SOF 0x20 -#define SL811_USB_CTRL_TOGGLE_1 0x40 -#define SL811_USB_CTRL_PREAMBLE 0x80 - -/* USB status register bits (addr 0x03 and addr 0x0B) */ -#define SL811_USB_STS_ACK 0x01 -#define SL811_USB_STS_ERROR 0x02 -#define SL811_USB_STS_TIMEOUT 0x04 -#define SL811_USB_STS_TOGGLE_1 0x08 -#define SL811_USB_STS_SETUP 0x10 -#define SL811_USB_STS_OVERFLOW 0x20 -#define SL811_USB_STS_NAK 0x40 -#define SL811_USB_STS_STALL 0x80 - -/* Control register 1 bits (addr 0x05) */ -#define SL811_CTRL1_SOF 0x01 -#define SL811_CTRL1_RESET 0x08 -#define SL811_CTRL1_JKSTATE 0x10 -#define SL811_CTRL1_SPEED_LOW 0x20 -#define SL811_CTRL1_SUSPEND 0x40 - -/* Interrut enable (addr 0x06) and interrupt status register bits (addr 0x0D) */ -#define SL811_INTR_DONE_A 0x01 -#define SL811_INTR_DONE_B 0x02 -#define SL811_INTR_SOF 0x10 -#define SL811_INTR_INSRMV 0x20 -#define SL811_INTR_DETECT 0x40 -#define SL811_INTR_NOTPRESENT 0x40 -#define SL811_INTR_SPEED_FULL 0x80 /* only in status reg */ - -/* HW rev and SOF lo register bits (addr 0x0E) */ -#define SL811_HWR_HWREV 0xF0 - -/* SOF counter and control reg 2 (addr 0x0F) */ -#define SL811_CTL2_SOFHI 0x3F -#define SL811_CTL2_DSWAP 0x40 -#define SL811_CTL2_HOST 0x80 - -/* Set up for 1-ms SOF time. */ -#define SL811_12M_LOW 0xE0 -#define SL811_12M_HI 0x2E - -#define SL811_DATA_START 0x10 -#define SL811_DATA_LIMIT 240 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 - - -#define PIDEP(pid, ep) (((pid) & 0x0f) << 4 | (ep)) - -#endif /* __UBOOT_SL811_H */ diff --git a/drivers/usb/host/utmi-armada100.c b/drivers/usb/host/utmi-armada100.c deleted file mode 100644 index 5d66e5881f3..00000000000 --- a/drivers/usb/host/utmi-armada100.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact@8051projects.net> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <usb.h> -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> -#include <asm/arch/utmi-armada100.h> -#include <linux/delay.h> - -static int utmi_phy_init(void) -{ - struct armd1usb_phy_reg *phy_regs = - (struct armd1usb_phy_reg *)UTMI_PHY_BASE; - int timeout; - - setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); - udelay(1000); - setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); - - clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); - setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); - - setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); - - /* Calibrate pll */ - timeout = 10000; - while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) - ; - if (!timeout) - return -1; - - udelay(200); - setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); - udelay(400); - clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); - - udelay(200); - setbits_le32(&phy_regs->utmi_tx, RCAL_START); - udelay(400); - clrbits_le32(&phy_regs->utmi_tx, RCAL_START); - - timeout = 10000; - while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) - ; - if (!timeout) - return -1; - - return 0; -} - -/* - * Initialize USB host controller's UTMI Physical interface - */ -int utmi_init(void) -{ - struct armd1mpmu_registers *mpmu_regs = - (struct armd1mpmu_registers *)ARMD1_MPMU_BASE; - - struct armd1apmu_registers *apmu_regs = - (struct armd1apmu_registers *)ARMD1_APMU_BASE; - - /* Turn on 26Mhz ref clock for UTMI PLL */ - setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); - - /* USB Clock reset */ - writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc); - writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc); - - /* Initialize UTMI transceiver */ - return utmi_phy_init(); -} diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 75c789a9570..cdb7d9a54d4 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -32,12 +32,10 @@ obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o -obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o -obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o diff --git a/drivers/video/exynos/Makefile b/drivers/video/exynos/Makefile index 0f58954e49c..45067f562cb 100644 --- a/drivers/video/exynos/Makefile +++ b/drivers/video/exynos/Makefile @@ -7,4 +7,3 @@ obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o -obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o diff --git a/drivers/video/lg4573.c b/drivers/video/lg4573.c deleted file mode 100644 index dd87fc461b9..00000000000 --- a/drivers/video/lg4573.c +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * LCD: LG4573, TFT 4.3", 480x800, RGB24 - * LCD initialization via SPI - * - */ -#include <common.h> -#include <backlight.h> -#include <command.h> -#include <display.h> -#include <dm.h> -#include <log.h> -#include <dm/read.h> -#include <dm/uclass-internal.h> -#include <errno.h> -#include <spi.h> -#include <asm/gpio.h> -#include <linux/delay.h> - -#define PWR_ON_DELAY_MSECS 120 - -static int lb043wv_spi_write_u16(struct spi_slave *slave, u16 val) -{ - unsigned short buf16 = htons(val); - int ret = 0; - - ret = spi_xfer(slave, 16, &buf16, NULL, - SPI_XFER_BEGIN | SPI_XFER_END); - if (ret) - debug("%s: Failed to send: %d\n", __func__, ret); - - return ret; -} - -static void lb043wv_spi_write_u16_array(struct spi_slave *slave, u16 *buff, - int size) -{ - int i; - - for (i = 0; i < size; i++) - lb043wv_spi_write_u16(slave, buff[i]); -} - -static void lb043wv_display_mode_settings(struct spi_slave *slave) -{ - static u16 display_mode_settings[] = { - 0x703A, - 0x7270, - 0x70B1, - 0x7208, - 0x723B, - 0x720F, - 0x70B2, - 0x7200, - 0x72C8, - 0x70B3, - 0x7200, - 0x70B4, - 0x7200, - 0x70B5, - 0x7242, - 0x7210, - 0x7210, - 0x7200, - 0x7220, - 0x70B6, - 0x720B, - 0x720F, - 0x723C, - 0x7213, - 0x7213, - 0x72E8, - 0x70B7, - 0x7246, - 0x7206, - 0x720C, - 0x7200, - 0x7200, - }; - - debug("transfer display mode settings\n"); - lb043wv_spi_write_u16_array(slave, display_mode_settings, - ARRAY_SIZE(display_mode_settings)); -} - -static void lb043wv_power_settings(struct spi_slave *slave) -{ - static u16 power_settings[] = { - 0x70C0, - 0x7201, - 0x7211, - 0x70C3, - 0x7207, - 0x7203, - 0x7204, - 0x7204, - 0x7204, - 0x70C4, - 0x7212, - 0x7224, - 0x7218, - 0x7218, - 0x7202, - 0x7249, - 0x70C5, - 0x726F, - 0x70C6, - 0x7241, - 0x7263, - }; - - debug("transfer power settings\n"); - lb043wv_spi_write_u16_array(slave, power_settings, - ARRAY_SIZE(power_settings)); -} - -static void lb043wv_gamma_settings(struct spi_slave *slave) -{ - static u16 gamma_settings[] = { - 0x70D0, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D1, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D2, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D3, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D4, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D5, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - }; - - debug("transfer gamma settings\n"); - lb043wv_spi_write_u16_array(slave, gamma_settings, - ARRAY_SIZE(gamma_settings)); -} - -static void lb043wv_display_on(struct spi_slave *slave) -{ - static u16 sleep_out = 0x7011; - static u16 display_on = 0x7029; - - lb043wv_spi_write_u16(slave, sleep_out); - mdelay(PWR_ON_DELAY_MSECS); - lb043wv_spi_write_u16(slave, display_on); -} - -static int lg4573_spi_startup(struct spi_slave *slave) -{ - int ret; - - ret = spi_claim_bus(slave); - if (ret) - return ret; - - lb043wv_display_mode_settings(slave); - lb043wv_power_settings(slave); - lb043wv_gamma_settings(slave); - lb043wv_display_on(slave); - - spi_release_bus(slave); - return 0; -} - -static int do_lgset(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct spi_slave *slave; - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_DISPLAY, - DM_DRIVER_GET(lg4573_lcd), &dev); - if (ret) { - printf("%s: Could not get lg4573 device\n", __func__); - return ret; - } - slave = dev_get_parent_priv(dev); - if (!slave) { - printf("%s: No slave data\n", __func__); - return -ENODEV; - } - lg4573_spi_startup(slave); - - return 0; -} - -U_BOOT_CMD( - lgset, 2, 1, do_lgset, - "set lgdisplay", - "" -); - -static int lg4573_bind(struct udevice *dev) -{ - return 0; -} - -static int lg4573_probe(struct udevice *dev) -{ - return 0; -} - -static const struct udevice_id lg4573_ids[] = { - { .compatible = "lg,lg4573" }, - { } -}; - -struct lg4573_lcd_priv { - struct display_timing timing; - struct udevice *backlight; - struct gpio_desc enable; - int panel_bpp; - u32 power_on_delay; -}; - -static int lg4573_lcd_read_timing(struct udevice *dev, - struct display_timing *timing) -{ - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - - memcpy(timing, &priv->timing, sizeof(struct display_timing)); - - return 0; -} - -static int lg4573_lcd_enable(struct udevice *dev, int bpp, - const struct display_timing *edid) -{ - struct spi_slave *slave = dev_get_parent_priv(dev); - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - int ret = 0; - - dm_gpio_set_value(&priv->enable, 1); - ret = backlight_enable(priv->backlight); - - mdelay(priv->power_on_delay); - lg4573_spi_startup(slave); - - return ret; -}; - -static const struct dm_display_ops lg4573_lcd_ops = { - .read_timing = lg4573_lcd_read_timing, - .enable = lg4573_lcd_enable, -}; - -static int lg4573_of_to_plat(struct udevice *dev) -{ - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - int ret; - - ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, - "backlight", &priv->backlight); - if (ret) { - debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); - return log_ret(ret); - } - ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, - GPIOD_IS_OUT); - if (ret) { - debug("%s: Warning: cannot get enable GPIO: ret=%d\n", - __func__, ret); - if (ret != -ENOENT) - return log_ret(ret); - } - - priv->power_on_delay = dev_read_u32_default(dev, "power-on-delay", 10); - - return 0; -} - -U_BOOT_DRIVER(lg4573_lcd) = { - .name = "lg4573", - .id = UCLASS_DISPLAY, - .ops = &lg4573_lcd_ops, - .of_to_plat = lg4573_of_to_plat, - .of_match = lg4573_ids, - .bind = lg4573_bind, - .probe = lg4573_probe, - .priv_auto = sizeof(struct lg4573_lcd_priv), -}; diff --git a/drivers/video/scf0403_lcd.c b/drivers/video/scf0403_lcd.c deleted file mode 100644 index 54f0f88b4c9..00000000000 --- a/drivers/video/scf0403_lcd.c +++ /dev/null @@ -1,297 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * scf0403.c -- support for DataImage SCF0403 LCD - * - * Copyright (c) 2013 Adapted from Linux driver: - * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved. - * Copyright (c) 2012 CompuLab, Ltd - * Dmitry Lifshitz <lifshitz@compulab.co.il> - * Ilya Ledvich <ilya@compulab.co.il> - * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> & - * Marek Vasut work in l4f00242t03.c - * - * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il> - */ - -#include <common.h> -#include <malloc.h> -#include <asm/gpio.h> -#include <spi.h> -#include <linux/delay.h> - -struct scf0403_cmd { - u16 cmd; - u16 *params; - int count; -}; - -struct scf0403_initseq_entry { - struct scf0403_cmd cmd; - int delay_ms; -}; - -struct scf0403_priv { - struct spi_slave *spi; - unsigned int reset_gpio; - u32 rddid; - struct scf0403_initseq_entry *init_seq; - int seq_size; -}; - -struct scf0403_priv priv; - -#define SCF0403852GGU04_ID 0x000080 - -/* SCF0403526GGU20 model commands parameters */ -static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06}; -static u16 spiinttype_params_sn20[] = {0x60}; -static u16 bc_params_sn20[] = { - 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B, - 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01, - 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40, -}; -static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67}; -static u16 be_params_sn20[] = { - 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22, -}; -static u16 vcom_params_sn20[] = {0x74}; -static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00}; -static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00}; -static u16 lvglvolt_params_sn20[] = {0x08}; -static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20}; -static u16 dispfunc_params_sn20[] = {0xa0}; -static u16 dvddvolt_params_sn20[] = {0x74}; -static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00}; -static u16 panelres_params_sn20[] = {0x82}; -static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13}; -static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28}; -static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20}; -static u16 memaccess_params_sn20[] = {0x00}; -static u16 pixfmt_params_sn20[] = {0x66}; -static u16 pgamma_params_sn20[] = { - 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04, - 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10, -}; -static u16 ngamma_params_sn20[] = { - 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03, - 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00, -}; -static u16 tearing_params_sn20[] = {0x00}; - -/* SCF0403852GGU04 model commands parameters */ -static u16 memaccess_params_sn04[] = {0x08}; -static u16 pixfmt_params_sn04[] = {0x66}; -static u16 modectl_params_sn04[] = {0x01}; -static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04}; -static u16 vcom_params_sn04[] = {0x00, 0x6A}; -static u16 pgamma_params_sn04[] = { - 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c, - 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f, -}; -static u16 ngamma_params_sn04[] = { - 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05, - 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00, -}; -static u16 dispinv_params_sn04[] = {0x02}; - -/* Common commands */ -static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0}; -static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0}; - -/* SCF0403852GGU04 init sequence */ -static struct scf0403_initseq_entry scf0403_initseq_sn04[] = { - {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0}, - {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0}, - {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0}, - {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0}, - {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0}, - {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20}, - {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0}, - {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100}, -}; - -/* SCF0403526GGU20 init sequence */ -static struct scf0403_initseq_entry scf0403_initseq_sn20[] = { - {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0}, - {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0}, - {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0}, - {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0}, - {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0}, - {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0}, - {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0}, - {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0}, - {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0}, - {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0}, - {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0}, - {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0}, - {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0}, - {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0}, - {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0}, - {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0}, - {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0}, - {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0}, - {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0}, - {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0}, - {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0}, - {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0}, -}; - -static void scf0403_gpio_reset(unsigned int gpio) -{ - if (!gpio_is_valid(gpio)) - return; - - gpio_set_value(gpio, 1); - mdelay(100); - gpio_set_value(gpio, 0); - mdelay(40); - gpio_set_value(gpio, 1); - mdelay(100); -} - -static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid) -{ - int error = 0; - u8 ids_buf = 0x00; - u16 dummy_buf = 0x00; - u16 cmd = 0x04; - - error = spi_set_wordlen(spi, 9); - if (error) - return error; - - /* Here 9 bits required to transmit a command */ - error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE); - if (error) - return error; - - /* - * Here 8 + 1 bits required to arrange extra clock cycle - * before the first data bit. - * According to the datasheet - first parameter is the dummy data. - */ - error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE); - if (error) - return error; - - error = spi_set_wordlen(spi, 8); - if (error) - return error; - - /* Read rest of the data */ - error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE); - if (error) - return error; - - *rddid = ids_buf; - - return 0; -} - -static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd) -{ - int i, error; - u32 command = cmd->cmd; - u32 msg; - - error = spi_set_wordlen(spi, 9); - if (error) - return error; - - error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE); - if (error) - return error; - - for (i = 0; i < cmd->count; i++) { - msg = (cmd->params[i] | 0x100); - error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE); - if (error) - return error; - } - - return 0; -} - -static void scf0403_lcd_init(struct scf0403_priv *priv) -{ - int i; - - /* reset LCD */ - scf0403_gpio_reset(priv->reset_gpio); - - for (i = 0; i < priv->seq_size; i++) { - if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0) - puts("SPI transfer failed\n"); - - mdelay(priv->init_seq[i].delay_ms); - } -} - -static int scf0403_request_reset_gpio(unsigned gpio) -{ - int err = gpio_request(gpio, "lcd reset"); - - if (err) - return err; - - err = gpio_direction_output(gpio, 0); - if (err) - gpio_free(gpio); - - return err; -} - -int scf0403_init(int reset_gpio) -{ - int error; - - if (gpio_is_valid(reset_gpio)) { - error = scf0403_request_reset_gpio(reset_gpio); - if (error) { - printf("Failed requesting reset GPIO%d: %d\n", - reset_gpio, error); - return error; - } - } - - priv.reset_gpio = reset_gpio; - priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0); - error = spi_claim_bus(priv.spi); - if (error) - goto bus_claim_fail; - - /* reset LCD */ - scf0403_gpio_reset(reset_gpio); - - error = scf0403_spi_read_rddid(priv.spi, &priv.rddid); - if (error) { - puts("IDs read failed\n"); - goto readid_fail; - } - - if (priv.rddid == SCF0403852GGU04_ID) { - priv.init_seq = scf0403_initseq_sn04; - priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04); - } else { - priv.init_seq = scf0403_initseq_sn20; - priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20); - } - - scf0403_lcd_init(&priv); - - /* Start operation */ - scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison); - mdelay(100); - scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout); - spi_release_bus(priv.spi); - - return 0; - -readid_fail: - spi_release_bus(priv.spi); -bus_claim_fail: - if (gpio_is_valid(priv.reset_gpio)) - gpio_free(priv.reset_gpio); - - return error; -} diff --git a/dts/Kconfig b/dts/Kconfig index bc5f22029ff..44cc6bf1f6f 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -21,8 +21,8 @@ menu "Device Tree Control" config OF_CONTROL bool "Run-time configuration via Device Tree" - select OF_LIBFDT if !OF_PLATDATA - select OF_REAL if !OF_PLATDATA + select OF_LIBFDT + select OF_REAL help This feature provides for run-time configuration of U-Boot via a flattened device tree. diff --git a/env/Makefile b/env/Makefile index bb6e24b396d..673b979fdfa 100644 --- a/env/Makefile +++ b/env/Makefile @@ -16,7 +16,6 @@ extra-$(CONFIG_ENV_IS_IN_FLASH) += embedded.o obj-$(CONFIG_ENV_IS_IN_NVRAM) += embedded.o obj-$(CONFIG_ENV_IS_IN_NVRAM) += nvram.o obj-$(CONFIG_ENV_IS_IN_ONENAND) += onenand.o -obj-$(CONFIG_ENV_IS_IN_SATA) += sata.o obj-$(CONFIG_ENV_IS_IN_REMOTE) += remote.o obj-$(CONFIG_ENV_IS_IN_UBI) += ubi.o endif diff --git a/env/env.c b/env/env.c index 06078c7f374..0f73ebc08e0 100644 --- a/env/env.c +++ b/env/env.c @@ -78,9 +78,6 @@ static enum env_location env_locations[] = { #ifdef CONFIG_ENV_IS_IN_REMOTE ENVL_REMOTE, #endif -#ifdef CONFIG_ENV_IS_IN_SATA - ENVL_ESATA, -#endif #ifdef CONFIG_ENV_IS_IN_SPI_FLASH ENVL_SPI_FLASH, #endif diff --git a/env/sata.c b/env/sata.c deleted file mode 100644 index 9442cfcaf3c..00000000000 --- a/env/sata.c +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010-2016 Freescale Semiconductor, Inc. - */ - -/* #define DEBUG */ - -#include <common.h> - -#include <command.h> -#include <env.h> -#include <env_internal.h> -#include <linux/stddef.h> -#include <errno.h> -#include <memalign.h> -#include <sata.h> -#include <search.h> - -#if defined(CONFIG_ENV_OFFSET_REDUND) -#error ENV REDUND not supported -#endif - -#if !defined(CONFIG_ENV_OFFSET) || !defined(CONFIG_ENV_SIZE) -#error CONFIG_ENV_OFFSET or CONFIG_ENV_SIZE not defined -#endif - -__weak int sata_get_env_dev(void) -{ - return CONFIG_SYS_SATA_ENV_DEV; -} - -#ifdef CONFIG_CMD_SAVEENV -static inline int write_env(struct blk_desc *sata, unsigned long size, - unsigned long offset, void *buffer) -{ - uint blk_start, blk_cnt, n; - - blk_start = ALIGN(offset, sata->blksz) / sata->blksz; - blk_cnt = ALIGN(size, sata->blksz) / sata->blksz; - - n = blk_dwrite(sata, blk_start, blk_cnt, buffer); - - return (n == blk_cnt) ? 0 : -1; -} - -static int env_sata_save(void) -{ - ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); - struct blk_desc *sata = NULL; - int env_sata, ret; - - if (sata_initialize()) - return 1; - - env_sata = sata_get_env_dev(); - - sata = sata_get_dev(env_sata); - if (sata == NULL) { - printf("Unknown SATA(%d) device for environment!\n", - env_sata); - return 1; - } - - ret = env_export(env_new); - if (ret) - return 1; - - printf("Writing to SATA(%d)...", env_sata); - if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, (u_char *)env_new)) { - puts("failed\n"); - return 1; - } - - puts("done\n"); - return 0; -} -#endif /* CONFIG_CMD_SAVEENV */ - -static inline int read_env(struct blk_desc *sata, unsigned long size, - unsigned long offset, void *buffer) -{ - uint blk_start, blk_cnt, n; - - blk_start = ALIGN(offset, sata->blksz) / sata->blksz; - blk_cnt = ALIGN(size, sata->blksz) / sata->blksz; - - n = blk_dread(sata, blk_start, blk_cnt, buffer); - - return (n == blk_cnt) ? 0 : -1; -} - -static void env_sata_load(void) -{ - ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); - struct blk_desc *sata = NULL; - int env_sata; - - if (sata_initialize()) - return -EIO; - - env_sata = sata_get_env_dev(); - - sata = sata_get_dev(env_sata); - if (sata == NULL) { - printf("Unknown SATA(%d) device for environment!\n", env_sata); - return -EIO; - } - - if (read_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf)) { - env_set_default(NULL, 0); - return -EIO; - } - - return env_import(buf, 1, H_EXTERNAL); -} - -U_BOOT_ENV_LOCATION(sata) = { - .location = ENVL_ESATA, - ENV_NAME("SATA") - .load = env_sata_load, - .save = env_save_ptr(env_sata_save), -}; diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h deleted file mode 100644 index ccb7805375e..00000000000 --- a/include/faraday/ftpmu010.h +++ /dev/null @@ -1,234 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - */ - -/* - * Power Management Unit - */ -#ifndef __FTPMU010_H -#define __FTPMU010_H - -#ifndef __ASSEMBLY__ -struct ftpmu010 { - unsigned int IDNMBR0; /* 0x00 */ - unsigned int reserved0; /* 0x04 */ - unsigned int OSCC; /* 0x08 */ - unsigned int PMODE; /* 0x0C */ - unsigned int PMCR; /* 0x10 */ - unsigned int PED; /* 0x14 */ - unsigned int PEDSR; /* 0x18 */ - unsigned int reserved1; /* 0x1C */ - unsigned int PMSR; /* 0x20 */ - unsigned int PGSR; /* 0x24 */ - unsigned int MFPSR; /* 0x28 */ - unsigned int MISC; /* 0x2C */ - unsigned int PDLLCR0; /* 0x30 */ - unsigned int PDLLCR1; /* 0x34 */ - unsigned int AHBMCLKOFF; /* 0x38 */ - unsigned int APBMCLKOFF; /* 0x3C */ - unsigned int DCSRCR0; /* 0x40 */ - unsigned int DCSRCR1; /* 0x44 */ - unsigned int DCSRCR2; /* 0x48 */ - unsigned int SDRAMHTC; /* 0x4C */ - unsigned int PSPR0; /* 0x50 */ - unsigned int PSPR1; /* 0x54 */ - unsigned int PSPR2; /* 0x58 */ - unsigned int PSPR3; /* 0x5C */ - unsigned int PSPR4; /* 0x60 */ - unsigned int PSPR5; /* 0x64 */ - unsigned int PSPR6; /* 0x68 */ - unsigned int PSPR7; /* 0x6C */ - unsigned int PSPR8; /* 0x70 */ - unsigned int PSPR9; /* 0x74 */ - unsigned int PSPR10; /* 0x78 */ - unsigned int PSPR11; /* 0x7C */ - unsigned int PSPR12; /* 0x80 */ - unsigned int PSPR13; /* 0x84 */ - unsigned int PSPR14; /* 0x88 */ - unsigned int PSPR15; /* 0x8C */ - unsigned int AHBDMA_RACCS; /* 0x90 */ - unsigned int reserved2; /* 0x94 */ - unsigned int reserved3; /* 0x98 */ - unsigned int JSS; /* 0x9C */ - unsigned int CFC_RACC; /* 0xA0 */ - unsigned int SSP1_RACC; /* 0xA4 */ - unsigned int UART1TX_RACC; /* 0xA8 */ - unsigned int UART1RX_RACC; /* 0xAC */ - unsigned int UART2TX_RACC; /* 0xB0 */ - unsigned int UART2RX_RACC; /* 0xB4 */ - unsigned int SDC_RACC; /* 0xB8 */ - unsigned int I2SAC97_RACC; /* 0xBC */ - unsigned int IRDATX_RACC; /* 0xC0 */ - unsigned int reserved4; /* 0xC4 */ - unsigned int USBD_RACC; /* 0xC8 */ - unsigned int IRDARX_RACC; /* 0xCC */ - unsigned int IRDA_RACC; /* 0xD0 */ - unsigned int ED0_RACC; /* 0xD4 */ - unsigned int ED1_RACC; /* 0xD8 */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * ID Number 0 Register - */ -#define FTPMU010_ID_A320A 0x03200000 -#define FTPMU010_ID_A320C 0x03200010 -#define FTPMU010_ID_A320D 0x03200030 - -/* - * OSC Control Register - */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) - -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) - -/* - * Power Mode Register - */ -#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) -#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) - -/* - * Power Manager Status Register - */ -#define FTPMU010_PMSR_SMR (1 << 10) - -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) - -/* - * Multi-Function Port Setting Register - */ -#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) -#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) -#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) -#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) -#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) -#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) -#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) -#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) -#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) -#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) -#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) - -/* - * PLL/DLL Control Register 0 - * Note: - * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: - * Datasheet indicated it starts at bit #21 which was wrong. - * 2. FTPMU010_PDLLCR0_DLLFRAG: - * Datasheet indicated it has 2 bit which was wrong. - */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) -#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) - -/* - * SDRAM Signal Hold Time Control Register - */ -#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) -#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) -#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) -#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) -#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) -#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) -#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) -#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) -#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) -#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) - -#ifndef __ASSEMBLY__ -void ftpmu010_32768osc_enable(void); -void ftpmu010_dlldis_disable(void); -void ftpmu010_mfpsr_diselect_dev(unsigned int dev); -void ftpmu010_mfpsr_select_dev(unsigned int dev); -void ftpmu010_sdram_clk_disable(unsigned int cr0); -void ftpmu010_sdramhtc_set(unsigned int val); -#endif - -#ifdef __ASSEMBLY__ -#define FTPMU010_IDNMBR0 0x00 -#define FTPMU010_reserved0 0x04 -#define FTPMU010_OSCC 0x08 -#define FTPMU010_PMODE 0x0C -#define FTPMU010_PMCR 0x10 -#define FTPMU010_PED 0x14 -#define FTPMU010_PEDSR 0x18 -#define FTPMU010_reserved1 0x1C -#define FTPMU010_PMSR 0x20 -#define FTPMU010_PGSR 0x24 -#define FTPMU010_MFPSR 0x28 -#define FTPMU010_MISC 0x2C -#define FTPMU010_PDLLCR0 0x30 -#define FTPMU010_PDLLCR1 0x34 -#define FTPMU010_AHBMCLKOFF 0x38 -#define FTPMU010_APBMCLKOFF 0x3C -#define FTPMU010_DCSRCR0 0x40 -#define FTPMU010_DCSRCR1 0x44 -#define FTPMU010_DCSRCR2 0x48 -#define FTPMU010_SDRAMHTC 0x4C -#define FTPMU010_PSPR0 0x50 -#define FTPMU010_PSPR1 0x54 -#define FTPMU010_PSPR2 0x58 -#define FTPMU010_PSPR3 0x5C -#define FTPMU010_PSPR4 0x60 -#define FTPMU010_PSPR5 0x64 -#define FTPMU010_PSPR6 0x68 -#define FTPMU010_PSPR7 0x6C -#define FTPMU010_PSPR8 0x70 -#define FTPMU010_PSPR9 0x74 -#define FTPMU010_PSPR10 0x78 -#define FTPMU010_PSPR11 0x7C -#define FTPMU010_PSPR12 0x80 -#define FTPMU010_PSPR13 0x84 -#define FTPMU010_PSPR14 0x88 -#define FTPMU010_PSPR15 0x8C -#define FTPMU010_AHBDMA_RACCS 0x90 -#define FTPMU010_reserved2 0x94 -#define FTPMU010_reserved3 0x98 -#define FTPMU010_JSS 0x9C -#define FTPMU010_CFC_RACC 0xA0 -#define FTPMU010_SSP1_RACC 0xA4 -#define FTPMU010_UART1TX_RACC 0xA8 -#define FTPMU010_UART1RX_RACC 0xAC -#define FTPMU010_UART2TX_RACC 0xB0 -#define FTPMU010_UART2RX_RACC 0xB4 -#define FTPMU010_SDC_RACC 0xB8 -#define FTPMU010_I2SAC97_RACC 0xBC -#define FTPMU010_IRDATX_RACC 0xC0 -#define FTPMU010_reserved4 0xC4 -#define FTPMU010_USBD_RACC 0xC8 -#define FTPMU010_IRDARX_RACC 0xCC -#define FTPMU010_IRDA_RACC 0xD0 -#define FTPMU010_ED0_RACC 0xD4 -#define FTPMU010_ED1_RACC 0xD8 -#endif /* __ASSEMBLY__ */ - -#endif /* __FTPMU010_H */ diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h deleted file mode 100644 index 9999993543b..00000000000 --- a/include/linux/mtd/fsl_upm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * FSL UPM NAND driver - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - */ - -#ifndef __LINUX_MTD_NAND_FSL_UPM -#define __LINUX_MTD_NAND_FSL_UPM - -#include <linux/mtd/rawnand.h> - -#define FSL_UPM_WAIT_RUN_PATTERN 0x1 -#define FSL_UPM_WAIT_WRITE_BYTE 0x2 -#define FSL_UPM_WAIT_WRITE_BUFFER 0x4 - -struct fsl_upm { - void __iomem *mdr; - void __iomem *mxmr; - void __iomem *mar; - void __iomem *io_addr; -}; - -struct fsl_upm_nand { - struct fsl_upm upm; - - int width; - int upm_cmd_offset; - int upm_addr_offset; - int upm_mar_chip_offset; - int wait_flags; - int (*dev_ready)(int chip_nr); - int chip_delay; - int chip_offset; - int chip_nr; - - /* no need to fill */ - int last_ctrl; -}; - -extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); - -#endif diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h deleted file mode 100644 index 1d8a067f17e..00000000000 --- a/include/linux/mtd/fsmc_nand.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. - */ - -#ifndef __FSMC_NAND_H__ -#define __FSMC_NAND_H__ - -#include <linux/mtd/rawnand.h> - -struct fsmc_regs { - u32 ctrl; /* 0x00 */ - u8 reserved_1[0x40 - 0x04]; - u32 pc; /* 0x40 */ - u32 sts; /* 0x44 */ - u32 comm; /* 0x48 */ - u32 attrib; /* 0x4c */ - u32 ioata; /* 0x50 */ - u32 ecc1; /* 0x54 */ - u32 ecc2; /* 0x58 */ - u32 ecc3; /* 0x5c */ - u8 reserved_2[0xfe0 - 0x60]; - u32 peripid0; /* 0xfe0 */ - u32 peripid1; /* 0xfe4 */ - u32 peripid2; /* 0xfe8 */ - u32 peripid3; /* 0xfec */ - u32 pcellid0; /* 0xff0 */ - u32 pcellid1; /* 0xff4 */ - u32 pcellid2; /* 0xff8 */ - u32 pcellid3; /* 0xffc */ -}; - -/* ctrl register definitions */ -#define FSMC_WP (1 << 7) - -/* pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* sts register definitions */ -#define FSMC_CODE_RDY (1 << 15) - -/* comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -/* peripid2 register definitions */ -#define FSMC_REVISION_MSK (0xf) -#define FSMC_REVISION_SHFT (0x4) - -#define FSMC_VER8 0x8 - -/* - * There are 13 bytes of ecc for every 512 byte block and it has to be read - * consecutively and immediately after the 512 byte data block for hardware to - * generate the error bit offsets - * Managing the ecc bytes in the following way is easier. This way is similar to - * oobfree structure maintained already in u-boot nand driver - */ -#define FSMC_MAX_ECCPLACE_ENTRIES 32 - -struct fsmc_nand_eccplace { - u32 offset; - u32 length; -}; - -struct fsmc_eccplace { - struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES]; -}; - -extern int fsmc_nand_init(struct nand_chip *nand); -#endif diff --git a/include/netdev.h b/include/netdev.h index 2b4e474ed08..2a7f40e5040 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -71,7 +71,6 @@ int skge_initialize(struct bd_info *bis); int smc91111_initialize(u8 dev_num, phys_addr_t base_addr); int smc911x_initialize(u8 dev_num, phys_addr_t base_addr); int uli526x_initialize(struct bd_info *bis); -int armada100_fec_register(unsigned long base_addr); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. diff --git a/include/pca9698.h b/include/pca9698.h deleted file mode 100644 index 48a5f756e28..00000000000 --- a/include/pca9698.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef __PCA9698_H_ -#define __PCA9698_H_ - -int pca9698_request(unsigned gpio, const char *label); -void pca9698_free(unsigned gpio); -int pca9698_direction_input(u8 addr, unsigned gpio); -int pca9698_direction_output(u8 addr, unsigned gpio, int value); -int pca9698_get_value(u8 addr, unsigned gpio); -int pca9698_set_value(u8 addr, unsigned gpio, int value); - -#endif /* __PCA9698_H_ */ diff --git a/include/power/fg_battery_cell_params.h b/include/power/fg_battery_cell_params.h deleted file mode 100644 index 500c8ea7174..00000000000 --- a/include/power/fg_battery_cell_params.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#ifndef __FG_BATTERY_CELL_PARAMS_H_ -#define __FG_BATTERY_CELL_PARAMS_H_ - -#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TARGET_TRATS) - -/* Cell characteristics - Exynos4 TRATS development board */ -/* Shall be written to addr 0x80h */ -u16 cell_character0[16] = { - 0xA2A0, - 0xB6E0, - 0xB850, - 0xBAD0, - 0xBB20, - 0xBB70, - 0xBBC0, - 0xBC20, - 0xBC80, - 0xBCE0, - 0xBD80, - 0xBE20, - 0xC090, - 0xC420, - 0xC910, - 0xD070 -}; - -/* Shall be written to addr 0x90h */ -u16 cell_character1[16] = { - 0x0090, - 0x1A50, - 0x02F0, - 0x2060, - 0x2060, - 0x2E60, - 0x26A0, - 0x2DB0, - 0x2DB0, - 0x1870, - 0x2A20, - 0x16F0, - 0x08F0, - 0x0D40, - 0x08C0, - 0x08C0 -}; - -/* Shall be written to addr 0xA0h */ -u16 cell_character2[16] = { - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100 -}; -#endif -#endif /* __FG_BATTERY_CELL_PARAMS_H_ */ diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h deleted file mode 100644 index 07f8c643ba5..00000000000 --- a/include/scf0403_lcd.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013, Compulab Inc. - */ -#ifndef SCF0403_LCD_H_ -#define SCF0403_LCD_H_ - -int scf0403_init(int reset_gpio); - -#endif diff --git a/include/usb/fotg210.h b/include/usb/fotg210.h deleted file mode 100644 index 292ce54e0c4..00000000000 --- a/include/usb/fotg210.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday USB 2.0 OTG Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#ifndef _FOTG210_H -#define _FOTG210_H - -struct fotg210_regs { - /* USB Host Controller */ - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t rsvd1[3]; - uint32_t miscr; /* 0x40: Miscellaneous Register */ - uint32_t rsvd2[15]; - /* USB OTG Controller */ - uint32_t otgcsr;/* 0x80: OTG Control Status Register */ - uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */ - uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */ - uint32_t rsvd3[13]; - uint32_t isr; /* 0xC0: Global Interrupt Status Register */ - uint32_t imr; /* 0xC4: Global Interrupt Mask Register */ - uint32_t rsvd4[14]; - /* USB Device Controller */ - uint32_t dev_ctrl;/* 0x100: Device Control Register */ - uint32_t dev_addr;/* 0x104: Device Address Register */ - uint32_t dev_test;/* 0x108: Device Test Register */ - uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */ - uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */ - uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */ - uint32_t rsvd5[2]; - uint32_t cxfifo;/* 0x120: CX FIFO Register */ - uint32_t idle; /* 0x124: IDLE Counter Register */ - uint32_t rsvd6[2]; - uint32_t gimr; /* 0x130: Group Interrupt Mask Register */ - uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */ - uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */ - uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */ - uint32_t gisr; /* 0x140: Group Interrupt Status Register */ - uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */ - uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */ - uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */ - uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */ - uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */ - uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */ - uint32_t rsvd7[1]; - uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */ - uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */ - uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */ - uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */ - uint32_t fifomap;/* 0x1a8: FIFO Map Register */ - uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */ - uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */ - uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */ - uint32_t rsvd8[1]; - uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */ - uint32_t dma_addr; /* 0x1cc: DMA Address Register */ - uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */ -}; - -/* Miscellaneous Register */ -#define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */ -#define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* OTG Control Status Register */ -#define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */ -#define OTGCSR_SPD_LOW (1 << 22) -#define OTGCSR_SPD_FULL (0 << 22) -#define OTGCSR_SPD_MASK (3 << 22) -#define OTGCSR_SPD_SHIFT 22 -#define OTGCSR_SPD(x) (((x) >> 22) & 0x03) -#define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */ -#define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */ -#define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */ -#define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */ -#define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */ -#define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */ -#define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */ -#define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */ -#define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/ -#define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/ -#define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/ -#define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/ -#define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/ -#define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/ -#define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */ -#define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */ -#define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */ -#define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */ -#define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */ -#define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */ -#define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */ -#define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */ -#define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */ - -/* OTG Interrupt Status Register */ -#define OTGISR_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGISR_OVD (1 << 10) /* over-current detected */ -#define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGISR_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGISR_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGISR_BSRP (1 << 0) /* B-device SRP complete */ - -/* OTG Interrupt Enable Register */ -#define OTGIER_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGIER_OVD (1 << 10) /* over-current detected */ -#define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGIER_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGIER_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGIER_BSRP (1 << 0) /* B-device SRP complete */ - -/* Global Interrupt Status Register (W1C) */ -#define ISR_HOST (1 << 2) /* USB Host interrupt */ -#define ISR_OTG (1 << 1) /* USB OTG interrupt */ -#define ISR_DEV (1 << 0) /* USB Device interrupt */ -#define ISR_MASK 0x07 - -/* Global Interrupt Mask Register */ -#define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */ -#define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */ -#define IMR_HOST (1 << 2) /* USB Host interrupt */ -#define IMR_OTG (1 << 1) /* USB OTG interrupt */ -#define IMR_DEV (1 << 0) /* USB Device interrupt */ -#define IMR_MASK 0x0f - -/* Device Control Register */ -#define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */ -#define DEVCTRL_HS (1 << 6) /* High Speed Mode */ -#define DEVCTRL_FS (0 << 6) /* Full Speed Mode */ -#define DEVCTRL_EN (1 << 5) /* Chip Enable */ -#define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */ -#define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */ -#define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */ -#define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */ -#define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */ - -/* Device Address Register */ -#define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */ -#define DEVADDR_ADDR(x) ((x) & 0x7f) -#define DEVADDR_ADDR_MASK 0x7f - -/* Device Test Register */ -#define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */ -#define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */ -#define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */ -#define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */ -#define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */ -#define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */ -#define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */ - -/* SOF Frame Number Register */ -#define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */ -#define SOFFNR_FNR(x) ((x) & 0x7ff) /* SOF Frame Number */ - -/* SOF Mask Timer Register */ -#define SOFMTR_TMR(x) ((x) & 0xffff) - -/* PHY Test Mode Selector Register */ -#define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */ -#define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */ -#define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */ -#define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */ -#define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */ - -/* CX FIFO Register */ -#define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */ -#define CXFIFO_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */ -#define CXFIFO_FIFOE_FIFO0 (1 << 8) -#define CXFIFO_FIFOE_FIFO1 (1 << 9) -#define CXFIFO_FIFOE_FIFO2 (1 << 10) -#define CXFIFO_FIFOE_FIFO3 (1 << 11) -#define CXFIFO_FIFOE_MASK (0x0f << 8) -#define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */ -#define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */ -#define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */ -#define CXFIFO_CXSTALL (1 << 2) /* CX Stall */ -#define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */ -#define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */ - -/* IDLE Counter Register */ -#define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */ - -/* Group Interrupt Mask(Disable) Register */ -#define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */ -#define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */ -#define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */ -#define GIMR_MASK 0x07 - -/* Group Interrupt Mask(Disable) Register 0 (CX) */ -#define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GIMR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GIMR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ -#define GIMR0_MASK 0x3f - -/* Group Interrupt Mask(Disable) Register 1 (FIFO) */ -#define GIMR1_FIFO_IN(x) (1 << (((x) & 3) + 16)) /* FIFOx IN */ -#define GIMR1_FIFO_TX(x) GIMR1_FIFO_IN(x) -#define GIMR1_FIFO_OUT(x) (1 << (((x) & 3) * 2)) /* FIFOx OUT */ -#define GIMR1_FIFO_SPK(x) (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */ -#define GIMR1_FIFO_RX(x) (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x)) -#define GIMR1_MASK 0xf00ff - -/* Group Interrupt Mask(Disable) Register 2 (Device) */ -#define GIMR2_WAKEUP (1 << 10) /* Device waked up */ -#define GIMR2_IDLE (1 << 9) /* Device idle */ -#define GIMR2_DMAERR (1 << 8) /* DMA error */ -#define GIMR2_DMAFIN (1 << 7) /* DMA finished */ -#define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GIMR2_RESET (1 << 0) /* Reset Interrupt */ -#define GIMR2_MASK 0x7ff - -/* Group Interrupt Status Register */ -#define GISR_GRP2 (1 << 2) /* Interrupt group 2 */ -#define GISR_GRP1 (1 << 1) /* Interrupt group 1 */ -#define GISR_GRP0 (1 << 0) /* Interrupt group 0 */ - -/* Group Interrupt Status Register 0 (CX) */ -#define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GISR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GISR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ - -/* Group Interrupt Status Register 1 (FIFO) */ -#define GISR1_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */ -#define GISR1_OUT_FIFO(x) (1 << (((x) & 0x03) * 2)) /* FIFOx OUT */ -#define GISR1_SPK_FIFO(x) (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */ -#define GISR1_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */ - -/* Group Interrupt Status Register 2 (Device) */ -#define GISR2_WAKEUP (1 << 10) /* Device waked up */ -#define GISR2_IDLE (1 << 9) /* Device idle */ -#define GISR2_DMAERR (1 << 8) /* DMA error */ -#define GISR2_DMAFIN (1 << 7) /* DMA finished */ -#define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GISR2_RESET (1 << 0) /* Reset Interrupt */ - -/* Receive Zero-Length-Packet Register */ -#define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */ - -/* Transfer Zero-Length-Packet Register */ -#define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */ - -/* ISOC Error/Abort Status Register */ -#define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */ - -/* IN Endpoint Register */ -#define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */ -#define IEP_TNRHB(x) (((x) & 0x03) << 13) \ - /* Transaction Number for High-Bandwidth EP(ISOC) */ -#define IEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define IEP_STALL (1 << 11) /* Stall */ -#define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* OUT Endpoint Register */ -#define OEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define OEP_STALL (1 << 11) /* Stall */ -#define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* Endpoint Map Register (EP1 ~ EP4) */ -#define EPMAP14_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 0) -#define EPMAP14_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 4) -#define EPMAP14_SET(ep, in, out) \ - do { \ - EPMAP14_SET_IN(ep, in); \ - EPMAP14_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */ - -/* Endpoint Map Register (EP5 ~ EP8) */ -#define EPMAP58_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 0) -#define EPMAP58_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 4) -#define EPMAP58_SET(ep, in, out) \ - do { \ - EPMAP58_SET_IN(ep, in); \ - EPMAP58_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */ - -/* FIFO Map Register */ -#define FIFOMAP_BIDIR (2 << 4) -#define FIFOMAP_IN (1 << 4) -#define FIFOMAP_OUT (0 << 4) -#define FIFOMAP_DIR_MASK 0x30 -#define FIFOMAP_EP(x) ((x) & 0x0f) -#define FIFOMAP_EP_MASK 0x0f -#define FIFOMAP_CFG_MASK 0x3f -#define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */ -#define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Configuration Register */ -#define FIFOCFG_EN (1 << 5) -#define FIFOCFG_BLKSZ_1024 (1 << 4) -#define FIFOCFG_BLKSZ_512 (0 << 4) -#define FIFOCFG_3BLK (2 << 2) -#define FIFOCFG_2BLK (1 << 2) -#define FIFOCFG_1BLK (0 << 2) -#define FIFOCFG_NBLK_MASK 3 -#define FIFOCFG_NBLK_SHIFT 2 -#define FIFOCFG_INTR (3 << 0) -#define FIFOCFG_BULK (2 << 0) -#define FIFOCFG_ISOC (1 << 0) -#define FIFOCFG_RSVD (0 << 0) /* Reserved */ -#define FIFOCFG_TYPE_MASK 3 -#define FIFOCFG_TYPE_SHIFT 0 -#define FIFOCFG_CFG_MASK 0x3f -#define FIFOCFG(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Control Status Register */ -#define FIFOCSR_RESET (1 << 12) /* FIFO Reset */ -#define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */ - -/* DMA Target FIFO Register */ -#define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */ -#define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */ - -/* DMA Control Register */ -#define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */ -#define DMACTRL_LEN_SHIFT 8 -#define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */ -#define DMACTRL_ABORT (1 << 3) /* DMA abort */ -#define DMACTRL_IO2IO (1 << 2) /* IO to IO */ -#define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */ -#define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */ -#define DMACTRL_START (1 << 0) /* DMA start */ - -#endif diff --git a/include/usb/fusbh200.h b/include/usb/fusbh200.h deleted file mode 100644 index 6ae1d848801..00000000000 --- a/include/usb/fusbh200.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#ifndef _FUSBH200_H -#define _FUSBH200_H - -struct fusbh200_regs { - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ - uint32_t rsvd[2]; - uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ - uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ - uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ -}; - -/* EOF & Async. Schedule Sleep Timer Register */ -#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ -#define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ -#define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* Bus Monitor Control Status Register */ -#define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ -#define BMCSR_SPD_LOW (1 << 9) -#define BMCSR_SPD_FULL (0 << 9) -#define BMCSR_SPD_MASK (3 << 9) -#define BMCSR_SPD_SHIFT 9 -#define BMCSR_SPD(x) ((x >> 9) & 0x03) -#define BMCSR_VBUS (1 << 8) /* VBUS Valid */ -#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ -#define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ -#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ -#define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ -#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ -#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ -#define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ -#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ -#define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ - -/* Bus Monitor Interrupt Status Register */ -/* Bus Monitor Interrupt Enable Register */ -#define BMISR_DMAERR (1 << 4) /* DMA error */ -#define BMISR_DMA (1 << 3) /* DMA complete */ -#define BMISR_DEVRM (1 << 2) /* device removed */ -#define BMISR_OVD (1 << 1) /* over-current detected */ -#define BMISR_VBUSERR (1 << 0) /* VBUS error */ - -#endif diff --git a/tools/.gitignore b/tools/.gitignore index 28e8ce2a07a..788ea260a07 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -33,7 +33,6 @@ /relocate-rela /spl_size_limit /sunxi-spl-image-builder -/ubsha1 /update_octeon_header /version.h /xway-swap-bytes diff --git a/tools/Makefile b/tools/Makefile index edfa40903d9..041c437e65b 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -27,9 +27,7 @@ ifneq ($(HOST_TOOLS_ALL),) CONFIG_ARCH_KIRKWOOD = y CONFIG_CMD_LOADS = y CONFIG_CMD_NET = y -CONFIG_XWAY_SWAP_BYTES = y CONFIG_NETCONSOLE = y -CONFIG_SHA1_CHECK_UB_IMG = y CONFIG_ARCH_SUNXI = y endif @@ -62,9 +60,6 @@ HOSTCFLAGS_gen_ethaddr_crc.o := -pedantic hostprogs-$(CONFIG_CMD_LOADS) += img2srec HOSTCFLAGS_img2srec.o := -pedantic -hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes -HOSTCFLAGS_xway-swap-bytes.o := -pedantic - hostprogs-y += mkenvimage mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o @@ -158,9 +153,9 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o file2include-objs := file2include.o ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_TOOLS_LIBCRYPTO),) -# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register +# Add CFG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . -HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS +HOSTCFLAGS_mxsimage.o += -DCFG_MXS endif ifdef CONFIG_TOOLS_LIBCRYPTO @@ -217,11 +212,6 @@ hostprogs-$(CONFIG_ARCH_SUNXI) += sunxi-spl-image-builder sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o lib/bch.o hostprogs-$(CONFIG_NETCONSOLE) += ncb -hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1 - -ubsha1-objs := os_support.o ubsha1.o lib/sha1.o - -HOSTCFLAGS_ubsha1.o := -pedantic hostprogs-$(CONFIG_ARCH_KIRKWOOD) += kwboot hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot diff --git a/tools/moveconfig.py b/tools/moveconfig.py index 8f084a6070a..c4d72ede368 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -93,6 +93,18 @@ SIZES = { RE_REMOVE_DEFCONFIG = re.compile(r'(.*)_defconfig') +# CONFIG symbols present in the build system (from Linux) but not actually used +# in U-Boot; KCONFIG symbols +IGNORE_SYMS = ['DEBUG_SECTION_MISMATCH', 'FTRACE_MCOUNT_RECORD', 'GCOV_KERNEL', + 'GCOV_PROFILE_ALL', 'KALLSYMS', 'KASAN', 'MODVERSIONS', 'SHELL', + 'TPL_BUILD', 'VPL_BUILD', 'IS_ENABLED', 'FOO', 'IF_ENABLED_INT', + 'IS_ENABLED_', 'IS_ENABLED_1', 'IS_ENABLED_2', 'IS_ENABLED_3', + 'SPL_', 'TPL_', 'SPL_FOO', 'TPL_FOO', 'TOOLS_FOO', + 'ACME', 'SPL_ACME', 'TPL_ACME', 'TRACE_BRANCH_PROFILING', + 'VAL', '_UNDEFINED', 'SPL_BUILD', ] + +SPL_PREFIXES = ['SPL_', 'TPL_', 'VPL_', 'TOOLS_'] + ### helper functions ### def check_top_directory(): """Exit if we are not at the top of source directory.""" @@ -536,6 +548,7 @@ class KconfigScanner: os.environ['srctree'] = os.getcwd() os.environ['UBOOTVERSION'] = 'dummy' os.environ['KCONFIG_OBJDIR'] = '' + os.environ['CC'] = 'gcc' self.conf = kconfiglib.Kconfig() @@ -1593,6 +1606,319 @@ def prefix_config(cfg): return op + cfg +RE_MK_CONFIGS = re.compile('CONFIG_(\$\(SPL_(?:TPL_)?\))?([A-Za-z0-9_]*)') +RE_IFDEF = re.compile('(ifdef|ifndef)') +RE_C_CONFIGS = re.compile('CONFIG_([A-Za-z0-9_]*)') +RE_CONFIG_IS = re.compile('CONFIG_IS_ENABLED\(([A-Za-z0-9_]*)\)') + +class ConfigUse: + def __init__(self, cfg, is_spl, fname, rest): + self.cfg = cfg + self.is_spl = is_spl + self.fname = fname + self.rest = rest + + def __hash__(self): + return hash((self.cfg, self.is_spl)) + +def scan_makefiles(fnames): + """Scan Makefiles looking for Kconfig options + + Looks for uses of CONFIG options in Makefiles + + Args: + fnames (list of tuple): + str: Makefile filename where the option was found + str: Line of the Makefile + + Returns: + tuple: + dict: all_uses + key (ConfigUse): object + value (list of str): matching lines + dict: Uses by filename + key (str): filename + value (set of ConfigUse): uses in that filename + + >>> RE_MK_CONFIGS.search('CONFIG_FRED').groups() + (None, 'FRED') + >>> RE_MK_CONFIGS.search('CONFIG_$(SPL_)MARY').groups() + ('$(SPL_)', 'MARY') + >>> RE_MK_CONFIGS.search('CONFIG_$(SPL_TPL_)MARY').groups() + ('$(SPL_TPL_)', 'MARY') + """ + all_uses = collections.defaultdict(list) + fname_uses = {} + for fname, rest in fnames: + m_iter = RE_MK_CONFIGS.finditer(rest) + found = False + for m in m_iter: + found = True + real_opt = m.group(2) + if real_opt == '': + continue + is_spl = False + if m.group(1): + is_spl = True + use = ConfigUse(real_opt, is_spl, fname, rest) + if fname not in fname_uses: + fname_uses[fname] = set() + fname_uses[fname].add(use) + all_uses[use].append(rest) + return all_uses, fname_uses + + +def scan_src_files(fnames): + """Scan source files (other than Makefiles) looking for Kconfig options + + Looks for uses of CONFIG options + + Args: + fnames (list of tuple): + str: Makefile filename where the option was found + str: Line of the Makefile + + Returns: + tuple: + dict: all_uses + key (ConfigUse): object + value (list of str): matching lines + dict: Uses by filename + key (str): filename + value (set of ConfigUse): uses in that filename + + >>> RE_C_CONFIGS.search('CONFIG_FRED').groups() + ('FRED',) + >>> RE_CONFIG_IS.search('CONFIG_IS_ENABLED(MARY)').groups() + ('MARY',) + >>> RE_CONFIG_IS.search('#if CONFIG_IS_ENABLED(OF_PLATDATA)').groups() + ('OF_PLATDATA',) + """ + def add_uses(m_iter, is_spl): + for m in m_iter: + found = True + real_opt = m.group(1) + if real_opt == '': + continue + use = ConfigUse(real_opt, is_spl, fname, rest) + if fname not in fname_uses: + fname_uses[fname] = set() + fname_uses[fname].add(use) + all_uses[use].append(rest) + + all_uses = collections.defaultdict(list) + fname_uses = {} + for fname, rest in fnames: + m_iter = RE_C_CONFIGS.finditer(rest) + add_uses(m_iter, False) + + m_iter2 = RE_CONFIG_IS.finditer(rest) + add_uses(m_iter2, True) + + return all_uses, fname_uses + + +MODE_NORMAL, MODE_SPL, MODE_PROPER = range(3) + +def do_scan_source(path, do_update): + """Scan the source tree for Kconfig inconsistencies + + Args: + path (str): Path to source tree + do_update (bool) : True to write to scripts/kconf_... files + """ + def is_not_proper(name): + for prefix in SPL_PREFIXES: + if name.startswith(prefix): + return name[len(prefix):] + return False + + def check_not_found(all_uses, spl_mode): + """Check for Kconfig options mentioned in the source but not in Kconfig + + Args: + all_uses (dict): + key (ConfigUse): object + value (list of str): matching lines + spl_mode (int): If MODE_SPL, look at source code which implies + an SPL_ option, but for which there is none; + for MOD_PROPER, look at source code which implies a Proper + option (i.e. use of CONFIG_IS_ENABLED() or $(SPL_) or + $(SPL_TPL_) but for which there none; + if MODE_NORMAL, ignore SPL + + Returns: + dict: + key (str): CONFIG name (without 'CONFIG_' prefix + value (list of ConfigUse): List of uses of this CONFIG + """ + # Make sure we know about all the options + not_found = collections.defaultdict(list) + for use, rest in all_uses.items(): + name = use.cfg + if name in IGNORE_SYMS: + continue + check = True + + if spl_mode == MODE_SPL: + check = use.is_spl + + # If it is an SPL symbol, try prepending all SPL_ prefixes to + # find at least one SPL symbol + if use.is_spl: + add_to_dict = False + for prefix in SPL_PREFIXES: + try_name = prefix + name + sym = kconf.syms.get(try_name) + if sym: + break + if not sym: + not_found[f'SPL_{name}'].append(use) + continue + elif spl_mode == MODE_PROPER: + # Try to find the Proper version of this symbol, i.e. without + # the SPL_ prefix + proper_name = is_not_proper(name) + if proper_name: + name = proper_name + elif not use.is_spl: + check = False + else: # MODE_NORMAL + debug = False + sym = kconf.syms.get(name) + if not sym: + proper_name = is_not_proper(name) + if proper_name: + name = proper_name + sym = kconf.syms.get(name) + if not sym: + for prefix in SPL_PREFIXES: + try_name = prefix + name + sym = kconf.syms.get(try_name) + if sym: + break + if not sym: + not_found[name].append(use) + continue + + sym = kconf.syms.get(name) + if not sym and check: + not_found[name].append(use) + return not_found + + def show_uses(uses): + """Show a list of uses along with their filename and code snippet + + Args: + uses (dict): + key (str): CONFIG name (without 'CONFIG_' prefix + value (list of ConfigUse): List of uses of this CONFIG + """ + for name in sorted(uses): + print(f'{name}: ', end='') + for i, use in enumerate(uses[name]): + print(f'{" " if i else ""}{use.fname}: {use.rest.strip()}') + + + print('Scanning Kconfig') + kconf = KconfigScanner().conf + print(f'Scanning source in {path}') + args = ['git', 'grep', '-E', r'IS_ENABLED|\bCONFIG'] + with subprocess.Popen(args, stdout=subprocess.PIPE) as proc: + out, err = proc.communicate() + lines = out.splitlines() + re_fname = re.compile('^([^:]*):(.*)') + src_list = [] + mk_list = [] + for line in lines: + linestr = line.decode('utf-8') + m_fname = re_fname.search(linestr) + if not m_fname: + continue + fname, rest = m_fname.groups() + dirname, leaf = os.path.split(fname) + root, ext = os.path.splitext(leaf) + if ext == '.autoconf': + pass + elif ext in ['.c', '.h', '.S', '.lds', '.dts', '.dtsi', '.asl', '.cfg', + '.env', '.tmpl']: + src_list.append([fname, rest]) + elif 'Makefile' in root or ext == '.mk': + mk_list.append([fname, rest]) + elif ext in ['.yml', '.sh', '.py', '.awk', '.pl', '.rst', '', '.sed']: + pass + elif 'Kconfig' in root or 'Kbuild' in root: + pass + elif 'README' in root: + pass + elif dirname in ['configs']: + pass + elif dirname.startswith('doc') or dirname.startswith('scripts/kconfig'): + pass + else: + print(f'Not sure how to handle file {fname}') + + # Scan the Makefiles + all_uses, fname_uses = scan_makefiles(mk_list) + + spl_not_found = set() + proper_not_found = set() + + # Make sure we know about all the options + print('\nCONFIG options present in Makefiles but not Kconfig:') + not_found = check_not_found(all_uses, MODE_NORMAL) + show_uses(not_found) + + print('\nCONFIG options present in Makefiles but not Kconfig (SPL):') + not_found = check_not_found(all_uses, MODE_SPL) + show_uses(not_found) + spl_not_found |= set([is_not_proper(key) or key for key in not_found.keys()]) + + print('\nCONFIG options used as Proper in Makefiles but without a non-SPL_ variant:') + not_found = check_not_found(all_uses, MODE_PROPER) + show_uses(not_found) + proper_not_found |= set([key for key in not_found.keys()]) + + # Scan the source code + all_uses, fname_uses = scan_src_files(src_list) + + # Make sure we know about all the options + print('\nCONFIG options present in source but not Kconfig:') + not_found = check_not_found(all_uses, MODE_NORMAL) + show_uses(not_found) + + print('\nCONFIG options present in source but not Kconfig (SPL):') + not_found = check_not_found(all_uses, MODE_SPL) + show_uses(not_found) + spl_not_found |= set([is_not_proper(key) or key for key in not_found.keys()]) + + print('\nCONFIG options used as Proper in source but without a non-SPL_ variant:') + not_found = check_not_found(all_uses, MODE_PROPER) + show_uses(not_found) + proper_not_found |= set([key for key in not_found.keys()]) + + print('\nCONFIG options used as SPL but without an SPL_ variant:') + for item in sorted(spl_not_found): + print(f' {item}') + + print('\nCONFIG options used as Proper but without a non-SPL_ variant:') + for item in sorted(proper_not_found): + print(f' {item}') + + # Write out the updated information + if do_update: + with open(os.path.join(path, 'scripts', 'conf_nospl'), 'w') as out: + print('# These options should not be enabled in SPL builds\n', + file=out) + for item in sorted(spl_not_found): + print(item, file=out) + with open(os.path.join(path, 'scripts', 'conf_noproper'), 'w') as out: + print('# These options should not be enabled in Proper builds\n', + file=out) + for item in sorted(proper_not_found): + print(item, file=out) + + def main(): try: cpu_count = multiprocessing.cpu_count() @@ -1642,10 +1968,14 @@ doc/develop/moveconfig.rst for documentation.''' help='force sync by savedefconfig') parser.add_argument('-S', '--spl', action='store_true', default=False, help='parse config options defined for SPL build') + parser.add_argument('--scan-source', action='store_true', default=False, + help='scan source for uses of CONFIG options') parser.add_argument('-t', '--test', action='store_true', default=False, help='run unit tests') parser.add_argument('-y', '--yes', action='store_true', default=False, help="respond 'yes' to any prompts") + parser.add_argument('-u', '--update', action='store_true', default=False, + help="update scripts/ files (use with --scan-source)") parser.add_argument('-v', '--verbose', action='store_true', default=False, help='show any build errors as boards are built') parser.add_argument('configs', nargs='*') @@ -1660,6 +1990,10 @@ doc/develop/moveconfig.rst for documentation.''' return 1 unittest.main() + if args.scan_source: + do_scan_source(os.getcwd(), args.update) + return + if not any((len(configs), args.force_sync, args.build_db, args.imply, args.find)): parser.print_usage() diff --git a/tools/mxsimage.c b/tools/mxsimage.c index fee022aab46..fbe46c47fae 100644 --- a/tools/mxsimage.c +++ b/tools/mxsimage.c @@ -5,7 +5,7 @@ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> */ -#ifdef CONFIG_MXS +#ifdef CFG_MXS #include <errno.h> #include <fcntl.h> diff --git a/tools/ubsha1.c b/tools/ubsha1.c deleted file mode 100644 index 90a6f3f59d2..00000000000 --- a/tools/ubsha1.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, <hs@denx.de> - */ - -#include "os_support.h" -#include <stdio.h> -#include <stdlib.h> -#include <unistd.h> -#include <fcntl.h> -#include <errno.h> -#include <string.h> -#include <sys/stat.h> -#include <u-boot/sha1.h> - -int main (int argc, char **argv) -{ - unsigned char output[20]; - int i, len; - - char *imagefile; - char *cmdname = *argv; - unsigned char *ptr; - unsigned char *data; - struct stat sbuf; - unsigned char *ptroff; - int ifd; - int off; - - if (argc > 1) { - imagefile = argv[1]; - ifd = open (imagefile, O_RDWR|O_BINARY); - if (ifd < 0) { - fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - if (fstat (ifd, &sbuf) < 0) { - fprintf (stderr, "%s: Can't stat %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - len = sbuf.st_size; - ptr = (unsigned char *)mmap(0, len, - PROT_READ, MAP_SHARED, ifd, 0); - if (ptr == (unsigned char *)MAP_FAILED) { - fprintf (stderr, "%s: Can't read %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - /* create a copy, so we can blank out the sha1 sum */ - data = malloc (len); - memcpy (data, ptr, len); - off = SHA1_SUM_POS; - ptroff = &data[len + off]; - for (i = 0; i < SHA1_SUM_LEN; i++) { - ptroff[i] = 0; - } - - sha1_csum ((unsigned char *) data, len, (unsigned char *)output); - - printf ("U-Boot sum:\n"); - for (i = 0; i < 20 ; i++) { - printf ("%02X ", output[i]); - } - printf ("\n"); - /* overwrite the sum in the bin file, with the actual */ - lseek (ifd, SHA1_SUM_POS, SEEK_END); - if (write (ifd, output, SHA1_SUM_LEN) != SHA1_SUM_LEN) { - fprintf (stderr, "%s: Can't write %s: %s\n", - cmdname, imagefile, strerror(errno)); - exit (EXIT_FAILURE); - } - - free (data); - (void) munmap((void *)ptr, len); - (void) close (ifd); - } - - return EXIT_SUCCESS; -} diff --git a/tools/xway-swap-bytes.c b/tools/xway-swap-bytes.c deleted file mode 100644 index 3a6d82d54a0..00000000000 --- a/tools/xway-swap-bytes.c +++ /dev/null @@ -1,38 +0,0 @@ -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <unistd.h> - -#ifndef BUFSIZ -# define BUFSIZ 4096 -#endif - -#undef BUFSIZ -# define BUFSIZ 64 -int main (void) -{ - short ibuff[BUFSIZ], obuff[BUFSIZ]; - int rc, i, len; - - while ((rc = read (0, ibuff, sizeof (ibuff))) > 0) { - memset (obuff, 0, sizeof (obuff)); - for (i = 0; i < (rc + 1) / 2; i++) { - obuff[i] = ibuff[i ^ 1]; - } - - len = (rc + 1) & ~1; - - if (write (1, obuff, len) != len) { - perror ("read error"); - return (EXIT_FAILURE); - } - - memset (ibuff, 0, sizeof (ibuff)); - } - - if (rc < 0) { - perror ("read error"); - return (EXIT_FAILURE); - } - return (EXIT_SUCCESS); -} |