diff options
124 files changed, 5520 insertions, 574 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index ba351b9802d..db471e67107 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -295,7 +295,7 @@ stages: export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH} export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci # "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not - ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml + ./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_EXTRA} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml # the below corresponds to .gitlab-ci.yml "after_script" rm -rf /tmp/uboot-test-hooks /tmp/venv EOF @@ -318,6 +318,7 @@ stages: matrix: sandbox: TEST_PY_BD: "sandbox" + TEST_PY_EXTRA: "--timing" sandbox_asan: TEST_PY_BD: "sandbox" OVERRIDE: "-a ASAN" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 74dc05d58a7..a93703fdcea 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -96,7 +96,7 @@ stages: # "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not - export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH}; export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci; - ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} + ./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_EXTRA} ${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"} --build-dir "$UBOOT_TRAVIS_BUILD_DIR" --junitxml=/tmp/${TEST_PY_BD}/results.xml @@ -234,6 +234,7 @@ sandbox test.py: - ${DEFAULT_AMD64_TAG} variables: TEST_PY_BD: "sandbox" + TEST_PY_EXTRA: "--timing" <<: *buildman_and_testpy_dfn sandbox with clang test.py: diff --git a/MAINTAINERS b/MAINTAINERS index dc8e048dde4..247f525847e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -386,6 +386,14 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/pci/pci-aardvark.c F: drivers/pci/pci_mvebu.c +ARM MARVELL PXA1908 +M: Duje Mihanović <duje.mihanovic@skole.hr> +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: arch/arm/dts/pxa1908* +F: arch/arm/mach-mmp/ +F: include/configs/pxa1908.h + ARM MARVELL SERIAL DRIVERS M: Pali Rohár <pali@kernel.org> M: Stefan Roese <sr@denx.de> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 314916527c9..f504d7d0760 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -842,6 +842,15 @@ config ARCH_MEDIATEK Support for the MediaTek SoCs family developed by MediaTek Inc. Please refer to doc/README.mediatek for more information. +config ARCH_MMP + bool "Marvell MMP" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + select SAVE_PREV_BL_FDT_ADDR + select SAVE_PREV_BL_INITRAMFS_START_ADDR + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -2310,6 +2319,8 @@ source "arch/arm/mach-meson/Kconfig" source "arch/arm/mach-mediatek/Kconfig" +source "arch/arm/mach-mmp/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cb87a684754..7334e79965f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson +machine-$(CONFIG_ARCH_MMP) += mmp machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_NEXELL) += nexell machine-$(CONFIG_ARCH_NPCM) += npcm diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b7df72453ac..0bf3697bdbe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1226,6 +1226,8 @@ dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ corstone1000-fvp.dtb +dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb + include $(srctree)/scripts/Makefile.dts # Add any required device tree compiler flags here diff --git a/arch/arm/dts/mt7987-emmc.dtsi b/arch/arm/dts/mt7987-emmc.dtsi new file mode 100644 index 00000000000..80ab04d9d20 --- /dev/null +++ b/arch/arm/dts/mt7987-emmc.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +#include "mt7987-pinctrl.dtsi" + +/ { + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +/* Disable spi0/spi1 node since MSDC shares pins with spi0 and spi1*/ +&spi0 { + status = "disabled"; +}; + +&spi1 { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc_pins_default>; + pinctrl-1 = <&mmc_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x12814>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_3p3v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7987-netsys-u-boot.dtsi b/arch/arm/dts/mt7987-netsys-u-boot.dtsi new file mode 100644 index 00000000000..3d6640b33ab --- /dev/null +++ b/arch/arm/dts/mt7987-netsys-u-boot.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/clock/mediatek,mt7987-clk.h> +#include <dt-bindings/reset/mt7988-reset.h> + +&netsys { + eth0: ethernet@15110100 { + compatible = "mediatek,mt7987-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <0>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>; + mediatek,infracfg = <&topmisc>; + resets = <ðsys ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@15110200 { + compatible = "mediatek,mt7987-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <1>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + resets = <ðsys ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth2: ethernet@15110300 { + compatible = "mediatek,mt7987-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; + mediatek,gmac-id = <2>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + resets = <ðsys ETHDMA_FE_RST>; + reset-names = "fe"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/mt7987-pinctrl-u-boot.dtsi b/arch/arm/dts/mt7987-pinctrl-u-boot.dtsi new file mode 100644 index 00000000000..991f38efef9 --- /dev/null +++ b/arch/arm/dts/mt7987-pinctrl-u-boot.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +&pio { + /delete-node/ mmc-pins-default; + /delete-node/ mmc-pins-uhs; + /delete-node/ sd-pins-default; + /delete-node/ sd-pins-uhs; + /delete-node/ spi0-pins; + /delete-node/ spi2-pins; + + mmc_pins_default: mmc0default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + mmc_pins_uhs: mmc-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + sd_pins_default: sd-pins-default { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + }; + + sd_pins_uhs: sd-pins-uhs { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987-pinctrl.dtsi b/arch/arm/dts/mt7987-pinctrl.dtsi new file mode 100644 index 00000000000..b5e643feffe --- /dev/null +++ b/arch/arm/dts/mt7987-pinctrl.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +&pio { + mmc_pins_default: mmc-pins-default { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc_pins_uhs: mmc-pins-uhs { + mux { + function = "flash"; + groups = "emmc_45"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI0_HOLD", "SPI0_WP", + "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "USB_VBUS"; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + sd_pins_default: sd-pins-default { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + }; + + sd_pins_uhs: sd-pins-uhs { + mux { + function = "flash"; + groups = "sd"; + }; + conf-cmd-dat { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", + "SPI0_CS", "SPI1_MISO"; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "SPI1_CS"; + drive-strength = <MTK_DRIVE_6mA>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio"; + }; + + conf { + groups = "mdc_mdio"; + drive-strength = <MTK_DRIVE_6mA>; + }; + }; + + i2p5gbe_led0_pins: i2p5gbe0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + + i2p5gbe_led1_0_pins: i2p5gbe1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1_0"; + }; + }; + + i2p5gbe_led1_1_pins: i2p5gbe2-pins { + mux { + function = "led"; + groups = "2p5gbe_led1_1"; + }; + }; + + i2c0_pins: i2c0-pins-g2 { + mux { + function = "i2c"; + groups = "i2c0_2"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie0_pereset", "pcie0_clkreq", + "pcie0_wake"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie1_pereset", "pcie1_clkreq", + "pcie1_wake"; + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; + + spi2_flash_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; + + i2c1_pins: i2c1-pins { + mux { + function = "i2c"; + groups = "i2c0_2"; + }; + }; + + i2s_pins: i2s-pins { + mux { + function = "i2s"; + groups = "pcm0_1"; + }; + }; + + pcm_pins: pcm-pins { + mux { + function = "pcm"; + groups = "pcm0_1"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_2"; + }; + }; +}; diff --git a/arch/arm/dts/mt7987-sd.dtsi b/arch/arm/dts/mt7987-sd.dtsi new file mode 100644 index 00000000000..4c8ca48c293 --- /dev/null +++ b/arch/arm/dts/mt7987-sd.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "mt7987-pinctrl.dtsi" + +/ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +/* Disable spi0/spi1 node since MSDC shares pins with spi0 and spi1*/ +&spi0 { + status = "disabled"; +}; + +&spi1 { + status = "disabled"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&sd_pins_default>; + pinctrl-1 = <&sd_pins_uhs>; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm/dts/mt7987.dtsi b/arch/arm/dts/mt7987.dtsi new file mode 100644 index 00000000000..fd1585f658d --- /dev/null +++ b/arch/arm/dts/mt7987.dtsi @@ -0,0 +1,808 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/ti-syscon.h> +#include <dt-bindings/clock/mediatek,mt7987-clk.h> +#include <dt-bindings/pinctrl/mt65xx.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/regulator/richtek,rt5190a-regulator.h> + +/ { + compatible = "mediatek,mt7987"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clkxtal: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "clkxtal"; + }; + + vproc: regulator-vproc { + compatible = "regulator-fixed"; + regulator-name = "proc"; + regulator-min-microvolt = <8500000>; + regulator-max-microvolt = <8500000>; + regulator-boot-on; + regulator-always-on; + }; + + firmware { + optee { + method = "smc"; + compatible = "linaro,optee-tz"; + status = "okay"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x0>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x1>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x2>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + next-level-cache = <&l2_cache>; + reg = <0x3>; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&apmixedsys CLK_APMIXED_ARM_LL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <850000>; + }; + opp01 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <850000>; + }; + opp02 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <2000000000>; + opp-microvolt = <850000>; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + clk40m: clk40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + clkitg: clkitg { + compatible = "simple-bus"; + status = "disabled"; + }; + + clksys: soc_clksys { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7987-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7987-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7987-apmixedsys", "syscon"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7987-sgmiisys", + "mediatek,mt7987-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7987-sgmiisys", + "mediatek,mt7987-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + mcusys: mcusys@10400000 { + compatible = "mediatek,mt7987-mcusys", "syscon"; + reg = <0 0x10400000 0 0x1000>; + #clock-cells = <1>; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7987-ethdma", + "mediatek,mt7987-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = + <0x34 4 0x34 4 0x34 4 + (ASSERT_SET | DEASSERT_CLEAR | + STATUS_SET)>; + }; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 128 255>; + #cooling-cells = <2>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + wmcpu_emi: wmcpu-reserved@50000000 { + compatible = "mediatek,wmcpu-reserved"; + no-map; + reg = <0 0x50000000 0 0x00100000>; + }; + }; + + thermal-zones { + thermal_zone0: soc_thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active1: active1 { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active0: active0 { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <40000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-active-high { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active1>; + }; + + cpu-active-low { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active0>; + }; + + cpu-passive { + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + }; + + thermal_zone1: mcusys_thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 1>; + }; + + thermal_zone2: eth2p5g_thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 2>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + hwver: hwver@8000000 { + compatible = "mediatek,hwver", "syscon"; + reg = <0 0x8000000 0 0x1000>; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + infra_bus_prot: infra_bus_prot@1000310c { + compatible = "mediatek,infracfg_ao_bus_hang_prot"; + reg = <0 0x1000310c 0 0x14>; + status = "disabled"; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7622-wdt", + "mediatek,mt6589-wdt", + "syscon"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + status = "disabled"; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7987-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x11f60000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", + "iocfg_rt2", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 50>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + pcie1pereset { + gpio-hog; + gpios = <36 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; + + boottrap: boottrap@1001f6f0 { + compatible = "mediatek,boottrap"; + reg = <0 0x1001f6f0 0 0x20>; + status = "disabled"; + }; + + trng: trng@1020f000 { + compatible = "mediatek,mt7987-rng"; + status = "disabled"; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>, + <&clkxtal>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4","pwm5","pwm6","pwm7","pwm8"; + status = "disabled"; + }; + + uart0: serial@11000000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_52M_UART0_CK>, + <&infracfg CLK_INFRA_66M_UART0_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART0_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart1: serial@11000100 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000100 0 0x100>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_52M_UART1_CK>, + <&infracfg CLK_INFRA_66M_UART1_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART1_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart2: serial@11000200 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000200 0 0x100>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_52M_UART2_CK>, + <&infracfg CLK_INFRA_66M_UART2_PCK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART2_SEL>; + assigned-clock-parents = <&topckgen + CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11003000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@11007800 { + compatible = "mediatek,ipm-spi-quad", + "mediatek,spi-ipm"; + reg = <0 0x11007800 0 0x100>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI0>, + <&infracfg CLK_INFRA_66M_SPI0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_MUX_SPI0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + spi1: spi@11008800 { + compatible = "mediatek,ipm-spi-single", + "mediatek,spi-ipm"; + reg = <0 0x11008800 0 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI1>, + <&infracfg CLK_INFRA_66M_SPI1_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_MUX_SPI1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen + CLK_TOP_SPIM_MST_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + spi2: spi@11009800 { + compatible = "mediatek,ipm-spi-quad", + "mediatek,spi-ipm"; + reg = <0 0x11009800 0 0x100>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI2_BCK>, + <&infracfg CLK_INFRA_66M_SPI2_HCK>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg + CLK_INFRA_MUX_SPI2_BCK_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "hclk"; + status = "disabled"; + }; + + lvts: lvts@1100a000 { + compatible = "mediatek,mt7987-lvts"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100a000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; + clock-names = "lvts_clk"; + nvmem-cells = <&lvts_calibration>; + nvmem-cell-names = "e_data1"; + status = "disabled"; + }; + + usbtphy: usb-phy@11c50000 { + compatible = "mediatek,mt7987", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tphyu2port0: usb-phy@11c50000 { + reg = <0 0x11c50000 0 0x700>; + clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + + auto_load_valid; + nvmem-cells = <&u2_intr_p0>, + <&u2_auto_load_valid_p0>; + nvmem-cell-names = "intr", "auto_load_valid"; + }; + + tphyu3port0: usb-phy@11c50700 { + reg = <0 0x11c50700 0 0x900>; + clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + + auto_load_valid; + nvmem-cells = <&comb_intr_p0>, + <&comb_rx_imp_p0>, + <&comb_tx_imp_p0>, + <&comb_auto_load_valid>; + nvmem-cell-names = "intr", "rx_imp", "tx_imp", + "auto_load_valid"; + + /* MT7987: 4'b0010 default USB30 + * Don't change the '0' + */ + mediatek,syscon-type = <&topmisc 0x218 0>; + + status = "disabled"; + }; + }; + + xhci: xhci@11200000 { + compatible = "mediatek,mt7987-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + usb2-lpm-disable; + status = "disabled"; + }; + + afe: audio-controller@11210000 { + compatible = "mediatek,mt79xx-audio"; + reg = <0 0x11210000 0 0x9000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>, + <&infracfg CLK_INFRA_AUD_26M>, + <&infracfg CLK_INFRA_AUD_L>, + <&infracfg CLK_INFRA_AUD_AUD>, + <&infracfg CLK_INFRA_AUD_EG2>, + <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_AUD_I2S_M>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel", + "aud_i2s_m"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&apmixedsys + CLK_APMIXED_APLL2>, + <&topckgen + CLK_TOP_CB_APLL2_D4>, + <&apmixedsys + CLK_APMIXED_APLL2>, + <&topckgen + CLK_TOP_CB_APLL2_D4>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mediatek,mt7986-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_EMMC_200M_SEL>, + <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_MSDC200_SRC>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>; + clock-names = "source", "bus_clk", "axi_cg", "hclk", + "source_cg", "ahb_cg"; + status = "disabled"; + }; + + wed: wed { + compatible = "mediatek,wed"; + wed_num = <1>; + }; + + wed0: wed0@15010000 { + compatible = "mediatek,wed0"; + /* add this property for wed get the pci slot number */ + pci_slot_map = <0>; + reg = <0 0x15010000 0 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdma: wdma@15104800 { + compatible = "mediatek,wed-wdma"; + reg = <0 0x15104800 0 0x400>; + }; + + pcie0: pcie@11280000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7987-pcie", + "mediatek,mt7986-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <0>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x00200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x0fe00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@11290000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7987-pcie", + "mediatek,mt7986-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <1>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x30000000 0x00 + 0x30000000 0x00 0x00200000>, + <0x82000000 0x00 0x30200000 0x00 + 0x30200000 0x00 0x0fe00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + slot1: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + }; + }; + + topmisc: topmisc@10021000 { + compatible = "mediatek,mt7987-topmisc", "syscon", + "mediatek,mt7987-power-controller"; + reg = <0 0x10021000 0 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + /* power domain of the SoC */ + /* eth2p5@MT7988_POWER_DOMAIN_ETH2P5 { + * reg = <MT7988_POWER_DOMAIN_ETH2P5>; + * #power-domain-cells = <0>; + * }; + */ + }; + + efuse: efuse@11d30000 { + compatible = "mediatek,efuse"; + reg = <0 0x11d30000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_calibration: calib@918 { + reg = <0x918 0x10>; + }; + + comb_auto_load_valid: usb3-alv-imp@8ee { + reg = <0x8ee 1>; + bits = <0 1>; + }; + + comb_rx_imp_p0: usb3-rx-imp@8ec { + reg = <0x8ec 1>; + bits = <0 5>; + }; + + comb_tx_imp_p0: usb3-tx-imp@8ec { + reg = <0x8ec 2>; + bits = <5 5>; + }; + + comb_intr_p0: usb3-intr@8ec { + reg = <0x8ec 2>; + bits = <10 6>; + }; + + u2_auto_load_valid_p0: usb2-alv-p0@8cc { + reg = <0x8cc 1>; + bits = <0 1>; + }; + + u2_intr_p0: usb2-intr-p0@8cc { + reg = <0x8cc 1>; + bits = <1 5>; + }; + }; + + devapc: devapc@1a110000 { + compatible = "mediatek,mt7987-devapc"; + reg = <0 0x1a110000 0 0x1000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + netsys: soc_netsys { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + }; +}; diff --git a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi new file mode 100644 index 00000000000..54cf72b3bf8 --- /dev/null +++ b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +/ { + model = "mt7987"; + compatible = "mediatek,mt7987", "mediatek,mt7987-emmc-rfb"; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins_default>; + max-frequency = <48000000>; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-emmc-rfb.dts b/arch/arm/dts/mt7987a-emmc-rfb.dts new file mode 100644 index 00000000000..f59e5bd97bf --- /dev/null +++ b/arch/arm/dts/mt7987a-emmc-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include "mt7987-emmc.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987 EMMC RFB"; + compatible = "mediatek,mt7987a-emmc", + "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf ubi.block=0,firmware \ + root=/dev/fit0 rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi new file mode 100644 index 00000000000..f1ed51e21c4 --- /dev/null +++ b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nand@0; + spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-rfb.dts b/arch/arm/dts/mt7987a-rfb.dts new file mode 100644 index 00000000000..0ba6b8d9ad7 --- /dev/null +++ b/arch/arm/dts/mt7987a-rfb.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987A RFB"; + compatible = "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi new file mode 100644 index 00000000000..b07e6da41e2 --- /dev/null +++ b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "mt7987a-u-boot.dtsi" +#include "mt7987-netsys-u-boot.dtsi" + +/ { + model = "mt7987"; + compatible = "mediatek,mt7987", "mediatek,mt7987-sd-rfb"; +}; + +ð0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins>; + phy-mode = "2500base-x"; + mediatek,switch = "auto"; + reset-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins_default>; + max-frequency = <48000000>; + bus-width = <4>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_flash_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + must_tx; + enhance_timing; + dma_ext; + ipm_design; + support_quad; + tick_dly = <2>; + sample_sel = <0>; + + /delete-node/ spi_nor@0; + spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/mt7987a-sd-rfb.dts b/arch/arm/dts/mt7987a-sd-rfb.dts new file mode 100644 index 00000000000..85de4990682 --- /dev/null +++ b/arch/arm/dts/mt7987a-sd-rfb.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include "mt7987a.dtsi" +#include "mt7987-sd.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "MediaTek MT7987 SD RFB"; + compatible = "mediatek,mt7987a-sd", + "mediatek,mt7987a", "mediatek,mt7987"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf ubi.block=0,firmware \ + root=/dev/fit0 rootwait"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + }; + }; +}; diff --git a/arch/arm/dts/mt7987a-u-boot.dtsi b/arch/arm/dts/mt7987a-u-boot.dtsi new file mode 100644 index 00000000000..ec0a6389d8b --- /dev/null +++ b/arch/arm/dts/mt7987a-u-boot.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include "mt7987-pinctrl-u-boot.dtsi" + +/ { + cpus { + cpu@0 { + mediatek,hwver = <&hwver>; + }; + + cpu@1 { + mediatek,hwver = <&hwver>; + }; + + cpu@2 { + mediatek,hwver = <&hwver>; + }; + + cpu@3 { + mediatek,hwver = <&hwver>; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "disabled"; +}; + +&spi0 { + compatible = "mediatek,ipm-spi"; + clocks = <&infracfg CLK_INFRA_104M_SPI0>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "spi-clk", "sel-clk"; +}; + +&spi1 { + compatible = "mediatek,ipm-spi"; + clocks = <&infracfg CLK_INFRA_104M_SPI1>, + <&topckgen CLK_TOP_SPIM_MST_SEL>; + clock-names = "spi-clk", "sel-clk"; +}; + +&spi2 { + compatible = "mediatek,ipm-spi"; + clocks = <&infracfg CLK_INFRA_104M_SPI2_BCK>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "spi-clk", "sel-clk"; +}; diff --git a/arch/arm/dts/mt7987a.dtsi b/arch/arm/dts/mt7987a.dtsi new file mode 100644 index 00000000000..028f563fb39 --- /dev/null +++ b/arch/arm/dts/mt7987a.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +#include "mt7987.dtsi" +#include "mt7987-pinctrl.dtsi" + +/ { + compatible = "mediatek,mt7987a", "mediatek,mt7987"; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + +}; + +&afe { + pinctrl-names = "default"; + pinctrl-0 = <&pcm_pins>; + status = "okay"; +}; + +&boottrap { + status = "okay"; +}; + +&fan { + pwms = <&pwm 0 50000 0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&infra_bus_prot { + status = "okay"; +}; + +&lvts { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "disabled"; +}; + +&pwm { + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&xhci { + mediatek,u3p-dis-msk = <0x00000001>; + phys = <&tphyu2port0 PHY_TYPE_USB2>; + + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; + clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck", + "dma_ck"; + + status = "okay"; +}; diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts new file mode 100644 index 00000000000..588e39e9265 --- /dev/null +++ b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "pxa1908.dtsi" + +/ { + pxa,rev-id = <3928 2>; + model = "Samsung Galaxy Core Prime VE LTE"; + compatible = "samsung,coreprimevelte", "marvell,pxa1908"; + + aliases { + serial0 = &uart0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + /* S-Boot places the initramfs here */ + linux,initrd-start = <0x4d70000>; + linux,initrd-end = <0x5000000>; + + fb0: framebuffer@17177000 { + compatible = "simple-framebuffer"; + reg = <0 0x17177000 0 (480 * 800 * 4)>; + width = <480>; + height = <800>; + stride = <(480 * 4)>; + format = "a8r8g8b8"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x1000000 0 0x3f000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@17000000 { + reg = <0 0x17000000 0 0x1800000>; + no-map; + }; + + gpu@9000000 { + reg = <0 0x9000000 0 0x1000000>; + }; + + /* Communications processor, aka modem */ + cp@5000000 { + reg = <0 0x5000000 0 0x3000000>; + }; + + cm3@a000000 { + reg = <0 0xa000000 0 0x80000>; + }; + + seclog@8000000 { + reg = <0 0x8000000 0 0x100000>; + }; + + ramoops@8100000 { + compatible = "ramoops"; + reg = <0 0x8100000 0 0x40000>; + record-size = <0x8000>; + console-size = <0x20000>; + max-reason = <5>; + }; + }; +}; diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi new file mode 100644 index 00000000000..e8ec2606c25 --- /dev/null +++ b/arch/arm/dts/pxa1908.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell Armada PXA1908"; + compatible = "marvell,pxa1908"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0 3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@d1df9000 { + compatible = "arm,gic-400"; + reg = <0 0xd1df9000 0 0x1000>, + <0 0xd1dfa000 0 0x2000>, + /* The subsequent registers are guesses. */ + <0 0xd1dfc000 0 0x2000>, + <0 0xd1dfe000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apb@d4000000 { + compatible = "simple-bus"; + reg = <0 0xd4000000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xd4000000 0x200000>; + + uart0: serial@17000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x17000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart1: serial@18000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x18000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart2: serial@36000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; + reg = <0x36000 0x1000>; + clock-frequency = <117000000>; + reg-shift = <2>; + }; + }; + }; +}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 031d4e5ecd3..6761a9cb393 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -38,6 +38,7 @@ config TARGET_OPENRD bool "Marvell OpenRD Board" select KW88F6281 select SHEEVA_88SV131 + select KIRKWOOD_COMMON config TARGET_DREAMPLUG bool "DreamPlug Board" diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index ff1fdee5c8d..39eea055f70 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -59,6 +59,16 @@ config TARGET_MT7986 including UART, SPI, SPI flash, USB3.0, MMC, NAND, SNFI, PWM, PCIe, Gigabit Ethernet, I2C, built-in 4x4 Wi-Fi, and PCIe. +config TARGET_MT7987 + bool "MediaTek MT7987 SoC" + select ARM64 + select CPU + select MTK_TZ_MOVABLE + help + The MediaTek MT7987 is a ARM64-based SoC with a quad-core Cortex-A53. + including UART, I2C, PWM, SPI controller which support SPI flash, + USB3.0, MMC, PCIe, SGMII and built-in Ethernet PHY. + config TARGET_MT7988 bool "MediaTek MT7988 SoC" select ARM64 @@ -122,6 +132,7 @@ config SYS_BOARD default "mt7629" if TARGET_MT7629 default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 + default "mt7987" if TARGET_MT7987 default "mt7988" if TARGET_MT7988 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 @@ -139,6 +150,7 @@ config SYS_CONFIG_NAME default "mt7629" if TARGET_MT7629 default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 + default "mt7987" if TARGET_MT7987 default "mt7988" if TARGET_MT7988 default "mt8183" if TARGET_MT8183 default "mt8365" if TARGET_MT8365 @@ -150,7 +162,12 @@ config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 - default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988 + default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 default "lk=1" if TARGET_MT7623 +config MTK_TZ_MOVABLE + select ARCH_MISC_INIT + select OF_SYSTEM_SETUP + bool + endif diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index 3d9e4684fb4..344434c6029 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += cpu.o +obj-$(CONFIG_MTK_TZ_MOVABLE) += tzcfg.o obj-$(CONFIG_XPL_BUILD) += spl.o obj-$(CONFIG_MT8512) += mt8512/ @@ -9,6 +10,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt7623/ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ +obj-$(CONFIG_TARGET_MT7987) += mt7987/ obj-$(CONFIG_TARGET_MT7988) += mt7988/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ obj-$(CONFIG_TARGET_MT8365) += mt8365/ diff --git a/arch/arm/mach-mediatek/mt7987/Makefile b/arch/arm/mach-mediatek/mt7987/Makefile new file mode 100644 index 00000000000..007eb4a3679 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7987/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-mediatek/mt7987/init.c b/arch/arm/mach-mediatek/mt7987/init.c new file mode 100644 index 00000000000..8b268297809 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7987/init.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <fdtdec.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/global_data.h> +#include <asm/u-boot.h> +#include <asm/system.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_mem_size_base(); + if (ret) + return ret; + + gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_4G); + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +static struct mm_region mt7987_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x200000000ULL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt7987_mem_map; diff --git a/arch/arm/mach-mediatek/mt7987/lowlevel_init.S b/arch/arm/mach-mediatek/mt7987/lowlevel_init.S new file mode 100644 index 00000000000..2f972551277 --- /dev/null +++ b/arch/arm/mach-mediatek/mt7987/lowlevel_init.S @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +/* + * Switch from AArch64 EL2 to AArch32 EL2 + * @param inputs: + * x0: argument, zero + * x1: machine nr + * x2: fdt address + * x3: input argument + * x4: kernel entry point + * @param outputs for secure firmware: + * x0: function id + * x1: kernel entry point + * x2: machine nr + * x3: fdt address +*/ + +.global armv8_el2_to_aarch32 +armv8_el2_to_aarch32: + mov x3, x2 + mov x2, x1 + mov x1, x4 + mov x4, #0 + ldr x0, =0x82000200 + SMC #0 + ret diff --git a/arch/arm/mach-mediatek/tzcfg.c b/arch/arm/mach-mediatek/tzcfg.c new file mode 100644 index 00000000000..71982ba4d20 --- /dev/null +++ b/arch/arm/mach-mediatek/tzcfg.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <errno.h> +#include <stdio.h> +#include <asm/global_data.h> +#include <linux/kernel.h> +#include <linux/arm-smccc.h> +#include <linux/sizes.h> +#include <command.h> +#include <fdtdec.h> +#include <fdt_support.h> +#include <lmb.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define MTK_SIP_GET_BL31_REGION 0x82000300 +#define MTK_SIP_GET_BL32_REGION 0x82000301 + +#define BL31_DEFAULT_ADDR 0x43000000 +#define BL31_DEFAULT_SIZE 0x80000 + +#define TZ_REGION_MAX_SIZE SZ_16M +#define U_BOOT_MIN_SIZE SZ_4M +#define U_BOOT_MIN_STACK_SIZE SZ_1M +#define REGION_ALIGNMENT SZ_64K + +struct tz_reserved_region { + phys_addr_t addr; + phys_addr_t size; +}; + +static bool fix_tz_region(struct tz_reserved_region region[], + uint32_t used_regions) +{ + phys_addr_t size; + + if (region[0].addr + region[0].size > gd->ram_top) { + if (region[0].addr >= gd->ram_top) { + debug("Discarded region 0x%08llx, size 0x%llx\n", + region[0].addr, region[0].size); + + if (used_regions > 1) + region[0] = region[1]; + + return true; + } + + size = gd->ram_top - region[0].addr; + + debug("Truncated region 0x%08llx, size 0x%llx -> 0x%llx\n", + region[0].addr, region[0].size, size); + + region[0].size = size; + } + + return false; +} + +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + phys_addr_t uboot_ram_top, pstore_size, uboot_size = 0; + struct tz_reserved_region region[2], tmp; + phys_addr_t top_addr, low_addr; + struct arm_smccc_res res; + u32 used_regions = 1; + + /* BL31 region */ + arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { + /* Assume PIE is not enabled for BL31 */ + region[0].addr = BL31_DEFAULT_ADDR; + region[0].size = BL31_DEFAULT_SIZE; + } else { + region[0].addr = res.a1; + region[0].size = res.a2; + } + + debug("BL31 @ 0x%08llx, size 0x%llx\n", region[0].addr, + region[0].size); + + /* BL32 region is optional */ + arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0 && res.a1 && res.a2) { + region[used_regions].addr = res.a1; + region[used_regions].size = res.a2; + + debug("BL32 @ 0x%08llx, size 0x%llx\n", + region[used_regions].addr, region[used_regions].size); + + used_regions++; + } + + if (used_regions == 2) { + if (region[0].addr < region[1].addr) { + /* Make sure region[0] is higher than region[1] */ + tmp = region[0]; + region[0] = region[1]; + region[1] = tmp; + } + + top_addr = region[0].addr + region[0].size; + low_addr = min_t(phys_addr_t, region[0].addr, region[1].addr); + + if (top_addr - low_addr <= TZ_REGION_MAX_SIZE) { + /* Merge region if they're overlapped or close enough */ + region[0].size = top_addr - low_addr; + region[0].addr = low_addr; + + debug("Merged region @ 0x%08llx, size 0x%llx\n", + region[0].addr, region[0].size); + + used_regions = 1; + } + } + + debug("Effective memory @ 0x%08zx, size 0x%llx\n", gd->ram_base, + gd->ram_top - gd->ram_base); + + /* Discard/fix region which is outside the effective memory */ + if (fix_tz_region(region, used_regions)) { + used_regions--; + + if (used_regions) { + if (fix_tz_region(region, used_regions)) + used_regions--; + } + } + + /* Size needed for u-boot & pstore */ +#if IS_ENABLED(CONFIG_CMD_PSTORE) + /* pstore will be placed under ram top */ + pstore_size = (CONFIG_CMD_PSTORE_MEM_SIZE + REGION_ALIGNMENT - 1) & + ~(REGION_ALIGNMENT - 1); + /* u-boot will be placed under pstore */ + uboot_size += pstore_size; +#endif + + uboot_size += max_t(uintptr_t, U_BOOT_MIN_SIZE, total_size); + uboot_size += U_BOOT_MIN_STACK_SIZE + REGION_ALIGNMENT - 1; + uboot_size &= ~(REGION_ALIGNMENT - 1); + + uboot_ram_top = gd->ram_top & ~(REGION_ALIGNMENT - 1); + + if (!used_regions || + (uboot_ram_top - region[0].addr - region[0].size >= uboot_size)) { + /* No reserved region present, + * or gap between high region and ram top is large enough + */ + uboot_ram_top -= pstore_size; + return uboot_ram_top; + } + + uboot_ram_top = region[0].addr & ~(REGION_ALIGNMENT - 1); + + if (used_regions == 2 && + (uboot_ram_top - region[1].addr - region[1].size >= uboot_size)) { + /* Gap between high region and low region is large enough */ + uboot_ram_top -= pstore_size; + return uboot_ram_top; + } + + uboot_ram_top = region[used_regions - 1].addr & ~(REGION_ALIGNMENT - 1); + + /* Under low region */ + uboot_ram_top -= pstore_size; + return uboot_ram_top; +} + +int arch_misc_init(void) +{ + struct arm_smccc_res res; + + /* + * Since board_get_usable_ram_top is be called before arch_misc_init, + * there's no need to check the result + */ + arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + lmb_reserve(res.a1, res.a2, LMB_NOMAP); + + arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0 && res.a1 && res.a2) + lmb_reserve(res.a1, res.a2, LMB_NOMAP); + +#if IS_ENABLED(CONFIG_CMD_PSTORE) + char cmd[64]; + + /* Override default pstore address */ + snprintf(cmd, sizeof(cmd), "pstore set 0x%llx 0x%x", gd->ram_top, + CONFIG_CMD_PSTORE_MEM_SIZE); + run_command(cmd, 0); +#endif + + return 0; +} + +/* For board-level setup */ +__weak int mtk_ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + +int ft_system_setup(void *blob, struct bd_info *bd) +{ + struct arm_smccc_res res; + struct fdt_memory mem; + int ret; + + arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + + mem.start = res.a1; + mem.end = res.a1 + res.a2 - 1; + + ret = fdtdec_add_reserved_memory(blob, "secmon", &mem, NULL, 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); + if (ret < 0) { + log_err("Failed to add reserved-memory for BL31: %s\n", + fdt_strerror(ret)); + return ret; + } + + arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0 && res.a1 && res.a2) { + mem.start = res.a1; + mem.end = res.a1 + res.a2 - 1; + + ret = fdtdec_add_reserved_memory(blob, "trustzone", &mem, NULL, + 0, NULL, + FDTDEC_RESERVED_MEMORY_NO_MAP); + if (ret < 0) { + log_err("Failed to add reserved-memory for BL32: %s\n", + fdt_strerror(ret)); + return ret; + } + } + + return mtk_ft_system_setup(blob, bd); +} diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig new file mode 100644 index 00000000000..889f127fe82 --- /dev/null +++ b/arch/arm/mach-mmp/Kconfig @@ -0,0 +1,12 @@ +if ARCH_MMP + +config TARGET_COREPRIMEVELTE + bool "Support coreprimevelte" + select LINUX_KERNEL_IMAGE_HEADER + +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default TEXT_BASE + +source "board/samsung/coreprimevelte/Kconfig" + +endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile new file mode 100644 index 00000000000..99beaed05c2 --- /dev/null +++ b/arch/arm/mach-mmp/Makefile @@ -0,0 +1 @@ +obj-y += board.o mmu.o diff --git a/arch/arm/mach-mmp/board.c b/arch/arm/mach-mmp/board.c new file mode 100644 index 00000000000..3384e5377a7 --- /dev/null +++ b/arch/arm/mach-mmp/board.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović <duje.mihanovic@skole.hr> + */ +#include <errno.h> +#include <init.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Timer constants */ +#define APBC_COUNTER_CLK_SEL 0xd4015064 +#define COUNTER_BASE 0xd4101000 +#define COUNTER_EN BIT(0) +#define COUNTER_HALT_ON_DEBUG BIT(1) + +int timer_init(void) +{ + u32 tmp = readl(APBC_COUNTER_CLK_SEL); + + if ((tmp >> 16) != 0x319) + return -1; + + /* Set timer frequency to 26MHz */ + writel(tmp | 1, APBC_COUNTER_CLK_SEL); + writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE); + + gd->arch.timer_rate_hz = 26000000; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + puts("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +#ifndef CONFIG_SYSRESET +void reset_cpu(void) +{ +} +#endif + +/* Stolen from arch/arm/mach-snapdragon/board.c */ +int board_fdt_blob_setup(void **fdtp) +{ + struct fdt_header *fdt; + bool internal_valid, external_valid; + int ret = 0; + + fdt = (struct fdt_header *)get_prev_bl_fdt_addr(); + external_valid = fdt && !fdt_check_header(fdt); + internal_valid = !fdt_check_header(*fdtp); + + /* + * There is no point returning an error here, U-Boot can't do anything useful in this situation. + * Bail out while we can still print a useful error message. + */ + if (!internal_valid && !external_valid) + panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n", + (phys_addr_t)fdt); + + if (internal_valid) { + debug("Using built in FDT\n"); + ret = -EEXIST; + } else { + debug("Using external FDT\n"); + /* So we can use it before returning */ + *fdtp = fdt; + } + + return ret; +} diff --git a/arch/arm/mach-mmp/mmu.c b/arch/arm/mach-mmp/mmu.c new file mode 100644 index 00000000000..ad2f1e3d994 --- /dev/null +++ b/arch/arm/mach-mmp/mmu.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović <duje.mihanovic@skole.hr> + */ +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region pxa1908_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + 0, + } +}; + +struct mm_region *mem_map = pxa1908_mem_map; diff --git a/board/Marvell/openrd/openrd.env b/board/Marvell/openrd/openrd.env new file mode 100644 index 00000000000..70ca704b73e --- /dev/null +++ b/board/Marvell/openrd/openrd.env @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2024 Tony Dinh <mibodhi@gmail.com> + * + * Environment variables configurations + */ + +kernel_addr_r=0x800000 +fdt_addr_r=0x2c00000 +ramdisk_addr_r=0x01100000 +scriptaddr=0x200000 +fdtfile=CONFIG_DEFAULT_DEVICE_TREE.dtb +mtdparts=CONFIG_MTDPARTS_DEFAULT +console=ttyS0,115200 + +/* Standard Boot */ +bootcmd= + bootflow scan -lb +failed= + echo CONFIG_SYS_BOARD boot failed - please check your image diff --git a/board/beacon/beacon-rzg2m/Makefile b/board/beacon/beacon-rzg2m/Makefile index 332b41f35c0..10b7a7fbfa9 100644 --- a/board/beacon/beacon-rzg2m/Makefile +++ b/board/beacon/beacon-rzg2m/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := beacon-rzg2m.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o +obj-y := beacon-rzg2m.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o diff --git a/board/hoperun/hihope-rzg2/Makefile b/board/hoperun/hihope-rzg2/Makefile index 700e26daa2b..299769c9cb6 100644 --- a/board/hoperun/hihope-rzg2/Makefile +++ b/board/hoperun/hihope-rzg2/Makefile @@ -6,4 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := hihope-rzg2.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o +obj-y := hihope-rzg2.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o diff --git a/board/mediatek/mt7987/MAINTAINERS b/board/mediatek/mt7987/MAINTAINERS new file mode 100644 index 00000000000..c257d0b09df --- /dev/null +++ b/board/mediatek/mt7987/MAINTAINERS @@ -0,0 +1,8 @@ +MT7987 +M: Sam Shih <sam.shih@mediatek.com> +S: Maintained +F: board/mediatek/mt7987 +F: include/configs/mt7987.h +F: configs/mt7987_rfb_defconfig +F: configs/mt7987_emmc_rfb_defconfig +F: configs/mt7987_sd_rfb_defconfig diff --git a/board/mediatek/mt7987/Makefile b/board/mediatek/mt7987/Makefile new file mode 100644 index 00000000000..9f3f493f3c9 --- /dev/null +++ b/board/mediatek/mt7987/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt7987_rfb.o diff --git a/board/mediatek/mt7987/mt7987_rfb.c b/board/mediatek/mt7987/mt7987_rfb.c new file mode 100644 index 00000000000..fcb844deed8 --- /dev/null +++ b/board/mediatek/mt7987/mt7987_rfb.c @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +int board_init(void) +{ + return 0; +} diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile new file mode 100644 index 00000000000..347be5cc93c --- /dev/null +++ b/board/renesas/common/Makefile @@ -0,0 +1,49 @@ +# +# board/renesas/whitehawk/Makefile +# +# Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# R-Car SoCs +ifndef CONFIG_RZG2L + +# 32 bit SoCs +ifdef CONFIG_RCAR_32 +ifdef CONFIG_RCAR_GEN2 +endif +endif + +# 64 bit SoCs +ifdef CONFIG_RCAR_64 +ifdef CONFIG_XPL_BUILD +obj-y += rcar64-spl.o +else +obj-y += rcar64-common.o +endif + +ifdef CONFIG_RCAR_GEN3 +ifdef CONFIG_XPL_BUILD +obj-y += gen3-spl.o +else +obj-y += gen3-common.o +ifdef CONFIG_R8A77970 +obj-y += v3-common.o +endif +ifdef CONFIG_R8A77980 +obj-y += v3-common.o +endif +endif +endif + +ifdef CONFIG_RCAR_GEN4 +ifdef CONFIG_XPL_BUILD +obj-y += gen4-spl.o +else +obj-y += gen4-common.o +endif +endif +endif + +endif diff --git a/board/renesas/rcar-common/gen3-common.c b/board/renesas/common/gen3-common.c index 004feca6180..94da00985d3 100644 --- a/board/renesas/rcar-common/gen3-common.c +++ b/board/renesas/common/gen3-common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * board/renesas/rcar-common/gen3-common.c + * board/renesas/common/gen3-common.c * * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> @@ -18,8 +18,6 @@ #include <asm/arch/renesas.h> #include <linux/libfdt.h> -#ifdef CONFIG_RCAR_64 - DECLARE_GLOBAL_DATA_PTR; /* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ @@ -178,4 +176,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif -#endif diff --git a/board/renesas/common/gen3-spl.c b/board/renesas/common/gen3-spl.c new file mode 100644 index 00000000000..9590b5d6a2e --- /dev/null +++ b/board/renesas/common/gen3-spl.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R-Car Gen3 recovery SPL + * + * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> + */ + +#include <init.h> +#include <asm/io.h> +#include <spl.h> + +#define RCAR_CNTC_BASE 0xE6080000 +#define CNTCR_EN BIT(0) + +void board_init_f(ulong dummy) +{ + writel(CNTCR_EN, RCAR_CNTC_BASE); + timer_init(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_UART; +} + +void s_init(void) +{ +} + +void reset_cpu(void) +{ +} diff --git a/board/renesas/rcar-common/gen4-common.c b/board/renesas/common/gen4-common.c index 2abe9660cf8..52a0639073b 100644 --- a/board/renesas/rcar-common/gen4-common.c +++ b/board/renesas/common/gen4-common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * board/renesas/rcar-common/gen4-common.c + * board/renesas/common/gen4-common.c * * Copyright (C) 2021-2024 Renesas Electronics Corp. */ diff --git a/board/renesas/rcar-common/gen4-spl.c b/board/renesas/common/gen4-spl.c index 2aca8baf3dd..e46ef0a3075 100644 --- a/board/renesas/rcar-common/gen4-spl.c +++ b/board/renesas/common/gen4-spl.c @@ -76,23 +76,6 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_LOAD_ADDR + offset, 0); } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) -{ - debug("image entry point: 0x%lx\n", spl_image->entry_point); - if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { - typedef void (*image_entry_arg_t)(int, int, int, int) - __attribute__ ((noreturn)); - image_entry_arg_t image_entry = - (image_entry_arg_t)(uintptr_t) spl_image->entry_point; - image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0); - } else { - typedef void __noreturn (*image_entry_noargs_t)(void); - image_entry_noargs_t image_entry = - (image_entry_noargs_t)spl_image->entry_point; - image_entry(); - } -} - #define APMU_BASE 0xe6170000U #define CL0GRP3_BIT BIT(3) #define CL1GRP3_BIT BIT(7) diff --git a/board/renesas/rcar-common/common.c b/board/renesas/common/rcar64-common.c index 90eb468e4c4..69229ea3cb0 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/common/rcar64-common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * board/renesas/rcar-common/common.c + * board/renesas/common/common.c * * Copyright (C) 2013 Renesas Electronics Corporation * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> @@ -18,8 +18,6 @@ #include <asm/system.h> #include <linux/libfdt.h> -#ifdef CONFIG_RCAR_64 - DECLARE_GLOBAL_DATA_PTR; int dram_init(void) @@ -68,4 +66,7 @@ int __weak board_init(void) return 0; } -#endif +int __weak board_early_init_f(void) +{ + return 0; +} diff --git a/board/renesas/rcar-common/gen3-spl.c b/board/renesas/common/rcar64-spl.c index 44a20cef2df..76f2bde924e 100644 --- a/board/renesas/rcar-common/gen3-spl.c +++ b/board/renesas/common/rcar64-spl.c @@ -1,37 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /* - * R-Car Gen3 recovery SPL - * - * Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org> */ -#include <cpu_func.h> #include <image.h> -#include <init.h> -#include <log.h> -#include <asm/io.h> #include <spl.h> -#include <linux/bitops.h> - -#define RCAR_CNTC_BASE 0xE6080000 -#define CNTCR_EN BIT(0) - -void board_init_f(ulong dummy) -{ - writel(CNTCR_EN, RCAR_CNTC_BASE); - timer_init(); -} - -void spl_board_init(void) -{ - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); -} - -u32 spl_boot_device(void) -{ - return BOOT_DEVICE_UART; -} void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { @@ -49,11 +22,3 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry(); } } - -void s_init(void) -{ -} - -void reset_cpu(void) -{ -} diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/common/v3-common.c index 5d057edb0a6..5d057edb0a6 100644 --- a/board/renesas/rcar-common/v3-common.c +++ b/board/renesas/common/v3-common.c diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile deleted file mode 100644 index fe3a2fd3b7a..00000000000 --- a/board/renesas/condor/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/condor/Makefile -# -# Copyright (C) 2019 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile index 3ed7800b0e9..0a6a325d761 100644 --- a/board/renesas/draak/Makefile +++ b/board/renesas/draak/Makefile @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := draak.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD +obj-y += draak.o endif diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index a51bf65674f..564cf439aa6 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -6,43 +6,12 @@ * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> */ -#include <cpu_func.h> -#include <hang.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> #include <asm/io.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <asm/arch/renesas.h> -#define GSX_MSTP112 BIT(12) /* 3DG */ -#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ -#define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ -int board_early_init_f(void) -{ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) - /* DVFS for reset */ - mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); -#endif - return 0; -} - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile deleted file mode 100644 index 3f5fdab1bc2..00000000000 --- a/board/renesas/eagle/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/eagle/Makefile -# -# Copyright (C) 2015 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile deleted file mode 100644 index 8139391029d..00000000000 --- a/board/renesas/ebisu/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/ebisu/Makefile -# -# Copyright (C) 2018 Renesas Electronics Corporation -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/gen3-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/falcon/Makefile b/board/renesas/falcon/Makefile deleted file mode 100644 index 48fcfac9105..00000000000 --- a/board/renesas/falcon/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/falcon/Makefile -# -# Copyright (C) 2020 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o -endif diff --git a/board/renesas/grayhawk/Makefile b/board/renesas/grayhawk/Makefile deleted file mode 100644 index 7414b773326..00000000000 --- a/board/renesas/grayhawk/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# board/renesas/grayhawk/Makefile -# -# Copyright (C) 2023 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile index fe7c78ef2ff..538bbdddf76 100644 --- a/board/renesas/salvator-x/Makefile +++ b/board/renesas/salvator-x/Makefile @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := salvator-x.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD +obj-y += salvator-x.o endif diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 2c8860bcee4..6d33d005b4c 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -7,41 +7,13 @@ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> */ -#include <cpu_func.h> -#include <image.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> #include <asm/io.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <asm/arch/renesas.h> +#include <init.h> -#define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ -int board_early_init_f(void) -{ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) - /* DVFS for reset */ - mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); -#endif - return 0; -} - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) @@ -65,13 +37,6 @@ int board_init(void) return 0; } -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) -void reset_cpu(void) -{ - i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); -} -#endif - #ifdef CONFIG_MULTI_DTB_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/renesas/spider/Makefile b/board/renesas/spider/Makefile deleted file mode 100644 index 9489917278c..00000000000 --- a/board/renesas/spider/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# board/renesas/spider/Makefile -# -# Copyright (C) 2020 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o diff --git a/board/renesas/ulcb/Makefile b/board/renesas/ulcb/Makefile index c3c2f391e55..4f2dd1ca211 100644 --- a/board/renesas/ulcb/Makefile +++ b/board/renesas/ulcb/Makefile @@ -6,8 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ulcb.o cpld.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD +obj-y += ulcb.o cpld.o endif diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index 64f01b123cb..d02e5d0bfc5 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -6,40 +6,13 @@ * Copyright (C) 2017 Renesas Electronics Corporation */ -#include <image.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> #include <asm/io.h> -#include <linux/bitops.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; +#include <asm/arch/renesas.h> +#include <init.h> -#define DVFS_MSTP926 BIT(26) #define HSUSB_MSTP704 BIT(4) /* HSUSB */ -int board_early_init_f(void) -{ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) - /* DVFS for reset */ - mstp_clrbits_le32(SMSTPCR9, SMSTPCR9, DVFS_MSTP926); -#endif - return 0; -} - /* HSUSB block registers */ #define HSUSB_REG_LPSTS 0xE6590102 #define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile index ee04f67d986..e6db77468e6 100644 --- a/board/renesas/v3hsk/Makefile +++ b/board/renesas/v3hsk/Makefile @@ -7,9 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_SYSRESET) += cpld.o endif diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile index 63e06a4b5fd..211b8a32489 100644 --- a/board/renesas/v3msk/Makefile +++ b/board/renesas/v3msk/Makefile @@ -7,9 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_XPL_BUILD -obj-y := ../rcar-common/gen3-spl.o -else -obj-y := ../rcar-common/v3-common.o ../rcar-common/gen3-common.o ../rcar-common/common.o +ifndef CONFIG_XPL_BUILD obj-$(CONFIG_SYSRESET) += cpld.o endif diff --git a/board/renesas/whitehawk/Makefile b/board/renesas/whitehawk/Makefile deleted file mode 100644 index 80f92e6b041..00000000000 --- a/board/renesas/whitehawk/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# board/renesas/whitehawk/Makefile -# -# Copyright (C) 2021 Renesas Electronics Corp. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y := ../rcar-common/gen4-spl.o -else -obj-y := ../rcar-common/gen4-common.o ../rcar-common/common.o -endif diff --git a/board/samsung/coreprimevelte/Kconfig b/board/samsung/coreprimevelte/Kconfig new file mode 100644 index 00000000000..78a80379605 --- /dev/null +++ b/board/samsung/coreprimevelte/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COREPRIMEVELTE + +config SYS_BOARD + default "coreprimevelte" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "pxa1908" + +endif diff --git a/board/samsung/coreprimevelte/MAINTAINERS b/board/samsung/coreprimevelte/MAINTAINERS new file mode 100644 index 00000000000..0902117e8b3 --- /dev/null +++ b/board/samsung/coreprimevelte/MAINTAINERS @@ -0,0 +1,6 @@ +Samsung Galaxy Core Prime VE LTE support +M: Duje Mihanović <duje.mihanovic@skole.hr> +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: board/samsung/coreprimevelte/ +F: configs/coreprimevelte_defconfig diff --git a/board/silinux/ek874/Makefile b/board/silinux/ek874/Makefile index 879da9edacf..0beda63d115 100644 --- a/board/silinux/ek874/Makefile +++ b/board/silinux/ek874/Makefile @@ -7,7 +7,7 @@ # ifdef CONFIG_XPL_BUILD -obj-y := ../../renesas/rcar-common/gen3-spl.o +obj-y := ../../renesas/common/gen3-spl.o else -obj-y := ek874.o ../../renesas/rcar-common/gen3-common.o ../../renesas/rcar-common/common.o +obj-y := ek874.o ../../renesas/common/gen3-common.o ../../renesas/common/rcar64-common.o endif diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 2dbd071abd9..67b60d2e7b4 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -161,7 +161,7 @@ static struct mv_ddr_topology_map board_topology_map = { {0}, /* timing parameters */ { {0} }, /* electrical configuration */ {0,}, /* electrical parameters */ - 0, /* ODT configuration */ + 0x30000, /* ODT configuration */ 0x3, /* clock enable mask */ }; diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index 8517833f861..a62862e94f9 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -18,11 +18,14 @@ static int do_tpm2_startup(struct cmd_tbl *cmdtp, int flag, int argc, enum tpm2_startup_types mode; struct udevice *dev; int ret; + bool bon = true; ret = get_tpm(&dev); if (ret) return ret; - if (argc != 2) + + /* argv[2] is optional to perform a TPM2_CC_SHUTDOWN */ + if (argc > 3 || (argc == 3 && strcasecmp("off", argv[2]))) return CMD_RET_USAGE; if (!strcasecmp("TPM2_SU_CLEAR", argv[1])) { @@ -34,7 +37,10 @@ static int do_tpm2_startup(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - return report_return_code(tpm2_startup(dev, mode)); + if (argv[2]) + bon = false; + + return report_return_code(tpm2_startup(dev, bon, mode)); } static int do_tpm2_self_test(struct cmd_tbl *cmdtp, int flag, int argc, @@ -226,6 +232,106 @@ unmap_data: return report_return_code(rc); } +static u32 select_mask(u32 mask, enum tpm2_algorithms algo, bool select) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) { + if (hash_algo_list[i].hash_alg != algo) + continue; + + if (select) + mask |= hash_algo_list[i].hash_mask; + else + mask &= ~hash_algo_list[i].hash_mask; + + break; + } + + return mask; +} + +static bool +is_algo_in_pcrs(enum tpm2_algorithms algo, struct tpml_pcr_selection *pcrs) +{ + size_t i; + + for (i = 0; i < pcrs->count; i++) { + if (algo == pcrs->selection[i].hash) + return true; + } + + return false; +} + +static int do_tpm2_pcrallocate(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + int ret; + enum tpm2_algorithms algo; + const char *pw = (argc < 4) ? NULL : argv[3]; + const ssize_t pw_sz = pw ? strlen(pw) : 0; + static struct tpml_pcr_selection pcr = { 0 }; + u32 pcr_len = 0; + bool bon = false; + static u32 mask; + int i; + + /* argv[1]: algorithm (bank), argv[2]: on/off */ + if (argc < 3 || argc > 4) + return CMD_RET_USAGE; + + if (!strcasecmp("on", argv[2])) + bon = true; + else if (strcasecmp("off", argv[2])) + return CMD_RET_USAGE; + + algo = tpm2_name_to_algorithm(argv[1]); + if (algo == -EINVAL) + return CMD_RET_USAGE; + + ret = get_tpm(&dev); + if (ret) + return ret; + + if (!pcr.count) { + /* + * Get current active algorithms (banks), PCRs and mask via the + * first call + */ + ret = tpm2_get_pcr_info(dev, &pcr); + if (ret) + return ret; + + for (i = 0; i < pcr.count; i++) { + struct tpms_pcr_selection *sel = &pcr.selection[i]; + const char *name; + + if (!tpm2_is_active_bank(sel)) + continue; + + mask = select_mask(mask, sel->hash, true); + name = tpm2_algorithm_name(sel->hash); + if (name) + printf("Active bank[%d]: %s\n", i, name); + } + } + + if (!is_algo_in_pcrs(algo, &pcr)) { + printf("%s is not supported by the tpm device\n", argv[1]); + return CMD_RET_USAGE; + } + + mask = select_mask(mask, algo, bon); + ret = tpm2_pcr_config_algo(dev, mask, &pcr, &pcr_len); + if (ret) + return ret; + + return report_return_code(tpm2_send_pcr_allocate(dev, pw, pw_sz, &pcr, + pcr_len)); +} + static int do_tpm_dam_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -395,6 +501,7 @@ static struct cmd_tbl tpm2_commands[] = { do_tpm_pcr_setauthpolicy, "", ""), U_BOOT_CMD_MKENT(pcr_setauthvalue, 0, 1, do_tpm_pcr_setauthvalue, "", ""), + U_BOOT_CMD_MKENT(pcr_allocate, 0, 1, do_tpm2_pcrallocate, "", ""), }; struct cmd_tbl *get_tpm2_commands(unsigned int *size) @@ -420,11 +527,13 @@ U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command", " Initialize the software stack. Always the first command to issue.\n" " 'tpm startup' is the only acceptable command after a 'tpm init' has been\n" " issued\n" -"startup <mode>\n" +"startup <mode> [<op>]\n" " Issue a TPM2_Startup command.\n" " <mode> is one of:\n" " * TPM2_SU_CLEAR (reset state)\n" " * TPM2_SU_STATE (preserved state)\n" +" <op>:\n" +" * off - To shutdown the TPM\n" "self_test <type>\n" " Test the TPM capabilities.\n" " <type> is one of:\n" @@ -473,4 +582,17 @@ U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command", " <pcr>: index of the PCR\n" " <key>: secret to protect the access of PCR #<pcr>\n" " <password>: optional password of the PLATFORM hierarchy\n" +"pcr_allocate <algorithm> <on/off> [<password>]\n" +" Issue a TPM2_PCR_Allocate Command to reconfig PCR bank algorithm.\n" +" <algorithm> is one of:\n" +" * sha1\n" +" * sha256\n" +" * sha384\n" +" * sha512\n" +" <on|off> is one of:\n" +" * on - Select all available PCRs associated with the specified\n" +" algorithm (bank)\n" +" * off - Clear all available PCRs associated with the specified\n" +" algorithm (bank)\n" +" <password>: optional password\n" ); diff --git a/common/bloblist.c b/common/bloblist.c index 110bb9dc44a..ab48a3cdb98 100644 --- a/common/bloblist.c +++ b/common/bloblist.c @@ -223,13 +223,26 @@ static int bloblist_ensurerec(uint tag, struct bloblist_rec **recp, int size, void *bloblist_find(uint tag, int size) { + void *blob = NULL; + int blob_size; + + blob = bloblist_get_blob(tag, &blob_size); + + if (size && size != blob_size) + return NULL; + + return blob; +} + +void *bloblist_get_blob(uint tag, int *sizep) +{ struct bloblist_rec *rec; rec = bloblist_findrec(tag); if (!rec) return NULL; - if (size && size != rec->size) - return NULL; + + *sizep = rec->size; return (void *)rec + rec_hdr_size(rec); } diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 488115d9a5c..7b16923e34d 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index 2d6c83a5d5f..e6242e22509 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -85,7 +85,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_ANEG_TIMEOUT=8000 CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y diff --git a/configs/coreprimevelte_defconfig b/configs/coreprimevelte_defconfig new file mode 100644 index 00000000000..05116669200 --- /dev/null +++ b/configs/coreprimevelte_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=26000000 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MMP=y +CONFIG_TEXT_BASE=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="pxa1908-samsung-coreprimevelte" +CONFIG_TARGET_COREPRIMEVELTE=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_ARMV8_PSCI=y +CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DM=y +CONFIG_OF_BOARD=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index d212f91bf83..b53f2f37409 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index a4005438c19..d2cc1cf7981 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -52,7 +52,6 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_SMSC=y CONFIG_DM_ETH_PHY=y CONFIG_SH_ETHER=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 9bce9e33104..eeb97474b2a 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 0d4eed0ddf7..b5682526c8c 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/mt7987_emmc_rfb_defconfig b/configs/mt7987_emmc_rfb_defconfig new file mode 100644 index 00000000000..022ca32169b --- /dev/null +++ b/configs/mt7987_emmc_rfb_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-emmc-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-emmc-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig new file mode 100644 index 00000000000..00e3cea5264 --- /dev/null +++ b/configs/mt7987_rfb_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mt7987_sd_rfb_defconfig b/configs/mt7987_sd_rfb_defconfig new file mode 100644 index 00000000000..ca7714b1242 --- /dev/null +++ b/configs/mt7987_sd_rfb_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="mt7987a-sd-rfb" +CONFIG_TARGET_MT7987=y +CONFIG_SYS_BOOTM_LEN=0x6000000 +CONFIG_SYS_LOAD_ADDR=0x48000000 +CONFIG_DEBUG_UART_BASE=0x11000000 +CONFIG_DEBUG_UART_CLOCK=40000000 +CONFIG_DEBUG_UART=y +# CONFIG_EFI_LOADER is not set +CONFIG_FIT=y +# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7987a-sd-rfb" +CONFIG_SYS_CBSIZE=512 +CONFIG_SYS_PBSIZE=1049 +CONFIG_LOGLEVEL=7 +CONFIG_LOG=y +CONFIG_SYS_PROMPT="MT7987> " +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_UNLZ4 is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_PWM=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PING=y +CONFIG_CMD_SMC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_PUYA=y +CONFIG_SPI_FLASH_SILICONKAISER=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_ZBIT=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_MT7987=y +CONFIG_POWER_DOMAIN=y +CONFIG_MTK_POWER_DOMAIN=y +CONFIG_DM_PWM=y +CONFIG_PWM_MTK=y +CONFIG_DM_SERIAL=y +CONFIG_MTK_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MTK_SPIM=y +CONFIG_HEXDUMP=y diff --git a/configs/mvebu_espressobin_ultra-88f3720_defconfig b/configs/mvebu_espressobin_ultra-88f3720_defconfig index aa9026acc34..6f1a66f5f1d 100644 --- a/configs/mvebu_espressobin_ultra-88f3720_defconfig +++ b/configs/mvebu_espressobin_ultra-88f3720_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_LOAD_ADDR=0x6000000 CONFIG_PCI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_BOOTSTD_FULL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_PREBOOT=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 708bf5eefd0..1ca0b45d93f 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -4,22 +4,22 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_OPENRD=y CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-base" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nOpenRD-Base" -# CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set @@ -30,23 +30,17 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -59,7 +53,5 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 82a9c77761c..e0cc2e65db3 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_OPENRD=y CONFIG_BOARD_IS_OPENRD_CLIENT=y CONFIG_ENV_SIZE=0x20000 @@ -15,12 +17,10 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-client" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nOpenRD-Client" -# CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,23 +31,17 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -60,7 +54,5 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 10b46e2ec18..a115691daad 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -4,10 +4,12 @@ CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y CONFIG_SYS_KWD_CONFIG="board/Marvell/openrd/kwbimage.cfg" CONFIG_TEXT_BASE=0x600000 CONFIG_NR_DRAM_BANKS=2 -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 CONFIG_TARGET_OPENRD=y CONFIG_BOARD_IS_OPENRD_ULTIMATE=y CONFIG_ENV_SIZE=0x20000 @@ -15,12 +17,10 @@ CONFIG_ENV_OFFSET=0x80000 CONFIG_DEFAULT_DEVICE_TREE="marvell/kirkwood-openrd-ultimate" CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_IDENT_STRING="\nOpenRD-Ultimate" -# CONFIG_SYS_MALLOC_F is not set CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=524288 +CONFIG_BOOTSTD_FULL=y CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="${x_bootcmd_kernel}; setenv bootargs ${x_bootargs} ${x_bootargs_root}; ${x_bootcmd_usb}; bootm 0x6400000;" CONFIG_USE_PREBOOT=y CONFIG_LOGLEVEL=2 # CONFIG_DISPLAY_BOARDINFO is not set @@ -31,23 +31,17 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_JFFS2=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=nand_mtd" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand_mtd:0x100000@0x000000(uboot),0x400000@0x100000(uImage),0x1fb00000@0x500000(rootfs)" CONFIG_CMD_UBI=y -CONFIG_ISO_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SYS_ATA_STRIDE=4 CONFIG_SYS_ATA_DATA_OFFSET=0x100 CONFIG_SYS_ATA_REG_OFFSET=0x100 @@ -60,7 +54,5 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 98a67bee3e0..cb18024da12 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 6f5a86f7a96..763fc14468a 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -75,3 +75,4 @@ CONFIG_SEMIHOSTING=y CONFIG_MBEDTLS_LIB=y CONFIG_TPM=y CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y +CONFIG_TPM_PCR_ALLOCATE=y diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index aae4406bf04..f4f5c57451f 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_FDT_FILE="r8a779a0-falcon.dtb" CONFIG_SYS_PBSIZE=2068 CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index c74051d1af9..b49a81dcd49 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -19,7 +19,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index ef709214f03..5b9ad93a596 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_RENESAS_RAVB=y diff --git a/configs/renesas_rcar3.config b/configs/renesas_rcar3.config index 7f7fab7df1d..9f2413ae928 100644 --- a/configs/renesas_rcar3.config +++ b/configs/renesas_rcar3.config @@ -1,5 +1,4 @@ #include <configs/renesas_rcar64.config> CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_SYS_PBSIZE=2068 diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 53597e9dd4d..1c70a16bf5b 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -38,7 +38,6 @@ CONFIG_SH_MMCIF=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index a25a5627c2c..59bb7075013 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -36,7 +36,6 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:256k(u-boot-spl),512k(u-boot-env1),512k CONFIG_DM_MTD=y CONFIG_SPI_FLASH_MTD=y CONFIG_BITBANGMII=y -CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_SH_ETHER=y diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig index 5e3a46baa41..cecd26175d1 100644 --- a/configs/tools-only_defconfig +++ b/configs/tools-only_defconfig @@ -4,27 +4,27 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_SYS_LOAD_ADDR=0x0 CONFIG_PCI=y -# CONFIG_SANDBOX_SDL is not set -# CONFIG_EFI_LOADER is not set +CONFIG_SANDBOX_SDL=n +CONFIG_EFI_LOADER=n CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_TIMESTAMP=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y -# CONFIG_BOOTSTD_FULL is not set -# CONFIG_BOOTMETH_CROS is not set -# CONFIG_BOOTMETH_VBE is not set +CONFIG_BOOTSTD_FULL=n +CONFIG_BOOTMETH_CROS=n +CONFIG_BOOTMETH_VBE=n CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_BOOTM is not set -# CONFIG_CMD_BOOTI is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_EXTENSION is not set -# CONFIG_CMD_DATE is not set +CONFIG_CMD_BOOTD=n +CONFIG_CMD_BOOTM=n +CONFIG_CMD_BOOTI=n +CONFIG_CMD_ELF=n +CONFIG_CMD_EXTENSION=n +CONFIG_CMD_DATE=n CONFIG_OF_CONTROL=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y -# CONFIG_ACPIGEN is not set +CONFIG_ACPIGEN=n CONFIG_AXI=y CONFIG_AXI_SANDBOX=y CONFIG_SANDBOX_GPIO=y @@ -33,8 +33,8 @@ CONFIG_DM_RTC=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_TIMER=y -# CONFIG_VIRTIO_MMIO is not set -# CONFIG_VIRTIO_PCI is not set -# CONFIG_VIRTIO_SANDBOX is not set -# CONFIG_GENERATE_ACPI_TABLE is not set +CONFIG_VIRTIO_MMIO=n +CONFIG_VIRTIO_PCI=n +CONFIG_VIRTIO_SANDBOX=n +CONFIG_GENERATE_ACPI_TABLE=n CONFIG_TOOLS_MKEFICAPSULE=y diff --git a/doc/README.bitbangMII b/doc/README.bitbangMII index 0a2fa48a56f..05ab20376f3 100644 --- a/doc/README.bitbangMII +++ b/doc/README.bitbangMII @@ -7,28 +7,11 @@ The driver requires that the following macros should be defined into the board configuration file: CONFIG_BITBANGMII - Enable the miiphybb driver -CONFIG_BITBANGMII_MULTI - Enable the multi bus support -If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs -to define at least the following macros: - -MII_INIT - Generic code to enable the MII bus (optional) -MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional) -MDIO_ACTIVE - Activate the MDIO pin as out pin -MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin -MDIO_READ - Read the MDIO pin -MDIO(v) - Write v on the MDIO pin -MDC_DECLARE - Declaration needed to access to the MDC pin (optional) -MDC(v) - Write v on the MDC pin - -The previous macros make the driver compatible with the previous version -(that didn't support the multi-bus). - -When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill -the bb_miiphy_buses[] array with a record for each required bus and declare -the bb_miiphy_buses_num variable with the number of mii buses. -The record (struct bb_miiphy_bus) has the following fields/callbacks (see -miiphy.h for details): +The board code needs to fill the bb_miiphy_buses[] array with a record for +each required bus and declare the bb_miiphy_buses_num variable with the +number of mii buses. The record (struct bb_miiphy_bus) has the following +fields/callbacks (see miiphy.h for details): char name[] - The symbolic name that must be equal to the MII bus registered name diff --git a/doc/develop/py_testing.rst b/doc/develop/py_testing.rst index 6ff78103409..b50473039be 100644 --- a/doc/develop/py_testing.rst +++ b/doc/develop/py_testing.rst @@ -246,6 +246,39 @@ Command-line options sets the directory used to store persistent test data. This is test data that may be re-used across test runs, such as file-system images. +--timing + shows a histogram of test duration, at the end of the run. The columns are: + + Duration + the duration-bucket that this test was in + + Total + total time of all tests in this bucket + + Number of tests + graph showing the number of tests in this bucket, with the actual number + shown at the end + + Example:: + + Duration : Total | Number of tests + ======== : ======= |======================================== + <20ms : 418ms |## 23 + <30ms : 9.1s |######################################## 347 + <40ms : 10.0s |################################# 294 + <50ms : 3.1s |####### 69 + <75ms : 2.6s |#### 43 + <100ms : 1.7s |## 19 + <200ms : 3.0s |## 22 + <300ms : 1.7s | 7 + <400ms : 675ms | 2 + <500ms : 2.2s | 5 + <750ms : 8.3s |# 13 + <1.0s : 1.6s | 2 + <2.0s : 9.4s | 7 + <3.0s : 2.4s | 1 + <7.5s : 6.1s | 1 + `pytest` also implements a number of its own command-line options. Commonly used options are mentioned below. Please see `pytest` documentation for complete details. Execute `py.test --version` for a brief summary. Note that U-Boot's diff --git a/doc/usage/measured_boot.rst b/doc/usage/measured_boot.rst index 05c439e9ac6..488dd546f13 100644 --- a/doc/usage/measured_boot.rst +++ b/doc/usage/measured_boot.rst @@ -24,7 +24,6 @@ Requirements * A hardware TPM 2.0 supported by an enabled U-Boot driver * CONFIG_EFI_TCG2_PROTOCOL=y -* CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE=y * optional CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB=y will measure the loaded DTB in PCR 1 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e631f79e4dd..e412c92cafc 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o +obj-$(CONFIG_TARGET_MT7987) += clk-mt7987.o obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o obj-$(CONFIG_TARGET_MT8365) += clk-mt8365.o obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c new file mode 100644 index 00000000000..173686a38e8 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -0,0 +1,848 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek clock driver for MT7987 SoC + * + * Copyright (C) 2024 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#include <dm.h> +#include <log.h> +#include <asm/arch-mediatek/reset.h> +#include <asm/io.h> +#include <dt-bindings/clock/mediatek,mt7987-clk.h> +#include <linux/bitops.h> + +#include "clk-mtk.h" + +#define MT7987_XTAL_RATE (40 * MHZ) +#define MT7987_CLK_PDN 0x250 +#define MT7987_CLK_PDN_EN_WRITE BIT(31) + +#define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) + +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) + +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) + +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) + +/* FIXED PLLS */ +static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_ARM_LL, CLK_XTAL, 2000000000), + FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 384000000), +}; + +static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { + .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), + .fclks = apmixedsys_mtk_plls, + .flags = CLK_APMIXED, + .xtal_rate = 40 * MHZ, +}; + +static const struct udevice_id mt7987_fixed_pll_compat[] = { + { .compatible = "mediatek,mt7987-fixed-plls" }, + { .compatible = "mediatek,mt7987-apmixedsys" }, + {} +}; + +static int mt7987_fixed_pll_probe(struct udevice *dev) +{ + return mtk_common_clk_init(dev, &mt7987_fixed_pll_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_apmixedsys) = { + .name = "mt7987-clock-fixed-pll", + .id = UCLASS_CLK, + .of_match = mt7987_fixed_pll_compat, + .probe = mt7987_fixed_pll_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* TOPCKGEN FIXED DIV */ +static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { + PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3), + PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 6), + PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_CB_APLL2_D4, "cb_apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D3, "cb_net1_d3", CLK_APMIXED_NET1PLL, 1, 3), + PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_CB_NET1_D7, "cb_net1_d7", CLK_APMIXED_NET1PLL, 1, 7), + PLL_FACTOR(CLK_TOP_NET1_D7_D2, "net1_d7_d2", CLK_APMIXED_NET1PLL, 1, 14), + PLL_FACTOR(CLK_TOP_NET1_D7_D4, "net1_d7_d4", CLK_APMIXED_NET1PLL, 1, 28), + PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + PLL_FACTOR(CLK_TOP_NET1_D8_D8, "net1_d8_d8", CLK_APMIXED_NET1PLL, 1, 64), + PLL_FACTOR(CLK_TOP_NET1_D8_D16, "net1_d8_d16", CLK_APMIXED_NET1PLL, 1, 128), + PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET2_D4_D8, "net2_d4_d8", CLK_APMIXED_NET2PLL, 1, 32), + PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6), + PLL_FACTOR(CLK_TOP_NET2_D7_D2, "net2_d7_d2", CLK_APMIXED_NET2PLL, 1, 14), + PLL_FACTOR(CLK_TOP_CB_NET2_D8, "cb_net2_d8", CLK_APMIXED_NET2PLL, 1, 8), + PLL_FACTOR(CLK_TOP_MSDC_D2, "msdc_d2", CLK_APMIXED_MSDCPLL, 1, 2), + XTAL_FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), + TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), + TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), + TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1221), +}; + +/* TOPCKGEN MUX PARENTS */ +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) + +/* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */ +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D2) +}; + +/* CLK_TOP_NETSYS_500M_SEL (netsys_500m_sel) in topckgen */ +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D5), + TOP_PARENT(CLK_TOP_NET1_D5_D2) +}; + +/* CLK_TOP_NETSYS_2X_SEL (netsys_2x_sel) in topckgen */ +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_NET2PLL) +}; + +/* CLK_TOP_ETH_GMII_SEL (eth_gmii_sel) in topckgen */ +static const struct mtk_parent eth_gmii_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4) +}; + +/* CLK_TOP_EIP_SEL (eip_sel) in topckgen */ +static const struct mtk_parent eip_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET1_D3), + APMIXED_PARENT(CLK_APMIXED_NET2PLL), + TOP_PARENT(CLK_TOP_CB_NET1_D4), + TOP_PARENT(CLK_TOP_CB_NET1_D5) +}; + +/* CLK_TOP_AXI_INFRA_SEL (axi_infra_sel) in topckgen */ +static const struct mtk_parent axi_infra_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2) +}; + +/* CLK_TOP_UART_SEL (uart_sel) in topckgen */ +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D8), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_EMMC_250M_SEL (emmc_250m_sel) in topckgen */ +static const struct mtk_parent emmc_250m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2) +}; + +/* CLK_TOP_EMMC_400M_SEL (emmc_400m_sel) in topckgen */ +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_CB_NET1_D7), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6) +}; + +/* CLK_TOP_SPI_SEL (spi_sel) in topckgen */ +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_NFI_SEL (nfi_sel) in topckgen */ +static const struct mtk_parent nfi_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_CB_M_D3), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D7_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4), + TOP_PARENT(CLK_TOP_M_D3_D2), + TOP_PARENT(CLK_TOP_NET2_D7_D2), + TOP_PARENT(CLK_TOP_CB_M_D8) +}; + +/* CLK_TOP_PWM_SEL (pwm_sel) in topckgen */ +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D2), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K) +}; + +/* CLK_TOP_I2C_SEL (i2c_sel) in topckgen */ +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D4), + TOP_PARENT(CLK_TOP_CB_M_D4), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_PCIE_MBIST_250M_SEL (pcie_mbist_250m_sel) in topckgen */ +static const struct mtk_parent pcie_mbist_250m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D5_D2) +}; + +/* CLK_TOP_PEXTP_TL_SEL (pextp_tl_ck_sel) in topckgen */ +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D7_D4), + TOP_PARENT(CLK_TOP_M_D8_D2), + TOP_PARENT(CLK_TOP_CB_RTC_32K) +}; + +/* CLK_TOP_AUD_SEL (aud_sel) in topckgen */ +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_APLL2) +}; + +/* CLK_TOP_A1SYS_SEL (a1sys_sel) in topckgen */ +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_APLL2_D4) +}; + +/* CLK_TOP_AUD_L_SEL (aud_l_sel) in topckgen */ +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_APLL2), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_USB_PHY_SEL (usb_phy_sel) in topckgen */ +static const struct mtk_parent usb_phy_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_SGM_0_SEL (sgm_0_sel) in topckgen */ +static const struct mtk_parent sgm_0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + APMIXED_PARENT(CLK_APMIXED_SGMPLL) +}; + +/* CLK_TOP_SGM_SBUS_0_SEL (sgm_sbus_0_sel) in topckgen */ +static const struct mtk_parent sgm_sbus_0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET1_D8_D4) +}; + +/* CLK_TOP_SYSAPB_SEL (sysapb_sel) in topckgen */ +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D3_D2) +}; + +/* CLK_TOP_ETH_REFCK_50M_SEL (eth_refck_50m_sel) in topckgen */ +static const struct mtk_parent eth_refck_50m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_NET2_D4_D4) +}; + +/* CLK_TOP_ETH_SYS_200M_SEL (eth_sys_200m_sel) in topckgen */ +static const struct mtk_parent eth_sys_200m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D4) +}; + +/* CLK_TOP_ETH_XGMII_SEL (eth_xgmii_sel) in topckgen */ +static const struct mtk_parent eth_xgmii_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET1_D8_D8), + TOP_PARENT(CLK_TOP_NET1_D8_D16) +}; + +/* CLK_TOP_DRAMC_MD32_SEL (dramc_md32_sel) in topckgen */ +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_M_D2), + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL) +}; + +/* CLK_TOP_DA_XTP_GLB_P0_SEL (da_xtp_glb_p0_sel) in topckgen */ +static const struct mtk_parent da_xtp_glb_p0_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_CB_NET2_D8) +}; + +/* CLK_TOP_DA_CKM_XTAL_SEL (da_ckm_xtal_sel) in topckgen */ +static const struct mtk_parent da_ckm_xtal_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_M_D8_D2) +}; + +/* CLK_TOP_ETH_MII_SEL (eth_mii_sel) in topckgen */ +static const struct mtk_parent eth_mii_parents[] = { + TOP_PARENT(CLK_TOP_CKSQ_40M_D2), + TOP_PARENT(CLK_TOP_NET2_D4_D8) +}; + +/* CLK_TOP_EMMC_200M_SEL (emmc_200m_sel) in topckgen */ +static const struct mtk_parent emmc_200m_parents[] = { + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_MSDC_D2), + TOP_PARENT(CLK_TOP_NET1_D7_D2), + TOP_PARENT(CLK_TOP_CB_NET2_D6), + TOP_PARENT(CLK_TOP_NET1_D7_D4) +}; + +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd) \ + { \ + .id = (_id), .mux_reg = (_mux_ofs), \ + .mux_set_reg = (_mux_set_ofs), .mux_clr_reg = (_mux_clr_ofs), \ + .upd_reg = (_upd_ofs), .upd_shift = (_upd), \ + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ + .gate_reg = (_mux_ofs), .gate_shift = (_gate), \ + .parent_flags = (_parents), \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + } + +/* TOPCKGEN MUX_GATE */ +static const struct mtk_composite topckgen_mtk_muxes[] = { + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x000, 0x004, 0x008, 0, 1, 7, 0x1C0, 0), + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, 15, 0x1C0, 1), + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, + 0x000, 0x004, 0x008, 16, 1, 23, 0x1C0, 2), + TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, + 0x000, 0x004, 0x008, 24, 1, 31, 0x1C0, 3), + TOP_MUX(CLK_TOP_EIP_SEL, "eip_sel", eip_parents, + 0x010, 0x014, 0x018, 0, 3, 7, 0x1C0, 4), + TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, + 0x010, 0x014, 0x018, 8, 1, 15, 0x1C0, 5), + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, + 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, + 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, + 0x020, 0x024, 0x028, 0, 3, 7, 0x1C0, 8), + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, + 0x020, 0x024, 0x028, 8, 3, 15, 0x1C0, 9), + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x020, 0x024, 0x028, 16, 3, 23, 0x1C0, 10), + TOP_MUX(CLK_TOP_NFI_SEL, "nfi_sel", nfi_parents, + 0x020, 0x024, 0x028, 24, 4, 31, 0x1C0, 11), + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, + 0x030, 0x034, 0x038, 0, 3, 7, 0x1C0, 12), + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, + 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), + TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", + pcie_mbist_250m_parents, 0x030, 0x034, 0x038, 16, 1, 23, 0x1C0, 14), + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + 0x030, 0x034, 0x038, 24, 3, 31, 0x1C0, 15), + TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", + pextp_tl_ck_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x1C0, 16), + TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, + 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), + TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, + 0x040, 0x044, 0x048, 24, 1, 31, 0x1C0, 19), + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x050, 0x054, 0x058, 0, 1, 7, 0x1C0, 20), + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x050, 0x054, 0x058, 8, 2, 15, 0x1C0, 21), + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, + 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), + TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", usb_phy_parents, + 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), + TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, + 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), + TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", sgm_sbus_0_parents, + 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), + TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, + 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), + TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", sgm_sbus_0_parents, + 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, + 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, + 0x070, 0x074, 0x078, 8, 1, 15, 0x1C0, 29), + TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", + eth_refck_50m_parents, 0x070, 0x074, 0x078, 16, 1, 23, 0x1C0, 30), + TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", + eth_sys_200m_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), + TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, + 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1), + TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, + 0x080, 0x084, 0x088, 8, 2, 15, 0x1C4, 2), + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", usb_phy_parents, + 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3), + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + 0x080, 0x084, 0x088, 24, 2, 31, 0x1C4, 4), + TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", + usb_phy_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), + TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", usb_phy_parents, + 0x090, 0x094, 0x098, 8, 1, 15, 0x1C4, 6), + TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", usb_phy_parents, + 0x090, 0x094, 0x098, 16, 1, 23, 0x1C4, 7), + TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", + da_xtp_glb_p0_parents, 0x090, 0x094, 0x098, 24, 1, 31, 0x1C4, 8), + TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", + da_xtp_glb_p0_parents, 0x0A0, 0x0A4, 0x0A8, 0, 1, 7, 0x1C4, 9), + TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", usb_phy_parents, + 0x0A0, 0x0A4, 0x0A8, 8, 1, 15, 0x1C4, 10), + TOP_MUX(CLK_TOP_DA_CKM_XTAL_SEL, "da_ckm_xtal_sel", + da_ckm_xtal_parents, 0x0A0, 0x0A4, 0x0A8, 16, 1, 23, 0x1C4, 11), + TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", usb_phy_parents, + 0x0A0, 0x0A4, 0x0A8, 24, 1, 31, 0x1C4, 12), + TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, + 0x0B0, 0x0B4, 0x0B8, 0, 1, 7, 0x1C4, 13), + TOP_MUX(CLK_TOP_EMMC_200M_SEL, "emmc_200m_sel", emmc_200m_parents, + 0x0B0, 0x0B4, 0x0B8, 8, 3, 15, 0x1C4, 14), +}; + +static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { + .muxes_offs = CLK_TOP_NETSYS_SEL, + .fdivs = topckgen_mtk_fixed_factors, + .muxes = topckgen_mtk_muxes, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, + .xtal_rate = MT7987_XTAL_RATE, +}; + +static const struct udevice_id mt7987_topckgen_compat[] = { + { .compatible = "mediatek,mt7987-topckgen" }, + {} +}; + +static int mt7987_topckgen_probe(struct udevice *dev) +{ + struct mtk_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + writel(MT7987_CLK_PDN_EN_WRITE, priv->base + MT7987_CLK_PDN); + return mtk_common_clk_init(dev, &mt7987_topckgen_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_topckgen) = { + .name = "mt7987-clock-topckgen", + .id = UCLASS_CLK, + .of_match = mt7987_topckgen_compat, + .probe = mt7987_topckgen_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_topckgen_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* INFRASYS MUX PARENTS */ + +/* CLK_INFRA_MUX_UART0_SEL (infra_mux_uart0_sel) in infracfg */ +static const int infra_mux_uart0_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_UART1_SEL (infra_mux_uart1_sel) in infracfg */ +static const int infra_mux_uart1_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_UART2_SEL (infra_mux_uart2_sel) in infracfg */ +static const int infra_mux_uart2_parents[] = { + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL +}; + +/* CLK_INFRA_MUX_SPI0_SEL (infra_mux_spi0_sel) in infracfg */ +static const int infra_mux_spi0_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPI_SEL +}; + +/* CLK_INFRA_MUX_SPI1_SEL (infra_mux_spi1_sel) in infracfg */ +static const int infra_mux_spi1_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPIM_MST_SEL +}; + +/* CLK_INFRA_MUX_SPI2_BCK_SEL (infra_mux_spi2_bck_sel) in infracfg */ +static const int infra_mux_spi2_bck_parents[] = { + CLK_TOP_I2C_SEL, + CLK_TOP_SPI_SEL +}; + +/* CLK_INFRA_PWM_BCK_SEL (infra_pwm_bck_sel) in infracfg */ +static const int infra_pwm_bck_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_SYSAXI_SEL, + CLK_TOP_PWM_SEL +}; + +/* CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL (infra_pcie_gfmux_tl_ck_o_p0_sel) in infracfg */ +static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_SEL +}; + +/* CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL (infra_pcie_gfmux_tl_ck_o_p1_sel) in infracfg */ +static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { + CLK_TOP_CB_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P1_SEL +}; + +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ + { \ + .id = (_id), .mux_reg = (_reg) + 0x8, \ + .mux_clr_reg = (_reg) + 0x4, .mux_set_reg = (_reg) + 0x0, \ + .mux_shift = (_shift), .mux_mask = BIT(_width) - 1, \ + .gate_shift = -1, .upd_shift = -1, \ + .parent = (_parents), .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + } + +/* INFRA MUX */ +static const struct mtk_composite infracfg_mtk_mux[] = { + INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", + infra_mux_uart0_parents, 0x0010, 0, 1), + INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", + infra_mux_uart1_parents, 0x0010, 1, 1), + INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", + infra_mux_uart2_parents, 0x0010, 2, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", + infra_mux_spi0_parents, 0x0010, 4, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", + infra_mux_spi1_parents, 0x0010, 5, 1), + INFRA_MUX(CLK_INFRA_MUX_SPI2_BCK_SEL, "infra_mux_spi2_bck_sel", + infra_mux_spi2_bck_parents, 0x0010, 6, 1), + INFRA_MUX(CLK_INFRA_PWM_BCK_SEL, "infra_pwm_bck_sel", + infra_pwm_bck_parents, 0x0010, 14, 2), + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_ck_o_p0_sel", + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0020, 0, 2), + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_ck_o_p1_sel", + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0020, 2, 2), +}; + +static const struct mtk_gate_regs infra_0_cg_regs = { + .set_ofs = 0x10, + .clr_ofs = 0x14, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs infra_1_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra_2_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra_3_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_0_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_1_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_2_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) + +#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ + { \ + .id = (_id), .parent = (_parent), .regs = &infra_3_cg_regs, \ + .shift = (_shift), \ + .flags = (_flags), \ + } +#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) + +/* INFRA GATE */ +static const struct mtk_gate infracfg_mtk_gates[] = { + GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, + "infra_hf_66m_gpt_bck", CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, + "infra_hf_66m_pwm_hck", CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, + "infra_hf_66m_pwm_bck", CLK_INFRA_PWM_BCK_SEL, 2), + GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, + "infra_hf_133m_cqdma_bck", CLK_TOP_SYSAXI_SEL, 12), + GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, + "infra_66m_aud_slv_bck", CLK_TOP_SYSAXI_SEL, 13), + GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", + CLK_TOP_INFRA_F26M_SEL, 14), + GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15), + GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL, 16), + GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", + CLK_TOP_A_TUNER_SEL, 18), + GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", + CLK_TOP_INFRA_F26M_SEL, 19), + GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, + "infra_hf_133m_dbg_ackm", CLK_TOP_SYSAXI_SEL, 20), + GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, + "infra_66m_ap_dma_bck", CLK_TOP_SYSAXI_SEL, 21), + GATE_INFRA1_TOP(CLK_INFRA_MSDC200_SRC, "infra_f_fmsdc200_src", + CLK_TOP_EMMC_200M_SEL, 28), + GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, + "infra_hf_66m_sej_bck", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, + "infra_pre_ck_sej_f13m", CLK_TOP_INFRA_F26M_SEL, 30), + GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", + CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, + "infra_hf_26m_therm_system", CLK_TOP_INFRA_F26M_SEL, 0), + GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, + "infra_hf_66m_uart0_pck", CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, + "infra_hf_66m_uart1_pck", CLK_TOP_SYSAXI_SEL, 4), + GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, + "infra_hf_66m_uart2_pck", CLK_TOP_SYSAXI_SEL, 5), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, + "infra_f_52m_uart0", CLK_INFRA_MUX_UART0_SEL, 3), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, + "infra_f_52m_uart1", CLK_INFRA_MUX_UART1_SEL, 4), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, + "infra_f_52m_uart2", CLK_INFRA_MUX_UART2_SEL, 5), + GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI_SEL, 9), + GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, + "infra_hf_66m_nfi_hck", CLK_TOP_SYSAXI_SEL, 11), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", + CLK_INFRA_MUX_SPI0_SEL, 12), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", + CLK_INFRA_MUX_SPI1_SEL, 13), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, + "infra_hf_104m_spi2_bck", CLK_INFRA_MUX_SPI2_BCK_SEL, 14), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, + "infra_hf_66m_spi0_hck", CLK_TOP_SYSAXI_SEL, 15), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, + "infra_hf_66m_spi1_hck", CLK_TOP_SYSAXI_SEL, 16), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, + "infra_hf_66m_spi2_hck", CLK_TOP_SYSAXI_SEL, 17), + GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, + "infra_hf_66m_flashif_axi", CLK_TOP_SYSAXI_SEL, 18), + GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_CB_RTC_32K, 19), + GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", + CLK_TOP_INFRA_F26M_SEL, 20), + GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", + CLK_INFRA_26M_ADC_BCK, 21), + GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", + CLK_TOP_EMMC_400M_SEL, 22), + GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", + CLK_TOP_EMMC_250M_SEL, 23), + GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, + "infra_hf_133m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 24), + GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, + "infra_66m_msdc_0_hck", CLK_TOP_SYSAXI_SEL, 25), + GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, + "infra_hf_133m_cpum_bck", CLK_TOP_SYSAXI_SEL, 26), + GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", + CLK_TOP_NFI_SEL, 27), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, + "infra_hf_i2c_x16w_mck_ck_p1", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, + "infra_hf_i2c_x16w_pck_ck_p1", CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, + "infra_133m_usb_hck", CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, + "infra_133m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", + CLK_TOP_SYSAXI_SEL, 2), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, + "infra_66m_usb_hck_ck_p1", CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, + "infra_usb_sys_ck_p1", CLK_TOP_USB_SYS_P1_SEL, 5), + GATE_INFRA3_TOP(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", + CLK_TOP_CB_CKSQ_40M, 7), + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, + "infra_usb_frmcnt_ck_p1", CLK_TOP_CKSQ_40M_D2, 9), + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, + "infra_usb_pipe_ck_p1", CLK_XTAL, 11), + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, + "infra_usb_utmi_ck_p1", CLK_XTAL, 13), + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, + "infra_usb_xhci_ck_p1", CLK_TOP_USB_XHCI_P1_SEL, 15), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, + "infra_pcie_gfmux_tl_ck_p0", CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, + "infra_pcie_gfmux_tl_ck_p1", CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, + "infra_pcie_pipe_ck_p0", CLK_XTAL, 24), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, + "infra_pcie_pipe_ck_p1", CLK_XTAL, 25), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, + "infra_133m_pcie_ck_p0", CLK_TOP_SYSAXI_SEL, 28), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, + "infra_133m_pcie_ck_p1", CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0, + "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1, + "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8), +}; + +static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { + .muxes_offs = CLK_INFRA_MUX_UART0_SEL, + .gates_offs = CLK_INFRA_66M_GPT_BCK, + .muxes = infracfg_mtk_mux, + .gates = infracfg_mtk_gates, + .flags = CLK_BYPASS_XTAL, + .xtal_rate = MT7987_XTAL_RATE, +}; + +static const struct udevice_id mt7987_infracfg_compat[] = { + { .compatible = "mediatek,mt7987-infracfg_ao" }, + { .compatible = "mediatek,mt7987-infracfg" }, + {} +}; + +static int mt7987_infracfg_probe(struct udevice *dev) +{ + return mtk_common_clk_infrasys_init(dev, &mt7987_infracfg_clk_tree); +} + +U_BOOT_DRIVER(mtk_clk_infracfg) = { + .name = "mt7987-clock-infracfg", + .id = UCLASS_CLK, + .of_match = mt7987_infracfg_compat, + .probe = mt7987_infracfg_probe, + .priv_auto = sizeof(struct mtk_clk_priv), + .ops = &mtk_clk_infrasys_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* ethsys */ +static const struct mtk_gate_regs eth_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETH_TOP(_id, _name, _parent, _shift) \ + { \ + .id = (_id), .parent = (_parent), .regs = ð_cg_regs, \ + .shift = (_shift), \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate eth_cgs[] = { + GATE_ETH_TOP(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6), + GATE_ETH_TOP(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", CLK_TOP_NETSYS_500M_SEL, 7), + GATE_ETH_TOP(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", CLK_TOP_NETSYS_500M_SEL, 8), + GATE_ETH_TOP(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", CLK_TOP_NETSYS_500M_SEL, 10), +}; + +static int mt7987_ethsys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, + eth_cgs); +} + +static int mt7987_ethsys_bind(struct udevice *dev) +{ + int ret = 0; + + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) { + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + +static const struct udevice_id mt7987_ethsys_compat[] = { + { + .compatible = "mediatek,mt7987-ethsys", + }, + {} +}; + +U_BOOT_DRIVER(mtk_clk_ethsys) = { + .name = "mt7987-clock-ethsys", + .id = UCLASS_CLK, + .of_match = mt7987_ethsys_compat, + .probe = mt7987_ethsys_probe, + .bind = mt7987_ethsys_bind, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index d676cf9e314..2bc700b0d05 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -329,6 +329,7 @@ struct msdc_compatible { u8 clk_div_bits; bool pad_tune0; bool async_fifo; + bool async_fifo_crcsts; bool data_tune; bool busy_check; bool stop_clk_fix; @@ -1553,8 +1554,12 @@ static void msdc_init_hw(struct msdc_host *host) /* use async fifo to avoid tune internal delay */ clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGRESP); - clrbits_le32(&host->base->patch_bit2, - MSDC_PB2_CFGCRCSTS); + if (host->dev_comp->async_fifo_crcsts) + setbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGCRCSTS); + else + clrbits_le32(&host->base->patch_bit2, + MSDC_PB2_CFGCRCSTS); } if (host->dev_comp->data_tune) { @@ -1844,6 +1849,17 @@ static const struct msdc_compatible mt7986_compat = { .enhance_rx = true, }; +static const struct msdc_compatible mt7987_compat = { + .clk_div_bits = 12, + .pad_tune0 = true, + .async_fifo = true, + .async_fifo_crcsts = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, +}; + static const struct msdc_compatible mt7981_compat = { .clk_div_bits = 12, .pad_tune0 = true, @@ -1886,6 +1902,7 @@ static const struct udevice_id msdc_ids[] = { { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat }, { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat }, + { .compatible = "mediatek,mt7987-mmc", .data = (ulong)&mt7987_compat }, { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat }, { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat }, { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat }, diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 13e73810ad6..3132718e4f8 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -2,10 +2,6 @@ config BITBANGMII bool "Bit-banged ethernet MII management channel support" -config BITBANGMII_MULTI - bool "Enable the multi bus support" - depends on BITBANGMII - config MV88E6352_SWITCH bool "Marvell 88E6352 switch support" diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index b143137893f..171c1719b5b 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -17,90 +17,6 @@ #include <miiphy.h> #include <asm/global_data.h> -#ifndef CONFIG_BITBANGMII_MULTI - -/* - * If CONFIG_BITBANGMII_MULTI is not defined we use a - * compatibility layer with the previous miiphybb implementation - * based on macros usage. - * - */ -static int bb_mii_init_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MII_INIT - MII_INIT; -#endif - return 0; -} - -static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO_ACTIVE; - return 0; -} - -static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO_TRISTATE; - return 0; -} - -static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - MDIO(v); - return 0; -} - -static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v) -{ -#ifdef MDIO_DECLARE - MDIO_DECLARE; -#endif - *v = MDIO_READ; - return 0; -} - -static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v) -{ -#ifdef MDC_DECLARE - MDC_DECLARE; -#endif - MDC(v); - return 0; -} - -static int bb_delay_wrap(struct bb_miiphy_bus *bus) -{ - MIIDELAY; - return 0; -} - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = BB_MII_DEVNAME, - .init = bb_mii_init_wrap, - .mdio_active = bb_mdio_active_wrap, - .mdio_tristate = bb_mdio_tristate_wrap, - .set_mdio = bb_set_mdio_wrap, - .get_mdio = bb_get_mdio_wrap, - .set_mdc = bb_set_mdc_wrap, - .delay = bb_delay_wrap, - } -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); -#endif - int bb_miiphy_init(void) { int i; @@ -114,7 +30,6 @@ int bb_miiphy_init(void) static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) { -#ifdef CONFIG_BITBANGMII_MULTI int i; /* Search the correct bus */ @@ -124,10 +39,6 @@ static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname) } } return NULL; -#else - /* We have just one bitbanging bus */ - return &bb_miiphy_buses[0]; -#endif } /***************************************************************************** diff --git a/drivers/net/phy/ti_phy_init.c b/drivers/net/phy/ti_phy_init.c index a0878193ac0..850c0cbec96 100644 --- a/drivers/net/phy/ti_phy_init.c +++ b/drivers/net/phy/ti_phy_init.c @@ -10,12 +10,58 @@ #include <phy.h> #include "ti_phy_init.h" +#define DP83822_DEVADDR 0x1f + +#define MII_DP83822_RCSR 0x17 + +/* RCSR bits */ +#define DP83822_RX_CLK_SHIFT BIT(12) +#define DP83822_TX_CLK_SHIFT BIT(11) + +/* DP83822 specific RGMII RX/TX delay configuration. */ +static int dp83822_config(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 rgmii_delay = 0; + u32 rx_delay = 0; + u32 tx_delay = 0; + int ret; + + ret = ofnode_read_u32(node, "rx-internal-delay-ps", &rx_delay); + if (ret) { + rx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID; + } + + ret = ofnode_read_u32(node, "tx-internal-delay-ps", &tx_delay); + if (ret) { + tx_delay = phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID; + } + + /* Bit set means Receive path internal clock shift is ENABLED */ + if (rx_delay) + rgmii_delay |= DP83822_RX_CLK_SHIFT; + + /* Bit set means Transmit path internal clock shift is DISABLED */ + if (!tx_delay) + rgmii_delay |= DP83822_TX_CLK_SHIFT; + + ret = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR, + DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, + rgmii_delay); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + U_BOOT_PHY_DRIVER(dp83822) = { .name = "TI DP83822", .uid = 0x2000a240, .mask = 0xfffffff0, .features = PHY_BASIC_FEATURES, - .config = &genphy_config_aneg, + .config = &dp83822_config, .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 231764e60b5..7286ad19598 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -560,12 +560,12 @@ static int ravb_remove(struct udevice *dev) return 0; } -int ravb_bb_init(struct bb_miiphy_bus *bus) +static int ravb_bb_init(struct bb_miiphy_bus *bus) { return 0; } -int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) +static int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) { struct ravb_priv *eth = bus->priv; @@ -574,7 +574,7 @@ int ravb_bb_mdio_active(struct bb_miiphy_bus *bus) return 0; } -int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) +static int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) { struct ravb_priv *eth = bus->priv; @@ -583,7 +583,7 @@ int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus) return 0; } -int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +static int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { struct ravb_priv *eth = bus->priv; @@ -595,7 +595,7 @@ int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v) return 0; } -int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +static int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { struct ravb_priv *eth = bus->priv; @@ -604,7 +604,7 @@ int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) return 0; } -int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +static int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { struct ravb_priv *eth = bus->priv; @@ -616,7 +616,7 @@ int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v) return 0; } -int ravb_bb_delay(struct bb_miiphy_bus *bus) +static int ravb_bb_delay(struct bb_miiphy_bus *bus) { udelay(10); diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 34d23cece51..8b9180bd2aa 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -24,6 +24,10 @@ config PINCTRL_MT7986 bool "MT7986 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT7987 + bool "MT7987 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT7988 bool "MT7988 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index de39d1ea436..b25e74e4e00 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7987.c b/drivers/pinctrl/mediatek/pinctrl-mt7987.c new file mode 100644 index 00000000000..db672d26798 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 MediaTek Inc. + * Author: Tim.Kuo <tim.kuo@mediatek.com> + */ + +#include <dm.h> +#include "pinctrl-mtk-common.h" + +enum MT7987_PINCTRL_REG_PAGE { + GPIO_BASE, + IOCFG_RB_BASE, + IOCFG_LB_BASE, + IOCFG_RT1_BASE, + IOCFG_RT2_BASE, + IOCFG_TL_BASE, +}; + +/* + * IO_TYPE_GRP0 / IO_TYPE_GRP1 + * MT7987 pins can be divided into two groups: + * - PUPD_R0_R1 + * - PU/PD + * Here, we divide pins with PU/PD to be IO_TYPE_GRP0 and those with PUPD_R0_R1 + * to be IO_TYPE_GRP1. + * - PUPD_R0_R1 : IO_TYPE_GRP0 + * - PU/PD : IO_TYPE_GRP1 + * DRV_GRP4 + * For MT7987, thr driving of pins can start from 2mA and increase by 2mA + * increments up to 16mA. + */ +#define MT7987_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT7987_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +#define PIN_FIELD_GPIO(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, GPIO_BASE, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = { + PIN_FIELD_GPIO(0, 49, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = { + PIN_FIELD_GPIO(0, 49, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_di_range[] = { + PIN_FIELD_GPIO(0, 49, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_do_range[] = { + PIN_FIELD_GPIO(0, 49, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x10, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x10, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x10, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x10, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x10, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x20, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x20, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x20, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x20, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x20, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x20, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x20, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x20, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x20, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x20, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0xA0, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0xA0, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0xA0, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0xA0, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0xA0, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0xA0, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0xA0, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0xA0, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0xA0, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0xA0, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0xA0, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0xA0, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0xA0, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0xA0, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0xA0, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0xA0, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = { + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x0, 0x10, 24, 3), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x0, 0x10, 24, 3), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x0, 0x10, 9, 3), + PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x0, 0x10, 6, 3), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x0, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x0, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x0, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x0, 0x10, 15, 3), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x0, 0x10, 18, 3), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x0, 0x10, 27, 3), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3), +}; + +static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x20, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x20, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x20, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x20, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x20, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x30, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x30, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x40, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x40, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x40, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x40, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x40, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x50, 0x10, 13, 1), + PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x50, 0x10, 14, 1), + PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1), + + PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1), +}; + +static const struct mtk_pin_reg_calc mt7987_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7987_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7987_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7987_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7987_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7987_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7987_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7987_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7987_pins[] = { + MT7987_TYPE0_PIN(0, "GPIO_WPS"), + MT7987_TYPE0_PIN(1, "GPIO_RESET"), + MT7987_TYPE0_PIN(2, "SYS_WATCHDOG"), + MT7987_TYPE0_PIN(3, "JTAG_JTDO"), + MT7987_TYPE0_PIN(4, "JTAG_JTDI"), + MT7987_TYPE0_PIN(5, "JTAG_JTMS"), + MT7987_TYPE0_PIN(6, "JTAG_JTCLK"), + MT7987_TYPE0_PIN(7, "JTAG_JTRST_N"), + MT7987_TYPE0_PIN(8, "PCM_DTX_I2S_DOUT"), + MT7987_TYPE0_PIN(9, "PCM_DRX_I2S_DIN"), + MT7987_TYPE0_PIN(10, "PCM_CLK_I2S_BCLK"), + MT7987_TYPE0_PIN(11, "PCM_FS_I2S_LRCK"), + MT7987_TYPE0_PIN(12, "PCM_MCK_I2S_MCLK"), + MT7987_TYPE0_PIN(13, "PWM0"), + MT7987_TYPE0_PIN(14, "USB_VBUS"), + MT7987_TYPE0_PIN(15, "SPI0_CLK"), + MT7987_TYPE0_PIN(16, "SPI0_MOSI"), + MT7987_TYPE0_PIN(17, "SPI0_MISO"), + MT7987_TYPE0_PIN(18, "SPI0_CS"), + MT7987_TYPE0_PIN(19, "SPI0_HOLD"), + MT7987_TYPE0_PIN(20, "SPI0_WP"), + MT7987_TYPE0_PIN(21, "SPI1_CLK"), + MT7987_TYPE0_PIN(22, "SPI1_MOSI"), + MT7987_TYPE0_PIN(23, "SPI1_MISO"), + MT7987_TYPE0_PIN(24, "SPI1_CS"), + MT7987_TYPE0_PIN(25, "SPI2_CLK"), + MT7987_TYPE0_PIN(26, "SPI2_MOSI"), + MT7987_TYPE0_PIN(27, "SPI2_MISO"), + MT7987_TYPE0_PIN(28, "SPI2_CS"), + MT7987_TYPE0_PIN(29, "SPI2_HOLD"), + MT7987_TYPE0_PIN(30, "SPI2_WP"), + MT7987_TYPE0_PIN(31, "UART0_RXD"), + MT7987_TYPE0_PIN(32, "UART0_TXD"), + MT7987_TYPE1_PIN(33, "PCIE_PERESET_N_0"), + MT7987_TYPE1_PIN(34, "PCIE_CLK_REQ_0"), + MT7987_TYPE1_PIN(35, "PCIE_WAKE_N_0"), + MT7987_TYPE1_PIN(36, "PCIE_PERESET_N_1"), + MT7987_TYPE1_PIN(37, "PCIE_CLK_REQ_1"), + MT7987_TYPE1_PIN(38, "PCIE_WAKE_N_1"), + MT7987_TYPE0_PIN(39, "SMI_MDC"), + MT7987_TYPE0_PIN(40, "SMI_MDIO"), + MT7987_TYPE0_PIN(41, "GBE_INT"), + MT7987_TYPE0_PIN(42, "GBE_RESET"), + MT7987_TYPE0_PIN(43, "I2C_SCLK"), + MT7987_TYPE0_PIN(44, "I2C_SDATA"), + MT7987_TYPE0_PIN(45, "2P5G_LED0"), + MT7987_TYPE0_PIN(46, "UART1_RXD"), + MT7987_TYPE0_PIN(47, "UART1_TXD"), + MT7987_TYPE0_PIN(48, "UART1_CTS"), + MT7987_TYPE0_PIN(49, "UART1_RTS"), +}; + +/* watchdog */ +static const int mt7987_watchdog_pins[] = {2}; +static const int mt7987_watchdog_funcs[] = {1}; + +/* jtag */ +static const int mt7987_jtag_pins[] = {3, 4, 5, 6, 7}; +static const int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1}; + +/* pcm */ +static const int mt7987_pcm0_0_pins[] = {3, 4, 5, 6, 7}; +static const int mt7987_pcm0_0_funcs[] = {2, 2, 2, 2, 2}; + +static const int mt7987_pcm0_1_pins[] = {8, 9, 10, 11, 12}; +static const int mt7987_pcm0_1_funcs[] = {1, 1, 1, 1, 1}; + +/* uart */ +static const int mt7987_uart0_pins[] = {31, 32}; +static const int mt7987_uart0_funcs[] = {1, 1}; + +static const int mt7987_uart1_0_pins[] = {3, 4, 5, 6}; +static const int mt7987_uart1_0_funcs[] = {3, 3, 3, 3}; + +static const int mt7987_uart1_1_pins[] = {21, 22, 23, 24}; +static const int mt7987_uart1_1_funcs[] = {3, 3, 3, 3}; + +static const int mt7987_uart1_2_pins[] = {46, 47, 48, 49}; +static const int mt7987_uart1_2_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_uart2_0_pins[] = {8, 9, 10, 11}; +static const int mt7987_uart2_0_funcs[] = {2, 2, 2, 2}; + +static const int mt7987_uart2_1_pins[] = {25, 26, 27, 28}; +static const int mt7987_uart2_1_funcs[] = {2, 2, 2, 2}; + +/* pwm */ +static const int mt7987_pwm0_pins[] = {13}; +static const int mt7987_pwm0_funcs[] = {1}; + +static const int mt7987_pwm1_0_pins[] = {7}; +static const int mt7987_pwm1_0_funcs[] = {3}; + +static const int mt7987_pwm1_1_pins[] = {43}; +static const int mt7987_pwm1_1_funcs[] = {2}; + +static const int mt7987_pwm2_0_pins[] = {12}; +static const int mt7987_pwm2_0_funcs[] = {2}; + +static const int mt7987_pwm2_1_pins[] = {44}; +static const int mt7987_pwm2_1_funcs[] = {2}; + +/* vbus */ +static const int mt7987_drv_vbus_p1_pins[] = {14}; +static const int mt7987_drv_vbus_p1_funcs[] = {1}; + +static const int mt7987_drv_vbus_pins[] = {48}; +static const int mt7987_drv_vbus_funcs[] = {3}; + +/* 2p5gbe_led */ +static const int mt7987_2p5gbe_led0_pins[] = {45}; +static const int mt7987_2p5gbe_led0_funcs[] = {1}; + +static const int mt7987_2p5gbe_led1_0_pins[] = {13}; +static const int mt7987_2p5gbe_led1_0_funcs[] = {2}; + +static const int mt7987_2p5gbe_led1_1_pins[] = {49}; +static const int mt7987_2p5gbe_led1_1_funcs[] = {3}; + +/* mdc, mdio */ +static const int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24}; +static const int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4}; + +static const int mt7987_mdc_mdio_pins[] = {39, 40}; +static const int mt7987_mdc_mdio_funcs[] = {1, 1}; + +/* spi */ +static const int mt7987_spi0_pins[] = {15, 16, 17, 18}; +static const int mt7987_spi0_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi0_wp_hold_pins[] = {19, 20}; +static const int mt7987_spi0_wp_hold_funcs[] = {1, 1}; + +static const int mt7987_spi1_pins[] = {21, 22, 23, 24}; +static const int mt7987_spi1_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi1_1_pins[] = {46, 47, 48, 49}; +static const int mt7987_spi1_1_funcs[] = {2, 2, 2, 2}; + +static const int mt7987_spi2_pins[] = {25, 26, 27, 28}; +static const int mt7987_spi2_funcs[] = {1, 1, 1, 1}; + +static const int mt7987_spi2_wp_hold_pins[] = {29, 30}; +static const int mt7987_spi2_wp_hold_funcs[] = {1, 1}; + +/* emmc */ +static const int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24}; +static const int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}; + +/* sd */ +static const int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24}; +static const int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2}; + +/* i2c */ +static const int mt7987_i2c0_0_pins[] = {29, 30}; +static const int mt7987_i2c0_0_funcs[] = {2, 2}; + +static const int mt7987_i2c0_1_pins[] = {39, 40}; +static const int mt7987_i2c0_1_funcs[] = {2, 2}; + +static const int mt7987_i2c0_2_pins[] = {43, 44}; +static const int mt7987_i2c0_2_funcs[] = {1, 1}; + +/* pcie */ +static const int mt7987_pcie0_pereset_pins[] = {33}; +static const int mt7987_pcie0_pereset_funcs[] = {1}; + +static const int mt7987_pcie0_clkreq_pins[] = {34}; +static const int mt7987_pcie0_clkreq_funcs[] = {1}; + +static const int mt7987_pcie0_wake_pins[] = {35}; +static const int mt7987_pcie0_wake_funcs[] = {1}; + +static const int mt7987_pcie1_pereset_pins[] = {36}; +static const int mt7987_pcie1_pereset_funcs[] = {1}; + +static const int mt7987_pcie1_clkreq_pins[] = {37}; +static const int mt7987_pcie1_clkreq_funcs[] = {1}; + +static const int mt7987_pcie1_wake_pins[] = {38}; +static const int mt7987_pcie1_wake_funcs[] = {1}; + +static const int mt7987_pcie_phy_i2c_pins[] = {43, 44}; +static const int mt7987_pcie_phy_i2c_funcs[] = {3, 3}; + +/* snfi */ +static const int mt7987_snfi_pins[] = {25, 26, 27, 28, 29, 30}; +static const int mt7987_snfi_funcs[] = {3, 3, 3, 3, 3, 3}; + +/* + * - int hsgmii : + * For pin41 and pin46, they now can only be used as gpio mode for polling + * event. Hence, there's no need to open their pinctrl setting. + * - dfd, udi : + * Due to dfd & udi functions are only used as detection pins for cpu during + * dvt testing stage, we also remove their pinctrl setting. + */ + +static const struct mtk_group_desc mt7987_groups[] = { + PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog), + PINCTRL_PIN_GROUP("jtag", mt7987_jtag), + PINCTRL_PIN_GROUP("pcm0_0", mt7987_pcm0_0), + PINCTRL_PIN_GROUP("pcm0_1", mt7987_pcm0_1), + PINCTRL_PIN_GROUP("uart0", mt7987_uart0), + PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0), + PINCTRL_PIN_GROUP("uart1_1", mt7987_uart1_1), + PINCTRL_PIN_GROUP("uart1_2", mt7987_uart1_2), + PINCTRL_PIN_GROUP("uart2_0", mt7987_uart2_0), + PINCTRL_PIN_GROUP("uart2_1", mt7987_uart2_1), + PINCTRL_PIN_GROUP("pwm0", mt7987_pwm0), + PINCTRL_PIN_GROUP("pwm1_0", mt7987_pwm1_0), + PINCTRL_PIN_GROUP("pwm1_1", mt7987_pwm1_1), + PINCTRL_PIN_GROUP("pwm2_0", mt7987_pwm2_0), + PINCTRL_PIN_GROUP("pwm2_1", mt7987_pwm2_1), + PINCTRL_PIN_GROUP("drv_vbus_p1", mt7987_drv_vbus_p1), + PINCTRL_PIN_GROUP("drv_vbus", mt7987_drv_vbus), + PINCTRL_PIN_GROUP("2p5gbe_led0", mt7987_2p5gbe_led0), + PINCTRL_PIN_GROUP("2p5gbe_led1_0", mt7987_2p5gbe_led1_0), + PINCTRL_PIN_GROUP("2p5gbe_led1_1", mt7987_2p5gbe_led1_1), + PINCTRL_PIN_GROUP("2p5g_ext_mdc_mdio", mt7987_2p5g_ext_mdc_mdio), + PINCTRL_PIN_GROUP("mdc_mdio", mt7987_mdc_mdio), + PINCTRL_PIN_GROUP("spi0", mt7987_spi0), + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7987_spi0_wp_hold), + PINCTRL_PIN_GROUP("spi1", mt7987_spi1), + PINCTRL_PIN_GROUP("spi1_1", mt7987_spi1_1), + PINCTRL_PIN_GROUP("spi2", mt7987_spi2), + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7987_spi2_wp_hold), + PINCTRL_PIN_GROUP("emmc_45", mt7987_emmc_45), + PINCTRL_PIN_GROUP("sd", mt7987_sd), + PINCTRL_PIN_GROUP("i2c0_0", mt7987_i2c0_0), + PINCTRL_PIN_GROUP("i2c0_1", mt7987_i2c0_1), + PINCTRL_PIN_GROUP("i2c0_2", mt7987_i2c0_2), + PINCTRL_PIN_GROUP("pcie_phy_i2c", mt7987_pcie_phy_i2c), + PINCTRL_PIN_GROUP("pcie0_pereset", mt7987_pcie0_pereset), + PINCTRL_PIN_GROUP("pcie0_clkreq", mt7987_pcie0_clkreq), + PINCTRL_PIN_GROUP("pcie0_wake", mt7987_pcie0_wake), + PINCTRL_PIN_GROUP("pcie1_pereset", mt7987_pcie1_pereset), + PINCTRL_PIN_GROUP("pcie1_clkreq", mt7987_pcie1_clkreq), + PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake), + PINCTRL_PIN_GROUP("snfi", mt7987_snfi), +}; + +static const struct mtk_io_type_desc mt7987_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "18OD33", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP1] = { + .name = "18A01", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +static const char *const mt7987_wdt_groups[] = {"watchdog",}; +static const char *const mt7987_jtag_groups[] = {"jtag",}; +static const char *const mt7987_pcm_groups[] = {"pcm0_0", "pcm0_1"}; +static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0", "uart1_1", + "uart1_2", "uart2_0", "uart2_1",}; +static const char *const mt7987_pwm_groups[] = {"pwm0", "pwm1_0", "pwm1_1", "pwm2_0", + "pwm2_1",}; +static const char *const mt7987_usb_groups[] = {"drv_vbus_p1", "drv_vbus",}; +static const char *const mt7987_led_groups[] = {"2p5gbe_led0", "2p5gbe_led1_0", + "2p5gbe_led1_1",}; +static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",}; +static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1", + "spi1_1", "spi2", "spi2_wp_hold",}; +static const char *const mt7987_flash_groups[] = {"emmc_45", "snfi", "sd",}; +static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",}; +static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset", + "pcie0_clkreq", "pcie0_wake", + "pcie1_pereset", "pcie1_clkreq", + "pcie1_wake",}; + +static const struct mtk_function_desc mt7987_functions[] = { + {"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)}, + {"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)}, + {"pcm", mt7987_pcm_groups, ARRAY_SIZE(mt7987_pcm_groups)}, + {"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)}, + {"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)}, + {"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)}, + {"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)}, + {"eth", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)}, + {"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)}, + {"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)}, + {"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)}, + {"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)}, +}; + +static const char *const mt7987_pinctrl_register_base_names[] = { + "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", "iocfg_rt2", "iocfg_tl", +}; + +static const struct mtk_pinctrl_soc mt7987_data = { + .name = "mt7987_pinctrl", + .reg_cal = mt7987_reg_cals, + .pins = mt7987_pins, + .npins = ARRAY_SIZE(mt7987_pins), + .grps = mt7987_groups, + .ngrps = ARRAY_SIZE(mt7987_groups), + .funcs = mt7987_functions, + .nfuncs = ARRAY_SIZE(mt7987_functions), + .io_type = mt7987_io_type_desc, + .ntype = ARRAY_SIZE(mt7987_io_type_desc), + .gpio_mode = 0, + .base_names = mt7987_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names), + .base_calc = 1, +}; + +static int mtk_pinctrl_mt7987_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt7987_data); +} + +static const struct udevice_id mt7987_pctrl_match[] = { + {.compatible = "mediatek,mt7987-pinctrl"}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt7987_pinctrl) = { + .name = "mt7987_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt7987_pctrl_match, + .ops = &mtk_pinctrl_ops, + .bind = mtk_pinctrl_common_bind, + .probe = mtk_pinctrl_mt7987_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 039da835f5f..0e267d097c5 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -605,6 +605,7 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, + { .compatible = "intel,xscale-uart", .data = PORT_NS16550 }, {} }; #endif /* OF_REAL */ diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index d59102d9a6b..01bc686d367 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -209,6 +209,15 @@ config TPM2_MMIO to the device using the standard TPM Interface Specification (TIS) protocol. +config TPM2_EVENT_LOG_SIZE + int "EventLog size" + depends on TPM_V2 + default 65536 + help + Define the size of the EventLog. Note that this is going to be + allocated twice. One for the eventlog it self and one for the + configuration table that is required from the TCG2 spec + endif # TPM_V2 endmenu diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index 6b6884fb209..12c0575cc97 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -439,7 +439,6 @@ static void clean_buf(const struct ubifs_info *c, void **buf, int lnum, { int empty_offs, pad_len; - lnum = lnum; dbg_rcvry("cleaning corruption at %d:%d", lnum, *offs); ubifs_assert(!(*offs & 7)); diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 7a6e46df5d9..2335e9e2d25 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -169,7 +169,6 @@ struct ubifs_scan_leb *ubifs_start_scan(const struct ubifs_info *c, int lnum, void ubifs_end_scan(const struct ubifs_info *c, struct ubifs_scan_leb *sleb, int lnum, int offs) { - lnum = lnum; dbg_scan("stop scanning LEB %d at offset %d", lnum, offs); ubifs_assert(offs % c->min_io_size == 0); diff --git a/include/bloblist.h b/include/bloblist.h index f999391f74b..52ba0ddcf84 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -250,6 +250,24 @@ static inline void *bloblist_check_magic(ulong addr) return ptr; } +#if CONFIG_IS_ENABLED(BLOBLIST) +/** + * bloblist_get_blob() - Find a blob and get the size of it + * + * Searches the bloblist and returns the blob with the matching tag + * + * @tag: Tag to search for (enum bloblist_tag_t) + * @sizep: Size of the blob found + * Return: pointer to bloblist if found, or NULL if not found + */ +void *bloblist_get_blob(uint tag, int *sizep); +#else +static inline void *bloblist_get_blob(uint tag, int *sizep) +{ + return NULL; +} +#endif + /** * bloblist_find() - Find a blob * diff --git a/include/configs/mt7987.h b/include/configs/mt7987.h new file mode 100644 index 00000000000..18ed3c7a55b --- /dev/null +++ b/include/configs/mt7987.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for MediaTek MT7987 SoC + * + * Copyright (C) 2025 MediaTek Inc. + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef __MT7987_H +#define __MT7987_H + +#define CFG_MAX_MEM_MAPPED 0xC0000000 + +#endif diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 1e6b16b4e70..f91e62a2e47 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -15,22 +15,4 @@ #include "mv-common.h" -/* - * Environment variables configurations - */ -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ - -/* - * Default environment variables - */ - -#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ - CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" - #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/pxa1908.h b/include/configs/pxa1908.h new file mode 100644 index 00000000000..b0d6cdfeb76 --- /dev/null +++ b/include/configs/pxa1908.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 + * Duje Mihanović <duje.mihanovic@skole.hr> + */ + +#ifndef __PXA1908_H +#define __PXA1908_H + +#define CFG_SYS_SDRAM_BASE 0x1000000 +#define CFG_SYS_INIT_RAM_ADDR 0x10000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 +#define CFG_SYS_NS16550_IER 0x40 +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_EXTRA_ENV_SETTINGS \ + "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt7987-clk.h b/include/dt-bindings/clock/mediatek,mt7987-clk.h new file mode 100644 index 00000000000..c7472ef9ebb --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt7987-clk.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Lu Tang <Lu.Tang@mediatek.com> + * Author: Sam Shih <sam.shih@mediatek.com> + */ + +#ifndef _DT_BINDINGS_CLK_MT7987_H +#define _DT_BINDINGS_CLK_MT7987_H + +/* INFRACFG */ + +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_BCK_SEL 5 +#define CLK_INFRA_PWM_BCK_SEL 6 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 7 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 8 +#define CLK_INFRA_66M_GPT_BCK 9 +#define CLK_INFRA_66M_PWM_HCK 10 +#define CLK_INFRA_66M_PWM_BCK 11 +#define CLK_INFRA_133M_CQDMA_BCK 12 +#define CLK_INFRA_66M_AUD_SLV_BCK 13 +#define CLK_INFRA_AUD_26M 14 +#define CLK_INFRA_AUD_L 15 +#define CLK_INFRA_AUD_AUD 16 +#define CLK_INFRA_AUD_EG2 17 +#define CLK_INFRA_DRAMC_F26M 18 +#define CLK_INFRA_133M_DBG_ACKM 19 +#define CLK_INFRA_66M_AP_DMA_BCK 20 +#define CLK_INFRA_MSDC200_SRC 21 +#define CLK_INFRA_66M_SEJ_BCK 22 +#define CLK_INFRA_PRE_CK_SEJ_F13M 23 +#define CLK_INFRA_66M_TRNG 24 +#define CLK_INFRA_26M_THERM_SYSTEM 25 +#define CLK_INFRA_I2C_BCK 26 +#define CLK_INFRA_66M_UART0_PCK 27 +#define CLK_INFRA_66M_UART1_PCK 28 +#define CLK_INFRA_66M_UART2_PCK 29 +#define CLK_INFRA_52M_UART0_CK 30 +#define CLK_INFRA_52M_UART1_CK 31 +#define CLK_INFRA_52M_UART2_CK 32 +#define CLK_INFRA_NFI 33 +#define CLK_INFRA_66M_NFI_HCK 34 +#define CLK_INFRA_104M_SPI0 35 +#define CLK_INFRA_104M_SPI1 36 +#define CLK_INFRA_104M_SPI2_BCK 37 +#define CLK_INFRA_66M_SPI0_HCK 38 +#define CLK_INFRA_66M_SPI1_HCK 39 +#define CLK_INFRA_66M_SPI2_HCK 40 +#define CLK_INFRA_66M_FLASHIF_AXI 41 +#define CLK_INFRA_RTC 42 +#define CLK_INFRA_26M_ADC_BCK 43 +#define CLK_INFRA_RC_ADC 44 +#define CLK_INFRA_MSDC400 45 +#define CLK_INFRA_MSDC2_HCK 46 +#define CLK_INFRA_133M_MSDC_0_HCK 47 +#define CLK_INFRA_66M_MSDC_0_HCK 48 +#define CLK_INFRA_133M_CPUM_BCK 49 +#define CLK_INFRA_BIST2FPC 50 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 51 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 52 +#define CLK_INFRA_133M_USB_HCK 53 +#define CLK_INFRA_133M_USB_HCK_CK_P1 54 +#define CLK_INFRA_66M_USB_HCK 55 +#define CLK_INFRA_66M_USB_HCK_CK_P1 56 +#define CLK_INFRA_USB_SYS_CK_P1 57 +#define CLK_INFRA_USB_CK_P1 58 +#define CLK_INFRA_USB_FRMCNT_CK_P1 59 +#define CLK_INFRA_USB_PIPE_CK_P1 60 +#define CLK_INFRA_USB_UTMI_CK_P1 61 +#define CLK_INFRA_USB_XHCI_CK_P1 62 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 63 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 64 +#define CLK_INFRA_PCIE_PIPE_P0 65 +#define CLK_INFRA_PCIE_PIPE_P1 66 +#define CLK_INFRA_133M_PCIE_CK_P0 67 +#define CLK_INFRA_133M_PCIE_CK_P1 68 +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 69 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 70 +#define CLK_INFRA_NR_CLK 71 + +/* TOPCKGEN */ + +#define CLK_TOP_CB_M_D2 0 +#define CLK_TOP_CB_M_D3 1 +#define CLK_TOP_M_D3_D2 2 +#define CLK_TOP_CB_M_D4 3 +#define CLK_TOP_CB_M_D8 4 +#define CLK_TOP_M_D8_D2 5 +#define CLK_TOP_CB_APLL2_D4 6 +#define CLK_TOP_CB_NET1_D3 7 +#define CLK_TOP_CB_NET1_D4 8 +#define CLK_TOP_CB_NET1_D5 9 +#define CLK_TOP_NET1_D5_D2 10 +#define CLK_TOP_NET1_D5_D4 11 +#define CLK_TOP_CB_NET1_D7 12 +#define CLK_TOP_NET1_D7_D2 13 +#define CLK_TOP_NET1_D7_D4 14 +#define CLK_TOP_NET1_D8_D2 15 +#define CLK_TOP_NET1_D8_D4 16 +#define CLK_TOP_NET1_D8_D8 17 +#define CLK_TOP_NET1_D8_D16 18 +#define CLK_TOP_CB_NET2_D2 19 +#define CLK_TOP_CB_NET2_D4 20 +#define CLK_TOP_NET2_D4_D4 21 +#define CLK_TOP_NET2_D4_D8 22 +#define CLK_TOP_CB_NET2_D6 23 +#define CLK_TOP_NET2_D7_D2 24 +#define CLK_TOP_CB_NET2_D8 25 +#define CLK_TOP_MSDC_D2 26 +#define CLK_TOP_CB_CKSQ_40M 27 +#define CLK_TOP_CKSQ_40M_D2 28 +#define CLK_TOP_CB_RTC_32K 29 +#define CLK_TOP_CB_RTC_32P7K 30 +#define CLK_TOP_NETSYS_SEL 31 +#define CLK_TOP_NETSYS_500M_SEL 32 +#define CLK_TOP_NETSYS_2X_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_EIP_SEL 35 +#define CLK_TOP_AXI_INFRA_SEL 36 +#define CLK_TOP_UART_SEL 37 +#define CLK_TOP_EMMC_250M_SEL 38 +#define CLK_TOP_EMMC_400M_SEL 39 +#define CLK_TOP_SPI_SEL 40 +#define CLK_TOP_SPIM_MST_SEL 41 +#define CLK_TOP_NFI_SEL 42 +#define CLK_TOP_PWM_SEL 43 +#define CLK_TOP_I2C_SEL 44 +#define CLK_TOP_PCIE_MBIST_250M_SEL 45 +#define CLK_TOP_PEXTP_TL_SEL 46 +#define CLK_TOP_PEXTP_TL_P1_SEL 47 +#define CLK_TOP_USB_SYS_P1_SEL 48 +#define CLK_TOP_USB_XHCI_P1_SEL 49 +#define CLK_TOP_AUD_SEL 50 +#define CLK_TOP_A1SYS_SEL 51 +#define CLK_TOP_AUD_L_SEL 52 +#define CLK_TOP_A_TUNER_SEL 53 +#define CLK_TOP_USB_PHY_SEL 54 +#define CLK_TOP_SGM_0_SEL 55 +#define CLK_TOP_SGM_SBUS_0_SEL 56 +#define CLK_TOP_SGM_1_SEL 57 +#define CLK_TOP_SGM_SBUS_1_SEL 58 +#define CLK_TOP_SYSAXI_SEL 59 +#define CLK_TOP_SYSAPB_SEL 60 +#define CLK_TOP_ETH_REFCK_50M_SEL 61 +#define CLK_TOP_ETH_SYS_200M_SEL 62 +#define CLK_TOP_ETH_SYS_SEL 63 +#define CLK_TOP_ETH_XGMII_SEL 64 +#define CLK_TOP_DRAMC_SEL 65 +#define CLK_TOP_DRAMC_MD32_SEL 66 +#define CLK_TOP_INFRA_F26M_SEL 67 +#define CLK_TOP_PEXTP_P0_SEL 68 +#define CLK_TOP_PEXTP_P1_SEL 69 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 70 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 71 +#define CLK_TOP_CKM_SEL 72 +#define CLK_TOP_DA_CKM_XTAL_SEL 73 +#define CLK_TOP_PEXTP_SEL 74 +#define CLK_TOP_ETH_MII_SEL 75 +#define CLK_TOP_EMMC_200M_SEL 76 +#define CLK_TOP_AUD_I2S_M 77 +#define CLK_TOP_NR_CLK 78 + +/* APMIXEDSYS */ + +#define CLK_APMIXED_MPLL 0 +#define CLK_APMIXED_APLL2 1 +#define CLK_APMIXED_NET1PLL 2 +#define CLK_APMIXED_NET2PLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_SGMPLL 5 +#define CLK_APMIXED_ARM_LL 6 +#define CLK_APMIXED_MSDCPLL 7 +#define CLK_APMIXED_NR_CLK 8 + +/* MCUSYS */ + +#define CLK_MCU_BUS_DIV_SEL 0 +#define CLK_MCU_NR_CLK 1 + +/* SGMIISYS_0 */ + +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGMII0_NR_CLK 2 + +/* SGMIISYS_1 */ + +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGMII1_NR_CLK 2 + +/* ETHDMA */ + +#define CLK_ETHDMA_FE_EN 0 +#define CLK_ETHDMA_GP2_EN 1 +#define CLK_ETHDMA_GP1_EN 2 +#define CLK_ETHDMA_GP3_EN 3 +#define CLK_ETHDMA_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT7987_H */ + diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index 8dfb1bc9527..7ed88809913 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -28,8 +28,6 @@ #define EFI_TCG2_MAX_PCR_INDEX 23 #define EFI_TCG2_FINAL_EVENTS_TABLE_VERSION 1 -#define TPM2_EVENT_LOG_SIZE CONFIG_EFI_TCG2_PROTOCOL_EVENTLOG_SIZE - typedef u32 efi_tcg_event_log_bitmap; typedef u32 efi_tcg_event_log_format; typedef u32 efi_tcg_event_algorithm_bitmap; diff --git a/include/miiphy.h b/include/miiphy.h index 5abffd8fb6b..1e6c7041fdc 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -64,7 +64,7 @@ void mdio_list_devices(void); #define BB_MII_DEVNAME "bb_miiphy" struct bb_miiphy_bus { - char name[16]; + char name[MDIO_NAME_LEN]; int (*init)(struct bb_miiphy_bus *bus); int (*mdio_active)(struct bb_miiphy_bus *bus); int (*mdio_tristate)(struct bb_miiphy_bus *bus); @@ -72,9 +72,7 @@ struct bb_miiphy_bus { int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); int (*set_mdc)(struct bb_miiphy_bus *bus, int v); int (*delay)(struct bb_miiphy_bus *bus); -#ifdef CONFIG_BITBANGMII_MULTI void *priv; -#endif }; extern struct bb_miiphy_bus bb_miiphy_buses[]; diff --git a/include/tpm-v2.h b/include/tpm-v2.h index 65681464b37..ece422df0c7 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -230,6 +230,8 @@ enum tpm2_command_codes { TPM2_CC_PCR_READ = 0x017E, TPM2_CC_PCR_EXTEND = 0x0182, TPM2_CC_PCR_SETAUTHVAL = 0x0183, + TPM2_CC_PCR_ALLOCATE = 0x012B, + TPM2_CC_SHUTDOWN = 0x0145, }; /** @@ -430,7 +432,7 @@ enum { * * Return: code of the operation */ -u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode); +u32 tpm2_startup(struct udevice *dev, bool onoff, enum tpm2_startup_types mode); /** * Issue a TPM2_SelfTest command. @@ -702,6 +704,55 @@ u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd, uint vendor_subcmd); /** + * tpm2_scan_masks - Scan the bitmask of algorithms based on the + * active/supported banks and the one from eventlog. + * + * @dev TPM device + * @log_active Active algorithm bitmask + * @mask Bitmask to set + * + * Return: zero on success, negative errno otherwise + */ +int tpm2_scan_masks(struct udevice *dev, u32 log_active, u32 *mask); + +/** + * tpm2_pcr_config_algo() - Allocate the active PCRs. Requires reboot + * + * @dev TPM device + * @algo_mask Mask of the algorithms + * @pcr PCR structure for allocation + * @pcr_len Actual PCR data length + * + * Return: code of the operation + */ +u32 tpm2_pcr_config_algo(struct udevice *dev, u32 algo_mask, + struct tpml_pcr_selection *pcr, u32 *pcr_len); + +/** + * tpm2_send_pcr_allocate() - Send PCR allocate command. Requires reboot + * + * @dev TPM device + * @pw Platform password + * @pw_sz Length of the password + * @pcr PCR structure for allocation + * @pcr_len Actual PCR data length + * + * Return: code of the operation + */ +u32 tpm2_send_pcr_allocate(struct udevice *dev, const char *pw, + const ssize_t pw_sz, struct tpml_pcr_selection *pcr, + u32 pcr_len); +/** + * tpm2_activate_banks() - Activate PCR banks + * + * @param dev TPM device + * @log_active Bitmask of eventlog algorithms + * + * Return: code of the operation + */ +int tpm2_activate_banks(struct udevice *dev, u32 log_active); + +/** * tpm2_auto_start() - start up the TPM and perform selftests. * If a testable function has not been tested and is * requested the TPM2 will return TPM_RC_NEEDS_TEST. diff --git a/lib/Kconfig b/lib/Kconfig index 0a295161385..b27965fc480 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -514,6 +514,18 @@ config VPL_TPM for the low-level TPM interface, but only one TPM is supported at a time by the TPM library. +config TPM_PCR_ALLOCATE + bool "Re-configurate TPM algorithms in run-time (PCR allocate)" + depends on TPM_V2 && (MEASURED_BOOT || EFI_TCG2_PROTOCOL) + help + This enables a detection for the dismatches of algorithms among TPM + device, eventlog from previous boot stage and U-Boot support. + A PCR allocate command will be sent to reconfigurate the TPM device + in run-time to make sure algorithms in TPM device, eventlog and + U-Boot are aligned with each other. + A system reboot will be proceeded after then to activate the new + algorithms. + endmenu menu "Android Verified Boot" diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index ad0bbdd8a77..d4f6b56afaa 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -438,15 +438,6 @@ config EFI_TCG2_PROTOCOL Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware of the platform. -config EFI_TCG2_PROTOCOL_EVENTLOG_SIZE - int "EFI_TCG2_PROTOCOL EventLog size" - depends on EFI_TCG2_PROTOCOL - default 65536 - help - Define the size of the EventLog for EFI_TCG2_PROTOCOL. Note that - this is going to be allocated twice. One for the eventlog it self - and one for the configuration table that is required from the spec - config EFI_TCG2_PROTOCOL_MEASURE_DTB bool "Measure DTB with EFI_TCG2_PROTOCOL" depends on EFI_TCG2_PROTOCOL diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index c697b53441a..210a846ebc8 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -112,7 +112,7 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, /* if ExitBootServices hasn't been called update the normal log */ if (!event_log.ebs_called) { if (event_log.truncated || - event_log.pos + event_size > TPM2_EVENT_LOG_SIZE) { + event_log.pos + event_size > CONFIG_TPM2_EVENT_LOG_SIZE) { event_log.truncated = true; return EFI_VOLUME_FULL; } @@ -125,7 +125,7 @@ static efi_status_t tcg2_agile_log_append(u32 pcr_index, u32 event_type, return ret; /* if GetEventLog has been called update FinalEventLog as well */ - if (event_log.final_pos + event_size > TPM2_EVENT_LOG_SIZE) + if (event_log.final_pos + event_size > CONFIG_TPM2_EVENT_LOG_SIZE) return EFI_VOLUME_FULL; log = (void *)((uintptr_t)event_log.final_buffer + event_log.final_pos); @@ -823,12 +823,12 @@ static efi_status_t create_final_event(void) * EFI_TCG2_GET_EVENT_LOGS need to be stored in an instance of an * EFI_CONFIGURATION_TABLE */ - ret = efi_allocate_pool(EFI_ACPI_MEMORY_NVS, TPM2_EVENT_LOG_SIZE, + ret = efi_allocate_pool(EFI_ACPI_MEMORY_NVS, CONFIG_TPM2_EVENT_LOG_SIZE, &event_log.final_buffer); if (ret != EFI_SUCCESS) goto out; - memset(event_log.final_buffer, 0xff, TPM2_EVENT_LOG_SIZE); + memset(event_log.final_buffer, 0xff, CONFIG_TPM2_EVENT_LOG_SIZE); final_event = event_log.final_buffer; final_event->number_of_events = 0; final_event->version = EFI_TCG2_FINAL_EVENTS_TABLE_VERSION; @@ -914,7 +914,8 @@ static efi_status_t efi_init_event_log(void) if (tcg2_platform_get_tpm2(&dev)) return EFI_DEVICE_ERROR; - ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, TPM2_EVENT_LOG_SIZE, + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, + CONFIG_TPM2_EVENT_LOG_SIZE, (void **)&event_log.buffer); if (ret != EFI_SUCCESS) return ret; @@ -923,7 +924,7 @@ static efi_status_t efi_init_event_log(void) * initialize log area as 0xff so the OS can easily figure out the * last log entry */ - memset(event_log.buffer, 0xff, TPM2_EVENT_LOG_SIZE); + memset(event_log.buffer, 0xff, CONFIG_TPM2_EVENT_LOG_SIZE); /* * The log header is defined to be in SHA1 event log entry format. @@ -940,7 +941,7 @@ static efi_status_t efi_init_event_log(void) * platforms can use different ways to do so. */ elog.log = event_log.buffer; - elog.log_size = TPM2_EVENT_LOG_SIZE; + elog.log_size = CONFIG_TPM2_EVENT_LOG_SIZE; rc = tcg2_log_prepare_buffer(dev, &elog, false); if (rc) { ret = (rc == -ENOBUFS) ? EFI_BUFFER_TOO_SMALL : EFI_DEVICE_ERROR; diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index bc750b7ca19..9ca7933c094 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -44,12 +44,134 @@ static int tpm2_update_active_banks(struct udevice *dev) return 0; } -u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode) +static void tpm2_print_selected_algorithm_name(u32 selected) { + size_t i; + const char *str; + + for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) { + const struct digest_info *algo = &hash_algo_list[i]; + + if (!(selected & algo->hash_mask)) + continue; + + str = tpm2_algorithm_name(algo->hash_alg); + if (str) + log_info("%s\n", str); + } +} + +int tpm2_scan_masks(struct udevice *dev, u32 log_active, u32 *mask) +{ + struct tpml_pcr_selection pcrs; + u32 active = 0; + u32 supported = 0; + int rc, i; + + *mask = 0; + + rc = tpm2_get_pcr_info(dev, &pcrs); + if (rc) + return rc; + + for (i = 0; i < pcrs.count; i++) { + struct tpms_pcr_selection *sel = &pcrs.selection[i]; + size_t j; + u32 hash_mask = 0; + + for (j = 0; j < ARRAY_SIZE(hash_algo_list); j++) { + if (hash_algo_list[j].hash_alg == sel->hash) + hash_mask = hash_algo_list[j].hash_mask; + } + + if (tpm2_algorithm_supported(sel->hash)) + supported |= hash_mask; + + if (tpm2_is_active_bank(sel)) + active |= hash_mask; + } + + /* All eventlog algorithm(s) must be supported */ + if (log_active & ~supported) { + log_err("EventLog contains U-Boot unsupported algorithm(s)\n"); + tpm2_print_selected_algorithm_name(log_active & ~supported); + rc = -1; + } + if (log_active && active & ~log_active) { + log_warning("TPM active algorithm(s) not exist in eventlog\n"); + tpm2_print_selected_algorithm_name(active & ~log_active); + *mask = log_active; + } + + /* Any active algorithm(s) which are not supported must be removed */ + if (active & ~supported) { + log_warning("TPM active algorithm(s) unsupported by u-boot\n"); + tpm2_print_selected_algorithm_name(active & ~supported); + if (*mask) + *mask = active & supported & *mask; + else + *mask = active & supported; + } + + return rc; +} + +static int tpm2_pcr_allocate(struct udevice *dev, u32 algo_mask) +{ + struct tpml_pcr_selection pcr = { 0 }; + u32 pcr_len = 0; + int rc; + + rc = tpm2_get_pcr_info(dev, &pcr); + if (rc) + return rc; + + rc = tpm2_pcr_config_algo(dev, algo_mask, &pcr, &pcr_len); + if (rc) + return rc; + + /* Assume no password */ + rc = tpm2_send_pcr_allocate(dev, NULL, 0, &pcr, pcr_len); + if (rc) + return rc; + + /* Send TPM2_Shutdown, assume mode = TPM2_SU_CLEAR */ + return tpm2_startup(dev, false, TPM2_SU_CLEAR); +} + +int tpm2_activate_banks(struct udevice *dev, u32 log_active) +{ + u32 algo_mask = 0; + int rc; + + rc = tpm2_scan_masks(dev, log_active, &algo_mask); + if (rc) + return rc; + + if (algo_mask) { + if (!IS_ENABLED(CONFIG_TPM_PCR_ALLOCATE)) + return -1; + + rc = tpm2_pcr_allocate(dev, algo_mask); + if (rc) + return rc; + + log_info("PCR allocate done, shutdown TPM and reboot\n"); + do_reset(NULL, 0, 0, NULL); + log_err("reset does not work!\n"); + return -1; + } + + return 0; +} + +u32 tpm2_startup(struct udevice *dev, bool bon, enum tpm2_startup_types mode) +{ + int op = bon ? TPM2_CC_STARTUP : TPM2_CC_SHUTDOWN; const u8 command_v2[12] = { tpm_u16(TPM2_ST_NO_SESSIONS), tpm_u32(12), - tpm_u32(TPM2_CC_STARTUP), + tpm_u32(op), tpm_u16(mode), }; int ret; @@ -59,7 +181,7 @@ u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode) * but will return RC_INITIALIZE otherwise. */ ret = tpm_sendrecv_command(dev, command_v2, NULL, NULL); - if (ret && ret != TPM2_RC_INITIALIZE) + if ((ret && ret != TPM2_RC_INITIALIZE) || !bon) return ret; return tpm2_update_active_banks(dev); @@ -84,7 +206,7 @@ u32 tpm2_auto_start(struct udevice *dev) rc = tpm2_self_test(dev, TPMI_YES); if (rc == TPM2_RC_INITIALIZE) { - rc = tpm2_startup(dev, TPM2_SU_CLEAR); + rc = tpm2_startup(dev, true, TPM2_SU_CLEAR); if (rc) return rc; @@ -222,7 +344,10 @@ u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm, if (!tpm2_check_active_banks(dev)) { log_err("Cannot extend PCRs if all the TPM enabled algorithms are not supported\n"); - return -EINVAL; + + ret = tpm2_pcr_allocate(dev, 0); + if (ret) + return -EINVAL; } /* * Fill the command structure starting from the first buffer: @@ -399,6 +524,130 @@ u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property, return 0; } +u32 tpm2_pcr_config_algo(struct udevice *dev, u32 algo_mask, + struct tpml_pcr_selection *pcr, u32 *pcr_len) +{ + int i; + + if (pcr->count > TPM2_NUM_PCR_BANKS) + return TPM_LIB_ERROR; + + *pcr_len = sizeof(pcr->count); + + for (i = 0; i < pcr->count; i++) { + struct tpms_pcr_selection *sel = &pcr->selection[i]; + u8 pad = 0; + int j; + + if (sel->size_of_select > TPM2_PCR_SELECT_MAX) + return TPM_LIB_ERROR; + + /* + * Found the algorithm (bank) that matches, and enable all PCR + * bits. + * TODO: only select the bits needed + */ + for (j = 0; j < ARRAY_SIZE(hash_algo_list); j++) { + if (hash_algo_list[j].hash_alg != sel->hash) + continue; + + if (algo_mask & hash_algo_list[j].hash_mask) + pad = 0xff; + } + + for (j = 0; j < sel->size_of_select; j++) + sel->pcr_select[j] = pad; + + log_info("set bank[%d] %s %s\n", i, + tpm2_algorithm_name(sel->hash), + tpm2_is_active_bank(sel) ? "on" : "off"); + + *pcr_len += sizeof(sel->hash) + sizeof(sel->size_of_select) + + sel->size_of_select; + } + + return 0; +} + +u32 tpm2_send_pcr_allocate(struct udevice *dev, const char *pw, + const ssize_t pw_sz, struct tpml_pcr_selection *pcr, + u32 pcr_len) +{ + /* Length of the message header, up to start of password */ + uint offset = 27; + u8 command_v2[COMMAND_BUFFER_SIZE] = { + tpm_u16(TPM2_ST_SESSIONS), /* TAG */ + tpm_u32(offset + pw_sz + pcr_len), /* Length */ + tpm_u32(TPM2_CC_PCR_ALLOCATE), /* Command code */ + + /* handles 4 bytes */ + tpm_u32(TPM2_RH_PLATFORM), /* Primary platform seed */ + + /* AUTH_SESSION */ + tpm_u32(9 + pw_sz), /* Authorization size */ + tpm_u32(TPM2_RS_PW), /* Session handle */ + tpm_u16(0), /* Size of <nonce> */ + /* <nonce> (if any) */ + 0, /* Attributes: Cont/Excl/Rst */ + tpm_u16(pw_sz), /* Size of <hmac/password> */ + /* STRING(pw) <hmac/password> (if any) */ + + /* TPML_PCR_SELECTION */ + }; + u8 response[COMMAND_BUFFER_SIZE]; + size_t response_len = COMMAND_BUFFER_SIZE; + u32 i; + int ret; + + /* + * Fill the command structure starting from the first buffer: + * the password (if any) + */ + if (pack_byte_string(command_v2, sizeof(command_v2), "s", offset, pw, + pw_sz)) + return TPM_LIB_ERROR; + + offset += pw_sz; + + /* Pack the count field */ + if (pack_byte_string(command_v2, sizeof(command_v2), "d", offset, pcr->count)) + return TPM_LIB_ERROR; + + offset += sizeof(pcr->count); + + /* Pack each tpms_pcr_selection */ + for (i = 0; i < pcr->count; i++) { + struct tpms_pcr_selection *sel = &pcr->selection[i]; + + /* Pack hash (16-bit) */ + if (pack_byte_string(command_v2, sizeof(command_v2), "w", offset, + sel->hash)) + return TPM_LIB_ERROR; + + offset += sizeof(sel->hash); + + /* Pack size_of_select (8-bit) */ + if (pack_byte_string(command_v2, sizeof(command_v2), "b", offset, + sel->size_of_select)) + return TPM_LIB_ERROR; + + offset += sizeof(sel->size_of_select); + + /* Pack pcr_select array */ + if (pack_byte_string(command_v2, sizeof(command_v2), "s", offset, + sel->pcr_select, sel->size_of_select)) + return TPM_LIB_ERROR; + + offset += sel->size_of_select; + } + + ret = tpm_sendrecv_command(dev, command_v2, response, &response_len); + if (!ret) + tpm_init(dev); + + return ret; +} + static int tpm2_get_num_pcr(struct udevice *dev, u32 *num_pcr) { u8 response[(sizeof(struct tpms_capability_data) - diff --git a/lib/tpm_api.c b/lib/tpm_api.c index 39a5121e302..576d601e5ff 100644 --- a/lib/tpm_api.c +++ b/lib/tpm_api.c @@ -28,7 +28,7 @@ u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode) case TPM_ST_DEACTIVATED: return -EINVAL; } - return tpm2_startup(dev, type); + return tpm2_startup(dev, true, type); } else { return -ENOSYS; } @@ -60,7 +60,7 @@ u32 tpm_resume(struct udevice *dev) if (tpm_is_v1(dev)) return tpm1_startup(dev, TPM_ST_STATE); else if (tpm_is_v2(dev)) - return tpm2_startup(dev, TPM2_SU_STATE); + return tpm2_startup(dev, true, TPM2_SU_STATE); else return -ENOSYS; } diff --git a/lib/tpm_tcg2.c b/lib/tpm_tcg2.c index 4134d93a358..c314b401d0b 100644 --- a/lib/tpm_tcg2.c +++ b/lib/tpm_tcg2.c @@ -19,6 +19,7 @@ #include <linux/unaligned/generic.h> #include <linux/unaligned/le_byteshift.h> #include "tpm-utils.h" +#include <bloblist.h> int tcg2_get_pcr_info(struct udevice *dev, u32 *supported_bank, u32 *active_bank, u32 *bank_num) @@ -358,12 +359,12 @@ static int tcg2_replay_eventlog(struct tcg2_event_log *elog, return 0; } -static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) +static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog, + u32 *log_active) { struct tpml_digest_values digest_list; struct tcg_efi_spec_id_event *event; struct tcg_pcr_event *log; - u32 log_active; u32 calc_size; u32 active; u32 count; @@ -374,6 +375,8 @@ static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) int rc; u32 i; + *log_active = 0; + if (elog->log_size <= offsetof(struct tcg_pcr_event, event)) return 0; @@ -419,7 +422,6 @@ static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) * algorithms, so just check the EvenLog against the TPM active ones. */ digest_list.count = 0; - log_active = 0; for (i = 0; i < count; ++i) { algo = get_unaligned_le16(&event->digest_sizes[i].algorithm_id); mask = tcg2_algorithm_to_mask(algo); @@ -445,17 +447,15 @@ static int tcg2_log_parse(struct udevice *dev, struct tcg2_event_log *elog) algo); return -1; } - log_active |= mask; + *log_active |= mask; } rc = tcg2_get_active_pcr_banks(dev, &active); if (rc) return rc; /* If the EventLog and active algorithms don't match exit */ - if (log_active != active) { - log_err("EventLog doesn't contain all active PCR banks\n"); - return -1; - } + if (*log_active != active) + return -ERESTARTSYS; /* Read PCR0 to check if previous firmware extended the PCRs or not. */ rc = tcg2_pcr_read(dev, 0, &digest_list); @@ -552,43 +552,21 @@ int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, bool ignore_existing_log) { struct tcg2_event_log log; - int rc, i; + int rc; + u32 log_active = 0; elog->log_position = 0; elog->found = false; - /* - * Make sure U-Boot is compiled with all the active PCRs - * since we are about to create an EventLog and we won't - * measure anything if the PCR banks don't match - */ - if (!tpm2_check_active_banks(dev)) { - log_err("Cannot create EventLog\n"); - log_err("Mismatch between U-Boot and TPM hash algos\n"); - log_info("TPM:\n"); - tpm2_print_active_banks(dev); - log_info("U-Boot:\n"); - for (i = 0; i < ARRAY_SIZE(hash_algo_list); i++) { - const struct digest_info *algo = &hash_algo_list[i]; - const char *str; - - if (!algo->supported) - continue; - - str = tpm2_algorithm_name(algo->hash_alg); - if (str) - log_info("%s\n", str); - } - return -EINVAL; - } - rc = tcg2_platform_get_log(dev, (void **)&log.log, &log.log_size); if (!rc) { log.log_position = 0; log.found = false; if (!ignore_existing_log) { - rc = tcg2_log_parse(dev, &log); + rc = tcg2_log_parse(dev, &log, &log_active); + if (rc == -ERESTARTSYS && log_active) + goto pcr_allocate; if (rc) return rc; } @@ -615,6 +593,11 @@ int tcg2_log_prepare_buffer(struct udevice *dev, struct tcg2_event_log *elog, elog->found = log.found; } +pcr_allocate: + rc = tpm2_activate_banks(dev, log_active); + if (rc) + return rc; + /* * Initialize the log buffer if no log was discovered and the buffer is * valid. User's can pass in their own buffer as a fallback if no @@ -672,21 +655,42 @@ void tcg2_measurement_term(struct udevice *dev, struct tcg2_event_log *elog, __weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size) { - const __be32 *addr_prop; - const __be32 *size_prop; + const __be32 *addr_prop = NULL; + const __be32 *size_prop = NULL; int asize; int ssize; + struct ofnode_phandle_args args; + phys_addr_t a; + fdt_size_t s; *addr = NULL; *size = 0; - addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize); - if (!addr_prop) - addr_prop = dev_read_prop(dev, "linux,sml-base", &asize); + *addr = bloblist_get_blob(BLOBLISTT_TPM_EVLOG, size); + if (*addr && *size) { + *addr = map_physmem((uintptr_t)(*addr), *size, MAP_NOCACHE); + return 0; + } - size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize); - if (!size_prop) + /* + * TODO: + * Replace BLOBLIST with a new kconfig for handoff all components + * (fdt, tpm event log, etc...) from previous boot stage via bloblist + * mandatorily following Firmware Handoff spec. + */ + if (!CONFIG_IS_ENABLED(BLOBLIST)) { + addr_prop = dev_read_prop(dev, "tpm_event_log_addr", &asize); + size_prop = dev_read_prop(dev, "tpm_event_log_size", &ssize); + } + + /* + * If no eventlog was observed, a sml buffer is required for the kernel + * to discover the eventlog. + */ + if (!addr_prop || !size_prop) { + addr_prop = dev_read_prop(dev, "linux,sml-base", &asize); size_prop = dev_read_prop(dev, "linux,sml-size", &ssize); + } if (addr_prop && size_prop) { u64 a = of_read_number(addr_prop, asize / sizeof(__be32)); @@ -694,22 +698,19 @@ __weak int tcg2_platform_get_log(struct udevice *dev, void **addr, u32 *size) *addr = map_physmem(a, s, MAP_NOCACHE); *size = (u32)s; - } else { - struct ofnode_phandle_args args; - phys_addr_t a; - fdt_size_t s; - if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, - 0, &args)) - return -ENODEV; + return 0; + } - a = ofnode_get_addr_size(args.node, "reg", &s); - if (a == FDT_ADDR_T_NONE) - return -ENOMEM; + if (dev_read_phandle_with_args(dev, "memory-region", NULL, 0, 0, &args)) + return -ENODEV; - *addr = map_physmem(a, s, MAP_NOCACHE); - *size = (u32)s; - } + a = ofnode_get_addr_size(args.node, "reg", &s); + if (a == FDT_ADDR_T_NONE) + return -ENOMEM; + + *addr = map_physmem(a, s, MAP_NOCACHE); + *size = (u32)s; return 0; } diff --git a/test/common/bloblist.c b/test/common/bloblist.c index 9467abfa8e1..ab8f41c6808 100644 --- a/test/common/bloblist.c +++ b/test/common/bloblist.c @@ -98,10 +98,12 @@ static int bloblist_test_blob(struct unit_test_state *uts) struct bloblist_hdr *hdr; struct bloblist_rec *rec, *rec2; char *data; + int size = 0; /* At the start there should be no records */ hdr = clear_bloblist(); ut_assertnull(bloblist_find(TEST_TAG, TEST_BLOBLIST_SIZE)); + ut_assertnull(bloblist_get_blob(TEST_TAG, &size)); ut_assertok(bloblist_new(TEST_ADDR, TEST_BLOBLIST_SIZE, 0, 0)); ut_asserteq(sizeof(struct bloblist_hdr), bloblist_get_size()); ut_asserteq(TEST_BLOBLIST_SIZE, bloblist_get_total_size()); @@ -114,6 +116,8 @@ static int bloblist_test_blob(struct unit_test_state *uts) ut_asserteq_addr(rec + 1, data); data = bloblist_find(TEST_TAG, TEST_SIZE); ut_asserteq_addr(rec + 1, data); + ut_asserteq_addr(bloblist_get_blob(TEST_TAG, &size), data); + ut_asserteq(size, TEST_SIZE); /* Check the data is zeroed */ ut_assertok(check_zero(data, TEST_SIZE)); diff --git a/test/py/conftest.py b/test/py/conftest.py index 3bd333bfd24..31043a697e2 100644 --- a/test/py/conftest.py +++ b/test/py/conftest.py @@ -25,6 +25,7 @@ import re from _pytest.runner import runtestprotocol import subprocess import sys +import time from u_boot_spawn import BootFail, Timeout, Unexpected, handle_exception # Globals: The HTML log file, and the connection to the U-Boot console. @@ -91,6 +92,9 @@ def pytest_addoption(parser): parser.addoption('--role', help='U-Boot board role (for Labgrid-sjg)') parser.addoption('--use-running-system', default=False, action='store_true', help="Assume that U-Boot is ready and don't wait for a prompt") + parser.addoption('--timing', default=False, action='store_true', + help='Show info on test timing') + def run_build(config, source_dir, build_dir, board_type, log): """run_build: Build U-Boot @@ -322,6 +326,7 @@ def pytest_configure(config): ubconfig.use_running_system = config.getoption('use_running_system') ubconfig.dtb = build_dir + '/arch/sandbox/dts/test.dtb' ubconfig.connection_ok = True + ubconfig.timing = config.getoption('timing') env_vars = ( 'board_type', @@ -516,6 +521,12 @@ tests_skipped = [] tests_warning = [] tests_passed = [] +# Duration of each test: +# key (string): test name +# value (float): duration in ms +test_durations = {} + + def pytest_itemcollected(item): """pytest hook: Called once for each test found during collection. @@ -531,6 +542,73 @@ def pytest_itemcollected(item): tests_not_run.append(item.name) + +def show_timings(): + """Write timings for each test, along with a histogram""" + + def get_time_delta(msecs): + """Convert milliseconds into a user-friendly string""" + if msecs >= 1000: + return f'{msecs / 1000:.1f}s' + else: + return f'{msecs:.0f}ms' + + def show_bar(key, msecs, value): + """Show a single bar (line) of the histogram + + Args: + key (str): Key to write on the left + value (int): Value to display, i.e. the relative length of the bar + """ + if value: + bar_length = int((value / max_count) * max_bar_length) + print(f"{key:>8} : {get_time_delta(msecs):>7} |{'#' * bar_length} {value}", file=buf) + + # Create the buckets we will use, each has a count and a total time + bucket = {} + for power in range(5): + for i in [1, 2, 3, 4, 5, 7.5]: + bucket[i * 10 ** power] = {'count': 0, 'msecs': 0.0} + max_dur = max(bucket.keys()) + + # Collect counts for each bucket; if outside the range, add to too_long + # Also show a sorted list of test timings from longest to shortest + too_long = 0 + too_long_msecs = 0.0 + max_count = 0 + with log.section('Timing Report', 'timing_report'): + for name, dur in sorted(test_durations.items(), key=lambda kv: kv[1], + reverse=True): + log.info(f'{get_time_delta(dur):>8} {name}') + greater = [k for k in bucket.keys() if dur <= k] + if greater: + buck = bucket[min(greater)] + buck['count'] += 1 + max_count = max(max_count, buck['count']) + buck['msecs'] += dur + else: + too_long += 1 + too_long_msecs += dur + + # Set the maximum length of a histogram bar, in characters + max_bar_length = 40 + + # Show a a summary with histogram + buf = io.StringIO() + with log.section('Timing Summary', 'timing_summary'): + print('Duration : Total | Number of tests', file=buf) + print(f'{"=" * 8} : {"=" * 7} |{"=" * max_bar_length}', file=buf) + for dur, buck in bucket.items(): + if buck['count']: + label = get_time_delta(dur) + show_bar(f'<{label}', buck['msecs'], buck['count']) + if too_long: + show_bar(f'>{get_time_delta(max_dur)}', too_long_msecs, too_long) + log.info(buf.getvalue()) + if ubconfig.timing: + print(buf.getvalue(), end='') + + def cleanup(): """Clean up all global state. @@ -580,6 +658,7 @@ def cleanup(): for test in tests_not_run: anchor = anchors.get(test, None) log.status_fail('... ' + test, anchor) + show_timings() log.close() atexit.register(cleanup) @@ -713,7 +792,9 @@ def pytest_runtest_protocol(item, nextitem): log.get_and_reset_warning() ihook = item.ihook ihook.pytest_runtest_logstart(nodeid=item.nodeid, location=item.location) + start = time.monotonic() reports = runtestprotocol(item, nextitem=nextitem) + duration = round((time.monotonic() - start) * 1000, 1) ihook.pytest_runtest_logfinish(nodeid=item.nodeid, location=item.location) was_warning = log.get_and_reset_warning() @@ -726,6 +807,7 @@ def pytest_runtest_protocol(item, nextitem): start_test_section(item) failure_cleanup = False + record_duration = True if not was_warning: test_list = tests_passed msg = 'OK' @@ -756,6 +838,11 @@ def pytest_runtest_protocol(item, nextitem): test_list = tests_skipped msg = 'SKIPPED:\n' + str(report.longrepr) msg_log = log.status_skipped + record_duration = False + + msg += f' {duration} ms' + if record_duration: + test_durations[item.name] = duration if failure_cleanup: console.drain_console() |