21 files changed, 418 insertions, 421 deletions

diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 8608fa004fd..abb3aa5b635 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -176,7 +176,6 @@
 
 						tee-os {
 							filename = "tee.bin";
-							optional;
 						};
 					};
 #endif
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index bf2bb0f17c7..96a6df94c6c 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -252,7 +252,6 @@
 
 						tee-os {
 							filename = "tee.bin";
-							optional;
 						};
 					};
 #endif
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index 9e590c3bba0..6de9ab5d37c 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -197,7 +197,6 @@
 
 						tee-os {
 							filename = "tee.bin";
-							optional;
 						};
 					};
 #endif
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index 458657fc474..8a536b16e8f 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -156,7 +156,6 @@
 
 						tee-os {
 							filename = "tee.bin";
-							optional;
 						};
 					};
 #endif
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 67ef5f34a8a..52fa820f518 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/net/fsl_enetc.c
@@ -5,6 +5,7 @@
  * Copyright 2023-2025 NXP
  */
 
+#include <clk.h>
 #include <dm.h>
 #include <errno.h>
 #include <fdt_support.h>
@@ -981,11 +982,31 @@ static const struct eth_ops enetc_ops_imx = {
 	.read_rom_hwaddr	= enetc_read_rom_hwaddr,
 };
 
+static int enetc_probe_imx(struct udevice *dev)
+{
+	struct clk *clk;
+	int ret;
+
+	clk = devm_clk_get_optional(dev, "ref");
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	ret = clk_enable(clk);
+	if (ret)
+		return ret;
+
+	ret = enetc_probe(dev);
+	if (ret)
+		clk_disable(clk);
+
+	return ret;
+}
+
 U_BOOT_DRIVER(eth_enetc_imx) = {
 	.name		= ENETC_DRIVER_NAME,
 	.id		= UCLASS_ETH,
 	.bind		= enetc_bind,
-	.probe		= enetc_probe,
+	.probe		= enetc_probe_imx,
 	.remove		= enetc_remove,
 	.ops		= &enetc_ops_imx,
 	.priv_auto	= sizeof(struct enetc_priv),
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 06c26f156f6..d13c5f2a6d5 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -1,14 +1,15 @@
 config PINCTRL_IMX
 	bool
 
-config PINCTRL_IMX_SCU
+config PINCTRL_IMX_MMIO
 	bool
+	select PINCTRL_IMX
 
 config PINCTRL_IMX5
 	bool "IMX5 pinctrl driver"
 	depends on ARCH_MX5 && PINCTRL_FULL
 	select DEVRES
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imx5 pinctrl driver
 
@@ -22,7 +23,7 @@ config PINCTRL_IMX6
 	bool "IMX6 pinctrl driver"
 	depends on ARCH_MX6 && PINCTRL_FULL
 	select DEVRES
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imx6 pinctrl driver
 
@@ -36,7 +37,7 @@ config PINCTRL_IMX7
 	bool "IMX7 pinctrl driver"
 	depends on ARCH_MX7 && PINCTRL_FULL
 	select DEVRES
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imx7 pinctrl driver
 
@@ -50,7 +51,7 @@ config PINCTRL_IMX7ULP
 	bool "IMX7ULP pinctrl driver"
 	depends on ARCH_MX7ULP && PINCTRL_FULL
 	select DEVRES
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imx7ulp pinctrl driver
 
@@ -64,7 +65,7 @@ config PINCTRL_IMX8ULP
 	bool "IMX8ULP pinctrl driver"
 	depends on ARCH_IMX8ULP && PINCTRL_FULL
 	select DEVRES
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imx8ulp pinctrl driver
 
@@ -79,7 +80,6 @@ config PINCTRL_IMX8
 	depends on ARCH_IMX8 && PINCTRL_FULL
 	select DEVRES
 	select PINCTRL_IMX
-	select PINCTRL_IMX_SCU
 	help
 	  Say Y here to enable the imx8 pinctrl driver
 
@@ -92,7 +92,7 @@ config PINCTRL_IMX8
 config PINCTRL_IMX8M
 	bool "IMX8M pinctrl driver"
 	depends on ARCH_IMX8M && PINCTRL_FULL
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imx8m pinctrl driver
 
@@ -105,7 +105,7 @@ config PINCTRL_IMX8M
 config PINCTRL_IMX93
 	bool "IMX8M pinctrl driver"
 	depends on ARCH_IMX9 && PINCTRL_FULL
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imx8m pinctrl driver
 
@@ -129,7 +129,7 @@ config PINCTRL_IMXRT
 	bool "IMXRT pinctrl driver"
 	depends on ARCH_IMXRT && PINCTRL_FULL
 	select DEVRES
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the imxrt pinctrl driver
 
@@ -143,7 +143,7 @@ config PINCTRL_VYBRID
 	bool "Vybrid (vf610) pinctrl driver"
 	depends on ARCH_VF610 && PINCTRL_FULL
 	select DEVRES
-	select PINCTRL_IMX
+	select PINCTRL_IMX_MMIO
 	help
 	  Say Y here to enable the Vybrid (vf610) pinctrl driver
 
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index f10aa6ef188..44e37c631e5 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -1,10 +1,10 @@
 obj-$(CONFIG_PINCTRL_IMX)		+= pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX_MMIO)		+= pinctrl-imx-mmio.o
 obj-$(CONFIG_PINCTRL_IMX5)		+= pinctrl-imx5.o
 obj-$(CONFIG_PINCTRL_IMX6)		+= pinctrl-imx6.o
 obj-$(CONFIG_PINCTRL_IMX7)		+= pinctrl-imx7.o
 obj-$(CONFIG_PINCTRL_IMX7ULP)		+= pinctrl-imx7ulp.o
 obj-$(CONFIG_PINCTRL_IMX8ULP)		+= pinctrl-imx8ulp.o
-obj-$(CONFIG_PINCTRL_IMX_SCU)		+= pinctrl-scu.o
 obj-$(CONFIG_PINCTRL_IMX8)		+= pinctrl-imx8.o
 obj-$(CONFIG_PINCTRL_IMX8M)		+= pinctrl-imx8m.o
 obj-$(CONFIG_PINCTRL_IMX93)		+= pinctrl-imx93.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c
new file mode 100644
index 00000000000..6ee108a0120
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ */
+
+#include <malloc.h>
+#include <mapmem.h>
+#include <asm/global_data.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config)
+{
+	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+	struct imx_pinctrl_soc_info *info = priv->info;
+	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
+	u32 input_val, mux_mode, config_val;
+	int mux_reg, conf_reg, input_reg;
+	int npins, pin_size;
+	int i, j = 0, ret;
+	u32 *pin_data;
+
+	if (info->flags & SHARE_MUX_CONF_REG)
+		pin_size = SHARE_FSL_PIN_SIZE;
+	else
+		pin_size = FSL_PIN_SIZE;
+
+	ret = imx_pinctrl_set_state_common(dev, config, pin_size,
+					   &pin_data, &npins);
+	if (ret)
+		return ret;
+
+	/*
+	 * Refer to linux documentation for details:
+	 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+	 */
+	for (i = 0; i < npins; i++) {
+		mux_reg = pin_data[j++];
+
+		if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+			mux_reg = -1;
+
+		if (info->flags & SHARE_MUX_CONF_REG) {
+			conf_reg = mux_reg;
+		} else {
+			conf_reg = pin_data[j++];
+			if (!(info->flags & ZERO_OFFSET_VALID) &&
+			    !conf_reg)
+				conf_reg = -1;
+		}
+
+		if ((mux_reg == -1) || (conf_reg == -1)) {
+			dev_err(dev, "Error mux_reg or conf_reg\n");
+			devm_kfree(dev, pin_data);
+			return -EINVAL;
+		}
+
+		input_reg = pin_data[j++];
+		mux_mode = pin_data[j++];
+		input_val = pin_data[j++];
+		config_val = pin_data[j++];
+
+		dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
+			mux_reg, conf_reg, input_reg, mux_mode,
+			input_val, config_val);
+
+		if (config_val & IMX_PAD_SION)
+			mux_mode |= IOMUXC_CONFIG_SION;
+
+		config_val &= ~IMX_PAD_SION;
+
+		/* Set Mux */
+		if (info->flags & SHARE_MUX_CONF_REG) {
+			clrsetbits_le32(info->base + mux_reg,
+					info->mux_mask,
+					mux_mode << mux_shift);
+		} else {
+			writel(mux_mode, info->base + mux_reg);
+		}
+
+		dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
+			mux_reg, mux_mode);
+
+		/*
+		 * Set select input
+		 *
+		 * If the select input value begins with 0xff,
+		 * it's a quirky select input and the value should
+		 * be interpreted as below.
+		 *     31     23      15      7        0
+		 *     | 0xff | shift | width | select |
+		 * It's used to work around the problem that the
+		 * select input for some pin is not implemented in
+		 * the select input register but in some general
+		 * purpose register. We encode the select input
+		 * value, width and shift of the bit field into
+		 * input_val cell of pin function ID in device tree,
+		 * and then decode them here for setting up the select
+		 * input bits in general purpose register.
+		 */
+
+		if (input_val >> 24 == 0xff) {
+			u32 val = input_val;
+			u8 select = val & 0xff;
+			u8 width = (val >> 8) & 0xff;
+			u8 shift = (val >> 16) & 0xff;
+			u32 mask = ((1 << width) - 1) << shift;
+			/*
+			 * The input_reg[i] here is actually some
+			 * IOMUXC general purpose register, not
+			 * regular select input register.
+			 */
+			val = readl(info->base + input_reg);
+			val &= ~mask;
+			val |= select << shift;
+			writel(val, info->base + input_reg);
+		} else if (input_reg) {
+			/*
+			 * Regular select input register can never be
+			 * at offset 0, and we only print register
+			 * value for regular case.
+			 */
+			if (info->input_sel_base)
+				writel(input_val,
+				       info->input_sel_base +
+				       input_reg);
+			else
+				writel(input_val,
+				       info->base + input_reg);
+
+			dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
+				input_reg, input_val);
+		}
+
+		/* Set config */
+		if (!(config_val & IMX_NO_PAD_CTL)) {
+			if (info->flags & SHARE_MUX_CONF_REG) {
+				clrsetbits_le32(info->base + conf_reg,
+						~info->mux_mask,
+						config_val);
+			} else {
+				writel(config_val,
+				       info->base + conf_reg);
+			}
+
+			dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
+				conf_reg, config_val);
+		}
+	}
+
+	devm_kfree(dev, pin_data);
+
+	return 0;
+}
+
+
+int imx_pinctrl_probe_mmio(struct udevice *dev)
+{
+	struct imx_pinctrl_soc_info *info =
+		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+	struct ofnode_phandle_args arg;
+	ofnode node = dev_ofnode(dev);
+	fdt_addr_t addr;
+	fdt_size_t size;
+	int ret;
+
+	ret = imx_pinctrl_probe_common(dev);
+	if (ret)
+		return ret;
+
+	addr = ofnode_get_addr_size_index(node, 0, &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	info->base = map_sysmem(addr, size);
+	if (!info->base)
+		return -ENOMEM;
+	priv->info = info;
+
+	info->mux_mask = ofnode_read_u32_default(node, "fsl,mux_mask", 0);
+	/*
+	 * Refer to linux documentation for details:
+	 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+	 */
+	if (ofnode_read_bool(node, "fsl,input-sel")) {
+		ret = ofnode_parse_phandle_with_args(node, "fsl,input-sel",
+						     NULL, 0, 0, &arg);
+		if (ret) {
+			dev_err(dev, "iomuxc fsl,input-sel property not found\n");
+			return -EINVAL;
+		}
+
+		addr = ofnode_get_addr_size(arg.node, "reg", &size);
+		if (addr == FDT_ADDR_T_NONE)
+			return -EINVAL;
+
+		info->input_sel_base = map_sysmem(addr, size);
+		if (!info->input_sel_base)
+			return -ENOMEM;
+	}
+
+	dev_dbg(dev, "initialized IMX pinctrl driver\n");
+
+	return 0;
+}
+
+int imx_pinctrl_remove_mmio(struct udevice *dev)
+{
+	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+	struct imx_pinctrl_soc_info *info = priv->info;
+
+	if (info->input_sel_base)
+		unmap_sysmem(info->input_sel_base);
+	if (info->base)
+		unmap_sysmem(info->base);
+
+	return 0;
+}
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c
index 54cec37327c..7d91ccfb26f 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -18,28 +18,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config,
+				 int pin_size, u32 **pin_data, int *npins)
 {
-	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
-	struct imx_pinctrl_soc_info *info = priv->info;
 	ofnode node = dev_ofnode(config);
 	const struct fdt_property *prop;
-	u32 *pin_data;
-	int npins, size, pin_size;
-	int mux_reg, conf_reg, input_reg;
-	u32 input_val, mux_mode, config_val;
-	u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
-	int i, j = 0;
+	int size;
 
 	dev_dbg(dev, "%s: %s\n", __func__, config->name);
 
-	if (info->flags & IMX8_USE_SCU)
-		pin_size = SHARE_IMX8_PIN_SIZE;
-	else if (info->flags & SHARE_MUX_CONF_REG)
-		pin_size = SHARE_FSL_PIN_SIZE;
-	else
-		pin_size = FSL_PIN_SIZE;
-
 	prop = ofnode_get_property(node, "fsl,pins", &size);
 	if (!prop) {
 		dev_err(dev, "No fsl,pins property in node %s\n", config->name);
@@ -52,161 +39,26 @@ static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 		return -EINVAL;
 	}
 
-	pin_data = devm_kzalloc(dev, size, 0);
-	if (!pin_data)
+	*pin_data = devm_kzalloc(dev, size, 0);
+	if (!*pin_data)
 		return -ENOMEM;
 
-	if (ofnode_read_u32_array(node, "fsl,pins",
-				  pin_data, size >> 2)) {
+	if (ofnode_read_u32_array(node, "fsl,pins", *pin_data, size >> 2)) {
 		dev_err(dev, "Error reading pin data.\n");
-		devm_kfree(dev, pin_data);
+		devm_kfree(dev, *pin_data);
 		return -EINVAL;
 	}
 
-	npins = size / pin_size;
-
-	if (info->flags & IMX8_USE_SCU) {
-		imx_pinctrl_scu_conf_pins(info, pin_data, npins);
-	} else {
-		/*
-		 * Refer to linux documentation for details:
-		 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
-		 */
-		for (i = 0; i < npins; i++) {
-			mux_reg = pin_data[j++];
-
-			if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
-				mux_reg = -1;
-
-			if (info->flags & SHARE_MUX_CONF_REG) {
-				conf_reg = mux_reg;
-			} else {
-				conf_reg = pin_data[j++];
-				if (!(info->flags & ZERO_OFFSET_VALID) &&
-				    !conf_reg)
-					conf_reg = -1;
-			}
-
-			if ((mux_reg == -1) || (conf_reg == -1)) {
-				dev_err(dev, "Error mux_reg or conf_reg\n");
-				devm_kfree(dev, pin_data);
-				return -EINVAL;
-			}
-
-			input_reg = pin_data[j++];
-			mux_mode = pin_data[j++];
-			input_val = pin_data[j++];
-			config_val = pin_data[j++];
-
-			dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
-				"input_reg 0x%x, mux_mode 0x%x, "
-				"input_val 0x%x, config_val 0x%x\n",
-				mux_reg, conf_reg, input_reg, mux_mode,
-				input_val, config_val);
-
-			if (config_val & IMX_PAD_SION)
-				mux_mode |= IOMUXC_CONFIG_SION;
-
-			config_val &= ~IMX_PAD_SION;
-
-			/* Set Mux */
-			if (info->flags & SHARE_MUX_CONF_REG) {
-				clrsetbits_le32(info->base + mux_reg,
-						info->mux_mask,
-						mux_mode << mux_shift);
-			} else {
-				writel(mux_mode, info->base + mux_reg);
-			}
-
-			dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
-				mux_reg, mux_mode);
-
-			/*
-			 * Set select input
-			 *
-			 * If the select input value begins with 0xff,
-			 * it's a quirky select input and the value should
-			 * be interpreted as below.
-			 *     31     23      15      7        0
-			 *     | 0xff | shift | width | select |
-			 * It's used to work around the problem that the
-			 * select input for some pin is not implemented in
-			 * the select input register but in some general
-			 * purpose register. We encode the select input
-			 * value, width and shift of the bit field into
-			 * input_val cell of pin function ID in device tree,
-			 * and then decode them here for setting up the select
-			 * input bits in general purpose register.
-			 */
-
-			if (input_val >> 24 == 0xff) {
-				u32 val = input_val;
-				u8 select = val & 0xff;
-				u8 width = (val >> 8) & 0xff;
-				u8 shift = (val >> 16) & 0xff;
-				u32 mask = ((1 << width) - 1) << shift;
-				/*
-				 * The input_reg[i] here is actually some
-				 * IOMUXC general purpose register, not
-				 * regular select input register.
-				 */
-				val = readl(info->base + input_reg);
-				val &= ~mask;
-				val |= select << shift;
-				writel(val, info->base + input_reg);
-			} else if (input_reg) {
-				/*
-				 * Regular select input register can never be
-				 * at offset 0, and we only print register
-				 * value for regular case.
-				 */
-				if (info->input_sel_base)
-					writel(input_val,
-					       info->input_sel_base +
-					       input_reg);
-				else
-					writel(input_val,
-					       info->base + input_reg);
-
-				dev_dbg(dev, "select_input: offset 0x%x val "
-					"0x%x\n", input_reg, input_val);
-			}
-
-			/* Set config */
-			if (!(config_val & IMX_NO_PAD_CTL)) {
-				if (info->flags & SHARE_MUX_CONF_REG) {
-					clrsetbits_le32(info->base + conf_reg,
-							~info->mux_mask,
-							config_val);
-				} else {
-					writel(config_val,
-					       info->base + conf_reg);
-				}
-
-				dev_dbg(dev, "write config: offset 0x%x val "
-					"0x%x\n", conf_reg, config_val);
-			}
-		}
-	}
-
-	devm_kfree(dev, pin_data);
+	*npins = size / pin_size;
 
 	return 0;
 }
 
-const struct pinctrl_ops imx_pinctrl_ops  = {
-	.set_state = imx_pinctrl_set_state,
-};
-
-int imx_pinctrl_probe(struct udevice *dev,
-		      struct imx_pinctrl_soc_info *info)
+int imx_pinctrl_probe_common(struct udevice *dev)
 {
+	struct imx_pinctrl_soc_info *info =
+		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
 	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
-	struct ofnode_phandle_args arg;
-	ofnode node = dev_ofnode(dev);
-	fdt_addr_t addr;
-	fdt_size_t size;
-	int ret;
 
 	if (!info) {
 		dev_err(dev, "wrong pinctrl info\n");
@@ -216,57 +68,5 @@ int imx_pinctrl_probe(struct udevice *dev,
 	priv->dev = dev;
 	priv->info = info;
 
-	if (info->flags & IMX8_USE_SCU)
-		return 0;
-
-	addr = ofnode_get_addr_size_index(node, 0, &size);
-	if (addr == FDT_ADDR_T_NONE)
-		return -EINVAL;
-
-	info->base = map_sysmem(addr, size);
-	if (!info->base)
-		return -ENOMEM;
-	priv->info = info;
-
-	info->mux_mask = ofnode_read_u32_default(node, "fsl,mux_mask", 0);
-	/*
-	 * Refer to linux documentation for details:
-	 * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
-	 */
-	if (ofnode_read_bool(node, "fsl,input-sel")) {
-		ret = ofnode_parse_phandle_with_args(node, "fsl,input-sel",
-						     NULL, 0, 0, &arg);
-		if (ret) {
-			dev_err(dev, "iomuxc fsl,input-sel property not found\n");
-			return -EINVAL;
-		}
-
-		addr = ofnode_get_addr_size(arg.node, "reg", &size);
-		if (addr == FDT_ADDR_T_NONE)
-			return -EINVAL;
-
-		info->input_sel_base = map_sysmem(addr, size);
-		if (!info->input_sel_base)
-			return -ENOMEM;
-	}
-
-	dev_dbg(dev, "initialized IMX pinctrl driver\n");
-
-	return 0;
-}
-
-int imx_pinctrl_remove(struct udevice *dev)
-{
-	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
-	struct imx_pinctrl_soc_info *info = priv->info;
-
-	if (info->flags & IMX8_USE_SCU)
-		return 0;
-
-	if (info->input_sel_base)
-		unmap_sysmem(info->input_sel_base);
-	if (info->base)
-		unmap_sysmem(info->base);
-
 	return 0;
 }
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h
index fa4c084e2fc..9adf999d3bb 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.h
+++ b/drivers/pinctrl/nxp/pinctrl-imx.h
@@ -28,8 +28,6 @@ struct imx_pinctrl_priv {
 	struct imx_pinctrl_soc_info *info;
 };
 
-extern const struct pinctrl_ops imx_pinctrl_ops;
-
 #define IMX_NO_PAD_CTL	0x80000000	/* no pin config need */
 #define IMX_PAD_SION	0x40000000	/* set SION */
 
@@ -50,19 +48,13 @@ extern const struct pinctrl_ops imx_pinctrl_ops;
 
 #define IOMUXC_CONFIG_SION	(0x1 << 4)
 
-int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
+int imx_pinctrl_probe_common(struct udevice *dev);
+int imx_pinctrl_probe_mmio(struct udevice *dev);
 
-int imx_pinctrl_remove(struct udevice *dev);
+int imx_pinctrl_remove_mmio(struct udevice *dev);
 
-#ifdef CONFIG_PINCTRL_IMX_SCU
-int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
-			      u32 *pin_data, int npins);
-#else
-static inline int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info,
-					    u32 *pin_data, int npins)
-{
-	return 0;
-}
-#endif
+int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config,
+				 int pin_size, u32 **pin_data, int *npins);
+int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config);
 
 #endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c
index 6b690fdce8f..af853bea180 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx5.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx5.c
@@ -11,14 +11,6 @@
 
 static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info __section(".data");
 
-static int imx5_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imx5_pinctrl_match[] = {
 	{
 		.compatible = "fsl,imx53-iomuxc",
@@ -31,13 +23,17 @@ static const struct udevice_id imx5_pinctrl_match[] = {
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx5_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(imx5_pinctrl) = {
 	.name = "imx5-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx5_pinctrl_match),
-	.probe = imx5_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx5_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c
index 322eec87ff5..5c6aac56eb7 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx6.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -20,14 +20,6 @@ static struct imx_pinctrl_soc_info imx6_snvs_pinctrl_soc_info = {
 	.flags = ZERO_OFFSET_VALID,
 };
 
-static int imx6_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imx6_pinctrl_match[] = {
 	{ .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
 	{ .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
@@ -40,14 +32,18 @@ static const struct udevice_id imx6_pinctrl_match[] = {
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx6_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(fsl_imx6q_iomuxc) = {
 	.name = "fsl_imx6q_iomuxc",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx6_pinctrl_match),
-	.probe = imx6_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx6_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c
index a8275e26456..14c3d4d4e77 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx7.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx7.c
@@ -14,27 +14,23 @@ static struct imx_pinctrl_soc_info imx7_lpsr_pinctrl_soc_info = {
 	.flags = ZERO_OFFSET_VALID,
 };
 
-static int imx7_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imx7_pinctrl_match[] = {
 	{ .compatible = "fsl,imx7d-iomuxc", .data = (ulong)&imx7_pinctrl_soc_info },
 	{ .compatible = "fsl,imx7d-iomuxc-lpsr", .data = (ulong)&imx7_lpsr_pinctrl_soc_info },
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx7_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(imx7_pinctrl) = {
 	.name = "imx7-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx7_pinctrl_match),
-	.probe = imx7_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx7_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c
index 7ea2dbe7d36..400e1266822 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx7ulp.c
@@ -18,27 +18,23 @@ static struct imx_pinctrl_soc_info imx7ulp_pinctrl_soc_info1 = {
 	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
 };
 
-static int imx7ulp_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imx7ulp_pinctrl_match[] = {
 	{ .compatible = "fsl,imx7ulp-iomuxc-0", .data = (ulong)&imx7ulp_pinctrl_soc_info0 },
 	{ .compatible = "fsl,imx7ulp-iomuxc-1", .data = (ulong)&imx7ulp_pinctrl_soc_info1 },
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx7ulp_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(imx7ulp_pinctrl) = {
 	.name = "imx7ulp-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx7ulp_pinctrl_match),
-	.probe = imx7ulp_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx7ulp_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c
index 4e9a9ea6808..9b3b5aec07a 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8.c
@@ -3,6 +3,12 @@
  * Copyright 2018 NXP
  */
 
+#include <dm.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <asm/io.h>
+#include <firmware/imx/sci/sci.h>
+#include <misc.h>
 #include <asm/global_data.h>
 #include <dm/device.h>
 #include <dm/pinctrl.h>
@@ -11,31 +17,91 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = {
-	.flags = IMX8_USE_SCU,
-};
+#define PADRING_IFMUX_EN_SHIFT		31
+#define PADRING_IFMUX_EN_MASK		BIT(31)
+#define PADRING_GP_EN_SHIFT		30
+#define PADRING_GP_EN_MASK		BIT(30)
+#define PADRING_IFMUX_SHIFT		27
+#define PADRING_IFMUX_MASK		GENMASK(29, 27)
 
-static int imx8_pinctrl_probe(struct udevice *dev)
+static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad,
+			       u32 mux, u32 val)
 {
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+	int ret;
+
+	/*
+	 * Mux should be done in pmx set, but we do not have a good api
+	 * to handle that in scfw, so config it in pad conf func
+	 */
+
+	if (!sc_rm_is_pad_owned(-1, pad)) {
+		debug("Pad[%u] is not owned by curr partition\n", pad);
+		return -EPERM;
+	}
 
-	return imx_pinctrl_probe(dev, info);
+	val |= PADRING_IFMUX_EN_MASK;
+	val |= PADRING_GP_EN_MASK;
+	val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK;
+
+	ret = sc_pad_set(-1, pad, val);
+	if (ret)
+		printf("%s %d\n", __func__, ret);
+
+	return 0;
 }
 
+int imx_pinctrl_set_state_scu(struct udevice *dev, struct udevice *config)
+{
+	struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+	struct imx_pinctrl_soc_info *info = priv->info;
+	int pin_id, mux, config_val;
+	u32 *pin_data;
+	int i, j = 0;
+	int npins;
+	int ret;
+
+	ret = imx_pinctrl_set_state_common(dev, config, SHARE_IMX8_PIN_SIZE,
+					   &pin_data, &npins);
+	if (ret)
+		return ret;
+
+	/*
+	 * Refer to linux documentation for details:
+	 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+	 */
+	for (i = 0; i < npins; i++) {
+		pin_id = pin_data[j++];
+		mux = pin_data[j++];
+		config_val = pin_data[j++];
+
+		ret = imx_pinconf_scu_set(info, pin_id, mux, config_val);
+		if (ret && ret != -EPERM)
+			printf("Set pin %d, mux %d, val %d, error\n", pin_id,
+			       mux, config_val);
+	}
+
+	return 0;
+}
+static struct imx_pinctrl_soc_info imx8_pinctrl_soc_info = {
+	.flags = IMX8_USE_SCU,
+};
+
 static const struct udevice_id imx8_pinctrl_match[] = {
 	{ .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
 	{ .compatible = "fsl,imx8qm-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx8_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_scu,
+};
+
 U_BOOT_DRIVER(imx8_pinctrl) = {
 	.name = "imx8_pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx8_pinctrl_match),
-	.probe = imx8_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_common,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx8_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
index 6ea66a080b2..d9c63b3aca6 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8m.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -10,14 +10,6 @@
 
 static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data");
 
-static int imx8mq_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imx8m_pinctrl_match[] = {
 	{ .compatible = "fsl,imx8mq-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
 	{ .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
@@ -26,13 +18,17 @@ static const struct udevice_id imx8m_pinctrl_match[] = {
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx8m_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(imx8mq_pinctrl) = {
 	.name = "imx8mq-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx8m_pinctrl_match),
-	.probe = imx8mq_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx8m_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
index 73d3c009d5b..2df63625191 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8ulp.c
@@ -17,27 +17,23 @@ static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info1 = {
 	.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
 };
 
-static int imx8ulp_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imx8ulp_pinctrl_match[] = {
 	{ .compatible = "fsl,imx8ulp-iomuxc0", .data = (ulong)&imx8ulp_pinctrl_soc_info0 },
 	{ .compatible = "fsl,imx8ulp-iomuxc1", .data = (ulong)&imx8ulp_pinctrl_soc_info1 },
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx8ulp_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(imx8ulp_pinctrl) = {
 	.name = "imx8ulp-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx8ulp_pinctrl_match),
-	.probe = imx8ulp_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto = sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx8ulp_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c
index 8d8ffec6d9a..5d250db1081 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx93.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx93.c
@@ -12,27 +12,23 @@ static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info __section(".data") = {
 	.flags = ZERO_OFFSET_VALID,
 };
 
-static int imx93_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imx93_pinctrl_match[] = {
 	{ .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
 	{ .compatible = "fsl,imx91-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imx93_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(imx93_pinctrl) = {
 	.name = "imx93-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imx93_pinctrl_match),
-	.probe = imx93_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imx93_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-imxrt.c b/drivers/pinctrl/nxp/pinctrl-imxrt.c
index 23f07f8d1e0..39000ceb923 100644
--- a/drivers/pinctrl/nxp/pinctrl-imxrt.c
+++ b/drivers/pinctrl/nxp/pinctrl-imxrt.c
@@ -13,27 +13,23 @@ static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
 	.flags = ZERO_OFFSET_VALID,
 };
 
-static int imxrt_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id imxrt_pinctrl_match[] = {
 	{ .compatible = "fsl,imxrt-iomuxc",
 	  .data = (ulong)&imxrt_pinctrl_soc_info },
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops imxrt_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(imxrt_pinctrl) = {
 	.name = "imxrt-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(imxrt_pinctrl_match),
-	.probe = imxrt_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &imxrt_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c
deleted file mode 100644
index 42d5c96468c..00000000000
--- a/drivers/pinctrl/nxp/pinctrl-scu.c
+++ /dev/null
@@ -1,70 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018-2019 NXP
- */
-
-#include <errno.h>
-#include <linux/bitops.h>
-#include <asm/io.h>
-#include <firmware/imx/sci/sci.h>
-#include <misc.h>
-
-#include "pinctrl-imx.h"
-
-#define PADRING_IFMUX_EN_SHIFT		31
-#define PADRING_IFMUX_EN_MASK		BIT(31)
-#define PADRING_GP_EN_SHIFT		30
-#define PADRING_GP_EN_MASK		BIT(30)
-#define PADRING_IFMUX_SHIFT		27
-#define PADRING_IFMUX_MASK		GENMASK(29, 27)
-
-static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad,
-			       u32 mux, u32 val)
-{
-	int ret;
-
-	/*
-	 * Mux should be done in pmx set, but we do not have a good api
-	 * to handle that in scfw, so config it in pad conf func
-	 */
-
-	if (!sc_rm_is_pad_owned(-1, pad)) {
-		debug("Pad[%u] is not owned by curr partition\n", pad);
-		return -EPERM;
-	}
-
-	val |= PADRING_IFMUX_EN_MASK;
-	val |= PADRING_GP_EN_MASK;
-	val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK;
-
-	ret = sc_pad_set(-1, pad, val);
-	if (ret)
-		printf("%s %d\n", __func__, ret);
-
-	return 0;
-}
-
-int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data,
-			      int npins)
-{
-	int pin_id, mux, config_val;
-	int i, j = 0;
-	int ret;
-
-	/*
-	 * Refer to linux documentation for details:
-	 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
-	 */
-	for (i = 0; i < npins; i++) {
-		pin_id = pin_data[j++];
-		mux = pin_data[j++];
-		config_val = pin_data[j++];
-
-		ret = imx_pinconf_scu_set(info, pin_id, mux, config_val);
-		if (ret && ret != -EPERM)
-			printf("Set pin %d, mux %d, val %d, error\n", pin_id,
-			       mux, config_val);
-	}
-
-	return 0;
-}
diff --git a/drivers/pinctrl/nxp/pinctrl-vf610.c b/drivers/pinctrl/nxp/pinctrl-vf610.c
index adf3073f1be..cbff8dcefd8 100644
--- a/drivers/pinctrl/nxp/pinctrl-vf610.c
+++ b/drivers/pinctrl/nxp/pinctrl-vf610.c
@@ -13,27 +13,23 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = {
 	.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
 };
 
-static int vf610_pinctrl_probe(struct udevice *dev)
-{
-	struct imx_pinctrl_soc_info *info =
-		(struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-	return imx_pinctrl_probe(dev, info);
-}
-
 static const struct udevice_id vf610_pinctrl_match[] = {
 	{ .compatible = "fsl,vf610-iomuxc",
 	  .data = (ulong)&vf610_pinctrl_soc_info },
 	{ /* sentinel */ }
 };
 
+static const struct pinctrl_ops vf610_pinctrl_ops = {
+	.set_state = imx_pinctrl_set_state_mmio,
+};
+
 U_BOOT_DRIVER(vf610_pinctrl) = {
 	.name = "vf610-pinctrl",
 	.id = UCLASS_PINCTRL,
 	.of_match = of_match_ptr(vf610_pinctrl_match),
-	.probe = vf610_pinctrl_probe,
-	.remove = imx_pinctrl_remove,
+	.probe = imx_pinctrl_probe_mmio,
+	.remove = imx_pinctrl_remove_mmio,
 	.priv_auto	= sizeof(struct imx_pinctrl_priv),
-	.ops = &imx_pinctrl_ops,
+	.ops = &vf610_pinctrl_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };