diff options
101 files changed, 4801 insertions, 856 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 81c455a7d4a..2a42fd81d9d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1047,6 +1047,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-venice-gw7902.dtb \ imx8mm-venice-gw7903.dtb \ imx8mm-venice-gw7904.dtb \ + imx8mm-venice-gw7905-0x.dtb \ imx8mm-verdin-wifi-dev.dtb \ phycore-imx8mm.dtb \ imx8mn-bsh-smm-s2.dtb \ @@ -1064,13 +1065,21 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-beacon-kit.dtb \ imx8mp-data-modul-edm-sbc.dtb \ + imx8mp-dhcom-som-overlay-rev100.dtbo \ + imx8mp-dhcom-som-overlay-eth1xfast.dtbo \ + imx8mp-dhcom-som-overlay-eth2xfast.dtbo \ + imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo \ imx8mp-dhcom-pdk2.dtb \ imx8mp-dhcom-pdk3.dtb \ + imx8mp-dhcom-pdk3-overlay-rev100.dtbo \ imx8mp-evk.dtb \ imx8mp-icore-mx8mp-edimm2.2.dtb \ imx8mp-msc-sm2s.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-venice.dtb \ + imx8mp-venice-gw71xx-2x.dtb \ + imx8mp-venice-gw72xx-2x.dtb \ + imx8mp-venice-gw73xx-2x.dtb \ imx8mp-venice-gw74xx.dtb \ imx8mp-venice-gw7905-2x.dtb \ imx8mp-verdin-wifi-dev.dtb \ diff --git a/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi index a6c2cc8c1ad..0b185712f9b 100644 --- a/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi +++ b/arch/arm/dts/imx6ull-14x14-evk-u-boot.dtsi @@ -6,3 +6,7 @@ &pinctrl_uart1 { bootph-all; }; + +&rngb { + bootph-all; +}; diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi index e4a27b8dd5a..71bfd80aab8 100644 --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi +++ b/arch/arm/dts/imx7d-sdb-u-boot.dtsi @@ -1,5 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT + #include "imx7s-u-boot.dtsi" +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + &fec2 { status = "disable"; }; @@ -58,3 +68,7 @@ >; }; }; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx7d-smegw01-u-boot.dtsi b/arch/arm/dts/imx7d-smegw01-u-boot.dtsi index 90f7500ee34..611bfe52fd8 100644 --- a/arch/arm/dts/imx7d-smegw01-u-boot.dtsi +++ b/arch/arm/dts/imx7d-smegw01-u-boot.dtsi @@ -1,3 +1,16 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "imx7s-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + +&wdog1 { + bootph-pre-ram; +}; + diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi index d93e1cbd8a7..c4327d31873 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi @@ -6,13 +6,6 @@ #include "imx8mm-u-boot.dtsi" / { - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - wdt-reboot { compatible = "wdt-reboot"; bootph-pre-ram; diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi index 1878c4e13fb..219504f6110 100644 --- a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi @@ -6,13 +6,6 @@ #include "imx8mm-u-boot.dtsi" / { - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - wdt-reboot { compatible = "wdt-reboot"; bootph-pre-ram; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 13688ec0d0f..9a5b0795133 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -11,13 +11,6 @@ wdt = <&wdog1>; bootph-pre-ram; }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; }; &aips4 { @@ -72,22 +65,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &usbmisc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi index 65dfd33725e..ae542fdcffa 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi @@ -16,29 +16,6 @@ wdt = <&wdog1>; bootph-pre-ram; }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; }; &i2c1 { diff --git a/arch/arm/dts/imx8mm-phg-u-boot.dtsi b/arch/arm/dts/imx8mm-phg-u-boot.dtsi index 3ced97cfaaf..c9e0b442050 100644 --- a/arch/arm/dts/imx8mm-phg-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-phg-u-boot.dtsi @@ -11,13 +11,6 @@ wdt = <&wdog1>; bootph-pre-ram; }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; }; &aips4 { diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 6085128e24e..06f2f73a03f 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -7,8 +7,23 @@ binman: binman { multiple-images; }; + +#ifdef CONFIG_OPTEE + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +#endif }; +#ifdef CONFIG_FSL_CAAM +&crypto { + bootph-pre-ram; +}; +#endif + &soc { bootph-all; bootph-pre-ram; @@ -207,6 +222,20 @@ bootph-pre-ram; }; +#ifdef CONFIG_FSL_CAAM +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; +#endif + &spba1 { bootph-all; bootph-pre-ram; diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi new file mode 100644 index 00000000000..c259026d1a8 --- /dev/null +++ b/arch/arm/dts/imx8mm-venice-gw7905-0x-u-boot.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ +#include "imx8mm-venice-gw700x-u-boot.dtsi" + +&gpio1 { + app_gpioa { + gpio-hog; + input; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "gpioa"; + }; + + app_gpiob { + gpio-hog; + input; + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "gpiob"; + }; +}; + +&gpio4 { + pci_usb_sel { + gpio-hog; + output-low; + gpios = <3 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <7 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; + +&gpio5 { + app_gpioc { + gpio-hog; + input; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "gpioc"; + }; + + app_gpiod { + gpio-hog; + input; + gpios = <5 GPIO_ACTIVE_HIGH>; + line-name = "gpiod"; + }; +}; + +/* Disable SOM interfaces not used on baseboard */ +&fec1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw7905-0x.dts b/arch/arm/dts/imx8mm-venice-gw7905-0x.dts new file mode 100644 index 00000000000..914753f062c --- /dev/null +++ b/arch/arm/dts/imx8mm-venice-gw7905-0x.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mm.dtsi" +#include "imx8mm-venice-gw700x.dtsi" +#include "imx8mm-venice-gw7905.dtsi" + +/ { + model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit"; + compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; + +/* Disable SOM interfaces not used on baseboard */ +&fec1 { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mm-venice-gw7905.dtsi b/arch/arm/dts/imx8mm-venice-gw7905.dtsi new file mode 100644 index 00000000000..9646eb9e492 --- /dev/null +++ b/arch/arm/dts/imx8mm-venice-gw7905.dtsi @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + compatible = "regulator-fixed"; + regulator-name = "SD2_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "gpioa", "gpiob", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "pci_usb_sel", + "", "", "", "pci_wdis#", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", + "gpioc", "gpiod", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* USB1 - Type C front panel SINK port J14 */ +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB: + * P1 - USBC connector (host only) + * P2 - USB2 test connector + * P3 - miniPCIe full card + * P4 - miniPCIe half card + */ +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi index 2b268f55cb9..8efa4ddc734 100644 --- a/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-wifi-dev-u-boot.dtsi @@ -6,13 +6,6 @@ #include "imx8mm-u-boot.dtsi" / { - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - wdt-reboot { compatible = "wdt-reboot"; bootph-pre-ram; @@ -34,6 +27,10 @@ bootph-pre-ram; }; +&aips4 { + bootph-pre-ram; +}; + &binman_uboot { offset = <0x5fc00>; }; @@ -124,6 +121,19 @@ bootph-pre-ram; }; +&usbmisc1 { + bootph-pre-ram; +}; + +/* Verdin USB_1 */ +&usbotg1 { + bootph-pre-ram; +}; + +&usbphynop1 { + bootph-pre-ram; +}; + &usdhc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 315714f3984..c31f3dec3de 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -57,22 +57,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &usdhc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index bc57566a108..96b1a1bc802 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -8,12 +8,14 @@ multiple-images; }; +#ifdef CONFIG_OPTEE firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; }; }; +#endif wdt-reboot { compatible = "wdt-reboot"; @@ -52,6 +54,12 @@ /delete-property/ assigned-clock-rates; }; +#ifdef CONFIG_FSL_CAAM +&crypto { + bootph-pre-ram; +}; +#endif + &iomuxc { bootph-pre-ram; }; @@ -61,6 +69,20 @@ bootph-all; }; +#ifdef CONFIG_FSL_CAAM +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; +#endif + &spba1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi index b56f3a2bd2e..393fd8ec2e5 100644 --- a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi @@ -11,13 +11,6 @@ wdt = <&wdog1>; bootph-pre-ram; }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; }; &{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { @@ -28,10 +21,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - &eqos { /delete-property/ assigned-clocks; /delete-property/ assigned-clock-parents; @@ -138,18 +127,6 @@ u-boot,off-on-delay-us = <20000>; }; -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &tpm { compatible = "tcg,tpm_tis-spi"; }; diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi index dd0f34f3447..eafe9b9308c 100644 --- a/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include "imx8mp-u-boot.dtsi" +#include "imx8mp-pinfunc.h" / { aliases { @@ -17,6 +18,17 @@ dmo,ram-coding-gpios = <&gpio3 20 0>, <&gpio4 3 0>, <&gpio4 1 0>; }; + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB1_PWR"; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -113,6 +125,10 @@ bootph-pre-ram; }; +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; +}; + &usdhc2 { bootph-pre-ram; sd-uhs-sdr104; @@ -128,3 +144,17 @@ &wdog1 { bootph-pre-ram; }; + +&iomuxc { + usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80 + >; + }; + + pinctrl_usb1_vbus: usb1-vbus-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x6 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts new file mode 100644 index 00000000000..3b397776920 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut <marex@denx.de> + */ +/dts-v1/; +/plugin/; + +ðphypdk { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts new file mode 100644 index 00000000000..f27e6429abe --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut <marex@denx.de> + */ +/dts-v1/; +/plugin/; + +ðphy0g { + reg = <7>; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3.dts b/arch/arm/dts/imx8mp-dhcom-pdk3.dts index c5f0607f43b..867d238f2b5 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk3.dts +++ b/arch/arm/dts/imx8mp-dhcom-pdk3.dts @@ -227,10 +227,6 @@ }; }; -ðphy0g { - reg = <7>; -}; - &fec { /* Second ethernet */ pinctrl-0 = <&pinctrl_fec_rgmii>; phy-handle = <ðphypdk>; diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts new file mode 100644 index 00000000000..bb5a2b68175 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut <marex@denx.de> + */ +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/imx8mp-clock.h> + +&eqos { /* First ethernet */ + pinctrl-0 = <&pinctrl_eqos_rmii>; + phy-handle = <ðphy0f>; + phy-mode = "rmii"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; +}; + +ðphy0g { /* Micrel KSZ9131RNXI */ + status = "disabled"; +}; + +ðphy0f { /* SMSC LAN8740Ai */ + status = "okay"; +}; + +&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */ + status = "disabled"; +}; + +/* No WiFi/BT chipset on this SoM variant. */ + +&uart2 { + bluetooth { + status = "disabled"; + }; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts new file mode 100644 index 00000000000..82dadcea96c --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut <marex@denx.de> + */ +#include "imx8mp-dhcom-som-overlay-eth1xfast.dts" + +/* Dual RMII 100/Full Fast ethernet on this SoM variant. */ + +&fec { /* Second ethernet */ + pinctrl-0 = <&pinctrl_fec_rmii>; + phy-handle = <ðphy1f>; + phy-mode = "rmii"; + status = "okay"; + + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>, <0>; +}; + +ðphy1f { /* SMSC LAN8740Ai */ + status = "okay"; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts new file mode 100644 index 00000000000..5d9a00c9429 --- /dev/null +++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2023 Marek Vasut <marex@denx.de> + */ +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#include "imx8mp-pinfunc.h" + +&brcmf { + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +}; + +&eeprom0 { /* EEPROM with EQoS MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; +}; + +&eeprom1 { /* EEPROM with FEC MAC address */ + compatible = "atmel,24c02"; + pagesize = <16>; +}; + +ðphy0f { /* SMSC LAN8740Ai */ + pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +}; + +ðphy0g { /* Micrel KSZ9131RNXI */ + pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>; + reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; +}; + +&i2c3 { + adc@48 { + compatible = "ti,tla2024"; + interrupts-extended; + }; +}; + +&ioexp { + status = "disabled"; +}; + +®_eth_vio { + gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_enet_vio>; + pinctrl-names = "default"; +}; + +&rv3032 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; +}; + +&uart2 { + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_vbus>; +}; + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c + &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f + &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i + &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l + /* GPIO_M is connected to CLKOUT2 */ + &pinctrl_dhcom_int>; + + pinctrl_enet_vio: dhcom-enet-vio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 + >; + }; + + pinctrl_rtc: dhcom-rtc-grp { + fsl,pins = < + /* RTC_#INT Interrupt */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x400001c6 + >; + }; + + pinctrl_uart2_bt: dhcom-uart2-bt-grp { + fsl,pins = < + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + >; + }; + + pinctrl_usb0_vbus: dhcom-usb0-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 + >; + }; + + pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp { + fsl,pins = < + /* WL_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index 9fd8bce8065..ea2a567447a 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -25,9 +25,7 @@ reg_eth_vio: regulator-eth-vio { compatible = "regulator-fixed"; - gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_enet_vio>; - pinctrl-names = "default"; + gpio = <&ioexp 2 GPIO_ACTIVE_LOW>; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; @@ -49,6 +47,14 @@ startup-delay-us = <100>; vin-supply = <&buck4>; }; + + reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VDD_3P3V_AWO"; + }; }; &A53_0 { @@ -104,7 +110,7 @@ reg = <0>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; /* Non-default PHY population option. */ status = "disabled"; }; @@ -120,7 +126,7 @@ reg = <5>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; /* Default PHY population option. */ status = "okay"; }; @@ -320,8 +326,9 @@ }; adc@48 { - compatible = "ti,tla2024"; + compatible = "ti,ads1015"; reg = <0x48>; + interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; #size-cells = <0>; @@ -368,24 +375,40 @@ }; eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ - compatible = "atmel,24c02"; - pagesize = <16>; + compatible = "atmel,24c32"; /* M24C32-D */ + pagesize = <32>; reg = <0x50>; }; rv3032: rtc@51 { compatible = "microcrystal,rv3032"; reg = <0x51>; - interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>; }; eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ - compatible = "atmel,24c02"; - pagesize = <16>; + compatible = "atmel,24c32"; /* M24C32-D */ + pagesize = <32>; reg = <0x53>; }; + + ioexp: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ioexp>; + + gpio-line-names = + "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT", + "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY", + "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", + "BT_HOST_WAKE", "BT_DEV_WAKE", "", ""; + }; }; &i2c4 { @@ -427,6 +450,23 @@ pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; status = "okay"; + + /* + * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock, + * which with 16x oversampling yields 5 Mbdps baud base, + * which can be well divided by 5/4 to achieve 4 Mbdps, + * which is exactly the maximum rate supported by muRata + * 2AE bluetooth UART. + */ + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + assigned-clock-rates = <80000000>; + + bluetooth { + compatible = "cypress,cyw4373a0-bt"; + shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + }; }; &uart3 { @@ -451,8 +491,6 @@ }; &usb_dwc3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_vbus>; dr_mode = "otg"; status = "okay"; }; @@ -496,7 +534,7 @@ * connected to the SoC, but can be connected on to * SoC pin on the carrier board. */ - reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>; }; }; @@ -538,8 +576,9 @@ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l - /* GPIO_M is connected to CLKOUT2 */ - &pinctrl_dhcom_int>; + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_int>; pinctrl-names = "default"; pinctrl_dhcom_a: dhcom-a-grp { @@ -626,6 +665,55 @@ >; }; + pinctrl_dhcom_m: dhcom-m-grp { + fsl,pins = < + /* CSIx_MCLK */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2 + >; + }; + + pinctrl_dhcom_n: dhcom-n-grp { + fsl,pins = < + /* CSI2_D3- */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2 + >; + }; + + pinctrl_dhcom_o: dhcom-o-grp { + fsl,pins = < + /* CSI2_D3+ */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2 + >; + }; + + pinctrl_dhcom_p: dhcom-p-grp { + fsl,pins = < + /* CSI2_D2- */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2 + >; + }; + + pinctrl_dhcom_q: dhcom-q-grp { + fsl,pins = < + /* CSI2_D2+ */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2 + >; + }; + + pinctrl_dhcom_r: dhcom-r-grp { + fsl,pins = < + /* CSI2_D1- */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2 + >; + }; + + pinctrl_dhcom_s: dhcom-s-grp { + fsl,pins = < + /* CSI2_D1+ */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2 + >; + }; + pinctrl_dhcom_int: dhcom-int-grp { fsl,pins = < /* INT_HIGHEST_PRIO */ @@ -699,17 +787,9 @@ >; }; - pinctrl_enet_vio: dhcom-enet-vio-grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 - >; - }; - pinctrl_ethphy0: dhcom-ethphy0-grp { fsl,pins = < - /* ENET1_#RST Reset */ - MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 - /* ENET1_#INT Interrupt */ + /* ENET_QOS_#INT Interrupt */ MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 >; }; @@ -834,6 +914,13 @@ >; }; + pinctrl_ioexp: dhcom-ioexp-grp { + fsl,pins = < + /* #GPIO_EXP_INT */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 + >; + }; + pinctrl_pmic: dhcom-pmic-grp { fsl,pins = < /* PMIC_nINT */ @@ -847,10 +934,21 @@ >; }; - pinctrl_rtc: dhcom-rtc-grp { + pinctrl_tc9595: dhcom-tc9595-grp { fsl,pins = < - /* RTC_#INT Interrupt */ - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 + /* RESET_DSIBRIDGE */ + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000146 + /* DSI-CONV_INT Interrupt */ + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x141 + >; + }; + + pinctrl_sai3: dhcom-sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 >; }; @@ -897,12 +995,6 @@ >; }; - pinctrl_usb0_vbus: dhcom-usb0-grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 - >; - }; - pinctrl_usb1_vbus: dhcom-usb1-grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 @@ -918,10 +1010,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; }; @@ -933,10 +1021,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; }; @@ -948,10 +1032,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; }; diff --git a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi index 59d31eebc3e..b05be57e71b 100644 --- a/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-u-boot.dtsi @@ -42,6 +42,7 @@ }; &gpio3 { + bootph-all; bootph-pre-ram; }; @@ -133,3 +134,74 @@ &wdog1 { bootph-pre-ram; }; + +&binman { + itb { + fit { + images { + fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast { + description = "imx8mp-dhcom-som-overlay-eth1xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth1xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast { + description = "imx8mp-dhcom-som-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-eth2xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast { + description = "imx8mp-dhcom-pdk-overlay-eth2xfast"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk-overlay-eth2xfast.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-som-overlay-rev100 { + description = "imx8mp-dhcom-som-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-som-overlay-rev100.dtbo"; + }; + }; + + fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100 { + description = "imx8mp-dhcom-pdk3-overlay-rev100"; + type = "flat_dt"; + compression = "none"; + + blob-ext { + filename = "imx8mp-dhcom-pdk3-overlay-rev100.dtbo"; + }; + }; + }; + + configurations { + default = "@config-DEFAULT-SEQ"; + + @config-SEQ { + fdt = "fdt-1", + "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast", + "fdt-dto-imx8mp-dhcom-som-overlay-rev100", + "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 6784ed2e7c9..9ed62f1bb02 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -11,12 +11,6 @@ wdt = <&wdog1>; bootph-pre-ram; }; - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; }; ®_usdhc2_vmmc { @@ -71,22 +65,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &i2c1 { bootph-pre-ram; }; @@ -111,6 +89,19 @@ bootph-pre-ram; }; +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + &usdhc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi index d411cf79e85..cf2a87a9b90 100644 --- a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi @@ -12,13 +12,6 @@ wdt = <&wdog1>; bootph-pre-ram; }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; }; ®_usdhc2_vmmc { @@ -69,22 +62,6 @@ bootph-pre-ram; }; -&crypto { - bootph-pre-ram; -}; - -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &i2c1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi index c4ea536b29b..22171bd344e 100644 --- a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi @@ -12,13 +12,6 @@ wdt = <&wdog1>; bootph-pre-ram; }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; }; &iomuxc { diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 200938a9807..4fadcaea509 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -8,7 +8,22 @@ binman: binman { multiple-images; }; + +#ifdef CONFIG_OPTEE + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +#endif +}; + +#ifdef CONFIG_FSL_CAAM +&crypto { + bootph-pre-ram; }; +#endif &soc { bootph-all; @@ -53,6 +68,20 @@ bootph-pre-ram; }; +#ifdef CONFIG_FSL_CAAM +&sec_jr0 { + bootph-pre-ram; +}; + +&sec_jr1 { + bootph-pre-ram; +}; + +&sec_jr2 { + bootph-pre-ram; +}; +#endif + &binman { u-boot-spl-ddr { filename = "u-boot-spl-ddr.bin"; @@ -171,14 +200,16 @@ filename = "flash.bin"; pad-byte = <0x00>; - spl: blob-ext@1 { + spl { filename = "spl.bin"; offset = <0x0>; + type = "blob-ext"; }; - uboot: blob-ext@2 { + binman_uboot: uboot { filename = "u-boot.itb"; offset = <0x58000>; + type = "blob-ext"; }; }; }; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi new file mode 100644 index 00000000000..5c33f8c9cdc --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x-u-boot.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ +#include "imx8mp-venice-gw702x-u-boot.dtsi" + +&gpio4 { + dio_1 { + gpio-hog; + input; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + dio_3 { + gpio-hog; + input; + gpios = <24 GPIO_ACTIVE_HIGH>; + line-name = "dio3"; + }; + + dio_2 { + gpio-hog; + input; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "dio2"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; + +/* gpio-usb-con not supported yet in U-Boot so make this a host for now */ +&usb_dwc3_0 { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts new file mode 100644 index 00000000000..53120fc9cd7 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw71xx-2x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw71xx.dtsi" + +/ { + model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw71xx.dtsi b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi new file mode 100644 index 00000000000..86999f52d4b --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw71xx.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "dio1", "", "", "dio0", + "", "", "pci_usb_sel", "", + "", "", "", "", + "", "", "", "", + "dio3", "", "dio2", "", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB1 Type-C front panel */ +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "Type-C"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + }; +}; + +/* USB2 - MiniPCIe socket */ +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */ + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ + >; + }; + + pinctrl_usbcon1: usbcon1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi new file mode 100644 index 00000000000..7f2609ab546 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw72xx-2x-u-boot.dtsi @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ +#include "imx8mp-venice-gw702x-u-boot.dtsi" + +&gpio4 { + dio_1 { + gpio-hog; + input; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + mipi_gpio4 { + gpio-hog; + input; + gpios = <17 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + rs485_en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en"; + }; + + rs485_term { + gpio-hog; + output-low; + gpios = <23 GPIO_ACTIVE_HIGH>; + line-name = "rs485_term"; + }; + + mipi_gpio1 { + gpio-hog; + input; + gpios = <24 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; + + mipi_gpio3 { + gpio-hog; + input; + gpios = <25 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + mipi_gpio2 { + gpio-hog; + input; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; + + rs485_hd { + gpio-hog; + output-low; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "rs485_hd"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; + +/* gpio-usb-con not supported yet in U-Boot so make this a host for now */ +&usb_dwc3_0 { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts new file mode 100644 index 00000000000..255e36f66b0 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw72xx-2x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw72xx.dtsi" + +/ { + model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw72xx.dtsi b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi new file mode 100644 index 00000000000..e05fdecdaf4 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw72xx.dtsi @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb1_vbus: regulator-usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SD"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <100>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "dio1", "", "", "dio0", + "", "", "pci_usb_sel", "", + "", "", "", "", + "", "", "rs485_en", "rs485_term", + "", "", "", "rs485_half", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - OTG */ +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "otg"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + }; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 + >; + }; + + pinctrl_reg_usb1_en: regusb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ + >; + }; + + pinctrl_usbcon1: usbcon1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi new file mode 100644 index 00000000000..70433c07329 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x-u-boot.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Gateworks Corporation + */ +#include "imx8mp-venice-gw702x-u-boot.dtsi" + +ðphy0 { + reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <300000>; +}; + +&gpio4 { + dio_1 { + gpio-hog; + input; + gpios = <8 GPIO_ACTIVE_HIGH>; + line-name = "dio1"; + }; + + dio_0 { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "dio0"; + }; + + pci_usb_sel { + gpio-hog; + output-low; + gpios = <14 GPIO_ACTIVE_HIGH>; + line-name = "pci_usb_sel"; + }; + + mipi_gpio4 { + gpio-hog; + input; + gpios = <17 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio4"; + }; + + rs485_en { + gpio-hog; + output-low; + gpios = <22 GPIO_ACTIVE_HIGH>; + line-name = "rs485_en"; + }; + + rs485_term { + gpio-hog; + output-low; + gpios = <23 GPIO_ACTIVE_HIGH>; + line-name = "rs485_term"; + }; + + mipi_gpio1 { + gpio-hog; + input; + gpios = <24 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio1"; + }; + + mipi_gpio3 { + gpio-hog; + input; + gpios = <25 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio3"; + }; + + mipi_gpio2 { + gpio-hog; + input; + gpios = <26 GPIO_ACTIVE_HIGH>; + line-name = "mipi_gpio2"; + }; + + rs485_hd { + gpio-hog; + output-low; + gpios = <27 GPIO_ACTIVE_HIGH>; + line-name = "rs485_hd"; + }; + + pci_wdis { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + line-name = "pci_wdis#"; + }; +}; + +/* gpio-usb-con not supported yet in U-Boot so make this a host for now */ +&usb_dwc3_0 { + dr_mode = "host"; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts b/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts new file mode 100644 index 00000000000..000fd15e0c0 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw73xx-2x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw73xx.dtsi" + +/ { + model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw73xx.dtsi b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi new file mode 100644 index 00000000000..1c05398c862 --- /dev/null +++ b/arch/arm/dts/imx8mp-venice-gw73xx.dtsi @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb1_vbus: regulator-usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wifi_en: regulator-wifi-en { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SD"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <100>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "dio1", "", "", "dio0", + "", "", "pci_usb_sel", "", + "", "", "", "", + "", "", "rs485_en", "rs485_term", + "", "", "", "rs485_half", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* bluetooth HCI */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; + cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + }; +}; + +/* RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - OTG */ +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "otg"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + }; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ + >; + }; + + pinctrl_bten: btengrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146 + >; + }; + + pinctrl_reg_usb1_en: regusb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ + >; + }; + + pinctrl_usbcon1: usbcon1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi index c3fb040080b..240fbc1b568 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi @@ -6,13 +6,6 @@ #include "imx8mp-u-boot.dtsi" / { - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - wdt-reboot { compatible = "wdt-reboot"; bootph-pre-ram; @@ -53,67 +46,81 @@ &gpio2 { bootph-pre-ram; - pcie1_wdis_hog { + m2_pin20 { + gpio-hog; + input; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "m2_pin20"; + }; + + m2_pin22 { + gpio-hog; + input; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "m2_pin22"; + }; + + tpm_rst_hog { gpio-hog; - gpios = <17 GPIO_ACTIVE_HIGH>; output-high; - line-name = "pcie1_wdis#"; + gpios = <12 GPIO_ACTIVE_HIGH>; + line-name = "tpm_rst#"; }; - pcie2_wdis_hog { + pcie1_wdis_hog { gpio-hog; - gpios = <18 GPIO_ACTIVE_HIGH>; output-high; - line-name = "pcie2_wdis#"; + gpios = <13 GPIO_ACTIVE_HIGH>; + line-name = "pcie1_wdis#"; }; pcie3_wdis_hog { gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; output-high; + gpios = <14 GPIO_ACTIVE_HIGH>; line-name = "pcie3_wdis#"; }; -}; - -&gpio3 { - bootph-pre-ram; - m2_dis2_hog { + pcie2_wdis_hog { gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; output-high; - line-name = "m2_gdis#"; + gpios = <18 GPIO_ACTIVE_HIGH>; + line-name = "pcie2_wdis#"; }; +}; + +&gpio3 { + bootph-pre-ram; - m2rst_hog { + m2_rst { gpio-hog; + output-low; gpios = <6 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "m2_rst#"; + line-name = "m2_rst"; }; +}; + +&gpio4 { + bootph-pre-ram; - m2_off_hog { + m2_off { gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; output-high; + gpios = <2 GPIO_ACTIVE_HIGH>; line-name = "m2_off#"; }; -}; -&gpio4 { - bootph-pre-ram; - - m2_dis1_hog { + m2_wdis { gpio-hog; - gpios = <18 GPIO_ACTIVE_HIGH>; output-high; + gpios = <18 GPIO_ACTIVE_HIGH>; line-name = "m2_wdis#"; }; rs485_en { gpio-hog; - gpios = <31 GPIO_ACTIVE_HIGH>; output-low; + gpios = <31 GPIO_ACTIVE_HIGH>; line-name = "rs485_en"; }; }; @@ -123,15 +130,15 @@ rs485_half { gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; output-low; + gpios = <0 GPIO_ACTIVE_HIGH>; line-name = "rs485_hd"; }; rs485_term { gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; output-low; + gpios = <1 GPIO_ACTIVE_HIGH>; line-name = "rs485_term"; }; }; diff --git a/arch/arm/dts/imx8mp-venice-gw74xx.dts b/arch/arm/dts/imx8mp-venice-gw74xx.dts index ceeca4966fc..7eb28531573 100644 --- a/arch/arm/dts/imx8mp-venice-gw74xx.dts +++ b/arch/arm/dts/imx8mp-venice-gw74xx.dts @@ -125,12 +125,22 @@ regulator-max-microvolt = <5000000>; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_can2_stby: regulator-can2-stby { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can>; + pinctrl-0 = <&pinctrl_reg_can2>; regulator-name = "can2_stby"; - gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; + gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -164,6 +174,21 @@ cpu-supply = <®_arm>; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "tcg,tpm_tis-spi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x0>; + spi-max-frequency = <36000000>; + }; +}; + /* off-board header */ &ecspi2 { pinctrl-names = "default"; @@ -204,6 +229,13 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -214,38 +246,38 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "dio0", "", "dio1", "", "", "", + "", "dio0", "", "dio1", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &gpio2 { gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "pcie3_wdis#", "", + "", "", "", "", "", "", "m2_pin20", "", + "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "", "", "", "pcie2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &gpio3 { gpio-line-names = - "m2_gdis#", "", "", "", "", "", "", "m2_rst#", + "", "", "", "", "", "", "m2_rst", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "m2_off#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &gpio4 { gpio-line-names = + "", "", "m2_off#", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "m2_wdis#", "", "", "", - "", "", "", "", "", "", "", "uart_rs485"; + "", "", "m2_wdis#", "", "", "", "", "", + "", "", "", "", "", "", "", "rs485_en"; }; &gpio5 { gpio-line-names = - "uart_half", "uart_term", "", "", "", "", "", "", + "rs485_hd", "rs485_term", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; @@ -268,6 +300,8 @@ interrupts = <20 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; adc { compatible = "gw,gsc-adc"; @@ -286,6 +320,12 @@ label = "vdd_bat"; }; + channel@16 { + gw,mode = <4>; + reg = <0x16>; + label = "fan_tach"; + }; + channel@82 { gw,mode = <2>; reg = <0x82>; @@ -358,6 +398,11 @@ gw,voltage-divider-ohms = <10000 10000>; }; }; + + fan-controller@a { + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; }; gpio: gpio@23 { @@ -369,85 +414,6 @@ interrupts = <4>; }; - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - regulators { - BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - reg_arm: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1045000>; - regulator-max-microvolt = <1155000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -559,7 +525,6 @@ }; }; -/* off-board header */ &i2c3 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -568,6 +533,85 @@ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_arm: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; /* off-board header */ @@ -734,12 +778,14 @@ fsl,pins = < MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */ + MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ @@ -792,6 +838,13 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 @@ -877,7 +930,7 @@ pinctrl_pcie0: pciegrp { fsl,pins = < - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106 >; }; @@ -893,12 +946,18 @@ >; }; - pinctrl_reg_can: regcangrp { + pinctrl_reg_can1: regcan1grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 >; }; + pinctrl_reg_can2: regcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 + >; + }; + pinctrl_reg_usb2: regusb2grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 @@ -911,12 +970,12 @@ >; }; - pinctrl_sai2: sai2grp { + pinctrl_spi1: spi1grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 - MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 - MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 >; }; diff --git a/arch/arm/dts/imx8mp-venice-u-boot.dtsi b/arch/arm/dts/imx8mp-venice-u-boot.dtsi index 99d76393d33..07813d03065 100644 --- a/arch/arm/dts/imx8mp-venice-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-venice-u-boot.dtsi @@ -73,6 +73,14 @@ bootph-pre-ram; }; +&i2c3 { + bootph-pre-ram; +}; + +&pinctrl_i2c3 { + bootph-pre-ram; +}; + &wdog1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mp-venice.dts b/arch/arm/dts/imx8mp-venice.dts index 77e5ac423db..372db26cc09 100644 --- a/arch/arm/dts/imx8mp-venice.dts +++ b/arch/arm/dts/imx8mp-venice.dts @@ -57,6 +57,13 @@ }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + /* console */ &uart2 { pinctrl-names = "default"; @@ -106,6 +113,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 diff --git a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi index 0162f9b2da3..2a1aa1935a7 100644 --- a/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi @@ -6,13 +6,6 @@ #include "imx8mp-u-boot.dtsi" / { - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - wdt-reboot { compatible = "wdt-reboot"; bootph-pre-ram; @@ -35,10 +28,6 @@ }; -&crypto { - bootph-pre-ram; -}; - &gpio1 { bootph-pre-ram; }; @@ -147,18 +136,6 @@ bootph-pre-ram; }; -&sec_jr0 { - bootph-pre-ram; -}; - -&sec_jr1 { - bootph-pre-ram; -}; - -&sec_jr2 { - bootph-pre-ram; -}; - &uart3 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index 5b465e2dbd9..93b4d91e4c3 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -126,3 +126,26 @@ bootph-pre-ram; status = "okay"; }; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi index 13cf32d4b27..90de635481f 100644 --- a/arch/arm/dts/imx93.dtsi +++ b/arch/arm/dts/imx93.dtsi @@ -254,8 +254,8 @@ compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44380000 0x1000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg"; + clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg", "per"; status = "disabled"; }; diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index aebfa6517bd..6904cf38802 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -142,7 +142,9 @@ u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE $(call if_changed,mkimage) quiet_cmd_u-boot-nand_imx = GEN $@ -cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@ +cmd_u-boot-nand_imx = (dd bs=1024 count=1 if=/dev/zero 2>/dev/null) | cat - $< > $@.zero-padded ; \ + (dd bs=10k count=1 if=/dev/zero 2>/dev/null) | cat $@.zero-padded - > $@ ; \ + rm -f $@.zero-padded u-boot-nand.imx: u-boot.imx FORCE $(call if_changed,u-boot-nand_imx) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index fc829588ce8..5de4d11a761 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1246,6 +1246,82 @@ static int fixup_thermal_trips(void *blob, const char *name) return 0; } +#define OPTEE_SHM_SIZE 0x00400000 +static int ft_add_optee_node(void *fdt, struct bd_info *bd) +{ + struct fdt_memory carveout; + const char *path, *subpath; + phys_addr_t optee_start; + size_t optee_size; + int offs; + int ret; + + /* + * No TEE space allocated indicating no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[1]) + return 0; + + optee_start = (phys_addr_t)rom_pointer[0]; + optee_size = rom_pointer[1] - OPTEE_SHM_SIZE; + + offs = fdt_increase_size(fdt, 512); + if (offs) { + printf("No Space for dtb\n"); + return 1; + } + + path = "/firmware"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + path = "/"; + offs = fdt_path_offset(fdt, path); + + if (offs < 0) { + printf("Could not find root node.\n"); + return offs; + } + + subpath = "firmware"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + return offs; + } + } + + subpath = "optee"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + return offs; + } + + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); + fdt_setprop_string(fdt, offs, "method", "smc"); + + carveout.start = optee_start, + carveout.end = optee_start + optee_size - 1, + ret = fdtdec_add_reserved_memory(fdt, "optee_core", &carveout, NULL, 0, + NULL, FDTDEC_RESERVED_MEMORY_NO_MAP); + if (ret < 0) { + printf("Could not create optee_core node.\n"); + return ret; + } + + carveout.start = optee_start + optee_size; + carveout.end = optee_start + optee_size + OPTEE_SHM_SIZE - 1; + ret = fdtdec_add_reserved_memory(fdt, "optee_shm", &carveout, NULL, 0, + NULL, FDTDEC_RESERVED_MEMORY_NO_MAP); + if (ret < 0) { + printf("Could not create optee_shm node.\n"); + return ret; + } + + return 0; +} + int ft_system_setup(void *blob, struct bd_info *bd) { #ifdef CONFIG_IMX8MQ @@ -1395,7 +1471,7 @@ usb_modify_speed: fixup_thermal_trips(blob, "soc-thermal")) printf("Failed to update soc-thermal trip(s)"); - return 0; + return ft_add_optee_node(blob, bd); } #endif diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index d3233d8d14f..ccce6a78caa 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -18,9 +18,6 @@ config TARGET_MX23EVK select PL01X_SERIAL select BOARD_EARLY_INIT_F -config TARGET_XFI3 - bool "Support xfi3" - endchoice config SYS_SOC diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 6c13b00ef10..b30cd962553 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -353,7 +353,7 @@ void *spl_load_simple_fit_fix_load(const void *fit) debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size); debug("%s: ivt self: %x\n", __func__, ivt->self); - if (imx_hab_authenticate_image((uintptr_t)fit, (uintptr_t)ivt, offset)) + if (imx_hab_authenticate_image((uintptr_t)fit, (uintptr_t)size, offset)) panic("spl: ERROR: image authentication unsuccessful\n"); return (void *)fit; diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 4af41699678..c4a4185eed1 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -133,6 +133,41 @@ err: return -1; } +struct stream_state { + u8 *base; + u8 *end; + u32 pagesize; +}; + +static ulong spl_romapi_read_stream(struct spl_load_info *load, ulong sector, + ulong count, void *buf) +{ + struct stream_state *ss = load->priv; + u8 *end = (u8*)(sector + count); + u32 bytes; + int ret; + + if (end > ss->end) { + bytes = end - ss->end; + bytes += ss->pagesize - 1; + bytes /= ss->pagesize; + bytes *= ss->pagesize; + + debug("downloading another 0x%x bytes\n", bytes); + ret = rom_api_download_image(ss->end, 0, bytes); + + if (ret != ROM_API_OKAY) { + printf("Failure download %d\n", bytes); + return 0; + } + + ss->end = end; + } + + memcpy(buf, (void *)(sector), count); + return count; +} + static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { @@ -149,23 +184,6 @@ static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector, return count; } -static ulong get_fit_image_size(void *fit) -{ - struct spl_image_info spl_image; - struct spl_load_info spl_load_info; - ulong last = (ulong)fit; - - memset(&spl_load_info, 0, sizeof(spl_load_info)); - spl_load_info.bl_len = 1; - spl_load_info.read = spl_ram_load_read; - spl_load_info.priv = &last; - - spl_load_simple_fit(&spl_image, &spl_load_info, - (uintptr_t)fit, fit); - - return last - (ulong)fit; -} - static u8 *search_fit_header(u8 *p, int size) { int i; @@ -226,9 +244,7 @@ static int img_info_size(void *img_hdr) static int img_total_size(void *img_hdr) { - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) { - return get_fit_image_size(img_hdr); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { + if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { int total = get_container_size((ulong)img_hdr, NULL); if (total < 0) { @@ -316,6 +332,21 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, } } + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) { + struct stream_state ss; + + ss.base = phdr; + ss.end = p; + ss.pagesize = pagesize; + + memset(&load, 0, sizeof(load)); + load.bl_len = 1; + load.read = spl_romapi_read_stream; + load.priv = &ss; + + return spl_load_simple_fit(spl_image, &load, (ulong)phdr, phdr); + } + total = img_total_size(phdr); total += 3; total &= ~0x3; @@ -336,9 +367,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, load.bl_len = 1; load.read = spl_ram_load_read; - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) - return spl_load_simple_fit(spl_image, &load, (ulong)phdr, phdr); - else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) + if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) return spl_load_imx_container(spl_image, &load, (ulong)phdr); return -1; diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 129efac6fa6..16df1186759 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec) return usec; } -#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_SPL_BUILD) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 760ea4be35c..5edb85e1de5 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -5,16 +5,12 @@ #include <common.h> #include <asm/arch/clock.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/arch/imx8mp_pins.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> #include <dm.h> -#include <dt-bindings/clock/imx8mp-clock.h> #include <env.h> #include <env_internal.h> #include <i2c_eeprom.h> -#include <linux/bitfield.h> #include <malloc.h> #include <net.h> #include <miiphy.h> @@ -120,227 +116,3 @@ enum env_location env_get_location(enum env_operation op, int prio) { return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH; } - -static const char *iomuxc_compat = "fsl,imx8mp-iomuxc"; -static const char *lan_compat = "ethernet-phy-id0007.c110"; -static const char *ksz_compat = "ethernet-phy-id0022.1642"; - -static int dh_dt_patch_som_eqos(const void *fdt_blob) -{ - const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR + - FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24); - int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode; - const char *mac_compat = "nxp,imx8mp-dwmac-eqos"; - void *blob = (void *)fdt_blob; - const fdt32_t *clk_prop; - bool is_gigabit; - u32 handle; - u32 clk[6]; - - setbits_le32(mux, IOMUX_CONFIG_SION); - is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24)); - clrbits_le32(mux, IOMUX_CONFIG_SION); - - /* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */ - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - if (mac_node < 0) - return 0; - - mdio_node = fdt_first_subnode(blob, mac_node); - if (mdio_node < 0) - return 0; - - /* KSZ9131RNXI */ - ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat); - if (ksz_node < 0) - return 0; - - /* LAN8740Ai */ - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - if (lan_node < 0) - return 0; - - iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat); - if (iomuxc_node < 0) - return 0; - - /* - * The code below adjusts the following DT properties: - * - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock - * - assigned-clock-rates .... 125 MHz RGMII / 50 MHz RMII ref clock - * - phy-handle .............. KSZ9131RNXI RGMII / LAN8740Ai RMII - * - phy-mode ................ RGMII / RMII - * - pinctrl-0 ............... RGMII / RMII - * - PHY subnode status ...... "disabled"/"okay" per RGMII / RMII - */ - - /* Perform all inplace changes first, string changes last. */ - clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL); - if (!clk_prop) - return 0; - clk[0] = clk_prop[0]; - clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M); - clk[2] = clk_prop[2]; - clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M); - clk[4] = clk_prop[4]; - clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) : - cpu_to_fdt32(IMX8MP_SYS_PLL2_50M); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents", - clk, 6 * sizeof(u32)); - - clk[0] = cpu_to_fdt32(0); - clk[1] = cpu_to_fdt32(100000000); - clk[2] = is_gigabit ? cpu_to_fdt32(125000000) : - cpu_to_fdt32(50000000); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates", - clk, 3 * sizeof(u32)); - - handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node); - fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle); - - fdt_for_each_subnode(subnode, blob, iomuxc_node) { - if (!strstr(fdt_get_name(blob, subnode, NULL), - is_gigabit ? "eqos-rgmii" : "eqos-rmii")) - continue; - - handle = fdt_get_phandle(blob, subnode); - fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle); - break; - } - - fdt_setprop_string(blob, mac_node, "phy-mode", - is_gigabit ? "rgmii-id" : "rmii"); - - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - mdio_node = fdt_first_subnode(blob, mac_node); - ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat); - fdt_setprop_string(blob, ksz_node, "status", - is_gigabit ? "okay" : "disabled"); - - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - mdio_node = fdt_first_subnode(blob, mac_node); - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - fdt_setprop_string(blob, lan_node, "status", - is_gigabit ? "disabled" : "okay"); - - return 0; -} - -static int dh_dt_patch_som_fec(const void *fdt_blob) -{ - const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR + - FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10); - int mac_node, mdio_node, iomuxc_node, lan_node, phy_node, subnode; - const char *mac_compat = "fsl,imx8mp-fec"; - void *blob = (void *)fdt_blob; - const fdt32_t *clk_prop; - bool is_gigabit; - u32 handle; - u32 clk[8]; - - setbits_le32(mux, IOMUX_CONFIG_SION); - is_gigabit = !(readl(GPIO4_BASE_ADDR) & BIT(10)); - clrbits_le32(mux, IOMUX_CONFIG_SION); - - /* Test for non-default SoM with 100/Full PHY attached to FEC */ - if (is_gigabit) - return 0; - - /* Adjust FEC node for Fast LAN8740Ai PHY */ - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - if (mac_node < 0) - return 0; - - /* Optional PHY pointed to by phy-handle, possibly on carrier board */ - phy_node = fdtdec_lookup_phandle(blob, mac_node, "phy-handle"); - if (phy_node > 0) { - fdt_setprop_string(blob, phy_node, "status", "disabled"); - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - } - - mdio_node = fdt_first_subnode(blob, mac_node); - if (mdio_node < 0) - return 0; - - /* LAN8740Ai */ - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - if (lan_node < 0) - return 0; - - iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat); - if (iomuxc_node < 0) - return 0; - - /* - * The code below adjusts the following DT properties: - * - assigned-clock-parents .. 50 MHz RMII ref clock - * - assigned-clock-rates .... 50 MHz RMII ref clock - * - phy-handle .............. LAN8740Ai RMII - * - phy-mode ................ RMII - * - pinctrl-0 ............... RMII - * - PHY subnode status ...... "okay" for RMII PHY - */ - - /* Perform all inplace changes first, string changes last. */ - clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL); - if (!clk_prop) - return 0; - clk[0] = clk_prop[0]; - clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M); - clk[2] = clk_prop[2]; - clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M); - clk[4] = clk_prop[4]; - clk[5] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M); - clk[6] = clk_prop[6]; - clk[7] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents", - clk, 8 * sizeof(u32)); - - clk[0] = cpu_to_fdt32(0); - clk[1] = cpu_to_fdt32(100000000); - clk[2] = cpu_to_fdt32(50000000); - clk[3] = cpu_to_fdt32(0); - fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates", - clk, 4 * sizeof(u32)); - - handle = fdt_get_phandle(blob, lan_node); - fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle); - - fdt_for_each_subnode(subnode, blob, iomuxc_node) { - if (!strstr(fdt_get_name(blob, subnode, NULL), "fec-rmii")) - continue; - - handle = fdt_get_phandle(blob, subnode); - fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle); - break; - } - - fdt_setprop_string(blob, mac_node, "phy-mode", "rmii"); - mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat); - mdio_node = fdt_first_subnode(blob, mac_node); - lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat); - fdt_setprop_string(blob, lan_node, "status", "okay"); - - return 0; -} - -static int dh_dt_patch_som(const void *fdt_blob) -{ - int ret; - - /* Do nothing if not i.MX8MP DHCOM SoM */ - ret = fdt_node_check_compatible(fdt_blob, 0, "dh,imx8mp-dhcom-som"); - if (ret) - return 0; - - ret = dh_dt_patch_som_eqos(fdt_blob); - if (ret) - return ret; - - return dh_dt_patch_som_fec(fdt_blob); -} - -int fdtdec_board_setup(const void *fdt_blob) -{ - return dh_dt_patch_som(fdt_blob); -} diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index a8fda139aa4..1b05da53c35 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -22,6 +22,8 @@ #include <dm/uclass-internal.h> #include <dm/device-internal.h> +#include <linux/bitfield.h> + #include <power/pmic.h> #include <power/pca9450.h> @@ -41,6 +43,9 @@ static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; +static bool dh_gigabit_eqos, dh_gigabit_fec; +static u8 dh_som_rev; + static void dh_imx8mp_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; @@ -144,6 +149,61 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) return BOOT_DEVICE_BOOTROM; } +int board_spl_fit_append_fdt_skip(const char *name) +{ + if (!dh_gigabit_eqos) { /* 1x or 2x RMII PHY SoM */ + if (dh_gigabit_fec) { /* 1x RMII PHY SoM */ + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth1xfast")) + return 0; + } else { /* 2x RMII PHY SoM */ + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-eth2xfast")) + return 0; + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk-overlay-eth2xfast")) { + /* 2x RMII PHY SoM on PDK2 or PDK3 */ + if (of_machine_is_compatible("dh,imx8mp-dhcom-pdk2") || + of_machine_is_compatible("dh,imx8mp-dhcom-pdk3")) + return 0; + } + } + } + + if (dh_som_rev == 0x0) { /* Prototype SoM rev.100 */ + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-som-overlay-rev100")) + return 0; + + if (!strcmp(name, "fdt-dto-imx8mp-dhcom-pdk3-overlay-rev100") && + of_machine_is_compatible("dh,imx8mp-dhcom-pdk3")) + return 0; + } + + return 1; /* Skip this DTO */ +} + +static void dh_imx8mp_board_cache_config(void) +{ + const void __iomem *mux_base = (void __iomem *)IOMUXC_BASE_ADDR; + const u32 mux_sion[] = { + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_NAND_DQS__GPIO3_IO14), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXD7__GPIO4_IO19), + FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI5_MCLK__GPIO3_IO25), + }; + int i; + + for (i = 0; i < ARRAY_SIZE(mux_sion); i++) + setbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION); + + dh_gigabit_eqos = !(readl(GPIO1_BASE_ADDR) & BIT(24)); + dh_gigabit_fec = !(readl(GPIO4_BASE_ADDR) & BIT(10)); + dh_som_rev = !!(readl(GPIO3_BASE_ADDR) & BIT(14)); + dh_som_rev |= !!(readl(GPIO4_BASE_ADDR) & BIT(19)) << 1; + dh_som_rev |= !!(readl(GPIO3_BASE_ADDR) & BIT(25)) << 2; + + for (i = 0; i < ARRAY_SIZE(mux_sion); i++) + clrbits_le32(mux_base + mux_sion[i], IOMUX_CONFIG_SION); +} + void board_init_f(ulong dummy) { struct udevice *dev; @@ -181,5 +241,7 @@ void board_init_f(ulong dummy) /* DDR initialization */ spl_dram_init(); + dh_imx8mp_board_cache_config(); + board_init_r(NULL, 0); } diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c index e73a498733b..f4297f8fd4d 100644 --- a/board/freescale/imx93_evk/imx93_evk.c +++ b/board/freescale/imx93_evk/imx93_evk.c @@ -33,8 +33,6 @@ int board_early_init_f(void) { imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - init_uart_clk(LPUART1_CLK_ROOT); - return 0; } diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 774a99041c8..31a23504175 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -159,9 +159,9 @@ static int power_init_board(void) } else if (!strncmp(model, "GW74", 4)) { - ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + ret = uclass_get_device_by_seq(UCLASS_I2C, 2, &bus); if (ret) { - printf("PMIC : failed I2C1 probe: %d\n", ret); + printf("PMIC : failed I2C3 probe: %d\n", ret); return ret; } ret = dm_i2c_probe(bus, 0x25, 0, &dev); diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig new file mode 100644 index 00000000000..3b1c5aa0d02 --- /dev/null +++ b/board/phytec/common/Kconfig @@ -0,0 +1,13 @@ +config PHYTEC_SOM_DETECTION + bool "Support SoM detection for PHYTEC platforms" + select SPL_CRC8 if SPL + help + Support of I2C EEPROM based SoM detection. + +config PHYTEC_IMX8M_SOM_DETECTION + bool "Support SoM detection for i.MX8M PHYTEC platforms" + depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION + default y + help + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC i.MX8MM/i.MX8MP boards diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile new file mode 100644 index 00000000000..fe28964ce21 --- /dev/null +++ b/board/phytec/common/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Author: Teresa Remmet <t.remmet@phytec.de> + +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +endif + +obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o +obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c new file mode 100644 index 00000000000..c6c96ed19cb --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <u-boot/crc.h> + +#include "imx8m_som_detection.h" + +extern struct phytec_eeprom_data eeprom_data; + +/* Check if the SoM is actually one of the following products: + * - i.MX8MM + * - i.MX8MN + * - i.MX8MP + * - i.MX8MQ + * + * Returns 0 in case it's a known SoM. Otherwise, returns -1. + */ +u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + char *opt; + u8 som; + + /* We can not do the check for early API revisions */ + if (data->api_rev < PHYTEC_API_REV2) + return -1; + + if (!data) + data = &eeprom_data; + + som = data->data.data_api2.som_no; + debug("%s: som id: %u\n", __func__, som); + + opt = phytec_get_opt(data); + if (!opt) + return -1; + + if (som == PHYTEC_IMX8MP_SOM && is_imx8mp()) + return 0; + + if (som == PHYTEC_IMX8MM_SOM) { + if ((PHYTEC_GET_OPTION(opt[0]) != 0) && + (PHYTEC_GET_OPTION(opt[1]) == 0) && is_imx8mm()) + return 0; + else if ((PHYTEC_GET_OPTION(opt[0]) == 0) && + (PHYTEC_GET_OPTION(opt[1]) != 0) && is_imx8mn()) + return 0; + } + + if (som == PHYTEC_IMX8MQ_SOM && is_imx8mq()) + return 0; + + pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); + return -1; +} + +/* + * All PHYTEC i.MX8M boards have RAM size definition at the + * same location. + */ +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + char *opt; + u8 ddr_id; + + if (!data) + data = &eeprom_data; + + opt = phytec_get_opt(data); + if (opt) + ddr_id = PHYTEC_GET_OPTION(opt[2]); + else + ddr_id = PHYTEC_EEPROM_INVAL; + + debug("%s: ddr id: %u\n", __func__, ddr_id); + return ddr_id; +} + +/* + * Filter SPI-NOR flash information. All i.MX8M boards have this at + * the same location. + * returns: 0x0 if no SPI is populated. Otherwise a board depended + * code for the size. PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + char *opt; + u8 spi; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) + spi = PHYTEC_GET_OPTION(opt[4]); + else + spi = PHYTEC_EEPROM_INVAL; + + debug("%s: spi: %u\n", __func__, spi); + return spi; +} + +/* + * Filter ethernet phy information. All i.MX8M boards have this at + * the same location. + * returns: 0x0 if no ethernet phy is populated. 0x1 if it is populated. + * PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + char *opt; + u8 eth; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) { + eth = PHYTEC_GET_OPTION(opt[5]); + eth &= 0x1; + } else { + eth = PHYTEC_EEPROM_INVAL; + } + + debug("%s: eth: %u\n", __func__, eth); + return eth; +} + +/* + * Filter RTC information for phyCORE-i.MX8MP. + * returns: 0 if no RTC is populated. 1 if it is populated. + * PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + char *opt; + u8 rtc; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) { + rtc = PHYTEC_GET_OPTION(opt[5]); + rtc &= 0x4; + rtc = !(rtc >> 2); + } else { + rtc = PHYTEC_EEPROM_INVAL; + } + debug("%s: rtc: %u\n", __func__, rtc); + return rtc; +} diff --git a/board/phytec/common/imx8m_som_detection.h b/board/phytec/common/imx8m_som_detection.h new file mode 100644 index 00000000000..88d3037bf36 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#ifndef _PHYTEC_IMX8M_SOM_DETECTION_H +#define _PHYTEC_IMX8M_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX8MQ_SOM 66 +#define PHYTEC_IMX8MM_SOM 69 +#define PHYTEC_IMX8MP_SOM 70 + +#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) + +u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data); + +#else + +inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + return -1; +} + +inline u8 __maybe_unused +phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */ + +#endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */ diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c new file mode 100644 index 00000000000..55562731270 --- /dev/null +++ b/board/phytec/common/phytec_som_detection.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#include <common.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <u-boot/crc.h> + +#include "phytec_som_detection.h" + +struct phytec_eeprom_data eeprom_data; + +int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, int addr_fallback) +{ + int ret; + + ret = phytec_eeprom_data_init(data, bus_num, addr); + if (ret) { + pr_err("%s: init failed. Trying fall back address 0x%x\n", + __func__, addr_fallback); + ret = phytec_eeprom_data_init(data, bus_num, addr_fallback); + } + + if (ret) + pr_err("%s: EEPROM data init failed\n", __func__); + + return ret; +} + +int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret; + + ret = phytec_eeprom_data_init(data, bus_num, addr); + if (ret) + pr_err("%s: EEPROM data init failed\n", __func__); + + return ret; +} + +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + unsigned int crc; + int *ptr; + + if (!data) + data = &eeprom_data; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); + if (ret) { + pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); + return ret; + } + + ret = dm_i2c_read(dev, 0, (uint8_t *)data, + sizeof(struct phytec_eeprom_data)); + if (ret) { + pr_err("%s: Unable to read EEPROM data\n", __func__); + return ret; + } +#else + i2c_set_bus_num(bus_num); + ret = i2c_read(addr, 0, 2, (uint8_t *)data, + sizeof(struct phytec_eeprom_data)); +#endif + + if (data->api_rev == 0xff) { + pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); + return -EINVAL; + } + + ptr = (int *)data; + for (i = 0; i < sizeof(struct phytec_eeprom_data); i += sizeof(ptr)) + if (*ptr != 0x0) + break; + + if (i == sizeof(struct phytec_eeprom_data)) { + pr_err("%s: EEPROM data is all zero. Erased?\n", __func__); + return -EINVAL; + } + + /* We are done here for early revisions */ + if (data->api_rev <= PHYTEC_API_REV1) + return 0; + + crc = crc8(0, (const unsigned char *)data, + sizeof(struct phytec_eeprom_data)); + debug("%s: crc: %x\n", __func__, crc); + + if (crc) { + pr_err("%s: CRC mismatch. EEPROM data is not usable\n", + __func__); + return -EINVAL; + } + + return 0; +} + +void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) +{ + struct phytec_api2_data *api2; + char pcb_sub_rev; + unsigned int ksp_no, sub_som_type1, sub_som_type2; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return; + + api2 = &data->data.data_api2; + + /* Calculate PCB subrevision */ + pcb_sub_rev = api2->pcb_sub_opt_rev & 0x0f; + pcb_sub_rev = pcb_sub_rev ? ((pcb_sub_rev - 1) + 'a') : ' '; + + /* print standard product string */ + if (api2->som_type <= 1) { + printf("SoM: %s-%03u-%s.%s PCB rev: %u%c\n", + phytec_som_type_str[api2->som_type], api2->som_no, + api2->opt, api2->bom_rev, api2->pcb_rev, pcb_sub_rev); + return; + } + /* print KSP/KSM string */ + if (api2->som_type <= 3) { + ksp_no = (api2->ksp_no << 8) | api2->som_no; + printf("SoM: %s-%u ", + phytec_som_type_str[api2->som_type], ksp_no); + /* print standard product based KSP/KSM strings */ + } else { + switch (api2->som_type) { + case 4: + sub_som_type1 = 0; + sub_som_type2 = 3; + break; + case 5: + sub_som_type1 = 0; + sub_som_type2 = 2; + break; + case 6: + sub_som_type1 = 1; + sub_som_type2 = 3; + break; + case 7: + sub_som_type1 = 1; + sub_som_type2 = 2; + break; + default: + break; + }; + + printf("SoM: %s-%03u-%s-%03u ", + phytec_som_type_str[sub_som_type1], + api2->som_no, phytec_som_type_str[sub_som_type2], + api2->ksp_no); + } + + printf("Option: %s BOM rev: %s PCB rev: %u%c\n", api2->opt, + api2->bom_rev, api2->pcb_rev, pcb_sub_rev); +} + +char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) +{ + char *opt; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + opt = data->data.data_api0.opt; + else + opt = data->data.data_api2.opt; + + return opt; +} + +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) +{ + struct phytec_api2_data *api2; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + api2 = &data->data.data_api2; + + return api2->pcb_rev; +} diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h new file mode 100644 index 00000000000..c68e2302cc4 --- /dev/null +++ b/board/phytec/common/phytec_som_detection.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet <t.remmet@phytec.de> + */ + +#ifndef _PHYTEC_SOM_DETECTION_H +#define _PHYTEC_SOM_DETECTION_H + +#define PHYTEC_MAX_OPTIONS 17 +#define PHYTEC_EEPROM_INVAL 0xff + +#define PHYTEC_GET_OPTION(option) \ + (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') + +enum { + PHYTEC_API_REV0 = 0, + PHYTEC_API_REV1, + PHYTEC_API_REV2, +}; + +static const char * const phytec_som_type_str[] = { + "PCM", + "PCL", + "KSM", + "KSP", +}; + +struct phytec_api0_data { + u8 pcb_rev; /* PCB revision of SoM */ + u8 som_type; /* SoM type */ + u8 ksp_no; /* KSP no */ + char opt[16]; /* SoM options */ + u8 mac[6]; /* MAC address (optional) */ + u8 pad[5]; /* padding */ + u8 cksum; /* checksum */ +} __packed; + +struct phytec_api2_data { + u8 pcb_rev; /* PCB revision of SoM */ + u8 pcb_sub_opt_rev; /* PCB subrevision and opt revision */ + u8 som_type; /* SoM type */ + u8 som_no; /* SoM number */ + u8 ksp_no; /* KSP information */ + char opt[PHYTEC_MAX_OPTIONS]; /* SoM options */ + char bom_rev[2]; /* BOM revision */ + u8 mac[6]; /* MAC address (optional) */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_eeprom_data { + u8 api_rev; + union { + struct phytec_api0_data data_api0; + struct phytec_api2_data data_api2; + } data; +} __packed; + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + +int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, + int addr_fallback); +int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr); +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr); +void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data); + +char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data); + +#else + +inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, + int addr_fallback) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) +{ +} + +inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) +{ + return NULL; +} + +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} +#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */ + +#endif /* _PHYTEC_SOM_DETECTION_H */ diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index c053a46fc9d..f846d10bad9 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,4 +12,5 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index e59dd74377c..f2707b85960 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -13,63 +13,68 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x323 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, - { 0x3d4000e0, 0x330000 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0xf10000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, + { 0x3d400190, 0x49b820a }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, + { 0x3d4001b4, 0x1b0a }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, + { 0x3d400108, 0x7101817 }, { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400250, 0x1f05 }, - { 0x3d400254, 0x1f }, - { 0x3d400264, 0x90003ff }, - { 0x3d40026c, 0x20003ff }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x1000e00 }, - { 0x3d400498, 0x3ff0000 }, - { 0x3d40049c, 0x1000e00 }, - { 0x3d4004a0, 0x3ff0000 }, - { 0x3d402020, 0x21 }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d040 }, + { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -89,12 +94,12 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x21 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d040 }, + { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -137,12 +142,12 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, { 0x130a2, 0x2 }, @@ -185,7 +190,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x18 }, + { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -194,11 +199,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, + { 0x20024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, + { 0x120024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, + { 0x220024, 0x1a3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -264,7 +269,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x3e8 }, + { 0x20008, 0x2ee }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -310,19 +315,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, }; @@ -1052,7 +1053,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1061,26 +1062,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1102,25 +1103,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1142,25 +1143,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1171,37 +1172,36 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1629,67 +1629,58 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x478 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1699,15 +1690,16 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x7d }, - { 0x2000c, 0xfa }, - { 0x2000d, 0x9c4 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1804,8 +1796,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 4000mts 1D */ - .drate = 4000, + /* P0 3000mts 1D */ + .drate = 3000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1817,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 4000mts 2D */ - .drate = 4000, + /* P0 3000mts 2D */ + .drate = 3000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1837,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, + .fsp_table = { 3000, 400, 100, }, }; diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index faed6fc3b76..d38f6368fe3 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -21,8 +21,13 @@ #include <power/pca9450.h> #include <spl.h> +#include "../common/imx8m_som_detection.h" + DECLARE_GLOBAL_DATA_PTR; +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 + int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -30,6 +35,79 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) void spl_dram_init(void) { + int ret; + + ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, + EEPROM_ADDR_FALLBACK); + if (ret) + goto out; + + ret = phytec_imx8m_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + + ret = phytec_get_rev(NULL); + if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) { + dram_timing.ddrc_cfg[3].val = 0x1323; + dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000; + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; + } + +out: ddr_init(&dram_timing); } diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c index 7b2c50a61e4..345191b31c2 100644 --- a/board/storopack/smegw01/smegw01.c +++ b/board/storopack/smegw01/smegw01.c @@ -111,18 +111,3 @@ uint mmc_get_env_part(struct mmc *mmc) return part; } -enum env_location env_get_location(enum env_operation op, int prio) -{ - if (op == ENVOP_SAVE || op == ENVOP_ERASE) - return ENVL_MMC; - - switch (prio) { - case 0: - return ENVL_NOWHERE; - - case 1: - return ENVL_MMC; - } - - return ENVL_UNKNOWN; -} diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 119e67b47f7..f0356af0082 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -53,6 +53,11 @@ DECLARE_GLOBAL_DATA_PTR; #define USB_CDET_GPIO IMX_GPIO_NR(7, 14) +#define FLASH_DETECTION_CTRL (PAD_CTL_HYS | PAD_CTL_PUE) +#define FLASH_DET_GPIO IMX_GPIO_NR(6, 11) + +static bool is_emmc; + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size()); @@ -60,6 +65,10 @@ int dram_init(void) return 0; } +static iomux_v3_cfg_t const flash_detection_pads[] = { + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL), +}; + static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -183,6 +192,16 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + /* + * Enable GPIO on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST + * is pulled high with 4.7k for eMMC devices. This allows to reliably + * detect eMMC/NAND flash + */ + imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads)); + gpio_request(FLASH_DET_GPIO, "flash-detection-gpio"); + is_emmc = gpio_get_value(FLASH_DET_GPIO); + gpio_free(FLASH_DET_GPIO); + #ifdef CONFIG_FEC_MXC setup_fec(); #endif @@ -348,6 +367,11 @@ int board_late_init(void) env_set("bootcmd", "sdp 0"); } #endif + if (is_emmc) + env_set("variant", "-emmc"); + else + env_set("variant", ""); + return 0; } #endif /* CONFIG_BOARD_LATE_INIT */ diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c index d114abf9d67..4dfec679b11 100644 --- a/board/toradex/verdin-imx8mm/lpddr4_timing.c +++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c @@ -1,12 +1,11 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2020 Toradex + * Copyright 2023 Toradex * * Generated code from MX8M_DDR_tool - * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga * - * DDR calibration created with mscale_ddr_tool_v210_setup.exe using - * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019. + * DDR calibration created with mscale_ddr_tool_v3.31_setup.exe using + * MX8M_Mini_LPDDR4_RPA_v22 Verdin iMX8MM V1.0.xlsx as of 7. Aug. 2023. */ #include <linux/kernel.h> @@ -17,22 +16,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400304, 0x1}, {0x3d400030, 0x1}, {0x3d400000, 0xa1080020}, - {0x3d400020, 0x203}, + {0x3d400020, 0x202}, {0x3d400024, 0x3a980}, - {0x3d400064, 0x5b00d2}, + {0x3d400064, 0x2d00d2}, {0x3d4000d0, 0xc00305ba}, {0x3d4000d4, 0x940000}, {0x3d4000dc, 0xd4002d}, {0x3d4000e0, 0x310000}, {0x3d4000e8, 0x66004d}, {0x3d4000ec, 0x16004d}, - {0x3d400100, 0x191e1920}, + {0x3d400100, 0x191e0c20}, {0x3d400104, 0x60630}, {0x3d40010c, 0xb0b000}, {0x3d400110, 0xe04080e}, {0x3d400114, 0x2040c0c}, {0x3d400118, 0x1010007}, - {0x3d40011c, 0x401}, + {0x3d40011c, 0x402}, {0x3d400130, 0x20600}, {0x3d400134, 0xc100002}, {0x3d400138, 0xd8}, @@ -49,7 +48,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d4001b0, 0x11}, {0x3d4001c0, 0x1}, {0x3d4001c4, 0x1}, - {0x3d4000f4, 0xc99}, + {0x3d4000f4, 0x699}, {0x3d400108, 0x70e1617}, {0x3d400200, 0x1f}, {0x3d40020c, 0x0}, @@ -57,6 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400204, 0x80808}, {0x3d400214, 0x7070707}, {0x3d400218, 0x7070707}, + {0x3d40021c, 0xf0f}, {0x3d400250, 0x29001701}, {0x3d400254, 0x2c}, {0x3d40025c, 0x4000030}, @@ -68,22 +68,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d400498, 0x620096}, {0x3d40049c, 0x1100e07}, {0x3d4004a0, 0xc8012c}, - {0x3d402020, 0x1}, + {0x3d402020, 0x0}, {0x3d402024, 0x7d00}, {0x3d402050, 0x20d040}, - {0x3d402064, 0xc001c}, + {0x3d402064, 0x6001c}, {0x3d4020dc, 0x840000}, {0x3d4020e0, 0x310000}, {0x3d4020e8, 0x66004d}, {0x3d4020ec, 0x16004d}, - {0x3d402100, 0xa040305}, + {0x3d402100, 0xa040105}, {0x3d402104, 0x30407}, {0x3d402108, 0x203060b}, {0x3d40210c, 0x505000}, {0x3d402110, 0x2040202}, {0x3d402114, 0x2030202}, {0x3d402118, 0x1010004}, - {0x3d40211c, 0x301}, + {0x3d40211c, 0x302}, {0x3d402130, 0x20300}, {0x3d402134, 0xa100002}, {0x3d402138, 0x1d}, @@ -92,8 +92,8 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d402190, 0x3818200}, {0x3d402194, 0x80303}, {0x3d4021b4, 0x100}, - {0x3d4020f4, 0xc99}, - {0x3d403020, 0x1}, + {0x3d4020f4, 0x599}, + {0x3d403020, 0x0}, {0x3d403024, 0x1f40}, {0x3d403050, 0x20d040}, {0x3d403064, 0x30007}, @@ -108,7 +108,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403110, 0x2040202}, {0x3d403114, 0x2030202}, {0x3d403118, 0x1010004}, - {0x3d40311c, 0x301}, + {0x3d40311c, 0x302}, {0x3d403130, 0x20300}, {0x3d403134, 0xa100002}, {0x3d403138, 0x8}, @@ -117,7 +117,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { {0x3d403190, 0x3818200}, {0x3d403194, 0x80303}, {0x3d4031b4, 0x100}, - {0x3d4030f4, 0xc99}, + {0x3d4030f4, 0x599}, {0x3d400028, 0x0}, }; @@ -205,8 +205,8 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { {0x220024, 0x1ab}, {0x2003a, 0x0}, {0x20056, 0x3}, - {0x120056, 0xa}, - {0x220056, 0xa}, + {0x120056, 0x3}, + {0x220056, 0x3}, {0x1004d, 0xe00}, {0x1014d, 0xe00}, {0x1104d, 0xe00}, @@ -1058,7 +1058,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { {0x54008, 0x131f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x2dd4}, {0x5401a, 0x31}, @@ -1098,7 +1097,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1138,7 +1136,6 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { {0x54008, 0x121f}, {0x54009, 0xc8}, {0x5400b, 0x2}, - {0x5400d, 0x100}, {0x54012, 0x110}, {0x54019, 0x84}, {0x5401a, 0x31}, @@ -1204,7 +1201,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { {0x5403b, 0x4d}, {0x5403c, 0x4d}, {0x5403d, 0x1600}, - { 0xd0000, 0x1 }, + {0xd0000, 0x1}, }; /* DRAM PHY init engine image */ @@ -1697,15 +1694,15 @@ struct dram_cfg_param ddr_phy_pie[] = { {0x400d6, 0x20a}, {0x400d7, 0x20b}, {0x2003a, 0x2}, - {0x2000b, 0x5d}, + {0x2000b, 0x34b}, {0x2000c, 0xbb}, {0x2000d, 0x753}, {0x2000e, 0x2c}, - {0x12000b, 0xc}, + {0x12000b, 0x70}, {0x12000c, 0x19}, {0x12000d, 0xfa}, {0x12000e, 0x10}, - {0x22000b, 0x3}, + {0x22000b, 0x1c}, {0x22000c, 0x6}, {0x22000d, 0x3e}, {0x22000e, 0x10}, @@ -1846,5 +1843,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = {3000, 400, 100,}, }; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index ce6b8aa370a..1409b926372 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -372,6 +372,11 @@ static bool os_takes_devicetree(uint8_t os) } } +__weak int board_spl_fit_append_fdt_skip(const char *name) +{ + return 0; /* Do not skip */ +} + static int spl_fit_append_fdt(struct spl_image_info *spl_image, struct spl_load_info *info, ulong sector, const struct spl_fit_info *ctx) @@ -414,11 +419,23 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, void *tmpbuffer = NULL; for (; ; index++) { - node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index); - if (node == -E2BIG) { + const char *str; + + ret = spl_fit_get_image_name(ctx, FIT_FDT_PROP, index, &str); + if (ret == -E2BIG) { debug("%s: No additional FDT node\n", __func__); + ret = 0; break; - } else if (node < 0) { + } else if (ret < 0) { + continue; + } + + ret = board_spl_fit_append_fdt_skip(str); + if (ret) + continue; + + node = fdt_subnode_offset(ctx->fit, ctx->images_node, str); + if (node < 0) { debug("%s: unable to find FDT node %d\n", __func__, index); continue; diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 71c86b1a670..01cfb96b0ee 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -75,7 +75,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904" +CONFIG_OF_LIST="imx8mm-venice imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x imx8mm-venice-gw7901 imx8mm-venice-gw7902 imx8mm-venice-gw7903 imx8mm-venice-gw7904 imx8mm-venice-gw7905-0x" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 diff --git a/configs/imx8mp_dhcom_pdk3_defconfig b/configs/imx8mp_dhcom_pdk3_defconfig index b617f74321c..c20273ec944 100644 --- a/configs/imx8mp_dhcom_pdk3_defconfig +++ b/configs/imx8mp_dhcom_pdk3_defconfig @@ -15,7 +15,6 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk3" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y -CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SPL_MMC=y @@ -39,6 +38,7 @@ CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000 +CONFIG_SPL_LOAD_FIT_APPLY_OVERLAY=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_BOOTARGS=y @@ -64,6 +64,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x4c000000 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +# CONFIG_SPL_FIT_IMAGE_TINY is not set CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y @@ -261,3 +262,4 @@ CONFIG_USB_FUNCTION_ACM=y CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_IMX_WATCHDOG=y +CONFIG_DM_PCA953X=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 14c749f4430..820dc36e9cd 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -59,6 +59,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -74,6 +77,14 @@ CONFIG_ETHPRIME="eth1" CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=2 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y @@ -94,10 +105,15 @@ CONFIG_DWC_ETH_QOS=y CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PHY_IMX8MQ_USB=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y @@ -109,4 +125,19 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_MX7 is not set +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_SDP_LOADADDR=0x0 CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 25f34b85da5..730c359779a 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -77,7 +77,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x" +CONFIG_OF_LIST="imx8mp-venice imx8mp-venice-gw71xx-2x imx8mp-venice-gw72xx-2x imx8mp-venice-gw73xx-2x imx8mp-venice-gw74xx imx8mp-venice-gw7905-2x" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_DEV=2 diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 3b5c7bd65a4..7c8fd0c665a 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -82,6 +82,8 @@ CONFIG_SPL_DM=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_ADC_IMX93=y +CONFIG_SPL_CLK_IMX93=y +CONFIG_CLK_IMX93=y CONFIG_CPU=y CONFIG_CPU_IMX=y CONFIG_IMX_RGPIO2P=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index df0cceaea71..4058d08f961 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_CMD_EXT4=y @@ -65,3 +66,11 @@ CONFIG_RTC_MXS=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MAX_CONTROLLER_COUNT=2 +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 26e68d30d26..1c8105f44f2 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -73,6 +73,8 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SOFT_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y @@ -85,4 +87,5 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_IMX_WATCHDOG=y CONFIG_ERRNO_STR=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 32845fd19f2..46efe181c37 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 613ed6cc94a..b598d8a6b7d 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 82d70c7f37a..93ef6b59132 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 289cf6ba7c1..18fb5d2514d 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -24,6 +24,7 @@ CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run distro_bootcmd" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index dbe4c5245b4..44caa8e2c61 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 613ed6cc94a..b598d8a6b7d 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index c5e34219ece..48364c7548e 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -22,6 +22,7 @@ CONFIG_BOARD_SIZE_LIMIT=715776 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" +# CONFIG_CONSOLE_MUX is not set CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index 5cfd3d2715d..9f2cac73b8f 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -48,7 +48,6 @@ CONFIG_CMD_SQUASHFS=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_NOWHERE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 @@ -82,5 +81,8 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y # CONFIG_CMD_BOOTEFI_BOOTMGR is not set diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 66c969f95e5..277f055aef2 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -29,7 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="usbarmory" -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y @@ -39,6 +39,7 @@ CONFIG_PINCTRL_IMX5=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_EHCI_MX5=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 392a582092f..7644471356e 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -69,6 +69,8 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_READ=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_BOOTCOUNT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -97,6 +99,12 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_GPIO_HOG=y CONFIG_SPL_GPIO_HOG=y CONFIG_MXC_GPIO=y @@ -120,6 +128,8 @@ CONFIG_PHY_FIXED=y CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_SPL_PHY=y +CONFIG_SPL_NOP_PHY=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y @@ -139,8 +149,18 @@ CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_TMU=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y CONFIG_HEXDUMP=y diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh index 65c143073cb..cd3b2614a2f 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf.sh +++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh @@ -75,5 +75,18 @@ dd if=ivt.bin of=flash.bin bs=1 seek=${ivt_block_offset} conv=notrunc # Generate CSF blob cst -i csf_fit.tmp -o csf_fit.bin + +# When loading flash.bin via USB, we must ensure that the file being +# served is as large as the target expects (see +# board_spl_fit_size_align()), otherwise the target will hang in +# rom_api_download_image() waiting for the remaining bytes. +# +# Note that in order for dd to actually extend the file, one must not +# pass conv=notrunc here. With a non-zero seek= argument, dd is +# documented to preserve the contents of the file seeked past; in +# particular, dd does not open the file with O_TRUNC. +CSF_SIZE=$(sed -n "/CONFIG_CSF_SIZE=/ s@.*=@@p" .config) +dd if=/dev/null of=csf_fit.bin bs=1 seek=$((CSF_SIZE - 0x20)) count=0 + # Patch CSF blob into flash.bin dd if=csf_fit.bin of=flash.bin bs=1 seek=${csf_block_offset} conv=notrunc diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt index 3d79edf2813..97f3eea573b 100644 --- a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt @@ -27,4 +27,4 @@ Verification index = 2 # FIXME: # Line 1 -- fitImage - Blocks = 0x401fcdc0 0x57c00 0xffff "flash.bin" + Blocks = CONFIG_SPL_LOAD_FIT_ADDRESS 0x57c00 0xffff "flash.bin" diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index abcb19ce6d5..56d893e0579 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -89,6 +89,24 @@ config CLK_IMX8MQ help This enables support clock driver for i.MX8MQ platforms. +config SPL_CLK_IMX93 + bool "SPL clock support for i.MX93" + depends on ARCH_IMX9 && SPL + select SPL_CLK + select SPL_CLK_CCF + select SPL_CLK_COMPOSITE_CCF + help + This enables SPL DM/DTS support for clock driver in i.MX93 + +config CLK_IMX93 + bool "Clock support for i.MX93" + depends on ARCH_IMX9 + select CLK + select CLK_CCF + select CLK_COMPOSITE_CCF + help + This enables support for clock driver in i.MX93 + config SPL_CLK_IMXRT1020 bool "SPL clock support for i.MXRT1020" depends on ARCH_IMXRT && SPL diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index b9c197f952e..6d4bcd35714 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -18,6 +18,8 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ clk-composite-8m.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \ clk-composite-8m.o +obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \ + clk-gate-93.o clk-composite-93.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c new file mode 100644 index 00000000000..6d71c0c03ff --- /dev/null +++ b/drivers/clk/imx/clk-composite-93.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ +#include <common.h> +#include <log.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <linux/iopoll.h> +#include <linux/clk-provider.h> +#include <clk.h> +#include "clk.h" +#include <linux/err.h> + +#define TIMEOUT_US 500U + +#define CCM_DIV_SHIFT 0 +#define CCM_DIV_WIDTH 8 +#define CCM_MUX_SHIFT 8 +#define CCM_MUX_MASK 3 +#define CCM_OFF_SHIFT 24 +#define CCM_BUSY_SHIFT 28 + +#define STAT_OFFSET 0x4 +#define AUTHEN_OFFSET 0x30 +#define TZ_NS_SHIFT 9 +#define TZ_NS_MASK BIT(9) + +#define WHITE_LIST_SHIFT 16 + +#define readl_poll_timeout_atomic readl_poll_timeout + +static int imx93_clk_composite_wait_ready(struct clk *clk, void __iomem *reg) +{ + int ret; + u32 val; + + ret = readl_poll_timeout_atomic(reg + STAT_OFFSET, val, !(val & BIT(CCM_BUSY_SHIFT)), + TIMEOUT_US); + if (ret) + pr_err("Slice[%s] busy timeout\n", "TODO"); + + return ret; +} + +static void imx93_clk_composite_gate_endisable(struct clk *clk, int enable) +{ + struct clk_gate *gate = to_clk_gate(clk); + u32 reg; + + reg = readl(gate->reg); + + if (enable) + reg &= ~BIT(gate->bit_idx); + else + reg |= BIT(gate->bit_idx); + + writel(reg, gate->reg); + + imx93_clk_composite_wait_ready(clk, gate->reg); +} + +static int imx93_clk_composite_gate_enable(struct clk *clk) +{ + imx93_clk_composite_gate_endisable(clk, 1); + + return 0; +} + +static int imx93_clk_composite_gate_disable(struct clk *clk) +{ + imx93_clk_composite_gate_endisable(clk, 0); + + return 0; +} + +static const struct clk_ops imx93_clk_composite_gate_ops = { + .enable = imx93_clk_composite_gate_enable, + .disable = imx93_clk_composite_gate_disable, +}; + +struct clk *imx93_clk_composite_flags(const char *name, + const char * const *parent_names, + int num_parents, void __iomem *reg, u32 domain_id, + unsigned long flags) +{ + struct clk *clk = ERR_PTR(-ENOMEM); + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + goto fail; + + mux->reg = reg; + mux->shift = CCM_MUX_SHIFT; + mux->mask = CCM_MUX_MASK; + mux->num_parents = num_parents; + mux->parent_names = parent_names; + mux->flags = flags; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + goto fail; + + div->reg = reg; + div->shift = CCM_DIV_SHIFT; + div->width = CCM_DIV_WIDTH; + div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto fail; + + gate->reg = reg; + gate->bit_idx = CCM_OFF_SHIFT; + gate->flags = flags; + + clk = clk_register_composite(NULL, name, + parent_names, num_parents, + &mux->clk, &clk_mux_ops, + &div->clk, &clk_divider_ops, + &gate->clk, &imx93_clk_composite_gate_ops, + flags); + + if (IS_ERR(clk)) + goto fail; + + return clk; + +fail: + kfree(gate); + kfree(div); + kfree(mux); + return ERR_CAST(clk); +} diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c new file mode 100644 index 00000000000..9228f279e27 --- /dev/null +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/iopoll.h> +#include <clk.h> +#include <div64.h> + +#include "clk.h" + +#define UBOOT_DM_CLK_IMX_FRACN_GPPLL "imx_clk_fracn_gppll" + +#define PLL_CTRL 0x0 +#define HW_CTRL_SEL BIT(16) +#define CLKMUX_BYPASS BIT(2) +#define CLKMUX_EN BIT(1) +#define POWERUP_MASK BIT(0) + +#define PLL_ANA_PRG 0x10 +#define PLL_SPREAD_SPECTRUM 0x30 + +#define PLL_NUMERATOR 0x40 +#define PLL_MFN_MASK GENMASK(31, 2) + +#define PLL_DENOMINATOR 0x50 +#define PLL_MFD_MASK GENMASK(29, 0) + +#define PLL_DIV 0x60 +#define PLL_MFI_MASK GENMASK(24, 16) +#define PLL_RDIV_MASK GENMASK(15, 13) +#define PLL_ODIV_MASK GENMASK(7, 0) + +#define PLL_DFS_CTRL(x) (0x70 + (x) * 0x10) + +#define PLL_STATUS 0xF0 +#define LOCK_STATUS BIT(0) + +#define DFS_STATUS 0xF4 + +#define LOCK_TIMEOUT_US 200 + +#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) \ + { \ + .rate = (_rate), \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .mfd = (_mfd), \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + } + +#define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv) \ + { \ + .rate = (_rate), \ + .mfi = (_mfi), \ + .mfn = 0, \ + .mfd = 0, \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + } + +struct clk_fracn_gppll { + struct clk clk; + void __iomem *base; + const struct imx_fracn_gppll_rate_table *rate_table; + int rate_count; + u32 flags; +}; + +/* + * Fvco = (Fref / rdiv) * (MFI + MFN / MFD) + * Fout = Fvco / odiv + * The (Fref / rdiv) should be in range 20MHz to 40MHz + * The Fvco should be in range 2.5Ghz to 5Ghz + */ +static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { + PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), + PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), + PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), + PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), + PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), + PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), + PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), + PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), + PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12) +}; + +struct imx_fracn_gppll_clk imx_fracn_gppll = { + .rate_table = fracn_tbl, + .rate_count = ARRAY_SIZE(fracn_tbl), +}; + +/* + * Fvco = (Fref / rdiv) * MFI + * Fout = Fvco / odiv + * The (Fref / rdiv) should be in range 20MHz to 40MHz + * The Fvco should be in range 2.5Ghz to 5Ghz + */ +static const struct imx_fracn_gppll_rate_table int_tbl[] = { + PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2), + PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3), + PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4), +}; + +struct imx_fracn_gppll_clk imx_fracn_gppll_integer = { + .rate_table = int_tbl, + .rate_count = ARRAY_SIZE(int_tbl), +}; + +#define to_clk_fracn_gppll(_clk) container_of(_clk, struct clk_fracn_gppll, clk) + +static const struct imx_fracn_gppll_rate_table * +imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate) +{ + const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; + int i; + + for (i = 0; i < pll->rate_count; i++) + if (rate == rate_table[i].rate) + return &rate_table[i]; + + return NULL; +} + +static unsigned long clk_fracn_gppll_round_rate(struct clk *clk, unsigned long rate) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk); + const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; + int i; + + /* Assuming rate_table is in descending order */ + for (i = 0; i < pll->rate_count; i++) + if (rate >= rate_table[i].rate) + return rate_table[i].rate; + + /* return minimum supported value */ + return rate_table[pll->rate_count - 1].rate; +} + +static unsigned long clk_fracn_gppll_recalc_rate(struct clk *clk) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk); + const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; + u32 pll_numerator, pll_denominator, pll_div; + u32 mfi, mfn, mfd, rdiv, odiv; + u64 fvco = clk_get_parent_rate(clk); + long rate = 0; + int i; + + pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR); + mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator); + + pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR); + mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator); + + pll_div = readl_relaxed(pll->base + PLL_DIV); + mfi = FIELD_GET(PLL_MFI_MASK, pll_div); + + rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div); + odiv = FIELD_GET(PLL_ODIV_MASK, pll_div); + + /* + * Sometimes, the recalculated rate has deviation due to + * the frac part. So find the accurate pll rate from the table + * first, if no match rate in the table, use the rate calculated + * from the equation below. + */ + for (i = 0; i < pll->rate_count; i++) { + if (rate_table[i].mfn == mfn && rate_table[i].mfi == mfi && + rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv && + rate_table[i].odiv == odiv) + rate = rate_table[i].rate; + } + + if (rate) + return (unsigned long)rate; + + if (!rdiv) + rdiv = rdiv + 1; + + switch (odiv) { + case 0: + odiv = 2; + break; + case 1: + odiv = 3; + break; + default: + break; + } + + if (pll->flags & CLK_FRACN_GPPLL_INTEGER) { + /* Fvco = (Fref / rdiv) * MFI */ + fvco = fvco * mfi; + do_div(fvco, rdiv * odiv); + } else { + /* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */ + fvco = fvco * mfi * mfd + fvco * mfn; + do_div(fvco, mfd * rdiv * odiv); + } + + return (unsigned long)fvco; +} + +static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll) +{ + u32 val; + + return readl_poll_timeout(pll->base + PLL_STATUS, val, + val & LOCK_STATUS, LOCK_TIMEOUT_US); +} + +static ulong clk_fracn_gppll_set_rate(struct clk *clk, unsigned long drate) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk); + const struct imx_fracn_gppll_rate_table *rate; + u32 tmp, pll_div, ana_mfn; + int ret; + + rate = imx_get_pll_settings(pll, drate); + + /* Hardware control select disable. PLL is control by register */ + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~HW_CTRL_SEL; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + /* Disable output */ + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~CLKMUX_EN; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + /* Power Down */ + tmp &= ~POWERUP_MASK; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + /* Disable BYPASS */ + tmp &= ~CLKMUX_BYPASS; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | + FIELD_PREP(PLL_MFI_MASK, rate->mfi); + writel_relaxed(pll_div, pll->base + PLL_DIV); + if (pll->flags & CLK_FRACN_GPPLL_FRACN) { + writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR); + writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR); + } + + /* Wait for 5us according to fracn mode pll doc */ + udelay(5); + + /* Enable Powerup */ + tmp |= POWERUP_MASK; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + /* Wait Lock */ + ret = clk_fracn_gppll_wait_lock(pll); + if (ret) + return ret; + + /* Enable output */ + tmp |= CLKMUX_EN; + writel_relaxed(tmp, pll->base + PLL_CTRL); + + ana_mfn = readl_relaxed(pll->base + PLL_STATUS); + ana_mfn = FIELD_GET(PLL_MFN_MASK, ana_mfn); + + WARN(ana_mfn != rate->mfn, "ana_mfn != rate->mfn\n"); + + return 0; +} + +static int clk_fracn_gppll_prepare(struct clk *clk) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk); + u32 val; + int ret; + + val = readl_relaxed(pll->base + PLL_CTRL); + if (val & POWERUP_MASK) + return 0; + + val |= CLKMUX_BYPASS; + writel_relaxed(val, pll->base + PLL_CTRL); + + val |= POWERUP_MASK; + writel_relaxed(val, pll->base + PLL_CTRL); + + val |= CLKMUX_EN; + writel_relaxed(val, pll->base + PLL_CTRL); + + ret = clk_fracn_gppll_wait_lock(pll); + if (ret) + return ret; + + val &= ~CLKMUX_BYPASS; + writel_relaxed(val, pll->base + PLL_CTRL); + + return 0; +} + +static int clk_fracn_gppll_unprepare(struct clk *clk) +{ + struct clk_fracn_gppll *pll = to_clk_fracn_gppll(dev_get_clk_ptr(clk->dev)); + u32 val; + + val = readl_relaxed(pll->base + PLL_CTRL); + val &= ~POWERUP_MASK; + writel_relaxed(val, pll->base + PLL_CTRL); + + return 0; +} + +static const struct clk_ops clk_fracn_gppll_ops = { + .enable = clk_fracn_gppll_prepare, + .disable = clk_fracn_gppll_unprepare, + .get_rate = clk_fracn_gppll_recalc_rate, + .set_rate = clk_fracn_gppll_set_rate, + .round_rate = clk_fracn_gppll_round_rate, +}; + +static struct clk *_imx_clk_fracn_gppll(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk, + u32 pll_flags) +{ + struct clk_fracn_gppll *pll; + struct clk *clk; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + pll->rate_table = pll_clk->rate_table; + pll->rate_count = pll_clk->rate_count; + pll->flags = pll_flags; + + clk = &pll->clk; + + ret = clk_register(clk, UBOOT_DM_CLK_IMX_FRACN_GPPLL, + name, parent_name); + if (ret) { + pr_err("%s: failed to register pll %s %d\n", __func__, name, ret); + kfree(pll); + return ERR_PTR(ret); + } + + return clk; +} + +struct clk *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk) +{ + return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN); +} + +struct clk *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk) +{ + return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER); +} + +U_BOOT_DRIVER(clk_fracn_gppll) = { + .name = UBOOT_DM_CLK_IMX_FRACN_GPPLL, + .id = UCLASS_CLK, + .ops = &clk_fracn_gppll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c new file mode 100644 index 00000000000..bc857413713 --- /dev/null +++ b/drivers/clk/imx/clk-gate-93.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * Peng Fan <peng.fan@nxp.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <linux/bug.h> +#include <linux/clk-provider.h> +#include <clk.h> +#include "clk.h" +#include <linux/err.h> + +#define UBOOT_DM_CLK_IMX_GATE93 "imx_clk_gate93" + +#define DIRECT_OFFSET 0x0 + +/* + * 0b000 - LPCG will be OFF in any CPU mode. + * 0b100 - LPCG will be ON in any CPU mode. + */ +#define LPM_SETTING_OFF 0x0 +#define LPM_SETTING_ON 0x4 + +#define LPM_CUR_OFFSET 0x1c + +#define AUTHEN_OFFSET 0x30 +#define CPULPM_EN BIT(2) +#define TZ_NS_SHIFT 9 +#define TZ_NS_MASK BIT(9) + +#define WHITE_LIST_SHIFT 16 + +struct imx93_clk_gate { + struct clk clk; + void __iomem *reg; + u32 bit_idx; + u32 val; + u32 mask; + unsigned int *share_count; +}; + +#define to_imx93_clk_gate(_clk) container_of(_clk, struct imx93_clk_gate, clk) + +static void imx93_clk_gate_do_hardware(struct clk *clk, bool enable) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + u32 val; + + val = readl(gate->reg + AUTHEN_OFFSET); + if (val & CPULPM_EN) { + val = enable ? LPM_SETTING_ON : LPM_SETTING_OFF; + writel(val, gate->reg + LPM_CUR_OFFSET); + } else { + val = readl(gate->reg + DIRECT_OFFSET); + val &= ~(gate->mask << gate->bit_idx); + if (enable) + val |= (gate->val & gate->mask) << gate->bit_idx; + writel(val, gate->reg + DIRECT_OFFSET); + } +} + +static int imx93_clk_gate_enable(struct clk *clk) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + + if (gate->share_count && (*gate->share_count)++ > 0) + return 0; + + imx93_clk_gate_do_hardware(clk, true); + + return 0; +} + +static int imx93_clk_gate_disable(struct clk *clk) +{ + struct imx93_clk_gate *gate = to_imx93_clk_gate(clk); + + if (gate->share_count) { + if (WARN_ON(*gate->share_count == 0)) + return 0; + else if (--(*gate->share_count) > 0) + return 0; + } + + imx93_clk_gate_do_hardware(clk, false); + + return 0; +} + +static ulong imx93_clk_set_rate(struct clk *clk, ulong rate) +{ + struct clk *parent = clk_get_parent(clk); + + if (parent) + return clk_set_rate(parent, rate); + + return -ENODEV; +} + +static const struct clk_ops imx93_clk_gate_ops = { + .enable = imx93_clk_gate_enable, + .disable = imx93_clk_gate_disable, + .get_rate = clk_generic_get_rate, + .set_rate = imx93_clk_set_rate, +}; + +struct clk *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, + u32 mask, u32 domain_id, unsigned int *share_count) +{ + struct imx93_clk_gate *gate; + struct clk *clk; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + gate->reg = reg; + gate->bit_idx = bit_idx; + gate->val = val; + gate->mask = mask; + gate->share_count = share_count; + + clk = &gate->clk; + + ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE93, name, parent_name); + if (ret) { + kfree(gate); + return ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(clk_gate93) = { + .name = UBOOT_DM_CLK_IMX_GATE93, + .id = UCLASS_CLK, + .ops = &imx93_clk_gate_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c new file mode 100644 index 00000000000..ce10d795316 --- /dev/null +++ b/drivers/clk/imx/clk-imx93.c @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP. + */ + +#include <common.h> +#include <clk.h> +#include <clk-uclass.h> +#include <dm.h> +#include <log.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <dt-bindings/clock/imx93-clock.h> + +#include "clk.h" + +enum clk_sel { + LOW_SPEED_IO_SEL, + NON_IO_SEL, + FAST_SEL, + AUDIO_SEL, + VIDEO_SEL, + TPM_SEL, + CKO1_SEL, + CKO2_SEL, + MISC_SEL, + MAX_SEL +}; + +static u32 share_count_sai1; +static u32 share_count_sai2; +static u32 share_count_sai3; +static u32 share_count_mub; + +static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"}; +static const char *parent_names[MAX_SEL][4] = { + {"clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"}, + {"clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"}, + {"clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "sys_pll_pfd2"}, + {"clock-osc-24m", "audio_pll", "video_pll", "clk_ext1"}, + {"clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd0"}, + {"clock-osc-24m", "sys_pll_pfd0", "audio_pll", "clk_ext1"}, + {"clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "audio_pll"}, + {"clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "video_pll"}, + {"clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd2"}, +}; + +static const struct imx93_clk_root { + u32 clk; + char *name; + u32 off; + enum clk_sel sel; + unsigned long flags; +} root_array[] = { + /* a55/m33/bus critical clk for system run */ + { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, }, + { IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, }, + { IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, }, + { IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, }, + { IMX93_CLK_FLEXSPI1, "flexspi1_root", 0x0b00, FAST_SEL, }, + { IMX93_CLK_CAN1, "can1_root", 0x0b80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_CAN2, "can2_root", 0x0c00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART1, "lpuart1_root", 0x0c80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART2, "lpuart2_root", 0x0d00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART3, "lpuart3_root", 0x0d80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART4, "lpuart4_root", 0x0e00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART5, "lpuart5_root", 0x0e80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART6, "lpuart6_root", 0x0f00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART7, "lpuart7_root", 0x0f80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPUART8, "lpuart8_root", 0x1000, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C1, "lpi2c1_root", 0x1080, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C2, "lpi2c2_root", 0x1100, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C3, "lpi2c3_root", 0x1180, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C4, "lpi2c4_root", 0x1200, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C5, "lpi2c5_root", 0x1280, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C6, "lpi2c6_root", 0x1300, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C7, "lpi2c7_root", 0x1380, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPI2C8, "lpi2c8_root", 0x1400, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI1, "lpspi1_root", 0x1480, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI2, "lpspi2_root", 0x1500, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI3, "lpspi3_root", 0x1580, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI4, "lpspi4_root", 0x1600, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI5, "lpspi5_root", 0x1680, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI6, "lpspi6_root", 0x1700, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI7, "lpspi7_root", 0x1780, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_LPSPI8, "lpspi8_root", 0x1800, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C1, "i3c1_root", 0x1880, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C2, "i3c2_root", 0x1900, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_USDHC1, "usdhc1_root", 0x1980, FAST_SEL, }, + { IMX93_CLK_USDHC2, "usdhc2_root", 0x1a00, FAST_SEL, }, + { IMX93_CLK_USDHC3, "usdhc3_root", 0x1a80, FAST_SEL, }, + { IMX93_CLK_SAI1, "sai1_root", 0x1b00, AUDIO_SEL, }, + { IMX93_CLK_SAI2, "sai2_root", 0x1b80, AUDIO_SEL, }, + { IMX93_CLK_SAI3, "sai3_root", 0x1c00, AUDIO_SEL, }, + { IMX93_CLK_CCM_CKO1, "ccm_cko1_root", 0x1c80, CKO1_SEL, }, + { IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, }, + { IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, }, + { IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, }, + /* + * Critical because clk is used for handshake between HSIOMIX and NICMIX when + * NICMIX power down/on during system suspend/resume + */ + { IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL}, + { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, + { IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, }, + { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, }, + { IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, }, + { IMX93_CLK_MEDIA_APB, "media_apb_root", 0x2300, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_MEDIA_LDB, "media_ldb_root", 0x2380, VIDEO_SEL, }, + { IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", 0x2400, VIDEO_SEL, }, + { IMX93_CLK_CAM_PIX, "cam_pix_root", 0x2480, VIDEO_SEL, }, + { IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", 0x2500, VIDEO_SEL, }, + { IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", 0x2580, VIDEO_SEL, }, + { IMX93_CLK_ADC, "adc_root", 0x2700, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_PDM, "pdm_root", 0x2780, AUDIO_SEL, }, + { IMX93_CLK_TSTMR1, "tstmr1_root", 0x2800, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_TSTMR2, "tstmr2_root", 0x2880, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_MQS1, "mqs1_root", 0x2900, AUDIO_SEL, }, + { IMX93_CLK_MQS2, "mqs2_root", 0x2980, AUDIO_SEL, }, + { IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", 0x2a00, NON_IO_SEL, }, + { IMX93_CLK_SPDIF, "spdif_root", 0x2a80, AUDIO_SEL, }, + { IMX93_CLK_ENET, "enet_root", 0x2b00, NON_IO_SEL, }, + { IMX93_CLK_ENET_TIMER1, "enet_timer1_root", 0x2b80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_ENET_TIMER2, "enet_timer2_root", 0x2c00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_ENET_REF, "enet_ref_root", 0x2c80, NON_IO_SEL, }, + { IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", 0x2d00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", 0x2d80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", 0x2e00, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", 0x2e80, LOW_SPEED_IO_SEL, }, + { IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", 0x2f00, MISC_SEL, } +}; + +static const struct imx93_clk_ccgr { + u32 clk; + char *name; + char *parent_name; + u32 off; + unsigned long flags; + u32 *shared_count; +} ccgr_array[] = { + { IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, }, + /* M33 critical clk for system run */ + { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL }, + { IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, }, + { IMX93_CLK_WDOG1_GATE, "wdog1", "clock-osc-24m", 0x8300, }, + { IMX93_CLK_WDOG2_GATE, "wdog2", "clock-osc-24m", 0x8340, }, + { IMX93_CLK_WDOG3_GATE, "wdog3", "clock-osc-24m", 0x8380, }, + { IMX93_CLK_WDOG4_GATE, "wdog4", "clock-osc-24m", 0x83c0, }, + { IMX93_CLK_WDOG5_GATE, "wdog5", "clock-osc-24m", 0x8400, }, + { IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, }, + { IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, }, + { IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED }, + { IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED }, + { IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub }, + { IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub }, + { IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, }, + { IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, }, + { IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, }, + { IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, }, + { IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, }, + { IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, }, + { IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, }, + { IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, }, + { IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, }, + { IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, }, + { IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, }, + { IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, }, + { IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, }, + { IMX93_CLK_TPM1_GATE, "tpm1", "bus_aon_root", 0x8b00, }, + { IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, }, + { IMX93_CLK_TPM3_GATE, "tpm3", "bus_wakeup_root", 0x8b80, }, + { IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, }, + { IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, }, + { IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, }, + { IMX93_CLK_CAN1_GATE, "can1", "can1_root", 0x8c80, }, + { IMX93_CLK_CAN2_GATE, "can2", "can2_root", 0x8cc0, }, + { IMX93_CLK_LPUART1_GATE, "lpuart1", "lpuart1_root", 0x8d00, }, + { IMX93_CLK_LPUART2_GATE, "lpuart2", "lpuart2_root", 0x8d40, }, + { IMX93_CLK_LPUART3_GATE, "lpuart3", "lpuart3_root", 0x8d80, }, + { IMX93_CLK_LPUART4_GATE, "lpuart4", "lpuart4_root", 0x8dc0, }, + { IMX93_CLK_LPUART5_GATE, "lpuart5", "lpuart5_root", 0x8e00, }, + { IMX93_CLK_LPUART6_GATE, "lpuart6", "lpuart6_root", 0x8e40, }, + { IMX93_CLK_LPUART7_GATE, "lpuart7", "lpuart7_root", 0x8e80, }, + { IMX93_CLK_LPUART8_GATE, "lpuart8", "lpuart8_root", 0x8ec0, }, + { IMX93_CLK_LPI2C1_GATE, "lpi2c1", "lpi2c1_root", 0x8f00, }, + { IMX93_CLK_LPI2C2_GATE, "lpi2c2", "lpi2c2_root", 0x8f40, }, + { IMX93_CLK_LPI2C3_GATE, "lpi2c3", "lpi2c3_root", 0x8f80, }, + { IMX93_CLK_LPI2C4_GATE, "lpi2c4", "lpi2c4_root", 0x8fc0, }, + { IMX93_CLK_LPI2C5_GATE, "lpi2c5", "lpi2c5_root", 0x9000, }, + { IMX93_CLK_LPI2C6_GATE, "lpi2c6", "lpi2c6_root", 0x9040, }, + { IMX93_CLK_LPI2C7_GATE, "lpi2c7", "lpi2c7_root", 0x9080, }, + { IMX93_CLK_LPI2C8_GATE, "lpi2c8", "lpi2c8_root", 0x90c0, }, + { IMX93_CLK_LPSPI1_GATE, "lpspi1", "lpspi1_root", 0x9100, }, + { IMX93_CLK_LPSPI2_GATE, "lpspi2", "lpspi2_root", 0x9140, }, + { IMX93_CLK_LPSPI3_GATE, "lpspi3", "lpspi3_root", 0x9180, }, + { IMX93_CLK_LPSPI4_GATE, "lpspi4", "lpspi4_root", 0x91c0, }, + { IMX93_CLK_LPSPI5_GATE, "lpspi5", "lpspi5_root", 0x9200, }, + { IMX93_CLK_LPSPI6_GATE, "lpspi6", "lpspi6_root", 0x9240, }, + { IMX93_CLK_LPSPI7_GATE, "lpspi7", "lpspi7_root", 0x9280, }, + { IMX93_CLK_LPSPI8_GATE, "lpspi8", "lpspi8_root", 0x92c0, }, + { IMX93_CLK_I3C1_GATE, "i3c1", "i3c1_root", 0x9300, }, + { IMX93_CLK_I3C2_GATE, "i3c2", "i3c2_root", 0x9340, }, + { IMX93_CLK_USDHC1_GATE, "usdhc1", "usdhc1_root", 0x9380, }, + { IMX93_CLK_USDHC2_GATE, "usdhc2", "usdhc2_root", 0x93c0, }, + { IMX93_CLK_USDHC3_GATE, "usdhc3", "usdhc3_root", 0x9400, }, + { IMX93_CLK_SAI1_GATE, "sai1", "sai1_root", 0x9440, 0, &share_count_sai1}, + { IMX93_CLK_SAI1_IPG, "sai1_ipg_clk", "bus_aon_root", 0x9440, 0, &share_count_sai1}, + { IMX93_CLK_SAI2_GATE, "sai2", "sai2_root", 0x9480, 0, &share_count_sai2}, + { IMX93_CLK_SAI2_IPG, "sai2_ipg_clk", "bus_wakeup_root", 0x9480, 0, &share_count_sai2}, + { IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, 0, &share_count_sai3}, + { IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3}, + { IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, }, + { IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, }, + { IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, }, + { IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, }, + { IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, }, + { IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, }, + { IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, }, + { IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, }, + { IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, }, + { IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "clock-osc-24m", 0x9a80, }, + { IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, }, + { IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, }, + { IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, }, + { IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, }, + { IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, }, + { IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "clock-osc-24m", 0x9dc0, }, + { IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, }, + { IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, }, + /* Critical because clk accessed during CPU idle */ + { IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "clock-osc-24m", 0x9e80, CLK_IS_CRITICAL}, + { IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, }, + { IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, }, + { IMX93_CLK_TMC_GATE, "tmc", "clock-osc-24m", 0x9f40, }, + { IMX93_CLK_PMRO_GATE, "pmro", "clock-osc-24m", 0x9f80, } +}; + +static int imx93_clk_probe(struct udevice *dev) +{ + const struct imx93_clk_root *root; + const struct imx93_clk_ccgr *ccgr; + struct clk osc_24m_clk, osc_32k_clk, ext1_clk; + void __iomem *base, *anatop_base; + int i, ret; + + clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL)); + + ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk); + if (ret) + return ret; + clk_dm(IMX93_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev)); + + ret = clk_get_by_name(dev, "osc_32k", &osc_32k_clk); + if (ret) + return ret; + clk_dm(IMX93_CLK_32K, dev_get_clk_ptr(osc_32k_clk.dev)); + + ret = clk_get_by_name(dev, "clk_ext1", &ext1_clk); + if (ret) + return ret; + clk_dm(IMX93_CLK_EXT1, dev_get_clk_ptr(ext1_clk.dev)); + + clk_dm(IMX93_CLK_SYS_PLL_PFD0, + clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000)); + clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2, + imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2)); + clk_dm(IMX93_CLK_SYS_PLL_PFD1, + clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000)); + clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2, + imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2)); + clk_dm(IMX93_CLK_SYS_PLL_PFD2, + clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000)); + clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2, + imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2)); + + base = (void *)ANATOP_BASE_ADDR; + + clk_dm(IMX93_CLK_ARM_PLL, + imx_clk_fracn_gppll_integer("arm_pll", "clock-osc-24m", + anatop_base + 0x1000, + &imx_fracn_gppll_integer)); + clk_dm(IMX93_CLK_AUDIO_PLL, + imx_clk_fracn_gppll("audio_pll", "clock-osc-24m", + anatop_base + 0x1200, &imx_fracn_gppll)); + clk_dm(IMX93_CLK_VIDEO_PLL, + imx_clk_fracn_gppll("video_pll", "clock-osc-24m", + anatop_base + 0x1400, &imx_fracn_gppll)); + + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(root_array); i++) { + root = &root_array[i]; + clk_dm(root->clk, imx93_clk_composite_flags(root->name, + parent_names[root->sel], + 4, base + root->off, 3, + root->flags)); + } + + for (i = 0; i < ARRAY_SIZE(ccgr_array); i++) { + ccgr = &ccgr_array[i]; + clk_dm(ccgr->clk, imx93_clk_gate(NULL, ccgr->name, ccgr->parent_name, + ccgr->flags, base + ccgr->off, 0, 1, 1, 3, + ccgr->shared_count)); + } + + clk_dm(IMX93_CLK_A55_SEL, + imx_clk_mux2("a55_sel", base + 0x4820, 0, 1, + a55_core_sels, ARRAY_SIZE(a55_core_sels))); + + return 0; +} + +static const struct udevice_id imx93_clk_ids[] = { + { .compatible = "fsl,imx93-ccm" }, + { /* Sentinel */ }, +}; + +U_BOOT_DRIVER(imx93_clk) = { + .name = "clk_imx93", + .id = UCLASS_CLK, + .of_match = imx93_clk_ids, + .ops = &ccf_clk_ops, + .probe = imx93_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 11f5dca1175..27a53ae5583 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -46,6 +46,34 @@ extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; +#define CLK_FRACN_GPPLL_INTEGER BIT(0) +#define CLK_FRACN_GPPLL_FRACN BIT(1) + +/* NOTE: Rate table should be kept sorted in descending order. */ +struct imx_fracn_gppll_rate_table { + unsigned int rate; + unsigned int mfi; + unsigned int mfn; + unsigned int mfd; + unsigned int rdiv; + unsigned int odiv; +}; + +struct imx_fracn_gppll_clk { + const struct imx_fracn_gppll_rate_table *rate_table; + int rate_count; + int flags; +}; + +struct clk *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk); +struct clk *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk); + +extern struct imx_fracn_gppll_clk imx_fracn_gppll; +extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer; + struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk); @@ -224,4 +252,18 @@ struct clk *imx8m_clk_composite_flags(const char *name, #define imx8m_clk_composite_critical(name, parent_names, reg) \ __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) +struct clk *imx93_clk_composite_flags(const char *name, + const char * const *parent_names, + int num_parents, + void __iomem *reg, + u32 domain_id, + unsigned long flags); +#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ + imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) + +struct clk *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, + u32 mask, u32 domain_id, unsigned int *share_count); + #endif /* __MACH_IMX_CLK_H */ diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 51e66abdbc1..ce08a6b4486 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -480,18 +480,30 @@ static int lpuart_serial_probe(struct udevice *dev) { #if CONFIG_IS_ENABLED(CLK) struct clk per_clk; + struct clk ipg_clk; int ret; ret = clk_get_by_name(dev, "per", &per_clk); if (!ret) { ret = clk_enable(&per_clk); if (ret) { - dev_err(dev, "Failed to get per clk: %d\n", ret); + dev_err(dev, "Failed to enable per clk: %d\n", ret); return ret; } } else { debug("%s: Failed to get per clk: %d\n", __func__, ret); } + + ret = clk_get_by_name(dev, "ipg", &ipg_clk); + if (!ret) { + ret = clk_enable(&ipg_clk); + if (ret) { + dev_err(dev, "Failed to enable ipg clk: %d\n", ret); + return ret; + } + } else { + debug("%s: Failed to get ipg clk: %d\n", __func__, ret); + } #endif if (is_lpuart32(dev)) diff --git a/drivers/usb/host/ehci-mxs.c b/drivers/usb/host/ehci-mxs.c index 147b2fa145d..ddf7cc2d00a 100644 --- a/drivers/usb/host/ehci-mxs.c +++ b/drivers/usb/host/ehci-mxs.c @@ -136,11 +136,12 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev) struct usb_plat *plat = dev_get_plat(dev); struct ehci_mxs_port *port = &priv->port; u32 phandle, phy_reg, clk_reg, clk_id; + ofnode np = dev_ofnode(dev); ofnode phy_node, clk_node; const char *mode; int ret; - mode = ofnode_read_string(dev->node_, "dr_mode"); + mode = ofnode_read_string(np, "dr_mode"); if (mode) { if (strcmp(mode, "peripheral") == 0) plat->init_type = USB_INIT_DEVICE; @@ -151,12 +152,12 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev) } /* Read base address of the USB IP block */ - ret = ofnode_read_u32(dev->node_, "reg", &port->usb_regs); + ret = ofnode_read_u32(np, "reg", &port->usb_regs); if (ret) return ret; /* Read base address of the USB PHY IP block */ - ret = ofnode_read_u32(dev->node_, "fsl,usbphy", &phandle); + ret = ofnode_read_u32(np, "fsl,usbphy", &phandle); if (ret) return ret; @@ -235,9 +236,9 @@ static int ehci_usb_probe(struct udevice *dev) debug("%s: No vbus supply\n", dev->name); if (!ret && priv->vbus_supply) { - ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? - false : true); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, + (type == USB_INIT_DEVICE) ? + false : true); if (ret) { puts("Error enabling VBUS supply\n"); return ret; @@ -264,7 +265,7 @@ static int ehci_usb_remove(struct udevice *dev) #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { - ret = regulator_set_enable(priv->vbus_supply, false); + ret = regulator_set_enable_if_allowed(priv->vbus_supply, false); if (ret) { puts("Error disabling VBUS supply\n"); return ret; diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 8cb1f1aff35..8072d5d503f 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -37,7 +37,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "bootcmd_mfg=fastboot 0\0" \ "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 942081ab84d..256bab089ff 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -36,20 +36,13 @@ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> -#if defined(CONFIG_TDX_EASY_INSTALLER) -# define BOOT_SCRIPT "boot-tezi.scr" -#else -# define BOOT_SCRIPT "boot.scr" -#endif - /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ - "bootcmd_mfg=fastboot 0\0" \ "boot_file=Image\0" \ - "boot_scripts=" BOOT_SCRIPT "\0" \ - "boot_script_dhcp=" BOOT_SCRIPT "\0" \ + "boot_scripts=boot.scr\0" \ + "boot_script_dhcp=boot.scr\0" \ "console=ttymxc2\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 8e02859d8ce..35a1f62053a 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -199,6 +199,10 @@ #define IMX93_CLK_MU1_B_GATE 194 #define IMX93_CLK_MU2_A_GATE 195 #define IMX93_CLK_MU2_B_GATE 196 -#define IMX93_CLK_END 197 +#define IMX93_CLK_NIC_AXI 197 +#define IMX93_CLK_ARM_PLL 198 +#define IMX93_CLK_A55_SEL 199 +#define IMX93_CLK_A55_CORE 200 +#define IMX93_CLK_END 201 #endif diff --git a/include/spl.h b/include/spl.h index 7d30fb57dac..1d416b4c929 100644 --- a/include/spl.h +++ b/include/spl.h @@ -918,6 +918,22 @@ void spl_perform_fixups(struct spl_image_info *spl_image); */ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size); +/** + * board_spl_fit_append_fdt_skip(): test whether DTO application should be skipped + * @name: DTO node name within fitImage images node + * + * A board-specific function used to indicate whether a DTO from fitImage + * configuration node 'fdt' property DT and DTO list should be applied onto + * the base DT or not applied. + * + * This is useful in case of DTOs which implement e.g. different board revision + * details, where such DTO should be applied on one board revision, and should + * not be applied on another board revision. + * + * Return: 0 to indicate DTO is not skipped, all else to indicate DTO is skipped. + */ +int board_spl_fit_append_fdt_skip(const char *name); + void board_boot_order(u32 *spl_boot_list); void spl_save_restore_data(void); |