diff options
530 files changed, 21670 insertions, 15702 deletions
@@ -209,6 +209,7 @@ config ENV_VARS_UBOOT_CONFIG config NR_DRAM_BANKS int "Number of DRAM banks" default 1 if ARCH_SUNXI || ARCH_OWL + default 2 if OMAP34XX default 4 help This defines the number of DRAM banks. @@ -236,6 +237,7 @@ config SYS_BOOT_GET_KBD config HAS_CUSTOM_SYS_INIT_SP_ADDR bool "Use a custom location for the initial stack pointer address" depends on ARC || (ARM && !INIT_SP_RELATIVE) || MIPS || PPC || RISCV + default y if OMAP34XX || AM33XX || AM43XX || DRA7XX default y if TFABOOT help Typically, we use an initial stack pointer address that is calculated @@ -249,6 +251,10 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR config CUSTOM_SYS_INIT_SP_ADDR hex "Static location for the initial stack pointer" depends on HAS_CUSTOM_SYS_INIT_SP_ADDR + default 0x4020ff00 if OMAP34XX + default 0x4030ff00 if AM33XX + default 0x4033ff00 if AM43XX + default 0x4037ff00 if DRA7XX default TEXT_BASE if TFABOOT config SYS_MALLOC_F @@ -615,6 +621,7 @@ config SYS_SRAM_SIZE config SYS_MONITOR_LEN int "Maximum size in bytes reserved for U-Boot in memory" default 1048576 if X86 + default 262144 if OMAP34XX default 786432 if ARCH_SUNXI default 0 help diff --git a/MAINTAINERS b/MAINTAINERS index ddcb7128db4..daaf0345d0e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -732,6 +732,7 @@ F: arch/arm/mach-omap2/ F: arch/arm/include/asm/arch-omap*/ F: arch/arm/include/asm/ti-common/ F: board/ti/ +F: doc/board/ti/ F: drivers/dma/ti* F: drivers/dma/ti*/ F: drivers/firmware/ti_sci.* @@ -1648,6 +1649,7 @@ F: arch/arm/mach-omap2/sec-common.c F: arch/arm/mach-omap2/config_secure.mk F: arch/arm/mach-k3/security.c F: configs/am335x_hs_evm_defconfig +F: configs/am335x_hs_evm_spi_defconfig F: configs/am335x_hs_evm_uart_defconfig F: configs/am43xx_hs_evm_defconfig F: configs/am43xx_hs_evm_qspi_defconfig @@ -1709,6 +1711,19 @@ M: Neha Malcom Francis <n-francis@ti.com> S: Maintained F: drivers/ufs/ +UPL +M: Simon Glass <sjg@chromium.org> +S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-dm.git +F: boot/upl* +F: cmd/upl.c +F: common/spl/spl_upl.c +F: doc/usage/upl.rst +F: doc/usage/cmd/upl.rst +F: include/upl.h +F: test/boot/upl.c +F: test/py/tests/test_upl.py + USB M: Marek Vasut <marex@denx.de> S: Maintained @@ -3,7 +3,7 @@ VERSION = 2024 PATCHLEVEL = 10 SUBLEVEL = -EXTRAVERSION = -rc2 +EXTRAVERSION = -rc3 NAME = # *DOCUMENTATION* @@ -1473,8 +1473,10 @@ u-boot.bin.lzma: u-boot.bin FORCE u-boot-lzma.img: u-boot.bin.lzma FORCE $(call if_changed,mkimage) +fit_image := $(if $(CONFIG_SANDBOX_VPL),u-boot,u-boot-nodtb.bin) + u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \ - $(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \ + $(if $(CONFIG_SPL_LOAD_FIT),$(fit_image) \ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SANDBOX),dts/dt.dtb) \ ,$(UBOOT_BIN)) FORCE $(call if_changed,mkimage) @@ -1839,7 +1841,7 @@ ENV_FILE := $(if $(ENV_SOURCE_FILE),$(ENV_FILE_CFG),$(wildcard $(ENV_FILE_BOARD) quiet_cmd_gen_envp = ENVP $@ cmd_gen_envp = \ if [ -s "$(ENV_FILE)" ]; then \ - $(CPP) -P $(CFLAGS) -x assembler-with-cpp -undef \ + $(CPP) -P $(cpp_flags) -x assembler-with-cpp -undef \ -D__ASSEMBLY__ \ -D__UBOOT_CONFIG__ \ -I . -I include -I $(srctree)/include \ @@ -771,21 +771,8 @@ The following options need to be configured: CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. - CFG_SYS_I2C_DIRECT_BUS - define this, if you don't use i2c muxes on your hardware. - if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can - omit this define. - - CFG_SYS_I2C_MAX_HOPS - define how many muxes are maximal consecutively connected - on one i2c bus. If you not use i2c muxes, omit this - define. - CFG_SYS_I2C_BUSES - hold a list of buses you want to use, only used if - CFG_SYS_I2C_DIRECT_BUS is not defined, for example - a board with CFG_SYS_I2C_MAX_HOPS = 1 and - CFG_SYS_NUM_I2C_BUSES = 9: + hold a list of buses you want to use CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ @@ -883,13 +870,6 @@ The following options need to be configured: You should define these to the GPIO value as given directly to the generic GPIO functions. - CFG_I2C_MULTI_BUS - - This option allows the use of multiple I2C buses, each of which - must have a controller. At any point in time, only one bus is - active. To switch to a different bus, use the 'i2c dev' command. - Note that bus numbering is zero-based. - CFG_SYS_I2C_NOPROBES This option specifies a list of I2C devices that will be skipped @@ -900,11 +880,6 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on a board with one I2C bus - CFG_SYS_RTC_BUS_NUM - - If defined, then this indicates the I2C bus number for the RTC. - If not defined, then U-Boot assumes that RTC is on I2C bus 0. - CONFIG_SOFT_I2C_READ_REPEATED_START defining this will force the i2c_read() function in diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ba0359fed5a..656f588a97c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -802,7 +802,7 @@ config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7A select GPIO_EXTRA_HEADER - select SPL_BOARD_INIT if SPL + select SPL_SOC_INIT if SPL select SPL_STACK_R if SPL select SUPPORT_SPL imply TI_SYSC if DM && OF_CONTROL diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 82d37adae3f..4d59e98e808 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -678,6 +678,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \ sun50i-h6-tanix-tx6.dtb \ sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_MACH_SUN50I_H616) += \ + sun50i-h313-tanix-tx1.dtb \ sun50i-h616-orangepi-zero2.dtb \ sun50i-h618-orangepi-zero2w.dtb \ sun50i-h618-orangepi-zero3.dtb \ @@ -763,8 +764,6 @@ dtb-y += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ - imx6dl-mba6a.dtb \ - imx6dl-mba6b.dtb \ imx6dl-mamoj.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-pico.dtb \ @@ -814,8 +813,6 @@ dtb-y += \ imx6q-kp.dtb \ imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ - imx6q-mba6a.dtb \ - imx6q-mba6b.dtb \ imx6q-mccmon6.dtb\ imx6q-nitrogen6x.dtb \ imx6q-novena.dtb \ @@ -953,13 +950,6 @@ endif dtb-$(CONFIG_RZA1) += \ r7s72100-gr-peach.dtb -dtb-$(CONFIG_ARCH_KEYSTONE) += keystone-k2hk-evm.dtb \ - keystone-k2l-evm.dtb \ - keystone-k2e-evm.dtb \ - keystone-k2g-evm.dtb \ - keystone-k2g-generic.dtb \ - keystone-k2g-ice.dtb - dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb diff --git a/arch/arm/dts/amd-versal2-mini.dts b/arch/arm/dts/amd-versal2-mini.dts new file mode 100644 index 00000000000..ac685772da2 --- /dev/null +++ b/arch/arm/dts/amd-versal2-mini.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Empty device tree for amd-versal2-mini + * + * Copyright (C) 2024, Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +/ { +}; diff --git a/arch/arm/dts/imx6dl-mba6b-u-boot.dtsi b/arch/arm/dts/imx6dl-mba6b-u-boot.dtsi new file mode 100644 index 00000000000..bb17ba9b424 --- /dev/null +++ b/arch/arm/dts/imx6dl-mba6b-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "imx6qdl-mba6-u-boot.dtsi" diff --git a/arch/arm/dts/imx6dl-mba6b.dts b/arch/arm/dts/imx6dl-mba6b.dts deleted file mode 100644 index 610b19d2db0..00000000000 --- a/arch/arm/dts/imx6dl-mba6b.dts +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <Markus.Niebel@tq-group.com> - */ - -/dts-v1/; - -#include <dt-bindings/gpio/gpio.h> -#include "imx6dl-tqma6b.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6b.dtsi" -#include "imx6dl-mba6.dtsi" - -/ { - model = "TQ TQMa6S/DL on MBa6x"; - compatible = "tq,imx6dl-mba6x-b", "tq,mba6b", - "tq,imx6dl-tqma6dl-b", "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-tqma6a.dtsi b/arch/arm/dts/imx6dl-tqma6a.dtsi deleted file mode 100644 index e891ef9b009..00000000000 --- a/arch/arm/dts/imx6dl-tqma6a.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-tqma6a.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/arch/arm/dts/imx6dl-tqma6b.dtsi b/arch/arm/dts/imx6dl-tqma6b.dtsi deleted file mode 100644 index 38cd8501a88..00000000000 --- a/arch/arm/dts/imx6dl-tqma6b.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include "imx6dl.dtsi" -#include "imx6qdl-tqma6b.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x20000000>; - }; -}; diff --git a/arch/arm/dts/imx6q-mba6b-u-boot.dtsi b/arch/arm/dts/imx6q-mba6b-u-boot.dtsi new file mode 100644 index 00000000000..bb17ba9b424 --- /dev/null +++ b/arch/arm/dts/imx6q-mba6b-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "imx6qdl-mba6-u-boot.dtsi" diff --git a/arch/arm/dts/imx6q-mba6b.dts b/arch/arm/dts/imx6q-mba6b.dts deleted file mode 100644 index 02c9f3e91b8..00000000000 --- a/arch/arm/dts/imx6q-mba6b.dts +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * - * Copyright 2013-2021 TQ-Systems GmbH - * Author: Markus Niebel <Markus.Niebel@tq-group.com> - */ - -/dts-v1/; - -#include "imx6q-tqma6b.dtsi" -#include "imx6qdl-mba6.dtsi" -#include "imx6qdl-mba6b.dtsi" -#include "imx6q-mba6.dtsi" - -/ { - model = "TQ TQMa6Q on MBa6x"; - compatible = "tq,imx6q-mba6x-b", "tq,mba6b", - "tq,imx6q-tqma6q-b", "fsl,imx6q"; -}; diff --git a/arch/arm/dts/imx6q-tqma6a.dtsi b/arch/arm/dts/imx6q-tqma6a.dtsi deleted file mode 100644 index ab4c07c13a1..00000000000 --- a/arch/arm/dts/imx6q-tqma6a.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include "imx6q.dtsi" -#include "imx6qdl-tqma6a.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/dts/imx6q-tqma6b.dtsi b/arch/arm/dts/imx6q-tqma6b.dtsi deleted file mode 100644 index 7224c376c31..00000000000 --- a/arch/arm/dts/imx6q-tqma6b.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - */ - -#include "imx6q.dtsi" -#include "imx6qdl-tqma6b.dtsi" -#include "imx6qdl-tqma6.dtsi" - -/ { - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; -}; diff --git a/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi new file mode 100644 index 00000000000..78457ef68f4 --- /dev/null +++ b/arch/arm/dts/imx6qdl-mba6-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "imx6qdl-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx6qdl-tqma6.dtsi b/arch/arm/dts/imx6qdl-tqma6.dtsi deleted file mode 100644 index 344ea935c7d..00000000000 --- a/arch/arm/dts/imx6qdl-tqma6.dtsi +++ /dev/null @@ -1,215 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "supply-3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - status = "okay"; - - m25p80: flash@0 { - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - m25p,fast-read; - }; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 - /* eCSPI1 SS1 */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 - >; - }; - - pinctrl_i2c1_recovery: i2c1recoverygrp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b899 - MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b899 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 - >; - }; - - pinctrl_i2c3_recovery: i2c3recoverygrp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b899 - MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b899 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - >; - }; -}; - -&pmic { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio6>; - interrupts = <10 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_vddcore: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_vddsoc: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-always-on; - }; - - reg_gen_3v3: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_ddr_1v5a: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - reg_ddr_1v5b: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_5v_600mA: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-always-on; - }; - - reg_snvs_3v: vsnvs { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - }; - - reg_vrefddr: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - reg_vgen1_1v5: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - /* not used */ - }; - - reg_vgen2_1v2_eth: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - reg_vgen3_2v8: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen4_1v8: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen5_1v8_eth: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_vgen6_3v3: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* eMMC */ -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; - non-removable; - disable-wp; - no-sd; - no-sdio; - bus-width = <8>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; diff --git a/arch/arm/dts/imx6qdl-tqma6a.dtsi b/arch/arm/dts/imx6qdl-tqma6a.dtsi deleted file mode 100644 index 7dc3f0005b0..00000000000 --- a/arch/arm/dts/imx6qdl-tqma6a.dtsi +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include <dt-bindings/gpio/gpio.h> - -&fec { - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; - fsl,err006687-workaround-present; -}; - -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_recovery>; - scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <100000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - }; - - sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -&iomuxc { - /* - * This pinmuxing is required for the ERR006687 workaround. Board - * DTS files that enable the FEC controller with - * fsl,err006687-workaround-present must include this group. - */ - pinctrl_enet_fix: enetfixgrp { - fsl,pins = < - /* ENET ping patch */ - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-tqma6b.dtsi b/arch/arm/dts/imx6qdl-tqma6b.dtsi deleted file mode 100644 index dd092576644..00000000000 --- a/arch/arm/dts/imx6qdl-tqma6b.dtsi +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2013 Sascha Hauer, Pengutronix - * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> - */ - -#include <dt-bindings/gpio/gpio.h> - -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - clock-frequency = <100000>; - status = "okay"; - - pmic: pmic@8 { - compatible = "fsl,pfuze100"; - reg = <0x08>; - }; - - sensor@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "st,24c64", "atmel,24c64"; - reg = <0x50>; - pagesize = <32>; - }; -}; diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi index 608bde3a2a3..f67fe166d31 100644 --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2021 NXP */ +#include "imx8ulp-u-boot.dtsi" + / { mu@27020000 { compatible = "fsl,imx8ulp-mu"; diff --git a/arch/arm/dts/imx8ulp-u-boot.dtsi b/arch/arm/dts/imx8ulp-u-boot.dtsi new file mode 100644 index 00000000000..30baaeff8ef --- /dev/null +++ b/arch/arm/dts/imx8ulp-u-boot.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#ifdef CONFIG_BINMAN +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + u-boot-spl-ddr { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x22020000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + u-boot-container { + filename = "u-boot-container.bin"; + + mkimage { + args = "-n u-boot-container.cfgout -T imx8image -e 0x0"; + + blob { + filename = "u-boot.bin"; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + filename = "spl.bin"; + offset = <0x0>; + align-size = <0x400>; + align = <0x400>; + }; + + uboot: blob-ext@2 { + filename = "u-boot-container.bin"; + }; + }; +}; +#endif diff --git a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi index 467cac68d0f..a067b0ba354 100644 --- a/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-beagleplay-u-boot.dtsi @@ -78,6 +78,23 @@ }; }; + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + ti-spl_unsigned { filename = "tispl.bin_unsigned"; symlink = "tispl.bin"; @@ -115,6 +132,19 @@ }; }; + tifsstub-gp { + description = "tifsstub"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { description = "DM binary"; type = "firmware"; @@ -158,7 +188,8 @@ conf-0 { description = "k3-am625-beagleplay"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "dm", "spl", + "tifsstub-gp"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi index dbee4aa8d8a..0961ca66f28 100644 --- a/arch/arm/dts/k3-am625-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am625-phycore-som-binman.dtsi @@ -150,12 +150,107 @@ filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; + + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x40000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + tifsstub-gp { + filename = "tifsstub.bin_gp"; + ti-secure-rom { + content = <&tifsstub_gp>; + core = "secure"; + load = <0x60000>; + sw-rev = <CONFIG_K3_X509_SWRV>; + keyfile = "ti-degenerate-key.pem"; + tifsstub; + }; + tifsstub_gp: tifsstub-gp.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62x-gp.bin"; + type = "blob-ext"; + optional; + }; + }; + + ti-spl { insert-template = <&ti_spl_template>; fit { images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; dm { ti-secure { content = <&dm>; @@ -187,7 +282,8 @@ conf-0 { description = "k3-am625-phyboard-lyra-rdk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; @@ -266,7 +362,8 @@ conf-0 { description = "k3-am625-phyboard-lyra-rdk"; firmware = "atf"; - loadables = "tee", "dm", "spl"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm", "spl"; fdt = "fdt-0"; }; }; diff --git a/arch/arm/dts/keystone-clocks.dtsi b/arch/arm/dts/keystone-clocks.dtsi deleted file mode 100644 index 33742d81971..00000000000 --- a/arch/arm/dts/keystone-clocks.dtsi +++ /dev/null @@ -1,411 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 clock tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mainmuxclk: mainmuxclk@2310108 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-mux-clock"; - clocks = <&mainpllclk>, <&refclksys>; - reg = <0x02310108 4>; - bit-shift = <23>; - bit-mask = <1>; - clock-output-names = "mainmuxclk"; - }; - - chipclk1: chipclk1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1"; - }; - - chipclk1rstiso: chipclk1rstiso { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&mainmuxclk>; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso"; - }; - - gemtraceclk: gemtraceclk@2310120 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310120 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "gemtraceclk"; - }; - - chipstmxptclk: chipstmxptclk@2310164 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-divider-clock"; - clocks = <&mainmuxclk>; - reg = <0x02310164 4>; - bit-shift = <0>; - bit-mask = <8>; - clock-output-names = "chipstmxptclk"; - }; - - chipclk12: chipclk12 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <2>; - clock-mult = <1>; - clock-output-names = "chipclk12"; - }; - - chipclk13: chipclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk13"; - }; - - paclk13: paclk13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&papllclk>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "paclk13"; - }; - - chipclk14: chipclk14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk14"; - }; - - chipclk16: chipclk16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk16"; - }; - - chipclk112: chipclk112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk112"; - }; - - chipclk124: chipclk124 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1>; - clock-div = <24>; - clock-mult = <1>; - clock-output-names = "chipclk114"; - }; - - chipclk1rstiso13: chipclk1rstiso13 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <3>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso13"; - }; - - chipclk1rstiso14: chipclk1rstiso14 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <4>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso14"; - }; - - chipclk1rstiso16: chipclk1rstiso16 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <6>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso16"; - }; - - chipclk1rstiso112: chipclk1rstiso112 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&chipclk1rstiso>; - clock-div = <12>; - clock-mult = <1>; - clock-output-names = "chipclk1rstiso112"; - }; - - clkmodrst0: clkmodrst0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "modrst0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkusb: clkusb@2350008 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemifspi: clkaemifspi@235000c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "aemif-spi"; - reg = <0x0235000c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - - clkdebugsstrc: clkdebugsstrc@2350014 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "debugss-trc"; - reg = <0x02350014 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clktetbtrc: clktetbtrc@2350018 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tetb-trc"; - reg = <0x02350018 0xb00>, <0x02350004 0x400>; - reg-names = "control", "domain"; - domain-id = <1>; - }; - - clkpa: clkpa@235001c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&paclk13>; - clock-output-names = "pa"; - reg = <0x0235001c 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkcpgmac: clkcpgmac@2350020 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "cpgmac"; - reg = <0x02350020 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clksa: clksa@2350024 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkpa>; - clock-output-names = "sa"; - reg = <0x02350024 0xb00>, <0x02350008 0x400>; - reg-names = "control", "domain"; - domain-id = <2>; - }; - - clkpcie: clkpcie@2350028 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x02350028 0xb00>, <0x0235000c 0x400>; - reg-names = "control", "domain"; - domain-id = <3>; - }; - - clksr: clksr@2350034 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso112>; - clock-output-names = "sr"; - reg = <0x02350034 0xb00>, <0x02350018 0x400>; - reg-names = "control", "domain"; - domain-id = <6>; - }; - - clkgem0: clkgem0@235003c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem0"; - reg = <0x0235003c 0xb00>, <0x02350020 0x400>; - reg-names = "control", "domain"; - domain-id = <8>; - }; - - clkddr30: clkddr30@235005c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "ddr3-0"; - reg = <0x0235005c 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clkwdtimer0: clkwdtimer0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer1: clkwdtimer1@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer2: clkwdtimer2@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkwdtimer3: clkwdtimer3@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clktimer15: clktimer15@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "timer15"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart0: clkuart0@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart0"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart1: clkuart1@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart1"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkaemif: clkaemif@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "aemif"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkusim: clkusim@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "usim"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clki2c: clki2c@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "i2c"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkspi: clkspi@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkaemifspi>; - clock-output-names = "spi"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkgpio: clkgpio@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "gpio"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkkeymgr: clkkeymgr@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "keymgr"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/arch/arm/dts/keystone-k2e-clocks.dtsi b/arch/arm/dts/keystone-k2e-clocks.dtsi deleted file mode 100644 index 46f8ab3a11d..00000000000 --- a/arch/arm/dts/keystone-k2e-clocks.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison SoC specific device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -clocks { - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkusb1: clkusb1@2350004 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb1"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkhyperlink0: clkhyperlink0@2350030 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkpcie1: clkpcie1@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie1"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkxge: clkxge@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi index 953c7502260..e77c53dbf7b 100644 --- a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi @@ -4,15 +4,23 @@ */ /{ - soc { - bootph-all; - }; aliases { usb0 = &usb; usb1 = &usb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + + chosen { + stdout-path = &uart0; }; }; +&soc0 { + bootph-all; +}; + &i2c1 { bootph-all; }; diff --git a/arch/arm/dts/keystone-k2e-evm.dts b/arch/arm/dts/keystone-k2e-evm.dts deleted file mode 100644 index bf884442617..00000000000 --- a/arch/arm/dts/keystone-k2e-evm.dts +++ /dev/null @@ -1,152 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison EVM device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2e.dtsi" - -/ { - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; - model = "Texas Instruments Keystone 2 Edison EVM"; - - soc { - - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-pass"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1FE80000>; - }; - }; - }; -}; - -&spi0 { - status = "okay"; - nor_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/arch/arm/dts/keystone-k2e-netcp.dtsi b/arch/arm/dts/keystone-k2e-netcp.dtsi deleted file mode 100644 index dd61503db39..00000000000 --- a/arch/arm/dts/keystone-k2e-netcp.dtsi +++ /dev/null @@ -1,203 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Edison Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - }; - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x24186000 0x100>, - <0x24187000 0x2a0>, - <0x24188000 0xb60>, - <0x24186100 0x80>, - <0x24189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@24000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x24000000 0x1000000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-9"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - port-4 { - slave-port = <4>; - link-interface = <2>; - }; - port-5 { - slave-port = <5>; - link-interface = <2>; - }; - port-6 { - slave-port = <6>; - link-interface = <2>; - }; - port-7 { - slave-port = <7>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 00]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/arch/arm/dts/keystone-k2e.dtsi b/arch/arm/dts/keystone-k2e.dtsi deleted file mode 100644 index 449cddcb814..00000000000 --- a/arch/arm/dts/keystone-k2e.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Edison soc device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "keystone-k2e-clocks.dtsi" - - usb: usb@2680000 { - interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; - usb@2690000 { - interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; - }; - }; - - usb1_phy: usb_phy@2620750 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620750 24>; - status = "disabled"; - }; - - usb1: usb@25000000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x25000000 0x10000>; - clocks = <&clkusb1>; - clock-names = "usb"; - interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb@25010000 { - compatible = "synopsys,dwc3"; - reg = <0x25010000 0x70000>; - interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; - usb-phy = <&usb1_phy>, <&usb1_phy>; - }; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - pcie1: pcie@21020000 { - compatible = "ti,keystone-pcie","snps,dw-pcie"; - clocks = <&clkpcie1>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; - ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 - 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ - <0 0 0 2 &pcie_intc1 1>, /* INT B */ - <0 0 0 3 &pcie_intc1 2>, /* INT C */ - <0 0 0 4 &pcie_intc1 3>; /* INT D */ - - pcie_msi_intc1: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>; - }; - - pcie_intc1: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>; - }; - }; - - mdio: mdio@24200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x24200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2e-netcp.dtsi" - }; -}; diff --git a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi index 72b67b232dd..19c78c97ae3 100644 --- a/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2g-evm-u-boot.dtsi @@ -4,20 +4,34 @@ */ /{ - soc { - bootph-all; - }; aliases { usb0 = &usb0; usb1 = &usb1; }; + + chosen { + stdout-path = &uart0; + }; +}; + +&soc0 { + bootph-all; + + pmmc@2900000 { + bootph-all; + compatible = "ti,power-processor"; + reg = <0x02900000 0x40000>; + ti,lpsc_module = <1>; + }; }; &i2c0 { + status = "okay"; bootph-all; }; &i2c1 { + status = "okay"; bootph-all; }; diff --git a/arch/arm/dts/keystone-k2g-evm.dts b/arch/arm/dts/keystone-k2g-evm.dts deleted file mode 100644 index 491fdc4b046..00000000000 --- a/arch/arm/dts/keystone-k2g-evm.dts +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G EVM - * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "keystone-k2g.dtsi" - -/ { - compatible = "ti,k2g-evm","ti,keystone"; - model = "Texas Instruments K2G General Purpose EVM"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&keystone_usb0 { - status = "okay"; -}; - -&usb0_phy { - status = "okay"; -}; - -&usb0 { - dr_mode = "host"; - status = "okay"; -}; - -&keystone_usb1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - -&usb1 { - dr_mode = "peripheral"; - status = "okay"; -}; - -&gbe0 { - phy-handle = <ðphy0>; -}; - -&netcp { - status = "okay"; -}; - -&spi1 { - status = "okay"; - - spi_nor: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&qspi { - status = "okay"; - - flash0: flash@0 { - compatible = "s25fl512s", "jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <96000000>; - #address-cells = <1>; - #size-cells = <1>; - cdns,tshsl-ns = <392>; - cdns,tsd2d-ns = <392>; - cdns,tchsh-ns = <100>; - cdns,tslch-ns = <100>; - block-size = <18>; - - partition@0 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "QSPI.u-boot-env"; - reg = <0x00100000 0x00040000>; - }; - partition@2 { - label = "QSPI.skern"; - reg = <0x00140000 0x0040000>; - }; - partition@3 { - label = "QSPI.pmmc-firmware"; - reg = <0x00180000 0x0040000>; - }; - partition@4 { - label = "QSPI.kernel"; - reg = <0x001C0000 0x0800000>; - }; - partition@5 { - label = "QSPI.file-system"; - reg = <0x009C0000 0x3640000>; - }; - }; -}; - -&mmc0 { - status = "okay"; -}; - -&mmc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi b/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi deleted file mode 100644 index 3634ed7268c..00000000000 --- a/arch/arm/dts/keystone-k2g-generic-u-boot.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/{ - soc { - bootph-all; - }; -}; - -&i2c0 { - bootph-all; -}; - -&i2c1 { - bootph-all; -}; diff --git a/arch/arm/dts/keystone-k2g-generic.dts b/arch/arm/dts/keystone-k2g-generic.dts deleted file mode 100644 index dc6c31a31b4..00000000000 --- a/arch/arm/dts/keystone-k2g-generic.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Device Tree Source for Generic 66AK2G0X EVM - * - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/dts-v1/; - -#include "keystone-k2g.dtsi" - -/ { - compatible = "ti,k2g-generic", "ti,k2g", "ti,keystone"; - model = "Texas Instruments 66AK2G02 Generic"; - - chosen { - stdout-path = &uart0; - }; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; diff --git a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi index 3634ed7268c..152744686b5 100644 --- a/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2g-ice-u-boot.dtsi @@ -4,15 +4,28 @@ */ /{ - soc { + chosen { + stdout-path = &uart0; + }; +}; + +&soc0 { + bootph-all; + + pmmc@2900000 { bootph-all; + compatible = "ti,power-processor"; + reg = <0x02900000 0x40000>; + ti,lpsc_module = <1>; }; }; &i2c0 { + status = "okay"; bootph-all; }; &i2c1 { + status = "okay"; bootph-all; }; diff --git a/arch/arm/dts/keystone-k2g-ice.dts b/arch/arm/dts/keystone-k2g-ice.dts deleted file mode 100644 index b898ae668a9..00000000000 --- a/arch/arm/dts/keystone-k2g-ice.dts +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G Industrial Communication Engine EVM - * - * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "keystone-k2g.dtsi" -#include <dt-bindings/net/ti-dp83867.h> - -/ { - compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone"; - model = "Texas Instruments K2G Industrial Communication EVM"; - - chosen { - stdout-path = &uart0; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; -}; - -&mmc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&qspi { - status = "okay"; - - flash0: flash@0 { - compatible = "s25fl256s1", "jedec,spi-nor"; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-max-frequency = <96000000>; - #address-cells = <1>; - #size-cells = <1>; - cdns,read-delay = <5>; - cdns,tshsl-ns = <500>; - cdns,tsd2d-ns = <500>; - cdns,tchsh-ns = <119>; - cdns,tslch-ns = <119>; - - partition@0 { - label = "QSPI.u-boot"; - reg = <0x00000000 0x00100000>; - }; - partition@1 { - label = "QSPI.u-boot-env"; - reg = <0x00100000 0x00040000>; - }; - partition@2 { - label = "QSPI.skern"; - reg = <0x00140000 0x0040000>; - }; - partition@3 { - label = "QSPI.pmmc-firmware"; - reg = <0x00180000 0x0040000>; - }; - partition@4 { - label = "QSPI.kernel"; - reg = <0x001c0000 0x0800000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x009c0000 0x0040000>; - }; - partition@6 { - label = "QSPI.file-system"; - reg = <0x00a00000 0x1600000>; - }; - }; -}; - -&qmss { - status = "okay"; -}; - -&knav_dmas { - status = "okay"; -}; - -&netcp { - pinctrl-names = "default"; - //pinctrl-0 = <&emac_pins>; - status = "okay"; -}; - -&mdio { - pinctrl-names = "default"; - //pinctrl-0 = <&mdio_pins>; - status = "okay"; - ethphy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; - ti,min-output-impedance; - ti,dp83867-rxctrl-strap-quirk; - }; -}; - -&gbe0 { - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; diff --git a/arch/arm/dts/keystone-k2g-netcp.dtsi b/arch/arm/dts/keystone-k2g-netcp.dtsi deleted file mode 100644 index 2afb48823c1..00000000000 --- a/arch/arm/dts/keystone-k2g-netcp.dtsi +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G Netcp driver - * - * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ - */ - -qmss: qmss@4020000 { - compatible = "ti,keystone-navigator-qmss-l"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ - /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */ - clock-names = "nss_vclk"; - ranges; - queue-range = <0 0x80>; - linkram0 = <0x4020000 0x7ff>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x80>; - reg = <0x4100000 0x800>, - <0x4040000 0x100>, - <0x4080000 0x800>, - <0x40c0000 0x800>; - reg-names = "peek", "config", - "region", "push"; - }; - - }; - queue-pools { - qpend { - qpend-0 { - qrange = <77 8>; - interrupts =<0 308 0xf04 0 309 0xf04 0 310 0xf04 - 0 311 0xf04 0 312 0xf04 0 313 0xf04 - 0 314 0xf04 0 315 0xf04>; - qalloc-by-id; - }; - }; - general-purpose { - gp-0 { - qrange = <112 8>; - }; - netcp-tx { - qrange = <5 8>; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <1023 128>; /* num_desc desc_size */ - link-index = <0x400>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - #address-cells = <1>; - #size-cells = <1>; - /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ - /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_VCLK>; */ - clock-names = "nss_vclk"; - ranges; - ti,navigator-cloud-address = <0x40c0000 0x40c0000 0x40c0000 0x40c0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x4010000 0x100>, - <0x4011000 0x2a0>, /* 21 Tx channels */ - <0x4012000 0x400>, /* 32 Rx channels */ - <0x4010100 0x80>, - <0x4013000 0x400>; /* 32 Rx flows */ - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; - -}; - -gbe_subsys: subsys@4200000 { - compatible = "syscon"; - reg = <0x4200000 0x100>; -}; - -netcp: netcp@4000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - status = "disabled"; - /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ - /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */ - clock-names = "ethss_clk"; - - /* NetCP address range */ - ranges = <0 0x4000000 0x1000000>; - - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, <&dma_gbe 5>; - ti,navigator-dma-names = "netrx0", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-2"; - syscon-subsys = <&gbe_subsys>; - reg = <0x200100 0xe00>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <5>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <5>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <512 12>; - tx-pool = <511 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <77>; - tx-completion-queue = <78>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - }; - }; -}; diff --git a/arch/arm/dts/keystone-k2g.dtsi b/arch/arm/dts/keystone-k2g.dtsi deleted file mode 100644 index 5c3ff127218..00000000000 --- a/arch/arm/dts/keystone-k2g.dtsi +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for K2G SOC - * - * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Texas Instruments K2G SoC"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - chosen { }; - - aliases { - serial0 = &uart0; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &qspi; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2561000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x1000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; - interrupt-parent = <&gic>; - ranges; - - uart0: serial@02530c00 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - clock-names = "uart"; - interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; - }; - - mdio: mdio@4200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - /* power-domains = <&k2g_pds K2G_DEV_NSS0>; */ - /* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */ - clock-names = "fck"; - reg = <0x04200f00 0x100>; - status = "disabled"; - bus_freq = <2500000>; - }; - - qspi: qspi@2940000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02940000 0x1000>, - <0x24000000 0x4000000>; - interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; - num-cs = <4>; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x24000000>; - status = "disabled"; - }; - - #include "keystone-k2g-netcp.dtsi" - - pmmc: pmmc@2900000 { - compatible = "ti,power-processor"; - reg = <0x02900000 0x40000>; - ti,lpsc_module = <1>; - }; - - spi0: spi@21805400 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21805400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@21805800 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21805800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@21805c00 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21805C00 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@21806000 { - compatible = "ti,keystone-spi", "ti,dm6441-spi"; - reg = <0x21806000 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c0: i2c@2530000 { - compatible = "ti,keystone-i2c"; - reg = <0x02530000 0x400>; - clock-frequency = <100000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@2530400 { - compatible = "ti,keystone-i2c"; - reg = <0x02530400 0x400>; - clock-frequency = <100000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@2530800 { - compatible = "ti,keystone-i2c"; - reg = <0x02530800 0x400>; - clock-frequency = <100000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@23000000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x23000000 0x400>; - interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>; - bus-width = <4>; - ti,needs-special-reset; - no-1-8-v; - max-frequency = <96000000>; - status = "disabled"; - }; - - mmc1: mmc@23100000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x23100000 0x400>; - interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>; - bus-width = <8>; - ti,needs-special-reset; - ti,non-removable; - max-frequency = <96000000>; - status = "disabled"; - clock-names = "fck"; - }; - - usb0_phy: usb-phy@0 { - compatible = "usb-nop-xceiv"; - status = "disabled"; - }; - - keystone_usb0: keystone-dwc3@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - /*power-domains = <&k2g_pds 0x0016>;*/ - - usb0: usb@2690000 { - compatible = "snps,dwc3"; - reg = <0x2690000 0x10000>; - interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; - maximum-speed = "high-speed"; - dr_mode = "otg"; - /*usb-phy = <&usb0_phy>;*/ - status = "disabled"; - }; - }; - - usb1_phy: usb-phy@1 { - compatible = "usb-nop-xceiv"; - status = "disabled"; - }; - - keystone_usb1: keystone-dwc3@2580000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2580000 0x10000>; - interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - /*power-domains = <&k2g_pds 0x0017>;*/ - - usb1: usb@2590000 { - compatible = "snps,dwc3"; - reg = <0x2590000 0x10000>; - interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; - maximum-speed = "high-speed"; - dr_mode = "otg"; - /*usb-phy = <&usb1_phy>;*/ - status = "disabled"; - }; - }; - }; -}; diff --git a/arch/arm/dts/keystone-k2hk-clocks.dtsi b/arch/arm/dts/keystone-k2hk-clocks.dtsi deleted file mode 100644 index 3ca4722087c..00000000000 --- a/arch/arm/dts/keystone-k2hk-clocks.dtsi +++ /dev/null @@ -1,422 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking SoC clock nodes - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkarm>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkpass>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3a>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - ddr3bpllclk: ddr3bpllclk@2620368 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclkddr3b>; - clock-output-names = "ddr-3b-pll-clk"; - reg = <0x02620368 4>; - reg-names = "control"; - }; - - clktsip: clktsip@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "tsip"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clksrio: clksrio@235002c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1rstiso13>; - clock-output-names = "srio"; - reg = <0x0235002c 0xb00>, <0x02350010 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkhyperlink0: clkhyperlink0@2350030 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-0"; - reg = <0x02350030 0xb00>, <0x02350014 0x400>; - reg-names = "control", "domain"; - domain-id = <5>; - }; - - clkgem1: clkgem1@2350040 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2@2350044 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3@2350048 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clkgem4: clkgem4@235004c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem4"; - reg = <0x0235004c 0xb00>, <0x02350030 0x400>; - reg-names = "control", "domain"; - domain-id = <12>; - }; - - clkgem5: clkgem5@2350050 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem5"; - reg = <0x02350050 0xb00>, <0x02350034 0x400>; - reg-names = "control", "domain"; - domain-id = <13>; - }; - - clkgem6: clkgem6@2350054 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem6"; - reg = <0x02350054 0xb00>, <0x02350038 0x400>; - reg-names = "control", "domain"; - domain-id = <14>; - }; - - clkgem7: clkgem7@2350058 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem7"; - reg = <0x02350058 0xb00>, <0x0235003c 0x400>; - reg-names = "control", "domain"; - domain-id = <15>; - }; - - clkddr31: clkddr31@2350060 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "ddr3-1"; - reg = <0x02350060 0xb00>, <0x02350040 0x400>; - reg-names = "control", "domain"; - domain-id = <16>; - }; - - clktac: clktac@2350064 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac01: clkrac01@2350068 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-01"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac23: clkrac23@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac-23"; - reg = <0x0235006c 0xb00>, <0x02350048 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0@2350070 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc1: clkfftc1@2350074 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x02350074 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkfftc2: clkfftc2@2350078 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-2"; - reg = <0x02350078 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc3: clkfftc3@235007c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-3"; - reg = <0x0235007c 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc4: clkfftc4@2350080 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-4"; - reg = <0x02350080 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkfftc5: clkfftc5@2350084 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-5"; - reg = <0x02350084 0xb00>, <0x02350050 0x400>; - reg-names = "control", "domain"; - domain-id = <20>; - }; - - clkaif: clkaif@2350088 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "aif"; - reg = <0x02350088 0xb00>, <0x02350054 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0@235008c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1@2350090 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350090 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d2: clktcp3d2@2350094 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-2"; - reg = <0x02350094 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clktcp3d3: clktcp3d3@2350098 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-3"; - reg = <0x02350098 0xb00>, <0x0235005c 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0@235009c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1@23500a0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2@23500a4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3@23500a8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp4: clkvcp4@23500ac { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-4"; - reg = <0x023500ac 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp5: clkvcp5@23500b0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-5"; - reg = <0x023500b0 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp6: clkvcp6@23500b4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-6"; - reg = <0x023500b4 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkvcp7: clkvcp7@23500b8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-7"; - reg = <0x023500b8 0xb00>, <0x02350064 0x400>; - reg-names = "control", "domain"; - domain-id = <25>; - }; - - clkbcp: clkbcp@23500bc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdxb: clkdxb@23500c0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dxb"; - reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkhyperlink1: clkhyperlink1@23500c4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "hyperlink-1"; - reg = <0x023500c4 0xb00>, <0x02350070 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkxge: clkxge@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "xge"; - reg = <0x023500c8 0xb00>, <0x02350074 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; -}; diff --git a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi index 3e38f228a6a..3b3d327562c 100644 --- a/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2hk-evm-u-boot.dtsi @@ -4,9 +4,19 @@ */ /{ - soc { - bootph-all; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; }; + + chosen { + stdout-path = &uart0; + }; +}; + +&soc0 { + bootph-all; }; &i2c1 { @@ -18,11 +28,9 @@ psc-domain = <2>; }; -&usb { - dwc3@2690000 { - phys = <&usb_phy>; - dr_mode = "host"; - snps,u2ss_inp3_quirk; - status = "okay"; - }; +&usb0 { + phys = <&usb_phy>; + dr_mode = "host"; + snps,u2ss_inp3_quirk; + status = "okay"; }; diff --git a/arch/arm/dts/keystone-k2hk-evm.dts b/arch/arm/dts/keystone-k2hk-evm.dts deleted file mode 100644 index 6222876f277..00000000000 --- a/arch/arm/dts/keystone-k2hk-evm.dts +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking EVM device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2hk.dtsi" - -/ { - compatible = "ti,k2hk-evm","ti,keystone"; - model = "Texas Instruments Keystone 2 Kepler/Hawking EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - - refclkpass: refclkpass { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-pass"; - }; - - refclkarm: refclkarm { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "refclk-arm"; - }; - - refclkddr3a: refclkddr3a { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3a"; - }; - - refclkddr3b: refclkddr3b { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - clock-output-names = "refclk-ddr3b"; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - led-debug-1-1 { - label = "keystone:green:debug1"; - gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ - }; - - led-debug-1-2 { - label = "keystone:red:debug1"; - gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ - }; - - led-debug-2 { - label = "keystone:blue:debug2"; - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ - }; - - led-debug-3 { - label = "keystone:blue:debug3"; - gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x1fe80000>; - }; - }; - }; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&spi0 { - status = "okay"; - nor_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/arch/arm/dts/keystone-k2hk-netcp.dtsi b/arch/arm/dts/keystone-k2hk-netcp.dtsi deleted file mode 100644 index 3f8c4c263a2..00000000000 --- a/arch/arm/dts/keystone-k2hk-netcp.dtsi +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Hawking Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x4000>; - linkram0 = <0x100000 0x8000>; - linkram1 = <0x0 0x10000>; - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - - qmgr1 { - managed-queues = <0x2000 0x2000>; - reg = <0x2a60000 0x20000>, - <0x2a06400 0x400>, - <0x2a04000 0x1000>, - <0x2a05000 0x1000>, - <0x23aa0000 0x20000>, - <0x2aa0000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <8704 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <8720 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <640 9>; - qalloc-by-id; - }; - netcpx-tx { - qrange = <8752 8>; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000 - 0x23aa0000 0x23ab0000>; - - dma_gbe: dma_gbe@0 { - reg = <0x2004000 0x100>, - <0x2004400 0x120>, - <0x2004800 0x300>, - <0x2004c00 0x120>, - <0x2005000 0x400>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@2000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x2000000 0x100000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 22>, - <&dma_gbe 23>, - <&dma_gbe 8>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - ranges; - #address-cells = <1>; - #size-cells = <1>; - gbe@90000 { /* ETHSS */ - #address-cells = <1>; - #size-cells = <1>; - label = "netcp-gbe"; - compatible = "ti,netcp-gbe"; - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>; - /* enable-ale; */ - tx-queue = <648>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8704>; - tx-completion-queue = <8706>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <8705>; - tx-completion-queue = <8707>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 6f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/arch/arm/dts/keystone-k2hk.dtsi b/arch/arm/dts/keystone-k2hk.dtsi deleted file mode 100644 index e5ab1fbb559..00000000000 --- a/arch/arm/dts/keystone-k2hk.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Kepler/Hawking soc specific device tree - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - - cpu@2 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <2>; - }; - - cpu@3 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <3>; - }; - }; - - soc { - /include/ "keystone-k2hk-clocks.dtsi" - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - dspgpio4: keystone_dsp_gpio@2620250 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x250>; - }; - - dspgpio5: keystone_dsp_gpio@2620254 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x254>; - }; - - dspgpio6: keystone_dsp_gpio@2620258 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x258>; - }; - - dspgpio7: keystone_dsp_gpio@262025c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x25c>; - }; - - mdio: mdio@02090300 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x02090300 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2hk-netcp.dtsi" - }; -}; diff --git a/arch/arm/dts/keystone-k2l-clocks.dtsi b/arch/arm/dts/keystone-k2l-clocks.dtsi deleted file mode 100644 index fcfc2fb6cc2..00000000000 --- a/arch/arm/dts/keystone-k2l-clocks.dtsi +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 lamarr SoC clock nodes - * - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -clocks { - armpllclk: armpllclk@2620370 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "arm-pll-clk"; - reg = <0x02620370 4>; - reg-names = "control"; - }; - - mainpllclk: mainpllclk@2310110 { - #clock-cells = <0>; - compatible = "ti,keystone,main-pll-clock"; - clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; - reg-names = "control", "multiplier", "post-divider"; - }; - - papllclk: papllclk@2620358 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "papllclk"; - reg = <0x02620358 4>; - reg-names = "control"; - }; - - ddr3apllclk: ddr3apllclk@2620360 { - #clock-cells = <0>; - compatible = "ti,keystone,pll-clock"; - clocks = <&refclksys>; - clock-output-names = "ddr-3a-pll-clk"; - reg = <0x02620360 4>; - reg-names = "control"; - }; - - clkdfeiqnsys: clkdfeiqnsys@2350004 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "dfe"; - reg-names = "control", "domain"; - reg = <0x02350004 0xb00>, <0x02350000 0x400>; - domain-id = <0>; - }; - - clkpcie1: clkpcie1@235002c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk12>; - clock-output-names = "pcie"; - reg = <0x0235002c 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <4>; - }; - - clkgem1: clkgem1@2350040 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem1"; - reg = <0x02350040 0xb00>, <0x02350024 0x400>; - reg-names = "control", "domain"; - domain-id = <9>; - }; - - clkgem2: clkgem2@2350044 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem2"; - reg = <0x02350044 0xb00>, <0x02350028 0x400>; - reg-names = "control", "domain"; - domain-id = <10>; - }; - - clkgem3: clkgem3@2350048 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk1>; - clock-output-names = "gem3"; - reg = <0x02350048 0xb00>, <0x0235002c 0x400>; - reg-names = "control", "domain"; - domain-id = <11>; - }; - - clktac: clktac@2350064 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tac"; - reg = <0x02350064 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkrac: clkrac@2350068 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "rac"; - reg = <0x02350068 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <17>; - }; - - clkdfepd0: clkdfepd0@235006c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd0"; - reg = <0x0235006c 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <18>; - }; - - clkfftc0: clkfftc0@2350070 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-0"; - reg = <0x02350070 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <19>; - }; - - clkosr: clkosr@2350088 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "osr"; - reg = <0x02350088 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <21>; - }; - - clktcp3d0: clktcp3d0@235008c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-0"; - reg = <0x0235008c 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <22>; - }; - - clktcp3d1: clktcp3d1@2350094 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "tcp3d-1"; - reg = <0x02350094 0xb00>, <0x02350058 0x400>; - reg-names = "control", "domain"; - domain-id = <23>; - }; - - clkvcp0: clkvcp0@235009c { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-0"; - reg = <0x0235009c 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp1: clkvcp1@23500a0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-1"; - reg = <0x023500a0 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp2: clkvcp2@23500a4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-2"; - reg = <0x023500a4 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkvcp3: clkvcp3@23500a8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "vcp-3"; - reg = <0x023500a8 0xb00>, <0x02350060 0x400>; - reg-names = "control", "domain"; - domain-id = <24>; - }; - - clkbcp: clkbcp@23500bc { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "bcp"; - reg = <0x023500bc 0xb00>, <0x02350068 0x400>; - reg-names = "control", "domain"; - domain-id = <26>; - }; - - clkdfepd1: clkdfepd1@23500c0 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "dfe-pd1"; - reg = <0x023500c0 0xb00>, <0x02350044 0x400>; - reg-names = "control", "domain"; - domain-id = <27>; - }; - - clkfftc1: clkfftc1@23500c4 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "fftc-1"; - reg = <0x023500c4 0xb00>, <0x023504c0 0x400>; - reg-names = "control", "domain"; - domain-id = <28>; - }; - - clkiqnail: clkiqnail@23500c8 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk13>; - clock-output-names = "iqn-ail"; - reg = <0x023500c8 0xb00>, <0x0235004c 0x400>; - reg-names = "control", "domain"; - domain-id = <29>; - }; - - clkuart2: clkuart2@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart2"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; - - clkuart3: clkuart3@2350000 { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&clkmodrst0>; - clock-output-names = "uart3"; - reg = <0x02350000 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; -}; diff --git a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi index f1aed14b0b5..d9dee805ebe 100644 --- a/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi +++ b/arch/arm/dts/keystone-k2l-evm-u-boot.dtsi @@ -3,16 +3,30 @@ * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ */ +/{ + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&soc0 { + bootph-all; +}; + &usb_phy { #phy-cells = <0>; psc-domain = <2>; }; -&usb { - dwc3@2690000 { - phys = <&usb_phy>; - dr_mode = "host"; - snps,u2ss_inp3_quirk; - status = "okay"; - }; +&usb0 { + phys = <&usb_phy>; + dr_mode = "host"; + snps,u2ss_inp3_quirk; + status = "okay"; }; diff --git a/arch/arm/dts/keystone-k2l-evm.dts b/arch/arm/dts/keystone-k2l-evm.dts deleted file mode 100644 index 9d2b4542e81..00000000000 --- a/arch/arm/dts/keystone-k2l-evm.dts +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Lamarr EVM device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ -/dts-v1/; - -#include "keystone.dtsi" -#include "keystone-k2l.dtsi" - -/ { - compatible = "ti,k2l-evm","ti,keystone"; - model = "Texas Instruments Keystone 2 Lamarr EVM"; - - soc { - clocks { - refclksys: refclksys { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <122880000>; - clock-output-names = "refclk-sys"; - }; - }; - }; -}; - -&usb_phy { - status = "okay"; -}; - -&usb { - status = "okay"; -}; - -&i2c0 { - dtt@50 { - compatible = "at,24c1024"; - reg = <0x50>; - }; -}; - -&aemif { - cs0 { - #address-cells = <2>; - #size-cells = <1>; - clock-ranges; - ranges; - - ti,cs-chipselect = <0>; - /* all timings in nanoseconds */ - ti,cs-min-turnaround-ns = <12>; - ti,cs-read-hold-ns = <6>; - ti,cs-read-strobe-ns = <23>; - ti,cs-read-setup-ns = <9>; - ti,cs-write-hold-ns = <8>; - ti,cs-write-strobe-ns = <23>; - ti,cs-write-setup-ns = <8>; - - nand@0,0 { - compatible = "ti,keystone-nand","ti,davinci-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0 0x4000000 - 1 0 0x0000100>; - - ti,davinci-chipselect = <0>; - ti,davinci-mask-ale = <0x2000>; - ti,davinci-mask-cle = <0x4000>; - ti,davinci-mask-chipsel = <0>; - nand-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - nand-on-flash-bbt; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "params"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "ubifs"; - reg = <0x180000 0x7FE80000>; - }; - }; - }; -}; - -&spi0 { - status ="okay"; - nor_flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "Micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <54000000>; - m25p,fast-read; - reg = <0>; - - partition@0 { - label = "u-boot-spl"; - reg = <0x0 0x80000>; - read-only; - }; - - partition@1 { - label = "misc"; - reg = <0x80000 0xf80000>; - }; - }; -}; - -&mdio { - status = "okay"; - ethphy0: ethernet-phy@0 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; diff --git a/arch/arm/dts/keystone-k2l-netcp.dtsi b/arch/arm/dts/keystone-k2l-netcp.dtsi deleted file mode 100644 index 2caa0583fc8..00000000000 --- a/arch/arm/dts/keystone-k2l-netcp.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for Keystone 2 Lamarr Netcp driver - * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -qmss: qmss@2a40000 { - compatible = "ti,keystone-navigator-qmss"; - dma-coherent; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&chipclk13>; - ranges; - queue-range = <0 0x2000>; - linkram0 = <0x100000 0x4000>; - linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */ - - qmgrs { - #address-cells = <1>; - #size-cells = <1>; - ranges; - qmgr0 { - managed-queues = <0 0x2000>; - reg = <0x2a40000 0x20000>, - <0x2a06000 0x400>, - <0x2a02000 0x1000>, - <0x2a03000 0x1000>, - <0x23a80000 0x20000>, - <0x2a80000 0x20000>; - reg-names = "peek", "status", "config", - "region", "push", "pop"; - }; - }; - queue-pools { - qpend { - qpend-0 { - qrange = <658 8>; - interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 - 0 43 0xf04 0 44 0xf04 0 45 0xf04 - 0 46 0xf04 0 47 0xf04>; - }; - qpend-1 { - qrange = <528 16>; - interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 - 0 51 0xf04 0 52 0xf04 0 53 0xf04 - 0 54 0xf04 0 55 0xf04 0 56 0xf04 - 0 57 0xf04 0 58 0xf04 0 59 0xf04 - 0 60 0xf04 0 61 0xf04 0 62 0xf04 - 0 63 0xf04>; - qalloc-by-id; - }; - qpend-2 { - qrange = <544 16>; - interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 - 0 59 0xf04 0 68 0xf04 0 69 0xf04 - 0 70 0xf04 0 71 0xf04 0 72 0xf04 - 0 73 0xf04 0 74 0xf04 0 75 0xf04 - 0 76 0xf04 0 77 0xf04 0 78 0xf04 - 0 79 0xf04>; - }; - }; - general-purpose { - gp-0 { - qrange = <4000 64>; - }; - netcp-tx { - qrange = <896 128>; - qalloc-by-id; - }; - }; - }; - - descriptor-regions { - #address-cells = <1>; - #size-cells = <1>; - ranges; - region-12 { - id = <12>; - region-spec = <8192 128>; /* num_desc desc_size */ - link-index = <0x4000>; - }; - }; -}; /* qmss */ - -knav_dmas: knav_dmas@0 { - compatible = "ti,keystone-navigator-dma"; - clocks = <&papllclk>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - ti,navigator-cloud-address = <0x23a80000 0x23a90000>; - - dma_gbe: dma_gbe@0 { - reg = <0x26186000 0x100>, - <0x26187000 0x2a0>, - <0x26188000 0xb60>, - <0x26186100 0x80>, - <0x26189000 0x1000>; - reg-names = "global", "txchan", "rxchan", - "txsched", "rxflow"; - }; -}; - -netcp: netcp@26000000 { - reg = <0x2620110 0x8>; - reg-names = "efuse"; - compatible = "ti,netcp-1.0"; - #address-cells = <1>; - #size-cells = <1>; - - /* NetCP address range */ - ranges = <0 0x26000000 0x1000000>; - - clocks = <&papllclk>, <&clkcpgmac>, <&chipclk12>; - dma-coherent; - - ti,navigator-dmas = <&dma_gbe 0>, - <&dma_gbe 8>, - <&dma_gbe 0>; - ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; - - netcp-devices { - #address-cells = <1>; - #size-cells = <1>; - ranges; - gbe@200000 { /* ETHSS */ - label = "netcp-gbe"; - compatible = "ti,netcp-gbe-5"; - reg = <0x200000 0x900>, <0x220000 0x20000>; - /* enable-ale; */ - tx-queue = <896>; - tx-channel = "nettx"; - - interfaces { - gbe0: interface-0 { - slave-port = <0>; - link-interface = <1>; - phy-handle = <ðphy0>; - }; - gbe1: interface-1 { - slave-port = <1>; - link-interface = <1>; - phy-handle = <ðphy1>; - }; - }; - - secondary-slave-ports { - port-2 { - slave-port = <2>; - link-interface = <2>; - }; - port-3 { - slave-port = <3>; - link-interface = <2>; - }; - }; - }; - }; - - netcp-interfaces { - interface-0 { - rx-channel = "netrx0"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <528>; - tx-completion-queue = <530>; - efuse-mac = <1>; - netcp-gbe = <&gbe0>; - - }; - interface-1 { - rx-channel = "netrx1"; - rx-pool = <1024 12>; - tx-pool = <1024 12>; - rx-queue-depth = <128 128 0 0>; - rx-buffer-size = <1518 4096 0 0>; - rx-queue = <529>; - tx-completion-queue = <531>; - efuse-mac = <0>; - local-mac-address = [02 18 31 7e 3e 7f]; - netcp-gbe = <&gbe1>; - }; - }; -}; diff --git a/arch/arm/dts/keystone-k2l.dtsi b/arch/arm/dts/keystone-k2l.dtsi deleted file mode 100644 index c8893e284f2..00000000000 --- a/arch/arm/dts/keystone-k2l.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Keystone 2 Lamarr SoC specific device tree - * - * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - interrupt-parent = <&gic>; - - cpu@0 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <0>; - }; - - cpu@1 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - reg = <1>; - }; - }; - - soc { - /include/ "keystone-k2l-clocks.dtsi" - - uart2: serial@2348400 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348400 0x100>; - clocks = <&clkuart2>; - interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>; - }; - - uart3: serial@2348800 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02348800 0x100>; - clocks = <&clkuart3>; - interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; - }; - - dspgpio0: keystone_dsp_gpio@02620240 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x240>; - }; - - dspgpio1: keystone_dsp_gpio@2620244 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x244>; - }; - - dspgpio2: keystone_dsp_gpio@2620248 { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x248>; - }; - - dspgpio3: keystone_dsp_gpio@262024c { - compatible = "ti,keystone-dsp-gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio,syscon-dev = <&devctrl 0x24c>; - }; - - mdio: mdio@26200f00 { - compatible = "ti,keystone_mdio", "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x26200f00 0x100>; - status = "disabled"; - clocks = <&clkcpgmac>; - clock-names = "fck"; - bus_freq = <2500000>; - }; - /include/ "keystone-k2l-netcp.dtsi" - }; -}; - -&spi0 { - ti,davinci-spi-num-cs = <5>; -}; - -&spi1 { - ti,davinci-spi-num-cs = <3>; -}; - -&spi2 { - ti,davinci-spi-num-cs = <5>; - /* Pin muxed. Enabled and configured by Bootloader */ - status = "disabled"; -}; diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi deleted file mode 100644 index 1538ccef81a..00000000000 --- a/arch/arm/dts/keystone.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/gpio/gpio.h> - -#include "skeleton.dtsi" - -/ { - model = "Texas Instruments Keystone 2 SoC"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - }; - - chosen { - stdout-path = &uart0; - }; - - memory { - reg = <0x80000000 0x40000000>; - }; - - gic: interrupt-controller { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x02561000 0x1000>, - <0x02562000 0x2000>, - <0x02564000 0x1000>, - <0x02566000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = - <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu"; - interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ti,keystone","simple-bus"; - interrupt-parent = <&gic>; - ranges; - - pllctrl: pll-controller@02310000 { - compatible = "ti,keystone-pllctrl", "syscon"; - reg = <0x02310000 0x200>; - }; - - devctrl: device-state-control@02620000 { - compatible = "ti,keystone-devctrl", "syscon"; - reg = <0x02620000 0x1000>; - }; - - rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>; - }; - - /include/ "keystone-clocks.dtsi" - - uart0: serial@2530c00 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02530c00 0x100>; - clocks = <&clkuart0>; - interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; - }; - - uart1: serial@2531000 { - compatible = "ns16550a"; - current-speed = <115200>; - reg-shift = <2>; - reg-io-width = <4>; - reg = <0x02531000 0x100>; - clocks = <&clkuart1>; - interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; - }; - - i2c0: i2c@2530000 { - compatible = "ti,davinci-i2c"; - reg = <0x02530000 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@2530400 { - compatible = "ti,davinci-i2c"; - reg = <0x02530400 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@2530800 { - compatible = "ti,davinci-i2c"; - reg = <0x02530800 0x400>; - clock-frequency = <100000>; - clocks = <&clki2c>; - interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@21000400 { - compatible = "ti,dm6441-spi"; - reg = <0x21000400 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@21000600 { - compatible = "ti,dm6441-spi"; - reg = <0x21000600 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi2: spi@21000800 { - compatible = "ti,dm6441-spi"; - reg = <0x21000800 0x200>; - num-cs = <4>; - ti,davinci-spi-intr-line = <0>; - interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkspi>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_phy: usb_phy@2620738 { - compatible = "ti,keystone-usbphy"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2620738 24>; - status = "disabled"; - }; - - usb: usb@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - clocks = <&clkusb>; - clock-names = "usb"; - interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; - ranges; - dma-coherent; - dma-ranges; - status = "disabled"; - - usb@2690000 { - compatible = "synopsys,dwc3"; - reg = <0x2690000 0x70000>; - interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; - usb-phy = <&usb_phy>, <&usb_phy>; - }; - }; - - wdt: wdt@22f0080 { - compatible = "ti,keystone-wdt","ti,davinci-wdt"; - reg = <0x022f0080 0x80>; - clocks = <&clkwdtimer0>; - }; - - clock_event: timer@22f0000 { - compatible = "ti,keystone-timer"; - reg = <0x022f0000 0x80>; - interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; - clocks = <&clktimer15>; - }; - - gpio0: gpio@260bf00 { - compatible = "ti,keystone-gpio"; - reg = <0x0260bf00 0x100>; - gpio-controller; - #gpio-cells = <2>; - /* HW Interrupts mapped to GPIO pins */ - interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; - clocks = <&clkgpio>; - clock-names = "gpio"; - ti,ngpio = <32>; - ti,davinci-gpio-unbanked = <32>; - }; - - aemif: aemif@21000A00 { - compatible = "ti,keystone-aemif", "ti,davinci-aemif"; - #address-cells = <2>; - #size-cells = <1>; - clocks = <&clkaemif>; - clock-names = "aemif"; - clock-ranges; - - reg = <0x21000A00 0x00000100>; - ranges = <0 0 0x30000000 0x10000000 - 1 0 0x21000A00 0x00000100>; - }; - - kirq0: keystone_irq@26202a0 { - compatible = "ti,keystone-irq"; - interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; - interrupt-controller; - #interrupt-cells = <1>; - ti,syscon-dev = <&devctrl 0x2a0>; - }; - - pcie0: pcie@21800000 { - compatible = "ti,keystone-pcie", "snps,dw-pcie"; - clocks = <&clkpcie>; - clock-names = "pcie"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; - ranges = <0x81000000 0 0 0x23250000 0 0x4000 - 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; - - status = "disabled"; - device_type = "pci"; - num-lanes = <2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ - <0 0 0 2 &pcie_intc0 1>, /* INT B */ - <0 0 0 3 &pcie_intc0 2>, /* INT C */ - <0 0 0 4 &pcie_intc0 3>; /* INT D */ - - pcie_msi_intc0: msi-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; - }; - - pcie_intc0: legacy-interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; - }; - }; - }; -}; diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi index 7aaa7770f83..a9991a121f1 100644 --- a/arch/arm/dts/mt7981.dtsi +++ b/arch/arm/dts/mt7981.dtsi @@ -98,14 +98,6 @@ bootph-all; }; - infracfg_ao: infracfg_ao@10001000 { - compatible = "mediatek,mt7981-infracfg_ao"; - reg = <0x10001000 0x80>; - clock-parent = <&infracfg>; - #clock-cells = <1>; - bootph-all; - }; - infracfg: infracfg@10001000 { compatible = "mediatek,mt7981-infracfg"; reg = <0x10001000 0x30>; @@ -140,14 +132,13 @@ #clock-cells = <1>; #pwm-cells = <2>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg CK_INFRA_PWM>, - <&infracfg_ao CK_INFRA_PWM_BSEL>, - <&infracfg_ao CK_INFRA_PWM1_CK>, - <&infracfg_ao CK_INFRA_PWM2_CK>, - /* FIXME */ - <&infracfg_ao CK_INFRA_PWM2_CK>; - assigned-clocks = <&topckgen CK_TOP_PWM_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_BSEL>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; + assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; status = "disabled"; }; @@ -158,8 +149,8 @@ <0x10217080 0x80>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clock-div = <1>; - clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, - <&infracfg_ao CK_INFRA_AP_DMA_CK>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; @@ -170,11 +161,11 @@ compatible = "mediatek,hsuart"; reg = <0x11002000 0x400>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao CK_INFRA_UART0_CK>; - assigned-clocks = <&topckgen CK_TOP_UART_SEL>, - <&infracfg_ao CK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg CK_INFRA_UART>; + clocks = <&infracfg CLK_INFRA_UART0_CK>; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; bootph-all; @@ -184,11 +175,11 @@ compatible = "mediatek,hsuart"; reg = <0x11003000 0x400>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao CK_INFRA_UART1_CK>; - assigned-clocks = <&topckgen CK_TOP_UART_SEL>, - <&infracfg_ao CK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg CK_INFRA_UART>; + clocks = <&infracfg CLK_INFRA_UART1_CK>; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -197,11 +188,11 @@ compatible = "mediatek,hsuart"; reg = <0x11004000 0x400>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao CK_INFRA_UART2_CK>; - assigned-clocks = <&topckgen CK_TOP_UART_SEL>, - <&infracfg_ao CK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg CK_INFRA_UART>; + clocks = <&infracfg CLK_INFRA_UART2_CK>; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, + <&topckgen CLK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -211,14 +202,14 @@ reg = <0x11005000 0x1000>, <0x11006000 0x1000>; reg-names = "nfi", "ecc"; - clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, - <&infracfg_ao CK_INFRA_NFI1_CK>, - <&infracfg_ao CK_INFRA_NFI_HCK_CK>; + clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, + <&infracfg CLK_INFRA_NFI1_CK>, + <&infracfg CLK_INFRA_NFI_HCK_CK>; clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, - <&topckgen CK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, - <&topckgen CK_TOP_CB_M_D8>; + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, + <&topckgen CLK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, + <&topckgen CLK_TOP_CB_M_D8>; status = "disabled"; }; @@ -244,14 +235,14 @@ }; sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7986-sgmiisys", "syscon"; + compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; reg = <0x10060000 0x1000>; pn_swap; #clock-cells = <1>; }; sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7986-sgmiisys", "syscon"; + compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; reg = <0x10070000 0x1000>; #clock-cells = <1>; }; @@ -265,13 +256,13 @@ spi0: spi@1100a000 { compatible = "mediatek,ipm-spi"; reg = <0x1100a000 0x100>; - clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, - <&topckgen CK_TOP_SPI_SEL>; - assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, - <&infracfg CK_INFRA_SPI0_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, - <&topckgen CK_INFRA_ISPI0>; - clock-names = "sel-clk", "spi-clk"; + clocks = <&infracfg CLK_INFRA_SPI0_CK>, + <&topckgen CLK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "spi-clk", "sel-clk"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -280,19 +271,26 @@ compatible = "mediatek,ipm-spi"; reg = <0x1100b000 0x100>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_SPI1_CK>, + <&topckgen CLK_TOP_SPIM_MST_SEL>; + assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>; + clock-names = "spi-clk", "sel-clk"; status = "disabled"; }; spi2: spi@11009000 { compatible = "mediatek,ipm-spi"; reg = <0x11009000 0x100>; - clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, - <&topckgen CK_TOP_SPI_SEL>; - assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, - <&infracfg CK_INFRA_SPI0_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, - <&topckgen CK_INFRA_ISPI0>; - clock-names = "sel-clk", "spi-clk"; + clocks = <&infracfg CLK_INFRA_SPI2_CK>, + <&topckgen CLK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, + <&topckgen CLK_TOP_SPI_SEL>; + clock-names = "spi-clk", "sel-clk"; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -302,13 +300,13 @@ reg = <0x11230000 0x1000>, <0x11C20000 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CK_TOP_EMMC_400M>, - <&topckgen CK_TOP_EMMC_208M>, - <&infracfg_ao CK_INFRA_MSDC_CK>; - assigned-clocks = <&topckgen CK_TOP_EMMC_400M_SEL>, - <&topckgen CK_TOP_EMMC_208M_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_D2>, - <&topckgen CK_TOP_CB_M_D2>; + clocks = <&topckgen CLK_TOP_EMMC_400M>, + <&topckgen CLK_TOP_EMMC_208M>, + <&infracfg CLK_INFRA_MSDC_CK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>, + <&topckgen CLK_TOP_EMMC_208M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>, + <&topckgen CLK_TOP_CB_M_D2>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi index 30b5a899701..f871f2394c5 100644 --- a/arch/arm/dts/mt7986.dtsi +++ b/arch/arm/dts/mt7986.dtsi @@ -78,7 +78,7 @@ compatible = "mediatek,mt7986-timer"; reg = <0x10008000 0x1000>; interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg CK_INFRA_CK_F26M>; + clocks = <&topckgen CLK_TOP_F26M_SEL>; clock-names = "gpt-clk"; bootph-all; }; @@ -115,13 +115,6 @@ #clock-cells = <1>; }; - infracfg_ao: infracfg_ao@10001000 { - compatible = "mediatek,mt7986-infracfg_ao"; - reg = <0x10001000 0x68>; - clock-parent = <&infracfg>; - #clock-cells = <1>; - }; - infracfg: infracfg@10001040 { compatible = "mediatek,mt7986-infracfg"; reg = <0x10001000 0x1000>; @@ -154,18 +147,18 @@ #clock-cells = <1>; #pwm-cells = <2>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg CK_INFRA_PWM>, - <&infracfg_ao CK_INFRA_PWM_BSEL>, - <&infracfg_ao CK_INFRA_PWM1_CK>, - <&infracfg_ao CK_INFRA_PWM2_CK>; - assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, - <&infracfg CK_INFRA_PWM_BSEL>, - <&infracfg CK_INFRA_PWM1_SEL>, - <&infracfg CK_INFRA_PWM2_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, - <&infracfg CK_INFRA_PWM>, - <&infracfg CK_INFRA_PWM>, - <&infracfg CK_INFRA_PWM>; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_BSEL>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_BSEL>, + <&infracfg CLK_INFRA_PWM1_SEL>, + <&infracfg CLK_INFRA_PWM2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D4>, + <&topckgen CLK_TOP_PWM_SEL>, + <&topckgen CLK_TOP_PWM_SEL>, + <&topckgen CLK_TOP_PWM_SEL>; clock-names = "top", "main", "pwm1", "pwm2"; status = "disabled"; bootph-all; @@ -175,11 +168,11 @@ compatible = "mediatek,hsuart"; reg = <0x11002000 0x400>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao CK_INFRA_UART0_CK>; - assigned-clocks = <&topckgen CK_TOP_UART_SEL>, - <&infracfg_ao CK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg CK_INFRA_UART>; + clocks = <&infracfg CLK_INFRA_UART0_CK>; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; mediatek,force-highspeed; status = "disabled"; bootph-all; @@ -189,9 +182,9 @@ compatible = "mediatek,hsuart"; reg = <0x11003000 0x400>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao CK_INFRA_UART1_CK>; - assigned-clocks = <&infracfg CK_INFRA_UART1_SEL>; - assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; + clocks = <&infracfg CLK_INFRA_UART1_CK>; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -200,9 +193,9 @@ compatible = "mediatek,hsuart"; reg = <0x11004000 0x400>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao CK_INFRA_UART2_CK>; - assigned-clocks = <&infracfg CK_INFRA_UART2_SEL>; - assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; + clocks = <&infracfg CLK_INFRA_UART2_CK>; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; mediatek,force-highspeed; status = "disabled"; }; @@ -212,14 +205,14 @@ reg = <0x11005000 0x1000>, <0x11006000 0x1000>; reg-names = "nfi", "ecc"; - clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, - <&infracfg_ao CK_INFRA_NFI1_CK>, - <&infracfg_ao CK_INFRA_NFI_HCK_CK>; + clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, + <&infracfg CLK_INFRA_NFI1_CK>, + <&infracfg CLK_INFRA_NFI_HCK_CK>; clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, - <&topckgen CK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, - <&topckgen CK_TOP_CB_M_D8>; + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, + <&topckgen CLK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, + <&topckgen CLK_TOP_MPLL_D8>; status = "disabled"; }; @@ -258,12 +251,12 @@ spi0: spi@1100a000 { compatible = "mediatek,ipm-spi"; reg = <0x1100a000 0x100>; - clocks = <&infracfg_ao CK_INFRA_SPI0_CK>, - <&topckgen CK_TOP_SPI_SEL>; - assigned-clocks = <&topckgen CK_TOP_SPI_SEL>, - <&infracfg CK_INFRA_SPI0_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_D2>, - <&topckgen CK_INFRA_ISPI0>; + clocks = <&infracfg CLK_INFRA_SPI0_CK>, + <&topckgen CLK_TOP_SPI_SEL>; + assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>; clock-names = "sel-clk", "spi-clk"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -281,13 +274,13 @@ reg = <0x11230000 0x1000>, <0x11C20000 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CK_TOP_EMMC_416M>, - <&topckgen CK_TOP_EMMC_250M>, - <&infracfg_ao CK_INFRA_MSDC_CK>; - assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>, - <&topckgen CK_TOP_EMMC_250M_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>, - <&topckgen CK_TOP_NET1_D5_D2>; + clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, + <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&infracfg CLK_INFRA_MSDC_CK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, + <&topckgen CLK_TOP_EMMC_250M_SEL>; + assigned-clock-parents = <&fixed_plls CLK_APMIXED_MPLL>, + <&topckgen CLK_TOP_NET1PLL_D5_D2>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi index 5c0c5bcfd6e..e120e5084ce 100644 --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi @@ -97,13 +97,6 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; - infracfg_ao_cgs: infracfg_ao_cgs@10001000 { - compatible = "mediatek,mt7988-infracfg_ao_cgs", "syscon"; - reg = <0 0x10001000 0 0x1000>; - clock-parent = <&infracfg_ao>; - #clock-cells = <1>; - }; - apmixedsys: apmixedsys@1001e000 { compatible = "mediatek,mt7988-fixed-plls", "syscon"; reg = <0 0x1001e000 0 0x1000>; @@ -251,7 +244,7 @@ #clock-cells = <1>; }; - infracfg_ao: infracfg@10001000 { + infracfg: infracfg@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; clock-parent = <&topckgen>; @@ -262,11 +255,11 @@ compatible = "mediatek,hsuart"; reg = <0 0x11000000 0 0x100>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART0_CK>; - assigned-clocks = <&topckgen CK_TOP_UART_SEL>, - <&infracfg_ao CK_INFRA_MUX_UART0_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg_ao CK_INFRA_UART_O0>; + clocks = <&infracfg CLK_INFRA_52M_UART0_CK>; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status = "disabled"; }; @@ -274,11 +267,11 @@ compatible = "mediatek,hsuart"; reg = <0 0x11000100 0 0x100>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART1_CK>; - assigned-clocks = <&topckgen CK_TOP_UART_SEL>, - <&infracfg_ao CK_INFRA_MUX_UART1_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg_ao CK_INFRA_UART_O1>; + clocks = <&infracfg CLK_INFRA_52M_UART1_CK>; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status = "disabled"; }; @@ -286,11 +279,11 @@ compatible = "mediatek,hsuart"; reg = <0 0x11000200 0 0x100>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao_cgs CK_INFRA_52M_UART2_CK>; - assigned-clocks = <&topckgen CK_TOP_UART_SEL>, - <&infracfg_ao CK_INFRA_MUX_UART2_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, - <&infracfg_ao CK_INFRA_UART_O2>; + clocks = <&infracfg CLK_INFRA_52M_UART2_CK>; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status = "disabled"; }; @@ -301,8 +294,8 @@ <0 0x10217080 0 0x80>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; clock-div = <1>; - clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, - <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; @@ -316,8 +309,8 @@ <0 0x10217100 0 0x80>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; clock-div = <1>; - clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, - <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; @@ -331,8 +324,8 @@ <0 0x10217180 0 0x80>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clock-div = <1>; - clocks = <&infracfg_ao CK_INFRA_I2C_BCK>, - <&infracfg_ao CK_INFRA_66M_AP_DMA_BCK>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; #address-cells = <1>; #size-cells = <0>; @@ -343,16 +336,16 @@ compatible = "mediatek,mt7988-pwm"; reg = <0 0x10048000 0 0x1000>; #pwm-cells = <2>; - clocks = <&infracfg_ao CK_INFRA_66M_PWM_BCK>, - <&infracfg_ao CK_INFRA_66M_PWM_HCK>, - <&infracfg_ao CK_INFRA_66M_PWM_CK1>, - <&infracfg_ao CK_INFRA_66M_PWM_CK2>, - <&infracfg_ao CK_INFRA_66M_PWM_CK3>, - <&infracfg_ao CK_INFRA_66M_PWM_CK4>, - <&infracfg_ao CK_INFRA_66M_PWM_CK5>, - <&infracfg_ao CK_INFRA_66M_PWM_CK6>, - <&infracfg_ao CK_INFRA_66M_PWM_CK7>, - <&infracfg_ao CK_INFRA_66M_PWM_CK8>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4","pwm5","pwm6","pwm7","pwm8"; status = "disabled"; @@ -365,14 +358,14 @@ <0 0x11002000 0 0x1000>; reg-names = "nfi", "ecc"; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao CK_INFRA_SPINFI>, - <&infracfg_ao CK_INFRA_NFI>, - <&infracfg_ao CK_INFRA_66M_NFI_HCK>; + clocks = <&infracfg CLK_INFRA_SPINFI>, + <&infracfg CLK_INFRA_NFI>, + <&infracfg CLK_INFRA_66M_NFI_HCK>; clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, - <&topckgen CK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, - <&topckgen CK_TOP_CB_M_D8>; + assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, + <&topckgen CLK_TOP_NFI1X_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>, + <&topckgen CLK_TOP_MPLL_D8>; status = "disabled"; }; @@ -408,10 +401,10 @@ "mediatek,mt7986-mmc"; reg = <0 0x11230000 0 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg_ao_cgs CK_INFRA_MSDC400>, - <&infracfg_ao_cgs CK_INFRA_MSDC2_HCK>, - <&infracfg_ao_cgs CK_INFRA_133M_MSDC_0_HCK>, - <&infracfg_ao_cgs CK_INFRA_66M_MSDC_0_HCK>; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>; clock-names = "source", "hclk", "source_cg", "axi_cg"; status = "disabled"; }; diff --git a/arch/arm/dts/omap3-sniper-u-boot.dtsi b/arch/arm/dts/omap3-sniper-u-boot.dtsi new file mode 100644 index 00000000000..d467f533a12 --- /dev/null +++ b/arch/arm/dts/omap3-sniper-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Paul Kocialkowski <contact@paulk.fr> + */ + +#include "omap3-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; +}; + +&i2c1 { + clock-frequency = <400000>; +}; diff --git a/arch/arm/dts/px30-firefly.dts b/arch/arm/dts/px30-firefly.dts index c0a8e3009ad..e678d6a0b28 100644 --- a/arch/arm/dts/px30-firefly.dts +++ b/arch/arm/dts/px30-firefly.dts @@ -13,6 +13,10 @@ model = "Firefly Core-PX30-JD4"; compatible = "rockchip,px30-firefly", "rockchip,px30"; + aliases { + ethernet0 = &gmac; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 59fa9f43a97..abc6b49e666 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -99,16 +99,20 @@ &gpio0 { bootph-all; + gpio-ranges = <&pinctrl 0 0 32>; }; &gpio1 { bootph-all; + gpio-ranges = <&pinctrl 0 32 32>; }; &gpio2 { bootph-all; + gpio-ranges = <&pinctrl 0 64 32>; }; &gpio3 { bootph-all; + gpio-ranges = <&pinctrl 0 96 32>; }; diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi deleted file mode 100644 index 3152bf107db..00000000000 --- a/arch/arm/dts/px30.dtsi +++ /dev/null @@ -1,2415 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/clock/px30-cru.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/power/px30-power.h> -#include <dt-bindings/soc/rockchip,boot-mode.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - compatible = "rockchip,px30"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - ethernet0 = &gmac; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - spi0 = &spi0; - spi1 = &spi1; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x0>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x1>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x2>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a35"; - reg = <0x0 0x3>; - enable-method = "psci"; - clocks = <&cru ARMCLK>; - #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; - dynamic-power-coefficient = <90>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - idle-states { - entry-method = "psci"; - - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <120>; - exit-latency-us = <250>; - min-residency-us = <900>; - }; - - CLUSTER_SLEEP: cluster-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x1010000>; - entry-latency-us = <400>; - exit-latency-us = <500>; - min-residency-us = <2000>; - }; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000 950000 1350000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1050000 1050000 1350000>; - clock-latency-ns = <40000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000 1175000 1350000>; - clock-latency-ns = <40000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1300000 1300000 1350000>; - clock-latency-ns = <40000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1350000 1350000 1350000>; - clock-latency-ns = <40000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a35-pmu"; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vopb_out>, <&vopl_out>; - status = "disabled"; - }; - - gmac_clkin: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "gmac_clkin"; - #clock-cells = <0>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - thermal_zones: thermal-zones { - soc_thermal: soc-thermal { - polling-delay-passive = <20>; - polling-delay = <1000>; - sustainable-power = <750>; - thermal-sensors = <&tsadc 0>; - - trips { - threshold: trip-point-0 { - temperature = <70000>; - hysteresis = <2000>; - type = "passive"; - }; - - target: trip-point-1 { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - - soc_crit: soc-crit { - temperature = <115000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&target>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - - map1 { - trip = <&target>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - contribution = <4096>; - }; - }; - }; - - gpu_thermal: gpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <1000>; /* milliseconds */ - thermal-sensors = <&tsadc 1>; - }; - }; - - xin24m: xin24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - }; - - pmu: power-management@ff000000 { - compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xff000000 0x0 0x1000>; - - power: power-controller { - compatible = "rockchip,px30-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - /* These power domains are grouped by VD_LOGIC */ - power-domain@PX30_PD_USB { - reg = <PX30_PD_USB>; - clocks = <&cru HCLK_HOST>, - <&cru HCLK_OTG>, - <&cru SCLK_OTG_ADP>; - pm_qos = <&qos_usb_host>, <&qos_usb_otg>; - #power-domain-cells = <0>; - }; - power-domain@PX30_PD_SDCARD { - reg = <PX30_PD_SDCARD>; - clocks = <&cru HCLK_SDMMC>, - <&cru SCLK_SDMMC>; - pm_qos = <&qos_sdmmc>; - #power-domain-cells = <0>; - }; - power-domain@PX30_PD_GMAC { - reg = <PX30_PD_GMAC>; - clocks = <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>, - <&cru SCLK_MAC_REF>, - <&cru SCLK_GMAC_RX_TX>; - pm_qos = <&qos_gmac>; - #power-domain-cells = <0>; - }; - power-domain@PX30_PD_MMC_NAND { - reg = <PX30_PD_MMC_NAND>; - clocks = <&cru HCLK_NANDC>, - <&cru HCLK_EMMC>, - <&cru HCLK_SDIO>, - <&cru HCLK_SFC>, - <&cru SCLK_EMMC>, - <&cru SCLK_NANDC>, - <&cru SCLK_SDIO>, - <&cru SCLK_SFC>; - pm_qos = <&qos_emmc>, <&qos_nand>, - <&qos_sdio>, <&qos_sfc>; - #power-domain-cells = <0>; - }; - power-domain@PX30_PD_VPU { - reg = <PX30_PD_VPU>; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>, - <&cru SCLK_CORE_VPU>; - pm_qos = <&qos_vpu>, <&qos_vpu_r128>; - #power-domain-cells = <0>; - }; - power-domain@PX30_PD_VO { - reg = <PX30_PD_VO>; - clocks = <&cru ACLK_RGA>, - <&cru ACLK_VOPB>, - <&cru ACLK_VOPL>, - <&cru DCLK_VOPB>, - <&cru DCLK_VOPL>, - <&cru HCLK_RGA>, - <&cru HCLK_VOPB>, - <&cru HCLK_VOPL>, - <&cru PCLK_MIPI_DSI>, - <&cru SCLK_RGA_CORE>, - <&cru SCLK_VOPB_PWM>; - pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, - <&qos_vop_m0>, <&qos_vop_m1>; - #power-domain-cells = <0>; - }; - power-domain@PX30_PD_VI { - reg = <PX30_PD_VI>; - clocks = <&cru ACLK_CIF>, - <&cru ACLK_ISP>, - <&cru HCLK_CIF>, - <&cru HCLK_ISP>, - <&cru SCLK_ISP>; - pm_qos = <&qos_isp_128>, <&qos_isp_rd>, - <&qos_isp_wr>, <&qos_isp_m1>, - <&qos_vip>; - #power-domain-cells = <0>; - }; - power-domain@PX30_PD_GPU { - reg = <PX30_PD_GPU>; - clocks = <&cru SCLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; - }; - - pmugrf: syscon@ff010000 { - compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xff010000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - pmu_io_domains: io-domains { - compatible = "rockchip,px30-pmu-io-voltage-domain"; - status = "disabled"; - }; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x200>; - mode-bootloader = <BOOT_BL_DOWNLOAD>; - mode-fastboot = <BOOT_FASTBOOT>; - mode-loader = <BOOT_BL_DOWNLOAD>; - mode-normal = <BOOT_NORMAL>; - mode-recovery = <BOOT_RECOVERY>; - }; - }; - - uart0: serial@ff030000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff030000 0x0 0x100>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 0>, <&dmac 1>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - status = "disabled"; - }; - - i2s0_8ch: i2s@ff060000 { - compatible = "rockchip,px30-i2s-tdm"; - reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac 16>, <&dmac 17>; - dma-names = "tx", "rx"; - rockchip,grf = <&grf>; - resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; - reset-names = "tx-m", "rx-m"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx - &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx - &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 - &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 - &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 - &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_2ch: i2s@ff070000 { - compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 18>, <&dmac 19>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck - &i2s1_2ch_sdi &i2s1_2ch_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@ff080000 { - compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xff080000 0x0 0x1000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; - clock-names = "i2s_clk", "i2s_hclk"; - dmas = <&dmac 20>, <&dmac 21>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck - &i2s2_2ch_sdi &i2s2_2ch_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@ff131000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0xff131000 0 0x1000>, - <0x0 0xff132000 0 0x2000>, - <0x0 0xff134000 0 0x2000>, - <0x0 0xff136000 0 0x2000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - grf: syscon@ff140000 { - compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; - reg = <0x0 0xff140000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,px30-io-voltage-domain"; - status = "disabled"; - }; - - lvds: lvds { - compatible = "rockchip,px30-lvds"; - phys = <&dsi_dphy>; - phy-names = "dphy"; - rockchip,grf = <&grf>; - rockchip,output = "lvds"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - lvds_vopb_in: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_lvds>; - }; - - lvds_vopl_in: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_lvds>; - }; - }; - }; - }; - }; - - uart1: serial@ff158000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff158000 0x0 0x100>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 2>, <&dmac 3>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; - status = "disabled"; - }; - - uart2: serial@ff160000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff160000 0x0 0x100>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 4>, <&dmac 5>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart2m0_xfer>; - status = "disabled"; - }; - - uart3: serial@ff168000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff168000 0x0 0x100>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 6>, <&dmac 7>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; - status = "disabled"; - }; - - uart4: serial@ff170000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff170000 0x0 0x100>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 8>, <&dmac 9>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; - status = "disabled"; - }; - - uart5: serial@ff178000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff178000 0x0 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac 10>, <&dmac 11>; - dma-names = "tx", "rx"; - reg-shift = <2>; - reg-io-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; - status = "disabled"; - }; - - i2c0: i2c@ff180000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff180000 0x0 0x1000>; - clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@ff190000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff190000 0x0 0x1000>; - clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@ff1a0000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff1a0000 0x0 0x1000>; - clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@ff1b0000 { - compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xff1b0000 0x0 0x1000>; - clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@ff1d0000 { - compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1d0000 0x0 0x1000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 12>, <&dmac 13>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@ff1d8000 { - compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xff1d8000 0x0 0x1000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac 14>, <&dmac 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - wdt: watchdog@ff1e0000 { - compatible = "rockchip,px30-wdt", "snps,dw-wdt"; - reg = <0x0 0xff1e0000 0x0 0x100>; - clocks = <&cru PCLK_WDT_NS>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pwm0: pwm@ff200000 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200000 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@ff200010 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200010 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@ff200020 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200020 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@ff200030 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff200030 0x0 0x10>; - clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm4: pwm@ff208000 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208000 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@ff208010 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208010 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm5_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@ff208020 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208020 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm6_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@ff208030 { - compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xff208030 0x0 0x10>; - clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pin>; - #pwm-cells = <3>; - status = "disabled"; - }; - - rktimer: timer@ff210000 { - compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xff210000 0x0 0x1000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; - clock-names = "pclk", "timer"; - }; - - dmac: dma-controller@ff240000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xff240000 0x0 0x4000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - tsadc: tsadc@ff280000 { - compatible = "rockchip,px30-tsadc"; - reg = <0x0 0xff280000 0x0 0x100>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <50000>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - rockchip,grf = <&grf>; - rockchip,hw-tshut-temp = <120000>; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&tsadc_otp_pin>; - pinctrl-1 = <&tsadc_otp_out>; - pinctrl-2 = <&tsadc_otp_pin>; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: saradc@ff288000 { - compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; - reg = <0x0 0xff288000 0x0 0x100>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - #io-channel-cells = <1>; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC_P>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - otp: nvmem@ff290000 { - compatible = "rockchip,px30-otp"; - reg = <0x0 0xff290000 0x0 0x4000>; - clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, - <&cru PCLK_OTP_PHY>; - clock-names = "otp", "apb_pclk", "phy"; - resets = <&cru SRST_OTP_PHY>; - reset-names = "phy"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - cpu_id: id@7 { - reg = <0x07 0x10>; - }; - cpu_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - performance: performance@1e { - reg = <0x1e 0x1>; - bits = <4 3>; - }; - }; - - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - clocks = <&xin24m>, <&pmucru PLL_GPLL>; - clock-names = "xin24m", "gpll"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>; - }; - - pmucru: clock-controller@ff2bc000 { - compatible = "rockchip,px30-pmucru"; - reg = <0x0 0xff2bc000 0x0 0x1000>; - clocks = <&xin24m>; - clock-names = "xin24m"; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - - assigned-clocks = - <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, - <&pmucru SCLK_WIFI_PMU>; - assigned-clock-rates = - <1200000000>, <100000000>, - <26000000>; - }; - - usb2phy_grf: syscon@ff2c0000 { - compatible = "rockchip,px30-usb2phy-grf", "syscon", - "simple-mfd"; - reg = <0x0 0xff2c0000 0x0 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy: usb2phy@100 { - compatible = "rockchip,px30-usb2phy"; - reg = <0x100 0x20>; - clocks = <&pmucru SCLK_USBPHY_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - assigned-clocks = <&cru USB480M>; - assigned-clock-parents = <&u2phy>; - clock-output-names = "usb480m_phy"; - status = "disabled"; - - u2phy_host: host-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy_otg: otg-port { - #phy-cells = <0>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - }; - - dsi_dphy: phy@ff2e0000 { - compatible = "rockchip,px30-dsi-dphy"; - reg = <0x0 0xff2e0000 0x0 0x10000>; - clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; - clock-names = "ref", "pclk"; - resets = <&cru SRST_MIPIDSIPHY_P>; - reset-names = "apb"; - #phy-cells = <0>; - power-domains = <&power PX30_PD_VO>; - status = "disabled"; - }; - - csi_dphy: phy@ff2f0000 { - compatible = "rockchip,px30-csi-dphy"; - reg = <0x0 0xff2f0000 0x0 0x4000>; - clocks = <&cru PCLK_MIPICSIPHY>; - clock-names = "pclk"; - #phy-cells = <0>; - power-domains = <&power PX30_PD_VI>; - resets = <&cru SRST_MIPICSIPHY_P>; - reset-names = "apb"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - usb20_otg: usb@ff300000 { - compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x0 0xff300000 0x0 0x40000>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy_otg>; - phy-names = "usb2-phy"; - power-domains = <&power PX30_PD_USB>; - status = "disabled"; - }; - - usb_host0_ehci: usb@ff340000 { - compatible = "generic-ehci"; - reg = <0x0 0xff340000 0x0 0x10000>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST>; - phys = <&u2phy_host>; - phy-names = "usb"; - power-domains = <&power PX30_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@ff350000 { - compatible = "generic-ohci"; - reg = <0x0 0xff350000 0x0 0x10000>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_HOST>; - phys = <&u2phy_host>; - phy-names = "usb"; - power-domains = <&power PX30_PD_USB>; - status = "disabled"; - }; - - gmac: ethernet@ff360000 { - compatible = "rockchip,px30-gmac"; - reg = <0x0 0xff360000 0x0 0x10000>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, - <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac", "clk_mac_speed"; - rockchip,grf = <&grf>; - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; - power-domains = <&power PX30_PD_GMAC>; - resets = <&cru SRST_GMAC_A>; - reset-names = "stmmaceth"; - status = "disabled"; - }; - - sdmmc: mmc@ff370000 { - compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff370000 0x0 0x4000>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <4>; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - power-domains = <&power PX30_PD_SDCARD>; - status = "disabled"; - }; - - sdio: mmc@ff380000 { - compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff380000 0x0 0x4000>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <4>; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; - power-domains = <&power PX30_PD_MMC_NAND>; - status = "disabled"; - }; - - emmc: mmc@ff390000 { - compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff390000 0x0 0x4000>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - fifo-depth = <0x100>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - power-domains = <&power PX30_PD_MMC_NAND>; - status = "disabled"; - }; - - sfc: spi@ff3a0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xff3a0000 0x0 0x4000>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; - pinctrl-names = "default"; - power-domains = <&power PX30_PD_MMC_NAND>; - status = "disabled"; - }; - - nfc: nand-controller@ff3b0000 { - compatible = "rockchip,px30-nfc"; - reg = <0x0 0xff3b0000 0x0 0x4000>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; - clock-names = "ahb", "nfc"; - assigned-clocks = <&cru SCLK_NANDC>; - assigned-clock-rates = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 - &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; - power-domains = <&power PX30_PD_MMC_NAND>; - status = "disabled"; - }; - - gpu_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <950000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <975000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - }; - opp-480000000 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <1125000>; - }; - }; - - gpu: gpu@ff400000 { - compatible = "rockchip,px30-mali", "arm,mali-bifrost"; - reg = <0x0 0xff400000 0x0 0x4000>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "job", "mmu", "gpu"; - clocks = <&cru SCLK_GPU>; - #cooling-cells = <2>; - power-domains = <&power PX30_PD_GPU>; - operating-points-v2 = <&gpu_opp_table>; - status = "disabled"; - }; - - vpu: video-codec@ff442000 { - compatible = "rockchip,px30-vpu"; - reg = <0x0 0xff442000 0x0 0x800>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power PX30_PD_VPU>; - }; - - vpu_mmu: iommu@ff442800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff442800 0x0 0x100>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power PX30_PD_VPU>; - }; - - dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; - reg = <0x0 0xff450000 0x0 0x10000>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_MIPI_DSI>; - clock-names = "pclk"; - phys = <&dsi_dphy>; - phy-names = "dphy"; - power-domains = <&power PX30_PD_VO>; - resets = <&cru SRST_MIPIDSI_HOST_P>; - reset-names = "apb"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - dsi_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_dsi>; - }; - - dsi_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_dsi>; - }; - }; - }; - }; - - vopb: vop@ff460000 { - compatible = "rockchip,px30-vop-big"; - reg = <0x0 0xff460000 0x0 0xefc>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, - <&cru HCLK_VOPB>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - power-domains = <&power PX30_PD_VO>; - status = "disabled"; - - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopb_out_dsi: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in_vopb>; - }; - - vopb_out_lvds: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds_vopb_in>; - }; - }; - }; - - vopb_mmu: iommu@ff460f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff460f00 0x0 0x100>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; - clock-names = "aclk", "iface"; - power-domains = <&power PX30_PD_VO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - vopl: vop@ff470000 { - compatible = "rockchip,px30-vop-lit"; - reg = <0x0 0xff470000 0x0 0xefc>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, - <&cru HCLK_VOPL>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopl_mmu>; - power-domains = <&power PX30_PD_VO>; - status = "disabled"; - - vopl_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vopl_out_dsi: endpoint@0 { - reg = <0>; - remote-endpoint = <&dsi_in_vopl>; - }; - - vopl_out_lvds: endpoint@1 { - reg = <1>; - remote-endpoint = <&lvds_vopl_in>; - }; - }; - }; - - vopl_mmu: iommu@ff470f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff470f00 0x0 0x100>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; - clock-names = "aclk", "iface"; - power-domains = <&power PX30_PD_VO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - isp: isp@ff4a0000 { - compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ - reg = <0x0 0xff4a0000 0x0 0x8000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "isp", "mi", "mipi"; - clocks = <&cru SCLK_ISP>, - <&cru ACLK_ISP>, - <&cru HCLK_ISP>, - <&cru PCLK_ISP>; - clock-names = "isp", "aclk", "hclk", "pclk"; - iommus = <&isp_mmu>; - phys = <&csi_dphy>; - phy-names = "dphy"; - power-domains = <&power PX30_PD_VI>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - }; - - isp_mmu: iommu@ff4a8000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff4a8000 0x0 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - power-domains = <&power PX30_PD_VI>; - rockchip,disable-mmu-reset; - #iommu-cells = <0>; - }; - - qos_gmac: qos@ff518000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff518000 0x0 0x20>; - }; - - qos_gpu: qos@ff520000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff520000 0x0 0x20>; - }; - - qos_sdmmc: qos@ff52c000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff52c000 0x0 0x20>; - }; - - qos_emmc: qos@ff538000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538000 0x0 0x20>; - }; - - qos_nand: qos@ff538080 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538080 0x0 0x20>; - }; - - qos_sdio: qos@ff538100 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538100 0x0 0x20>; - }; - - qos_sfc: qos@ff538180 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538180 0x0 0x20>; - }; - - qos_usb_host: qos@ff540000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff540000 0x0 0x20>; - }; - - qos_usb_otg: qos@ff540080 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff540080 0x0 0x20>; - }; - - qos_isp_128: qos@ff548000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548000 0x0 0x20>; - }; - - qos_isp_rd: qos@ff548080 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548080 0x0 0x20>; - }; - - qos_isp_wr: qos@ff548100 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548100 0x0 0x20>; - }; - - qos_isp_m1: qos@ff548180 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548180 0x0 0x20>; - }; - - qos_vip: qos@ff548200 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548200 0x0 0x20>; - }; - - qos_rga_rd: qos@ff550000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550000 0x0 0x20>; - }; - - qos_rga_wr: qos@ff550080 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550080 0x0 0x20>; - }; - - qos_vop_m0: qos@ff550100 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550100 0x0 0x20>; - }; - - qos_vop_m1: qos@ff550180 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550180 0x0 0x20>; - }; - - qos_vpu: qos@ff558000 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff558000 0x0 0x20>; - }; - - qos_vpu_r128: qos@ff558080 { - compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff558080 0x0 0x20>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,px30-pinctrl"; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmugrf>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gpio0: gpio@ff040000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff040000 0x0 0x100>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru PCLK_GPIO0_PMU>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@ff250000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff250000 0x0 0x100>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@ff260000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff260000 0x0 0x100>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@ff270000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xff270000 0x0 0x100>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_2ma: pcfg-pull-none-2ma { - bias-disable; - drive-strength = <2>; - }; - - pcfg_pull_up_2ma: pcfg-pull-up-2ma { - bias-pull-up; - drive-strength = <2>; - }; - - pcfg_pull_up_4ma: pcfg-pull-up-4ma { - bias-pull-up; - drive-strength = <4>; - }; - - pcfg_pull_none_4ma: pcfg-pull-none-4ma { - bias-disable; - drive-strength = <4>; - }; - - pcfg_pull_down_4ma: pcfg-pull-down-4ma { - bias-pull-down; - drive-strength = <4>; - }; - - pcfg_pull_none_8ma: pcfg-pull-none-8ma { - bias-disable; - drive-strength = <8>; - }; - - pcfg_pull_up_8ma: pcfg-pull-up-8ma { - bias-pull-up; - drive-strength = <8>; - }; - - pcfg_pull_none_12ma: pcfg-pull-none-12ma { - bias-disable; - drive-strength = <12>; - }; - - pcfg_pull_up_12ma: pcfg-pull-up-12ma { - bias-pull-up; - drive-strength = <12>; - }; - - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - pcfg_output_high: pcfg-output-high { - output-high; - }; - - pcfg_output_low: pcfg-output-low { - output-low; - }; - - pcfg_input_high: pcfg-input-high { - bias-pull-up; - input-enable; - }; - - pcfg_input: pcfg-input { - input-enable; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = - <0 RK_PB0 1 &pcfg_pull_none_smt>, - <0 RK_PB1 1 &pcfg_pull_none_smt>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = - <0 RK_PC2 1 &pcfg_pull_none_smt>, - <0 RK_PC3 1 &pcfg_pull_none_smt>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = - <2 RK_PB7 2 &pcfg_pull_none_smt>, - <2 RK_PC0 2 &pcfg_pull_none_smt>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = - <1 RK_PB4 4 &pcfg_pull_none_smt>, - <1 RK_PB5 4 &pcfg_pull_none_smt>; - }; - }; - - tsadc { - tsadc_otp_pin: tsadc-otp-pin { - rockchip,pins = - <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - tsadc_otp_out: tsadc-otp-out { - rockchip,pins = - <0 RK_PA6 1 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = - <0 RK_PB2 1 &pcfg_pull_up>, - <0 RK_PB3 1 &pcfg_pull_up>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = - <0 RK_PB4 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = - <0 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = - <1 RK_PC1 1 &pcfg_pull_up>, - <1 RK_PC0 1 &pcfg_pull_up>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = - <1 RK_PC2 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = - <1 RK_PC3 1 &pcfg_pull_none>; - }; - }; - - uart2-m0 { - uart2m0_xfer: uart2m0-xfer { - rockchip,pins = - <1 RK_PD2 2 &pcfg_pull_up>, - <1 RK_PD3 2 &pcfg_pull_up>; - }; - }; - - uart2-m1 { - uart2m1_xfer: uart2m1-xfer { - rockchip,pins = - <2 RK_PB4 2 &pcfg_pull_up>, - <2 RK_PB6 2 &pcfg_pull_up>; - }; - }; - - uart3-m0 { - uart3m0_xfer: uart3m0-xfer { - rockchip,pins = - <0 RK_PC0 2 &pcfg_pull_up>, - <0 RK_PC1 2 &pcfg_pull_up>; - }; - - uart3m0_cts: uart3m0-cts { - rockchip,pins = - <0 RK_PC2 2 &pcfg_pull_none>; - }; - - uart3m0_rts: uart3m0-rts { - rockchip,pins = - <0 RK_PC3 2 &pcfg_pull_none>; - }; - }; - - uart3-m1 { - uart3m1_xfer: uart3m1-xfer { - rockchip,pins = - <1 RK_PB6 2 &pcfg_pull_up>, - <1 RK_PB7 2 &pcfg_pull_up>; - }; - - uart3m1_cts: uart3m1-cts { - rockchip,pins = - <1 RK_PB4 2 &pcfg_pull_none>; - }; - - uart3m1_rts: uart3m1-rts { - rockchip,pins = - <1 RK_PB5 2 &pcfg_pull_none>; - }; - }; - - uart4 { - uart4_xfer: uart4-xfer { - rockchip,pins = - <1 RK_PD4 2 &pcfg_pull_up>, - <1 RK_PD5 2 &pcfg_pull_up>; - }; - - uart4_cts: uart4-cts { - rockchip,pins = - <1 RK_PD6 2 &pcfg_pull_none>; - }; - - uart4_rts: uart4-rts { - rockchip,pins = - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - uart5 { - uart5_xfer: uart5-xfer { - rockchip,pins = - <3 RK_PA2 4 &pcfg_pull_up>, - <3 RK_PA1 4 &pcfg_pull_up>; - }; - - uart5_cts: uart5-cts { - rockchip,pins = - <3 RK_PA3 4 &pcfg_pull_none>; - }; - - uart5_rts: uart5-rts { - rockchip,pins = - <3 RK_PA5 4 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = - <1 RK_PB7 3 &pcfg_pull_up_4ma>; - }; - - spi0_csn: spi0-csn { - rockchip,pins = - <1 RK_PB6 3 &pcfg_pull_up_4ma>; - }; - - spi0_miso: spi0-miso { - rockchip,pins = - <1 RK_PB5 3 &pcfg_pull_up_4ma>; - }; - - spi0_mosi: spi0-mosi { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_up_4ma>; - }; - - spi0_clk_hs: spi0-clk-hs { - rockchip,pins = - <1 RK_PB7 3 &pcfg_pull_up_8ma>; - }; - - spi0_miso_hs: spi0-miso-hs { - rockchip,pins = - <1 RK_PB5 3 &pcfg_pull_up_8ma>; - }; - - spi0_mosi_hs: spi0-mosi-hs { - rockchip,pins = - <1 RK_PB4 3 &pcfg_pull_up_8ma>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = - <3 RK_PB7 4 &pcfg_pull_up_4ma>; - }; - - spi1_csn0: spi1-csn0 { - rockchip,pins = - <3 RK_PB1 4 &pcfg_pull_up_4ma>; - }; - - spi1_csn1: spi1-csn1 { - rockchip,pins = - <3 RK_PB2 2 &pcfg_pull_up_4ma>; - }; - - spi1_miso: spi1-miso { - rockchip,pins = - <3 RK_PB6 4 &pcfg_pull_up_4ma>; - }; - - spi1_mosi: spi1-mosi { - rockchip,pins = - <3 RK_PB4 4 &pcfg_pull_up_4ma>; - }; - - spi1_clk_hs: spi1-clk-hs { - rockchip,pins = - <3 RK_PB7 4 &pcfg_pull_up_8ma>; - }; - - spi1_miso_hs: spi1-miso-hs { - rockchip,pins = - <3 RK_PB6 4 &pcfg_pull_up_8ma>; - }; - - spi1_mosi_hs: spi1-mosi-hs { - rockchip,pins = - <3 RK_PB4 4 &pcfg_pull_up_8ma>; - }; - }; - - pdm { - pdm_clk0m0: pdm-clk0m0 { - rockchip,pins = - <3 RK_PC6 2 &pcfg_pull_none>; - }; - - pdm_clk0m1: pdm-clk0m1 { - rockchip,pins = - <2 RK_PC6 1 &pcfg_pull_none>; - }; - - pdm_clk1: pdm-clk1 { - rockchip,pins = - <3 RK_PC7 2 &pcfg_pull_none>; - }; - - pdm_sdi0m0: pdm-sdi0m0 { - rockchip,pins = - <3 RK_PD3 2 &pcfg_pull_none>; - }; - - pdm_sdi0m1: pdm-sdi0m1 { - rockchip,pins = - <2 RK_PC5 2 &pcfg_pull_none>; - }; - - pdm_sdi1: pdm-sdi1 { - rockchip,pins = - <3 RK_PD0 2 &pcfg_pull_none>; - }; - - pdm_sdi2: pdm-sdi2 { - rockchip,pins = - <3 RK_PD1 2 &pcfg_pull_none>; - }; - - pdm_sdi3: pdm-sdi3 { - rockchip,pins = - <3 RK_PD2 2 &pcfg_pull_none>; - }; - - pdm_clk0m0_sleep: pdm-clk0m0-sleep { - rockchip,pins = - <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_clk0m_sleep1: pdm-clk0m1-sleep { - rockchip,pins = - <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_clk1_sleep: pdm-clk1-sleep { - rockchip,pins = - <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { - rockchip,pins = - <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { - rockchip,pins = - <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi1_sleep: pdm-sdi1-sleep { - rockchip,pins = - <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi2_sleep: pdm-sdi2-sleep { - rockchip,pins = - <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; - }; - - pdm_sdi3_sleep: pdm-sdi3-sleep { - rockchip,pins = - <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; - }; - }; - - i2s0 { - i2s0_8ch_mclk: i2s0-8ch-mclk { - rockchip,pins = - <3 RK_PC1 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sclktx: i2s0-8ch-sclktx { - rockchip,pins = - <3 RK_PC3 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { - rockchip,pins = - <3 RK_PB4 2 &pcfg_pull_none>; - }; - - i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { - rockchip,pins = - <3 RK_PC2 2 &pcfg_pull_none>; - }; - - i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { - rockchip,pins = - <3 RK_PB5 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo0: i2s0-8ch-sdo0 { - rockchip,pins = - <3 RK_PC4 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo1: i2s0-8ch-sdo1 { - rockchip,pins = - <3 RK_PC0 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo2: i2s0-8ch-sdo2 { - rockchip,pins = - <3 RK_PB7 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdo3: i2s0-8ch-sdo3 { - rockchip,pins = - <3 RK_PB6 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi0: i2s0-8ch-sdi0 { - rockchip,pins = - <3 RK_PC5 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi1: i2s0-8ch-sdi1 { - rockchip,pins = - <3 RK_PB3 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi2: i2s0-8ch-sdi2 { - rockchip,pins = - <3 RK_PB1 2 &pcfg_pull_none>; - }; - - i2s0_8ch_sdi3: i2s0-8ch-sdi3 { - rockchip,pins = - <3 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - i2s1 { - i2s1_2ch_mclk: i2s1-2ch-mclk { - rockchip,pins = - <2 RK_PC3 1 &pcfg_pull_none>; - }; - - i2s1_2ch_sclk: i2s1-2ch-sclk { - rockchip,pins = - <2 RK_PC2 1 &pcfg_pull_none>; - }; - - i2s1_2ch_lrck: i2s1-2ch-lrck { - rockchip,pins = - <2 RK_PC1 1 &pcfg_pull_none>; - }; - - i2s1_2ch_sdi: i2s1-2ch-sdi { - rockchip,pins = - <2 RK_PC5 1 &pcfg_pull_none>; - }; - - i2s1_2ch_sdo: i2s1-2ch-sdo { - rockchip,pins = - <2 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2s2 { - i2s2_2ch_mclk: i2s2-2ch-mclk { - rockchip,pins = - <3 RK_PA1 2 &pcfg_pull_none>; - }; - - i2s2_2ch_sclk: i2s2-2ch-sclk { - rockchip,pins = - <3 RK_PA2 2 &pcfg_pull_none>; - }; - - i2s2_2ch_lrck: i2s2-2ch-lrck { - rockchip,pins = - <3 RK_PA3 2 &pcfg_pull_none>; - }; - - i2s2_2ch_sdi: i2s2-2ch-sdi { - rockchip,pins = - <3 RK_PA5 2 &pcfg_pull_none>; - }; - - i2s2_2ch_sdo: i2s2-2ch-sdo { - rockchip,pins = - <3 RK_PA7 2 &pcfg_pull_none>; - }; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = - <1 RK_PD6 1 &pcfg_pull_none_8ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = - <1 RK_PD7 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_det: sdmmc-det { - rockchip,pins = - <0 RK_PA3 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = - <1 RK_PD2 1 &pcfg_pull_up_8ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = - <1 RK_PD2 1 &pcfg_pull_up_8ma>, - <1 RK_PD3 1 &pcfg_pull_up_8ma>, - <1 RK_PD4 1 &pcfg_pull_up_8ma>, - <1 RK_PD5 1 &pcfg_pull_up_8ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = - <1 RK_PC5 1 &pcfg_pull_none>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = - <1 RK_PC4 1 &pcfg_pull_up>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = - <1 RK_PC6 1 &pcfg_pull_up>, - <1 RK_PC7 1 &pcfg_pull_up>, - <1 RK_PD0 1 &pcfg_pull_up>, - <1 RK_PD1 1 &pcfg_pull_up>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = - <1 RK_PB1 2 &pcfg_pull_none_8ma>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = - <1 RK_PB2 2 &pcfg_pull_up_8ma>; - }; - - emmc_rstnout: emmc-rstnout { - rockchip,pins = - <1 RK_PB3 2 &pcfg_pull_none>; - }; - - emmc_bus1: emmc-bus1 { - rockchip,pins = - <1 RK_PA0 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus4: emmc-bus4 { - rockchip,pins = - <1 RK_PA0 2 &pcfg_pull_up_8ma>, - <1 RK_PA1 2 &pcfg_pull_up_8ma>, - <1 RK_PA2 2 &pcfg_pull_up_8ma>, - <1 RK_PA3 2 &pcfg_pull_up_8ma>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = - <1 RK_PA0 2 &pcfg_pull_up_8ma>, - <1 RK_PA1 2 &pcfg_pull_up_8ma>, - <1 RK_PA2 2 &pcfg_pull_up_8ma>, - <1 RK_PA3 2 &pcfg_pull_up_8ma>, - <1 RK_PA4 2 &pcfg_pull_up_8ma>, - <1 RK_PA5 2 &pcfg_pull_up_8ma>, - <1 RK_PA6 2 &pcfg_pull_up_8ma>, - <1 RK_PA7 2 &pcfg_pull_up_8ma>; - }; - }; - - flash { - flash_cs0: flash-cs0 { - rockchip,pins = - <1 RK_PB0 1 &pcfg_pull_none>; - }; - - flash_rdy: flash-rdy { - rockchip,pins = - <1 RK_PB1 1 &pcfg_pull_none>; - }; - - flash_dqs: flash-dqs { - rockchip,pins = - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - flash_ale: flash-ale { - rockchip,pins = - <1 RK_PB3 1 &pcfg_pull_none>; - }; - - flash_cle: flash-cle { - rockchip,pins = - <1 RK_PB4 1 &pcfg_pull_none>; - }; - - flash_wrn: flash-wrn { - rockchip,pins = - <1 RK_PB5 1 &pcfg_pull_none>; - }; - - flash_csl: flash-csl { - rockchip,pins = - <1 RK_PB6 1 &pcfg_pull_none>; - }; - - flash_rdn: flash-rdn { - rockchip,pins = - <1 RK_PB7 1 &pcfg_pull_none>; - }; - - flash_bus8: flash-bus8 { - rockchip,pins = - <1 RK_PA0 1 &pcfg_pull_up_12ma>, - <1 RK_PA1 1 &pcfg_pull_up_12ma>, - <1 RK_PA2 1 &pcfg_pull_up_12ma>, - <1 RK_PA3 1 &pcfg_pull_up_12ma>, - <1 RK_PA4 1 &pcfg_pull_up_12ma>, - <1 RK_PA5 1 &pcfg_pull_up_12ma>, - <1 RK_PA6 1 &pcfg_pull_up_12ma>, - <1 RK_PA7 1 &pcfg_pull_up_12ma>; - }; - }; - - sfc { - sfc_bus4: sfc-bus4 { - rockchip,pins = - <1 RK_PA0 3 &pcfg_pull_none>, - <1 RK_PA1 3 &pcfg_pull_none>, - <1 RK_PA2 3 &pcfg_pull_none>, - <1 RK_PA3 3 &pcfg_pull_none>; - }; - - sfc_bus2: sfc-bus2 { - rockchip,pins = - <1 RK_PA0 3 &pcfg_pull_none>, - <1 RK_PA1 3 &pcfg_pull_none>; - }; - - sfc_cs0: sfc-cs0 { - rockchip,pins = - <1 RK_PA4 3 &pcfg_pull_none>; - }; - - sfc_clk: sfc-clk { - rockchip,pins = - <1 RK_PB1 3 &pcfg_pull_none>; - }; - }; - - lcdc { - lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { - rockchip,pins = - <3 RK_PA0 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { - rockchip,pins = - <3 RK_PA1 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { - rockchip,pins = - <3 RK_PA2 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { - rockchip,pins = - <3 RK_PA3 1 &pcfg_pull_none_12ma>; - }; - - lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { - rockchip,pins = - <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ - <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ - <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ - <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ - <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ - <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ - <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ - <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ - <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ - }; - - lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { - rockchip,pins = - <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ - <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ - <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ - <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ - }; - - lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { - rockchip,pins = - <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ - <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ - <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ - <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ - }; - - lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { - rockchip,pins = - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ - <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ - <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ - <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ - <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ - <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ - }; - - lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { - rockchip,pins = - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ - <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ - <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ - }; - - lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { - rockchip,pins = - <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ - <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ - <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ - <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ - <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ - <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ - <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ - <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ - <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = - <0 RK_PB7 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = - <0 RK_PC0 1 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = - <2 RK_PB5 1 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = - <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - pwm4 { - pwm4_pin: pwm4-pin { - rockchip,pins = - <3 RK_PC2 3 &pcfg_pull_none>; - }; - }; - - pwm5 { - pwm5_pin: pwm5-pin { - rockchip,pins = - <3 RK_PC3 3 &pcfg_pull_none>; - }; - }; - - pwm6 { - pwm6_pin: pwm6-pin { - rockchip,pins = - <3 RK_PC4 3 &pcfg_pull_none>; - }; - }; - - pwm7 { - pwm7_pin: pwm7-pin { - rockchip,pins = - <3 RK_PC5 3 &pcfg_pull_none>; - }; - }; - - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ - <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ - <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ - <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ - <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ - <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ - <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ - <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ - <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ - }; - - mac_refclk_12ma: mac-refclk-12ma { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none_12ma>; - }; - - mac_refclk: mac-refclk { - rockchip,pins = - <2 RK_PB2 2 &pcfg_pull_none>; - }; - }; - - cif-m0 { - cif_clkout_m0: cif-clkout-m0 { - rockchip,pins = - <2 RK_PB3 1 &pcfg_pull_none>; - }; - - dvp_d2d9_m0: dvp-d2d9-m0 { - rockchip,pins = - <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ - <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ - <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ - <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ - <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ - <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ - <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ - <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ - <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ - <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ - <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ - <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ - }; - - dvp_d0d1_m0: dvp-d0d1-m0 { - rockchip,pins = - <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ - <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ - }; - - dvp_d10d11_m0:d10-d11-m0 { - rockchip,pins = - <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ - <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ - }; - }; - - cif-m1 { - cif_clkout_m1: cif-clkout-m1 { - rockchip,pins = - <3 RK_PD0 3 &pcfg_pull_none>; - }; - - dvp_d2d9_m1: dvp-d2d9-m1 { - rockchip,pins = - <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ - <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ - <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ - <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ - <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ - <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ - <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ - <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ - <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ - <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ - <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ - <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ - }; - - dvp_d0d1_m1: dvp-d0d1-m1 { - rockchip,pins = - <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ - <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ - }; - - dvp_d10d11_m1:d10-d11-m1 { - rockchip,pins = - <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ - <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ - }; - }; - - isp { - isp_prelight: isp-prelight { - rockchip,pins = - <3 RK_PD1 4 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi index a6fb8b12da3..ff5bab316a3 100644 --- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi @@ -4,17 +4,6 @@ */ #include "rk3308-u-boot.dtsi" -&emmc { - cap-sd-highspeed; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>; -}; - -&emmc_bus4 { - bootph-pre-ram; - bootph-some-ram; -}; - &u2phy_otg { /delete-property/ phy-supply; }; @@ -24,14 +13,6 @@ clock-frequency = <24000000>; }; -&uart0_cts { - bootph-all; -}; - -&uart0_rts { - bootph-all; -}; - &uart0_xfer { bootph-all; }; diff --git a/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi new file mode 100644 index 00000000000..84ca2ee0d5f --- /dev/null +++ b/arch/arm/dts/rk3308-rock-s0-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3308-u-boot.dtsi" + +&emmc_pwren { + bootph-pre-ram; + bootph-some-ram; +}; + +&uart0 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart0_xfer { + bootph-all; +}; + +&vdd_core { + regulator-init-microvolt = <1015000>; +}; diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi index 684fa7abddb..b7964e2756f 100644 --- a/arch/arm/dts/rk3308-u-boot.dtsi +++ b/arch/arm/dts/rk3308-u-boot.dtsi @@ -21,22 +21,6 @@ bootph-all; }; - otp: nvmem@ff210000 { - compatible = "rockchip,rk3308-otp"; - reg = <0x0 0xff210000 0x0 0x4000>; - clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, - <&cru PCLK_OTP_PHY>; - clock-names = "otp", "apb_pclk", "phy"; - resets = <&cru SRST_OTP_PHY>; - reset-names = "phy"; - #address-cells = <1>; - #size-cells = <1>; - - cpu_id: id@7 { - reg = <0x07 0x10>; - }; - }; - rng: rng@ff2f0000 { compatible = "rockchip,cryptov2-rng"; reg = <0x0 0xff2f0000 0x0 0x4000>; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index a31dea8db3e..a0ab8b69f2e 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -48,18 +48,22 @@ &gpio0 { bootph-all; + gpio-ranges = <&pinctrl 0 0 32>; }; &gpio1 { bootph-all; + gpio-ranges = <&pinctrl 0 32 32>; }; &gpio2 { bootph-all; + gpio-ranges = <&pinctrl 0 64 32>; }; &gpio3 { bootph-all; + gpio-ranges = <&pinctrl 0 96 32>; }; &grf { diff --git a/arch/arm/dts/rk3326.dtsi b/arch/arm/dts/rk3326.dtsi deleted file mode 100644 index 2ba6da12513..00000000000 --- a/arch/arm/dts/rk3326.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include "px30.dtsi" - -&display_subsystem { - ports = <&vopb_out>; -}; - -/delete-node/ &dsi_in_vopl; -/delete-node/ &lvds_vopl_in; -/delete-node/ &vopl; -/delete-node/ &vopl_mmu; diff --git a/arch/arm/dts/rk3566-orangepi-3b-u-boot.dtsi b/arch/arm/dts/rk3566-orangepi-3b-u-boot.dtsi new file mode 100644 index 00000000000..e44b699af72 --- /dev/null +++ b/arch/arm/dts/rk3566-orangepi-3b-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk356x-u-boot.dtsi" + +&gpio4 { + bootph-pre-ram; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3566-orangepi-3b-v1.1-u-boot.dtsi b/arch/arm/dts/rk3566-orangepi-3b-v1.1-u-boot.dtsi new file mode 100644 index 00000000000..50ea6ede728 --- /dev/null +++ b/arch/arm/dts/rk3566-orangepi-3b-v1.1-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-orangepi-3b-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-orangepi-3b-v1.1.dts b/arch/arm/dts/rk3566-orangepi-3b-v1.1.dts new file mode 100644 index 00000000000..f97e33bd810 --- /dev/null +++ b/arch/arm/dts/rk3566-orangepi-3b-v1.1.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <arm64/rockchip/rk3566-orangepi-3b-v1.1.dts> diff --git a/arch/arm/dts/rk3566-orangepi-3b-v2.1-u-boot.dtsi b/arch/arm/dts/rk3566-orangepi-3b-v2.1-u-boot.dtsi new file mode 100644 index 00000000000..50ea6ede728 --- /dev/null +++ b/arch/arm/dts/rk3566-orangepi-3b-v2.1-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include "rk3566-orangepi-3b-u-boot.dtsi" diff --git a/arch/arm/dts/rk3566-orangepi-3b-v2.1.dts b/arch/arm/dts/rk3566-orangepi-3b-v2.1.dts new file mode 100644 index 00000000000..0031e2477ab --- /dev/null +++ b/arch/arm/dts/rk3566-orangepi-3b-v2.1.dts @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <arm64/rockchip/rk3566-orangepi-3b-v2.1.dts> diff --git a/arch/arm/dts/rk3566-orangepi-3b.dts b/arch/arm/dts/rk3566-orangepi-3b.dts new file mode 100644 index 00000000000..44b9a9c89f0 --- /dev/null +++ b/arch/arm/dts/rk3566-orangepi-3b.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <arm64/rockchip/rk3566-orangepi-3b.dtsi> diff --git a/arch/arm/dts/rk3566-pinetab2-v0.1.dts b/arch/arm/dts/rk3566-pinetab2-v0.1.dts deleted file mode 100644 index 5fe6ca5da9d..00000000000 --- a/arch/arm/dts/rk3566-pinetab2-v0.1.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3566-pinetab2.dtsi" - -/ { - model = "Pine64 PineTab2 v0.1"; - compatible = "pine64,pinetab2-v0.1", "pine64,pinetab2", "rockchip,rk3566"; -}; - -&lcd { - reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; -}; - -&pinctrl { - lcd0 { - lcd0_rst_l: lcd0-rst-l { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc1 { - vmmc-supply = <&vcc3v3_sys>; -}; diff --git a/arch/arm/dts/rk3566-pinetab2-v2.0.dts b/arch/arm/dts/rk3566-pinetab2-v2.0.dts deleted file mode 100644 index 9349541cbbd..00000000000 --- a/arch/arm/dts/rk3566-pinetab2-v2.0.dts +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include "rk3566-pinetab2.dtsi" - -/ { - model = "Pine64 PineTab2 v2.0"; - compatible = "pine64,pinetab2-v2.0", "pine64,pinetab2", "rockchip,rk3566"; -}; - -&gpio_keys { - pinctrl-0 = <&kb_id_det>, <&hall_int_l>; - - event-hall-sensor { - debounce-interval = <20>; - gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; - label = "Hall Sensor"; - linux,code = <SW_LID>; - linux,input-type = <EV_SW>; - wakeup-event-action = <EV_ACT_DEASSERTED>; - wakeup-source; - }; -}; - -&lcd { - reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pwren_h &lcd0_rst_l>; -}; - -&pinctrl { - lcd0 { - lcd0_rst_l: lcd0-rst-l { - rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - hall { - hall_int_l: hall-int-l { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&sdmmc1 { - vmmc-supply = <&vcc_sys>; -}; diff --git a/arch/arm/dts/rk3566-pinetab2.dtsi b/arch/arm/dts/rk3566-pinetab2.dtsi deleted file mode 100644 index db40281eafb..00000000000 --- a/arch/arm/dts/rk3566-pinetab2.dtsi +++ /dev/null @@ -1,943 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/gpio-keys.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/soc/rockchip,vop2.h> -#include <dt-bindings/usb/pd.h> -#include "rk3566.dtsi" - -/ { - chassis-type = "tablet"; - - aliases { - mmc0 = &sdhci; - mmc1 = &sdmmc0; - }; - - chosen { - stdout-path = "serial2:1500000n8"; - }; - - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <25>; - - button-vol-up { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - press-threshold-microvolt = <297500>; - }; - - button-vol-down { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - press-threshold-microvolt = <1750>; - }; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm4 0 25000 0>; - brightness-levels = <20 220>; - num-interpolated-steps = <200>; - default-brightness-level = <100>; - power-supply = <&vcc_sys>; - }; - - battery: battery { - compatible = "simple-battery"; - charge-full-design-microamp-hours = <6000000>; - charge-term-current-microamp = <300000>; - constant-charge-current-max-microamp = <2000000>; - constant-charge-voltage-max-microvolt = <4300000>; - voltage-max-design-microvolt = <4350000>; - voltage-min-design-microvolt = <3400000>; - - ocv-capacity-celsius = <20>; - ocv-capacity-table-0 = <4322000 100>, <4250000 95>, <4192000 90>, <4136000 85>, - <4080000 80>, <4022000 75>, <3972000 70>, <3928000 65>, - <3885000 60>, <3833000 55>, <3798000 50>, <3780000 45>, - <3776000 40>, <3773000 35>, <3755000 30>, <3706000 25>, - <3640000 20>, <3589000 15>, <3535000 10>, <3492000 5>, - <3400000 0>; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&kb_id_det>; - - tablet-mode-switch { - debounce-interval = <20>; - gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; - label = "Tablet Mode"; - linux,input-type = <EV_SW>; - linux,code = <SW_TABLET_MODE>; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "d"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; - }; - - led-0 { - compatible = "regulator-led"; - vled-supply = <&vcc5v0_flashled>; - color = <LED_COLOR_ID_WHITE>; - function = LED_FUNCTION_FLASH; - }; - - rk817-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_det_l>; - simple-audio-card,format = "i2s"; - simple-audio-card,name = "rk817_ext"; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Internal Speakers"; - - simple-audio-card,routing = - "MICR", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Internal Speakers", "Speaker Amplifier OUTL", - "Internal Speakers", "Speaker Amplifier OUTR", - "Speaker Amplifier INL", "HPOL", - "Speaker Amplifier INR", "HPOR"; - simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; - simple-audio-card,aux-devs = <&speaker_amp>; - simple-audio-card,pin-switches = "Internal Speakers"; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - simple-audio-card,codec { - sound-dai = <&rk817>; - }; - }; - - speaker_amp: speaker-amplifier { - compatible = "simple-audio-amplifier"; - pinctrl-names = "default"; - pinctrl-0 = <&spk_ctl>; - enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - sound-name-prefix = "Speaker Amplifier"; - VCC-supply = <&vcc_bat>; - }; - - vcc_3v3: vcc-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc3v3_minipcie: vcc3v3-minipcie-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pwren_h>; - regulator-name = "vcc3v3_minipcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; - - vcc3v3_sd: vcc3v3-sd-regulator { - compatible = "regulator-fixed"; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_pwren_l>; - regulator-name = "vcc3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_sys>; - }; - - vcc5v0_flashled: vcc5v0-flashled-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&flash_led_en_h>; - regulator-name = "vcc5v0_flashled"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v_midu>; - }; - - vcc5v0_usb_host0: vcc5v0-usb-host0-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_host_pwren1_h>; - regulator-name = "vcc5v0_usb_host0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v_midu>; - }; - - vcc5v0_usb_host2: vcc5v0-usb-host2-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_host_pwren2_h>; - regulator-name = "vcc5v0_usb_host2"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v_midu>; - }; - - vcc_bat: vcc-bat-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_bat"; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_bat>; - }; - - vdd1v2_dvp: vdd1v2-dvp-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdd1v2_dvp"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <&vcc_3v3>; - }; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; -}; - -&cru { - assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, - <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; - assigned-clock-rates = <32768>, <1200000000>, <200000000>, <500000000>; - assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; -}; - -&csi_dphy { - status = "okay"; -}; - -&dsi0 { - status = "okay"; - clock-master; - #address-cells = <1>; - #size-cells = <0>; - - lcd: panel@0 { - compatible = "boe,th101mb31ig002-28a"; - reg = <0>; - backlight = <&backlight>; - enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - rotation = <90>; - power-supply = <&vcc_3v3>; - - port@0 { - panel_in_dsi: endpoint@0 { - remote-endpoint = <&dsi0_out_con>; - }; - }; - }; -}; - -&dsi0_in { - dsi0_in_vp1: endpoint { - remote-endpoint = <&vp1_out_dsi0>; - }; -}; - -&dsi0_out { - dsi0_out_con: endpoint { - remote-endpoint = <&panel_in_dsi>; - }; -}; - -&dsi_dphy0 { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_gpu_npu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda_0v9_p>; - avdd-1v8-supply = <&vcc_1v8>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; - assigned-clocks = <&cru I2S1_MCLKOUT_TX>; - assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; - clock-names = "mclk"; - clocks = <&cru I2S1_MCLKOUT_TX>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; - rockchip,system-power-controller; - #sound-dai-cells = <0>; - wakeup-source; - - vcc1-supply = <&vcc_sys>; - vcc2-supply = <&vcc_sys>; - vcc3-supply = <&vcc_sys>; - vcc4-supply = <&vcc_sys>; - vcc5-supply = <&vcc_sys>; - vcc6-supply = <&vcc_sys>; - vcc7-supply = <&vcc_sys>; - vcc8-supply = <&vcc_sys>; - vcc9-supply = <&vcc5v_midu>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_logic"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu_npu: DCDC_REG2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_gpu_npu"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc3v3_sys: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc3v3_sys"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdda_0v9_p: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9_p"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_1v8: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc1v8_dvp: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc1v8_dvp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc2v8_dvp: LDO_REG9 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "vcc2v8_dvp"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc5v_midu: BOOST { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "boost"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vbus: OTG_SWITCH { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "otg_switch"; - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - charger { - monitored-battery = <&battery>; - rockchip,resistor-sense-micro-ohms = <10000>; - rockchip,sleep-enter-current-microamp = <300000>; - rockchip,sleep-filter-current-microamp = <100000>; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt911"; - reg = <0x5d>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB0 IRQ_TYPE_EDGE_FALLING>; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int_l_pmuio2>, <&tp_rst_l_pmuio2>; - AVDD28-supply = <&vcc3v3_pmu>; - VDDIO-supply = <&vcca1v8_pmu>; - irq-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; - }; -}; - -&i2c2 { - clock-frequency = <400000>; - pinctrl-0 = <&i2c2m1_xfer>; - status = "okay"; - - vcm@c { - compatible = "dongwoon,dw9714"; - reg = <0x0c>; - vcc-supply = <&vcc1v8_dvp>; - }; - - camera@36 { - compatible = "ovti,ov5648"; - reg = <0x36>; - pinctrl-names = "default"; - pinctrl-0 = <&camerab_pdn_l &camerab_rst_l>; - - clocks = <&cru CLK_CIF_OUT>; - assigned-clocks = <&cru CLK_CIF_OUT>; - assigned-clock-rates = <24000000>; - - avdd-supply = <&vcc2v8_dvp>; - dvdd-supply = <&vdd1v2_dvp>; - dovdd-supply = <&vcc1v8_dvp>; - powerdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; - - port { - endpoint { - data-lanes = <1 2>; - remote-endpoint = <0>; - link-frequencies = /bits/ 64 <210000000 168000000>; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - accelerometer@18 { - compatible = "silan,sc7a20"; - reg = <0x18>; - interrupt-parent = <&gpio3>; - interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&gsensor_int_l>; - st,drdy-int-pin = <1>; - vdd-supply = <&vcc_1v8>; - vddio-supply = <&vcc_1v8>; - mount-matrix = "1", "0", "0", - "0", "0", "1", - "0", "1", "0"; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx - &i2s1m0_lrcktx - &i2s1m0_sdi0 - &i2s1m0_sdo0>; - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - -&pcie2x1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_h>; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_minipcie>; - status = "okay"; -}; - -&pinctrl { - camerab { - camerab_pdn_l: camerab-pdn-l { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - camerab_rst_l: camerab-rst-l { - rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - cameraf { - cameraf_pdn_l: cameraf-pdn-l { - rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - cameraf_rst_l: cameraf-rst-l { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - flash { - flash_led_en_h: flash-led-en-h { - rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - fspi { - fspi_dual_io_pins: fspi-dual-io-pins { - rockchip,pins = - /* fspi_clk */ - <1 RK_PD0 1 &pcfg_pull_none>, - /* fspi_cs0n */ - <1 RK_PD3 1 &pcfg_pull_none>, - /* fspi_d0 */ - <1 RK_PD1 1 &pcfg_pull_none>, - /* fspi_d1 */ - <1 RK_PD2 1 &pcfg_pull_none>; - }; - }; - - gsensor { - gsensor_int_l: gsensor-int-l { - rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - kb { - kb_id_det: kb-id-det { - rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - lcd { - lcd_pwren_h: lcd-pwren-h { - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pcie { - pcie_pwren_h: pcie-pwren-h { - rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pcie_reset_h: pcie-reset-h { - rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - sdmmc { - sdmmc_pwren_l: sdmmc-pwren-l { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - sound { - hp_det_l: hp-det-l { - rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - spk_ctl: spk-ctl { - rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - tp { - tp_int_l_pmuio2: tp-int-l-pmuio2 { - rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - tp_rst_l_pmuio2: tp-rst-l-pmuio2 { - rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - usb { - usbcc_int_l: usbcc-int-l { - rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb_host_pwren1_h: usb-host-pwren1-h { - rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - usb_host_pwren2_h: usb-host-pwren2-h { - rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - wifi { - host_wake_wl: host-wake-wl { - rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - wifi_wake_host_h: wifi-wake-host-h { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcca1v8_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_1v8>; - vccio6-supply = <&vcc1v8_dvp>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pwm4 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - no-sdio; - no-sd; - non-removable; - max-frequency = <200000000>; - mmc-hs200-1_8v; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 - &emmc_clk - &emmc_cmd - &emmc_datastrobe - &emmc_rstnout>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 - &sdmmc0_clk - &sdmmc0_cmd - &sdmmc0_det>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sdmmc1 { - bus-width = <4>; - cap-sd-highspeed; - cap-sdio-irq; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc1_bus4 - &sdmmc1_cmd - &sdmmc1_clk>; - sd-uhs-sdr104; - vqmmc-supply = <&vcca1v8_pmu>; - status = "okay"; -}; - -&sfc { - pinctrl-names = "default"; - pinctrl-0 = <&fspi_dual_io_pins>; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <100000000>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <1>; - }; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host0>; - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_otg { - phy-supply = <&vcc5v0_usb_host2>; - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = <ROCKCHIP_VOP2_EP_HDMI0>; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; - -&vp1 { - vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { - reg = <ROCKCHIP_VOP2_EP_MIPI0>; - remote-endpoint = <&dsi0_in_vp1>; - }; -}; diff --git a/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi new file mode 100644 index 00000000000..8af2581163b --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-zero-3e-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +&saradc { + bootph-pre-ram; +}; + +&usb_host0_xhci { + dr_mode = "otg"; +}; + +&vcca_1v8 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi new file mode 100644 index 00000000000..8af2581163b --- /dev/null +++ b/arch/arm/dts/rk3566-radxa-zero-3w-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +&saradc { + bootph-pre-ram; +}; + +&usb_host0_xhci { + dr_mode = "otg"; +}; + +&vcca_1v8 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi new file mode 100644 index 00000000000..f4124aa48fc --- /dev/null +++ b/arch/arm/dts/rk3566-rock-3c-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +/ { + leds { + led-0 { + default-state = "on"; + }; + }; +}; diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi index 5f4f14b3bda..5f4f14b3bda 100644 --- a/arch/arm/dts/rk3568-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3568-evb1-v10-u-boot.dtsi diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi index 9d18f5d0b36..0da3d9c56b8 100644 --- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi +++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi @@ -26,17 +26,12 @@ }; &sfc { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; bootph-pre-ram; bootph-some-ram; - spi-max-frequency = <24000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <1>; }; }; + +&usb_host0_ohci { + status = "disabled"; +}; diff --git a/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi new file mode 100644 index 00000000000..b1f324282ba --- /dev/null +++ b/arch/arm/dts/rk3568-rock-3b-u-boot.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" + +&sdhci { + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3588-friendlyelec-cm3588-nas-u-boot.dtsi b/arch/arm/dts/rk3588-friendlyelec-cm3588-nas-u-boot.dtsi new file mode 100644 index 00000000000..2e60f2dce8f --- /dev/null +++ b/arch/arm/dts/rk3588-friendlyelec-cm3588-nas-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; diff --git a/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi new file mode 100644 index 00000000000..1e5c2674e49 --- /dev/null +++ b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Collabora Ltd. + */ + +#include "rk3588-u-boot.dtsi" + +&fspim2_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&vcc3v3_mkey { + regulator-always-on; +}; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 8e318e624a8..4dd17ff408c 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -39,18 +39,6 @@ status = "okay"; }; -&u2phy1 { - status = "okay"; -}; - -&u2phy1_otg { - status = "okay"; -}; - -&usbdp_phy1 { - status = "okay"; -}; - &usbdp_phy0 { status = "okay"; }; @@ -60,8 +48,3 @@ maximum-speed = "high-speed"; status = "okay"; }; - -&usb_host1_xhci { - dr_mode = "host"; - status = "okay"; -}; diff --git a/arch/arm/dts/rockchip-pinconf.dtsi b/arch/arm/dts/rockchip-pinconf.dtsi deleted file mode 100644 index 5c645437b50..00000000000 --- a/arch/arm/dts/rockchip-pinconf.dtsi +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - -&pinctrl { - /omit-if-no-ref/ - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - /omit-if-no-ref/ - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - /omit-if-no-ref/ - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { - bias-disable; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { - bias-disable; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { - bias-disable; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { - bias-disable; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { - bias-disable; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { - bias-disable; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { - bias-disable; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { - bias-disable; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { - bias-disable; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { - bias-disable; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { - bias-disable; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { - bias-disable; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { - bias-disable; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { - bias-disable; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { - bias-disable; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { - bias-disable; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { - bias-pull-up; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { - bias-pull-up; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { - bias-pull-up; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { - bias-pull-up; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { - bias-pull-up; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { - bias-pull-up; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { - bias-pull-up; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { - bias-pull-up; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { - bias-pull-up; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { - bias-pull-up; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { - bias-pull-up; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { - bias-pull-up; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { - bias-pull-up; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { - bias-pull-up; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { - bias-pull-up; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { - bias-pull-up; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { - bias-pull-down; - drive-strength = <0>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { - bias-pull-down; - drive-strength = <1>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { - bias-pull-down; - drive-strength = <2>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { - bias-pull-down; - drive-strength = <3>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { - bias-pull-down; - drive-strength = <4>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { - bias-pull-down; - drive-strength = <5>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { - bias-pull-down; - drive-strength = <6>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { - bias-pull-down; - drive-strength = <7>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { - bias-pull-down; - drive-strength = <8>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { - bias-pull-down; - drive-strength = <9>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { - bias-pull-down; - drive-strength = <10>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { - bias-pull-down; - drive-strength = <11>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { - bias-pull-down; - drive-strength = <12>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { - bias-pull-down; - drive-strength = <13>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { - bias-pull-down; - drive-strength = <14>; - }; - - /omit-if-no-ref/ - pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { - bias-pull-down; - drive-strength = <15>; - }; - - /omit-if-no-ref/ - pcfg_pull_up_smt: pcfg-pull-up-smt { - bias-pull-up; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_down_smt: pcfg-pull-down-smt { - bias-pull-down; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_smt: pcfg-pull-none-smt { - bias-disable; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { - bias-disable; - drive-strength = <0>; - input-schmitt-enable; - }; - - /omit-if-no-ref/ - pcfg_output_high: pcfg-output-high { - output-high; - }; - - /omit-if-no-ref/ - pcfg_output_low: pcfg-output-low { - output-low; - }; -}; diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts index bf66b640816..92bc4e7864e 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -53,7 +53,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/dts/sun50i-a64-nanopi-a64.dts b/arch/arm/dts/sun50i-a64-nanopi-a64.dts index ffc3b4c7068..69dfe3bc4d8 100644 --- a/arch/arm/dts/sun50i-a64-nanopi-a64.dts +++ b/arch/arm/dts/sun50i-a64-nanopi-a64.dts @@ -41,7 +41,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm/dts/sun50i-a64-olinuxino.dts b/arch/arm/dts/sun50i-a64-olinuxino.dts index 22d350249c1..75217668382 100644 --- a/arch/arm/dts/sun50i-a64-olinuxino.dts +++ b/arch/arm/dts/sun50i-a64-olinuxino.dts @@ -52,7 +52,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts index 714a270a558..a037e15ab9d 100644 --- a/arch/arm/dts/sun50i-a64-orangepi-win.dts +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts @@ -68,7 +68,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts index 576eae13223..1a85d5f60c3 100644 --- a/arch/arm/dts/sun50i-a64-pinebook.dts +++ b/arch/arm/dts/sun50i-a64-pinebook.dts @@ -79,7 +79,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi index b25e7913f55..c62dc937def 100644 --- a/arch/arm/dts/sun50i-a64-pinephone.dtsi +++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi @@ -39,25 +39,35 @@ leds { compatible = "gpio-leds"; - led-0 { + led0: led-0 { function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_BLUE>; gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */ + retain-state-suspended; }; - led-1 { + led1: led-1 { function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_GREEN>; gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */ + retain-state-suspended; }; - led-2 { + led2: led-2 { function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_RED>; gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */ + retain-state-suspended; }; }; + multi-led { + compatible = "leds-group-multicolor"; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + leds = <&led0>, <&led1>, <&led2>; + }; + reg_ps: ps-regulator { compatible = "regulator-fixed"; regulator-name = "ps"; diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts index 0b2258ef88f..b6f42357b45 100644 --- a/arch/arm/dts/sun50i-a64-pinetab.dts +++ b/arch/arm/dts/sun50i-a64-pinetab.dts @@ -98,7 +98,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts index 945afdb508d..065b1861633 100644 --- a/arch/arm/dts/sun50i-a64-teres-i.dts +++ b/arch/arm/dts/sun50i-a64-teres-i.dts @@ -74,7 +74,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ }; diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 2240eaec5dd..b6928cc668d 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -107,27 +107,19 @@ gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; - opp-120000000 { - opp-hz = /bits/ 64 <120000000>; - }; - - opp-312000000 { - opp-hz = /bits/ 64 <312000000>; - }; - opp-432000000 { opp-hz = /bits/ 64 <432000000>; }; }; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -216,21 +208,21 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_alert1: cpu_alert1 { + cpu_alert1: cpu-alert1 { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "hot"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <110000>; hysteresis = <2000>; diff --git a/arch/arm/dts/sun50i-h313-tanix-tx1.dts b/arch/arm/dts/sun50i-h313-tanix-tx1.dts new file mode 100644 index 00000000000..bb2cde59bd0 --- /dev/null +++ b/arch/arm/dts/sun50i-h313-tanix-tx1.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Tanix TX1"; + compatible = "oranth,tanix-tx1", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + ethernet0 = &sdio_wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key { + label = "hidden"; + linux,code = <BTN_0>; + gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + default-state = "on"; + }; + }; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&ir { + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + vmmc-supply = <®_dldo1>; + vqmmc-supply = <®_aldo1>; + bus-width = <8>; + non-removable; + max-frequency = <100000000>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_aldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1120000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; /* USB A type receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts index 4c3921ac236..b69032c4455 100644 --- a/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts @@ -68,7 +68,7 @@ states = <1100000 0>, <1300000 1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts index a3e040da38a..3a7ee44708a 100644 --- a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts @@ -103,7 +103,7 @@ states = <1100000 0x0>, <1300000 0x1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ post-power-on-delay-ms = <200>; @@ -170,7 +170,7 @@ non-removable; status = "okay"; - rtl8189etv: sdio_wifi@1 { + rtl8189etv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts b/arch/arm/dts/sun50i-h5-orangepi-prime.dts index d7f8bad6bb9..b699bb900e1 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-prime.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts @@ -85,7 +85,7 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */ }; diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts index 7ec5ac850a0..ae85131aac9 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts @@ -97,7 +97,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189ftv: sdio_wifi@1 { + rtl8189ftv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts index 22530ace12d..734481e998b 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts @@ -52,7 +52,7 @@ regulator-max-microvolt = <3300000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts index 87432c4f1ff..529285fc34f 100644 --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -34,7 +34,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts index f1957bb1edb..bdcec466246 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-3.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts @@ -33,7 +33,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts index fb31dcb1cb6..a3f65a45bd2 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts @@ -11,7 +11,7 @@ serial1 = &uart1; /* BT-UART */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi index a5811d55bbe..4403769fc36 100644 --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi @@ -32,7 +32,7 @@ }; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts index b710f1a0f53..66fe03910d5 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts @@ -5,13 +5,13 @@ #include "sun50i-h6-pine-h64.dts" +/delete-node/ ®_gmac_3v3; + / { model = "Pine H64 model B"; compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; - /delete-node/ reg_gmac_3v3; - - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts index b868ad17af8..bfb46572bda 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -22,7 +22,7 @@ stdout-path = "serial0:115200n8"; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index 09e21689284..82aa5679fc4 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -68,7 +68,7 @@ status = "disabled"; }; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; diff --git a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi index af421ba24ce..d12b01c5f41 100644 --- a/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi +++ b/arch/arm/dts/sun50i-h616-bigtreetech-cb1.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -62,6 +63,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &mmc0 { vmmc-supply = <®_dldo1>; /* Card detection pin is not connected */ diff --git a/arch/arm/dts/sun50i-h616-cpu-opp.dtsi b/arch/arm/dts/sun50i-h616-cpu-opp.dtsi new file mode 100644 index 00000000000..aca22a7f019 --- /dev/null +++ b/arch/arm/dts/sun50i-h616-cpu-opp.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2023 Martin Botka <martin@somainline.org> + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "allwinner,sun50i-h616-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x12>; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x0d>; + }; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed4 = <940000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x12>; + }; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <900000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x0d>; + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt-speed0 = <950000>; + opp-microvolt-speed1 = <940000>; + opp-microvolt-speed2 = <950000>; + opp-microvolt-speed3 = <950000>; + opp-microvolt-speed4 = <1020000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt-speed0 = <1000000>; + opp-microvolt-speed2 = <1000000>; + opp-microvolt-speed3 = <1000000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x0d>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-speed0 = <1050000>; + opp-microvolt-speed1 = <1020000>; + opp-microvolt-speed2 = <1050000>; + opp-microvolt-speed3 = <1050000>; + opp-microvolt-speed4 = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1f>; + }; + + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x1d>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x0d>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt-speed1 = <1100000>; + opp-microvolt-speed3 = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-supported-hw = <0x0a>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts index b5d713926a3..a360d8567f9 100644 --- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts @@ -6,12 +6,17 @@ /dts-v1/; #include "sun50i-h616-orangepi-zero.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" / { model = "OrangePi Zero2"; compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; }; +&cpu0 { + cpu-supply = <®_dcdca>; +}; + &emac0 { allwinner,rx-delay-ps = <3100>; allwinner,tx-delay-ps = <700>; diff --git a/arch/arm/dts/sun50i-h616-x96-mate.dts b/arch/arm/dts/sun50i-h616-x96-mate.dts index 959b6fd1848..26d25b5b59e 100644 --- a/arch/arm/dts/sun50i-h616-x96-mate.dts +++ b/arch/arm/dts/sun50i-h616-x96-mate.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -32,6 +33,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdca>; +}; + &ehci0 { status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi index b2e85e52d1a..921d5f61d8d 100644 --- a/arch/arm/dts/sun50i-h616.dtsi +++ b/arch/arm/dts/sun50i-h616.dtsi @@ -26,6 +26,7 @@ reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -34,6 +35,7 @@ reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -42,6 +44,7 @@ reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -50,6 +53,7 @@ reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; + #cooling-cells = <2>; }; }; @@ -156,6 +160,10 @@ ths_calibration: thermal-sensor-calibration@14 { reg = <0x14 0x8>; }; + + cpu_speed_grade: cpu-speed-grade@0 { + reg = <0x0 2>; + }; }; watchdog: watchdog@30090a0 { @@ -194,7 +202,7 @@ }; i2c0_pins: i2c0-pins { - pins = "PI6", "PI7"; + pins = "PI5", "PI6"; function = "i2c0"; }; @@ -775,6 +783,15 @@ #reset-cells = <1>; }; + nmi_intc: interrupt-controller@7010320 { + compatible = "allwinner,sun50i-h616-nmi", + "allwinner,sun9i-a80-nmi"; + reg = <0x07010320 0xc>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + }; + r_pio: pinctrl@7022000 { compatible = "allwinner,sun50i-h616-r-pinctrl"; reg = <0x07022000 0x400>; diff --git a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi b/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi index 8c1263a3939..e92d150aaf1 100644 --- a/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi +++ b/arch/arm/dts/sun50i-h618-longan-module-3h.dtsi @@ -4,6 +4,11 @@ */ #include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; &mmc2 { pinctrl-names = "default"; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts index 21ca1977055..6a4f0da9723 100644 --- a/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts +++ b/arch/arm/dts/sun50i-h618-orangepi-zero2w.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -53,6 +54,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci1 { status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts index b3b1b869212..e1cd7572a14 100644 --- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts +++ b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts @@ -6,12 +6,17 @@ /dts-v1/; #include "sun50i-h616-orangepi-zero.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" / { model = "OrangePi Zero3"; compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &emac0 { allwinner,tx-delay-ps = <700>; phy-mode = "rgmii-rxid"; diff --git a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts index ac0a2b7ea6f..d6631bfe629 100644 --- a/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts +++ b/arch/arm/dts/sun50i-h618-transpeed-8k618-t.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -41,7 +42,7 @@ regulator-always-on; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rtc CLK_OSC32K_FANOUT>; clock-names = "ext_clock"; @@ -51,6 +52,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci0 { status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h64-remix-mini-pc.dts b/arch/arm/dts/sun50i-h64-remix-mini-pc.dts index c1a15d60bf3..464a3078afd 100644 --- a/arch/arm/dts/sun50i-h64-remix-mini-pc.dts +++ b/arch/arm/dts/sun50i-h64-remix-mini-pc.dts @@ -42,7 +42,7 @@ regulator-always-on; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts new file mode 100644 index 00000000000..ee30584b6ad --- /dev/null +++ b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-2024.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Anbernic RG35XX 2024"; + chassis-type = "handset"; + compatible = "anbernic,rg35xx-2024", "allwinner,sun50i-h700"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys_gamepad: gpio-keys-gamepad { + compatible = "gpio-keys"; + + button-a { + label = "Action-Pad A"; + gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_EAST>; + }; + + button-b { + label = "Action-Pad B"; + gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_SOUTH>; + }; + + button-down { + label = "D-Pad Down"; + gpios = <&pio 4 0 GPIO_ACTIVE_LOW>; /* PE0 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_DOWN>; + }; + + button-l1 { + label = "Key L1"; + gpios = <&pio 0 10 GPIO_ACTIVE_LOW>; /* PA10 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TL>; + }; + + button-l2 { + label = "Key L2"; + gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TL2>; + }; + + button-left { + label = "D-Pad left"; + gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-menu { + label = "Key Menu"; + gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_MODE>; + }; + + button-r1 { + label = "Key R1"; + gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TR>; + }; + + button-r2 { + label = "Key R2"; + gpios = <&pio 0 7 GPIO_ACTIVE_LOW>; /* PA7 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_TR2>; + }; + + button-right { + label = "D-Pad Right"; + gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-select { + label = "Key Select"; + gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_SELECT>; + }; + button-start { + label = "Key Start"; + gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_START>; + }; + + button-up { + label = "D-Pad Up"; + gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_DPAD_UP>; + }; + + button-x { + label = "Action-Pad X"; + gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_NORTH>; + }; + + button-y { + label = "Action Pad Y"; + gpios = <&pio 0 2 GPIO_ACTIVE_LOW>; /* PA2 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_WEST>; + }; + }; + + gpio-keys-volume { + compatible = "gpio-keys"; + autorepeat; + + button-vol-up { + label = "Key Volume Up"; + gpios = <&pio 4 1 GPIO_ACTIVE_LOW>; /* PE1 */ + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-vol-down { + label = "Key Volume Down"; + gpios = <&pio 4 2 GPIO_ACTIVE_LOW>; /* PE2 */ + linux,input-type = <EV_KEY>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ + default-state = "on"; + }; + }; + + reg_vcc5v: regulator-vcc5v { /* USB-C power input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc1>; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_cldo3>; + disable-wp; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + vcc-pa-supply = <®_cldo3>; + vcc-pc-supply = <®_cldo3>; + vcc-pe-supply = <®_cldo3>; + vcc-pf-supply = <®_cldo3>; + vcc-pg-supply = <®_aldo4>; + vcc-ph-supply = <®_cldo3>; + vcc-pi-supply = <®_cldo3>; +}; + +&r_rsb { + status = "okay"; + + axp717: pmic@3a3 { + compatible = "x-powers,axp717"; + reg = <0x3a3>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + vin4-supply = <®_vcc5v>; + + regulators { + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <940000>; + regulator-max-microvolt = <940000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + + reg_aldo1: aldo1 { + /* 1.8v - unused */ + }; + + reg_aldo2: aldo2 { + /* 1.8v - unused */ + }; + + reg_aldo3: aldo3 { + /* 1.8v - unused */ + }; + + reg_aldo4: aldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg"; + }; + + reg_bldo1: bldo1 { + /* 1.8v - unused */ + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll"; + }; + + reg_bldo3: bldo3 { + /* 2.8v - unused */ + }; + + reg_bldo4: bldo4 { + /* 1.2v - unused */ + }; + + reg_cldo1: cldo1 { + /* 3.3v - audio codec - not yet implemented */ + }; + + reg_cldo2: cldo2 { + /* 3.3v - unused */ + }; + + reg_cldo3: cldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; + }; + + reg_boost: boost { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5200000>; + regulator-name = "boost"; + }; + + reg_cpusldo: cpusldo { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +/* the AXP717 has USB type-C role switch functionality, not yet described by the binding */ +&usbotg { + dr_mode = "peripheral"; /* USB type-C receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts new file mode 100644 index 00000000000..63036256917 --- /dev/null +++ b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-h.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. + * Copyright (C) 2024 Chris Morgan <macroalpha82@gmail.com>. + */ + +#include "sun50i-h700-anbernic-rg35xx-plus.dts" + +/ { + model = "Anbernic RG35XX H"; + compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; +}; + +&gpio_keys_gamepad { + button-thumbl { + label = "GPIO Thumb Left"; + gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_THUMBL>; + }; + + button-thumbr { + label = "GPIO Thumb Right"; + gpios = <&pio 4 9 GPIO_ACTIVE_LOW>; /* PE9 */ + linux,input-type = <EV_KEY>; + linux,code = <BTN_THUMBR>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts new file mode 100644 index 00000000000..60a8e492210 --- /dev/null +++ b/arch/arm/dts/sun50i-h700-anbernic-rg35xx-plus.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) 2024 Ryan Walklin <ryan@testtoast.com>. + */ + +#include "sun50i-h700-anbernic-rg35xx-2024.dts" + +/ { + model = "Anbernic RG35XX Plus"; + compatible = "anbernic,rg35xx-plus", "allwinner,sun50i-h700"; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + pinctrl-0 = <&x32clk_fanout_pin>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + }; +}; + +/* SDIO WiFi RTL8821CS */ +&mmc1 { + vmmc-supply = <®_cldo4>; + vqmmc-supply = <®_aldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 15 IRQ_TYPE_LEVEL_LOW>; /* PG15 */ + interrupt-names = "host-wake"; + }; +}; + +/* Bluetooth RTL8821CS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; + device-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */ + enable-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>; /* PG19 */ + host-wake-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16 */ + }; +}; diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi index 3325ab07094..2c9152b151b 100644 --- a/arch/arm/dts/sun5i-a13.dtsi +++ b/arch/arm/dts/sun5i-a13.dtsi @@ -62,14 +62,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; diff --git a/arch/arm/dts/sun5i-gr8-chip-pro.dts b/arch/arm/dts/sun5i-gr8-chip-pro.dts index 5c3562b85a5..ffbd99c176d 100644 --- a/arch/arm/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/dts/sun5i-gr8-chip-pro.dts @@ -77,7 +77,7 @@ }; }; - mmc0_pwrseq: mmc0_pwrseq { + mmc0_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ }; diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts index 4192c23848c..8c784a2c086 100644 --- a/arch/arm/dts/sun5i-r8-chip.dts +++ b/arch/arm/dts/sun5i-r8-chip.dts @@ -77,7 +77,7 @@ }; }; - mmc0_pwrseq: mmc0_pwrseq { + mmc0_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */ }; diff --git a/arch/arm/dts/sun6i-a31-hummingbird.dts b/arch/arm/dts/sun6i-a31-hummingbird.dts index 486cec6f71e..41955fe5490 100644 --- a/arch/arm/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/dts/sun6i-a31-hummingbird.dts @@ -109,7 +109,7 @@ }; }; - reg_vga_3v3: vga_3v3_regulator { + reg_vga_3v3: vga-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "vga-3v3"; regulator-min-microvolt = <3300000>; @@ -119,7 +119,7 @@ gpio = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */ }; diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi index b32d2ab6aa2..a65c09ec054 100644 --- a/arch/arm/dts/sun6i-a31.dtsi +++ b/arch/arm/dts/sun6i-a31.dtsi @@ -179,14 +179,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <70000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; @@ -1315,7 +1315,7 @@ compatible = "allwinner,sun6i-a31-prcm"; reg = <0x01f01400 0x200>; - ar100: ar100_clk { + ar100: ar100-clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; clocks = <&rtc CLK_OSC32K>, <&osc24M>, @@ -1324,7 +1324,7 @@ clock-output-names = "ar100"; }; - ahb0: ahb0_clk { + ahb0: ahb0-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -1333,14 +1333,14 @@ clock-output-names = "ahb0"; }; - apb0: apb0_clk { + apb0: apb0-clk { compatible = "allwinner,sun6i-a31-apb0-clk"; #clock-cells = <0>; clocks = <&ahb0>; clock-output-names = "apb0"; }; - apb0_gates: apb0_gates_clk { + apb0_gates: apb0-gates-clk { compatible = "allwinner,sun6i-a31-apb0-gates-clk"; #clock-cells = <1>; clocks = <&apb0>; @@ -1350,14 +1350,14 @@ "apb0_i2c"; }; - ir_clk: ir_clk { + ir_clk: ir-clk { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; clocks = <&rtc CLK_OSC32K>, <&osc24M>; clock-output-names = "ir"; }; - apb0_rst: apb0_rst { + apb0_rst: apb0-rst { compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; }; diff --git a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts index efb25b949f3..2f3d93e56d7 100644 --- a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts +++ b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts @@ -75,7 +75,7 @@ }; }; - mmc2_pwrseq: mmc2_pwrseq { + mmc2_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */ }; diff --git a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts index caa935ca4f1..f2d7fab9978 100644 --- a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts @@ -86,7 +86,7 @@ }; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */ }; diff --git a/arch/arm/dts/sun7i-a20-cubietruck.dts b/arch/arm/dts/sun7i-a20-cubietruck.dts index 52160e36830..be9b31d0f4b 100644 --- a/arch/arm/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/dts/sun7i-a20-cubietruck.dts @@ -96,7 +96,7 @@ }; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ clocks = <&ccu CLK_OUT_A>; diff --git a/arch/arm/dts/sun7i-a20-hummingbird.dts b/arch/arm/dts/sun7i-a20-hummingbird.dts index 3def2a33059..f1e26b75cd9 100644 --- a/arch/arm/dts/sun7i-a20-hummingbird.dts +++ b/arch/arm/dts/sun7i-a20-hummingbird.dts @@ -65,7 +65,7 @@ stdout-path = "serial0:115200n8"; }; - reg_mmc3_vdd: mmc3_vdd { + reg_mmc3_vdd: regulator-mmc3-vdd { compatible = "regulator-fixed"; regulator-name = "mmc3_vdd"; regulator-min-microvolt = <3000000>; @@ -74,7 +74,7 @@ gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ }; - reg_gmac_vdd: gmac_vdd { + reg_gmac_vdd: regulator-gmac-vdd { compatible = "regulator-fixed"; regulator-name = "gmac_vdd"; regulator-min-microvolt = <3000000>; diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts index 20bf09b2226..fb835730bbc 100644 --- a/arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts +++ b/arch/arm/dts/sun7i-a20-olimex-som-evb-emmc.dts @@ -14,7 +14,7 @@ model = "Olimex A20-Olimex-SOM-EVB-eMMC"; compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20"; - mmc2_pwrseq: mmc2_pwrseq { + mmc2_pwrseq: pwrseq { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts index a59755a2e7a..e8977c2fe79 100644 --- a/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts +++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb-emmc.dts @@ -13,7 +13,7 @@ model = "Olimex A20-SOM204-EVB-eMMC"; compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20"; - mmc2_pwrseq: mmc2_pwrseq { + mmc2_pwrseq: pwrseq-1 { compatible = "mmc-pwrseq-emmc"; reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts index 54af6c18075..a5540665744 100644 --- a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts +++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts @@ -65,7 +65,7 @@ }; }; - rtl_pwrseq: rtl_pwrseq { + rtl_pwrseq: pwrseq-0 { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; }; @@ -177,7 +177,7 @@ non-removable; status = "okay"; - rtl8723bs: sdio_wifi@1 { + rtl8723bs: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts index ecb91fb899f..435a189332e 100644 --- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts @@ -82,7 +82,7 @@ }; }; - reg_axp_ipsout: axp_ipsout { + reg_axp_ipsout: regulator-axp-ipsout { compatible = "regulator-fixed"; regulator-name = "axp-ipsout"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts index 3bfae98f3cc..29199b6a3b4 100644 --- a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts +++ b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts @@ -60,7 +60,7 @@ stdout-path = "serial0:115200n8"; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ }; diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi index 5574299685a..5f44f09c554 100644 --- a/arch/arm/dts/sun7i-a20.dtsi +++ b/arch/arm/dts/sun7i-a20.dtsi @@ -153,14 +153,14 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <100000>; hysteresis = <2000>; diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index a0cac966af3..4ebb0a7a78f 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -108,7 +108,7 @@ #size-cells = <1>; ranges; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -116,7 +116,7 @@ clock-output-names = "osc24M"; }; - ext_osc32k: ext_osc32k_clk { + ext_osc32k: ext-osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; @@ -730,7 +730,7 @@ compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; - ar100: ar100_clk { + ar100: ar100-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -739,7 +739,7 @@ clock-output-names = "ar100"; }; - ahb0: ahb0_clk { + ahb0: ahb0-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <1>; @@ -748,14 +748,14 @@ clock-output-names = "ahb0"; }; - apb0: apb0_clk { + apb0: apb0-clk { compatible = "allwinner,sun8i-a23-apb0-clk"; #clock-cells = <0>; clocks = <&ahb0>; clock-output-names = "apb0"; }; - apb0_gates: apb0_gates_clk { + apb0_gates: apb0-gates-clk { compatible = "allwinner,sun8i-a23-apb0-gates-clk"; #clock-cells = <1>; clocks = <&apb0>; @@ -764,7 +764,7 @@ "apb0_i2c"; }; - apb0_rst: apb0_rst { + apb0_rst: apb0-rst { compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; }; diff --git a/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts index d5f6aebd721..0c585a6d990 100644 --- a/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -52,7 +52,7 @@ ethernet0 = &esp8089; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ /* The esp8089 needs 200 ms after driving wifi-en high */ @@ -76,7 +76,7 @@ non-removable; status = "okay"; - esp8089: sdio_wifi@1 { + esp8089: wifi@1 { compatible = "esp,esp8089"; reg = <1>; esp,crystal-26M-en = <2>; diff --git a/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts index 9f9232a2fef..63cb4e194a0 100644 --- a/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -52,7 +52,7 @@ ethernet0 = &esp8089; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ /* The esp8089 needs 200 ms after driving wifi-en high */ @@ -69,7 +69,7 @@ non-removable; status = "okay"; - esp8089: sdio_wifi@1 { + esp8089: wifi@1 { compatible = "esp,esp8089"; reg = <1>; esp,crystal-26M-en = <2>; diff --git a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts index 2dfdd0a3151..f00ce03ffc8 100644 --- a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts @@ -85,7 +85,7 @@ non-removable; status = "okay"; - rtl8703as: sdio_wifi@1 { + rtl8703as: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts index 065cb620aa9..162ba93f748 100644 --- a/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts +++ b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts @@ -78,7 +78,7 @@ non-removable; status = "okay"; - rtl8723bs: sdio_wifi@1 { + rtl8723bs: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 30fdd2703b1..36b2d78cdab 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -323,35 +323,35 @@ }; trips { - cpu_alert0: cpu_alert0 { + cpu_alert0: cpu-alert0 { /* milliCelsius */ temperature = <75000>; hysteresis = <2000>; type = "passive"; }; - gpu_alert0: gpu_alert0 { + gpu_alert0: gpu-alert0 { /* milliCelsius */ temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_alert1: cpu_alert1 { + cpu_alert1: cpu-alert1 { /* milliCelsius */ temperature = <90000>; hysteresis = <2000>; type = "hot"; }; - gpu_alert1: gpu_alert1 { + gpu_alert1: gpu-alert1 { /* milliCelsius */ temperature = <95000>; hysteresis = <2000>; type = "hot"; }; - cpu_crit: cpu_crit { + cpu_crit: cpu-crit { /* milliCelsius */ temperature = <110000>; hysteresis = <2000>; diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts index 197cf6959b5..582b919336f 100644 --- a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts @@ -95,7 +95,7 @@ gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts index e26af7cf10e..c5677f99e15 100644 --- a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts @@ -144,7 +144,7 @@ compatible = "linux,spdif-dit"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&ac100_rtc 1>; clock-names = "ext_clock"; diff --git a/arch/arm/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/dts/sun8i-a83t-tbs-a711.dts index 13ae10f60d5..a2685fb53e3 100644 --- a/arch/arm/dts/sun8i-a83t-tbs-a711.dts +++ b/arch/arm/dts/sun8i-a83t-tbs-a711.dts @@ -123,7 +123,7 @@ vin-supply = <®_vbat>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi index cc40622466a..90f2c08d051 100644 --- a/arch/arm/dts/sun8i-a83t.dtsi +++ b/arch/arm/dts/sun8i-a83t.dtsi @@ -164,7 +164,7 @@ ranges; /* TODO: PRCM block has a mux for this. */ - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -177,14 +177,14 @@ * It is an internal RC-based oscillator. * TODO: Its controls are in the PRCM block. */ - osc16M: osc16M_clk { + osc16M: osc16M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <16000000>; clock-output-names = "osc16M"; }; - osc16Md512: osc16Md512_clk { + osc16Md512: osc16Md512-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <512>; @@ -1126,7 +1126,7 @@ #reset-cells = <1>; }; - r_cpucfg@1f01c00 { + cpucfg@1f01c00 { compatible = "allwinner,sun8i-a83t-r-cpucfg"; reg = <0x1f01c00 0x400>; }; diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts index d729b7c705d..d3a7c9fa23e 100644 --- a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -103,7 +103,7 @@ cpu-supply = <®_vcc1v2>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts index 3356f4210d4..79b03b31c5e 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts @@ -43,11 +43,12 @@ /* Orange Pi R1 is based on Orange Pi Zero design */ #include "sun8i-h2-plus-orangepi-zero.dts" +/delete-node/ ®_vcc_wifi; + / { model = "Xunlong Orange Pi R1"; compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; - /delete-node/ reg_vcc_wifi; /* * Ths pin of this regulator is the same with the Wi-Fi extra @@ -89,7 +90,7 @@ vmmc-supply = <®_vcc3v3>; vqmmc-supply = <®_vcc3v3>; - rtl8189etv: sdio_wifi@1 { + rtl8189etv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index 3706216ffb4..1b001f2ad0e 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -80,7 +80,7 @@ }; }; - reg_vcc_wifi: reg_vcc_wifi { + reg_vcc_wifi: reg-vcc-wifi { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -105,7 +105,7 @@ states = <1100000 0>, <1300000 1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; post-power-on-delay-ms = <200>; @@ -149,7 +149,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - xr819: sdio_wifi@1 { + xr819: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts index a6d38ecee14..5b77300307d 100644 --- a/arch/arm/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts @@ -122,7 +122,7 @@ compatible = "linux,spdif-dit"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; @@ -185,7 +185,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - sdiowifi: sdio_wifi@1 { + sdiowifi: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts index 343b02b9715..2b0566d4b38 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-duo2.dts @@ -87,7 +87,7 @@ vin-supply = <®_vcc5v0>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; @@ -119,7 +119,7 @@ non-removable; status = "okay"; - sdio_wifi: sdio_wifi@1 { + sdio_wifi: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts index 4ba533b0340..59bd0746acf 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts @@ -62,7 +62,7 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; @@ -132,7 +132,7 @@ non-removable; status = "okay"; - sdio_wifi: sdio_wifi@1 { + sdio_wifi: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts index 9e1a33f94ca..6d85370e04f 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts @@ -73,7 +73,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ }; diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts index 42cd1131adf..870649760f7 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-r1.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts @@ -43,7 +43,7 @@ <1300000 0x1>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts index f1f9dbead32..d2ae47b074b 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -105,7 +105,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ }; @@ -169,7 +169,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189: sdio_wifi@1 { + rtl8189: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h3-orangepi-lite.dts index 305b34a321f..6a4316a5246 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts @@ -143,7 +143,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189ftv: sdio_wifi@1 { + rtl8189ftv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts index babf4cf1b2f..8a49b3376df 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts @@ -63,7 +63,7 @@ * Explicitly define the sdio device, so that we can add an ethernet * alias for it (which e.g. makes u-boot set a mac-address). */ - rtl8189ftv: sdio_wifi@1 { + rtl8189ftv: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts index 561ea1d2f86..7a6444a10e2 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -92,7 +92,7 @@ regulator-max-microvolt = <3300000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sun8i-q8-common.dtsi b/arch/arm/dts/sun8i-q8-common.dtsi index 3d9a1524e17..272584881bb 100644 --- a/arch/arm/dts/sun8i-q8-common.dtsi +++ b/arch/arm/dts/sun8i-q8-common.dtsi @@ -62,7 +62,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; /* * Q8 boards use various PL# pins as wifi-en. On other boards @@ -94,7 +94,7 @@ non-removable; status = "okay"; - sdio_wifi: sdio_wifi@1 { + sdio_wifi: wifi@1 { reg = <1>; }; }; diff --git a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts index f97218e70c1..5001f10c27a 100644 --- a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts +++ b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts @@ -88,7 +88,7 @@ regulator-max-microvolt = <5000000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/dts/sun8i-r16-parrot.dts b/arch/arm/dts/sun8i-r16-parrot.dts index 2be1b76fe2f..40109969cc8 100644 --- a/arch/arm/dts/sun8i-r16-parrot.dts +++ b/arch/arm/dts/sun8i-r16-parrot.dts @@ -75,7 +75,7 @@ }; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */ }; diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index 28197bbcb1d..cd2351acc32 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -100,7 +100,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ clocks = <&ccu CLK_OUTA>; diff --git a/arch/arm/dts/sun8i-r40-oka40i-c.dts b/arch/arm/dts/sun8i-r40-oka40i-c.dts index 0bd1336206b..15b0b4de626 100644 --- a/arch/arm/dts/sun8i-r40-oka40i-c.dts +++ b/arch/arm/dts/sun8i-r40-oka40i-c.dts @@ -62,7 +62,7 @@ regulator-max-microvolt = <5000000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN clocks = <&ccu CLK_OUTA>; diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts index 20966e954ed..e0d4404b595 100644 --- a/arch/arm/dts/sun8i-s3-pinecube.dts +++ b/arch/arm/dts/sun8i-s3-pinecube.dts @@ -51,7 +51,7 @@ startup-delay-us = <200000>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index e8a04476b77..9e13c2aa891 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -98,7 +98,7 @@ #size-cells = <1>; ranges; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -106,7 +106,7 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts index 434871040ac..6575ef27445 100644 --- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts @@ -94,7 +94,7 @@ enable-active-high; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ clocks = <&ccu CLK_OUTA>; diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi index 7d3f3300f43..a1ae0929cec 100644 --- a/arch/arm/dts/sun9i-a80.dtsi +++ b/arch/arm/dts/sun9i-a80.dtsi @@ -196,14 +196,14 @@ * The actual TX clock rate is not controlled by the * gmac_tx clock. */ - mii_phy_tx_clk: mii_phy_tx_clk { + mii_phy_tx_clk: mii-phy-tx-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; clock-output-names = "mii_phy_tx"; }; - gmac_int_tx_clk: gmac_int_tx_clk { + gmac_int_tx_clk: gmac-int-tx-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <125000000>; diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi index 1d1d127cf38..873817ddb4e 100644 --- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi @@ -98,7 +98,7 @@ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ clocks = <&rtc CLK_OSC32K_FANOUT>; diff --git a/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi index 60804b0e6c5..be5f5528a11 100644 --- a/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi +++ b/arch/arm/dts/sunxi-h3-h5-emlid-neutis.dtsi @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - wifi_pwrseq: wifi_pwrseq { + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ post-power-on-delay-ms = <200>; diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi index bdc796f4622..43f6938381c 100644 --- a/arch/arm/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/dts/sunxi-h3-h5.dtsi @@ -83,7 +83,7 @@ #size-cells = <1>; ranges; - osc24M: osc24M_clk { + osc24M: osc24M-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -91,7 +91,7 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + osc32k: osc32k-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi index 1abe44f4042..8735292a127 100644 --- a/arch/arm/dts/versal-mini-ospi.dtsi +++ b/arch/arm/dts/versal-mini-ospi.dtsi @@ -36,7 +36,7 @@ ranges; ospi: spi@f1010000 { - compatible = "cadence,qspi", "cdns,qspi-nor"; + compatible = "cdns,qspi-nor"; status = "okay"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; clock-names = "ref_clk", "pclk"; diff --git a/arch/arm/dts/versal-net-mini-emmc.dts b/arch/arm/dts/versal-net-mini-emmc.dts index 8a864ba3ed3..e200fb694c6 100644 --- a/arch/arm/dts/versal-net-mini-emmc.dts +++ b/arch/arm/dts/versal-net-mini-emmc.dts @@ -42,14 +42,14 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; - sdhci1: sdhci@f1050000 { + sdhci1: mmc@f1050000 { compatible = "xlnx,versal-net-emmc"; status = "okay"; non-removable; diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi index 5d188db62d9..a9bf7cc4248 100644 --- a/arch/arm/dts/versal-net-mini-ospi.dtsi +++ b/arch/arm/dts/versal-net-mini-ospi.dtsi @@ -42,7 +42,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <0x2>; @@ -50,7 +50,7 @@ ranges; ospi: spi@f1010000 { - compatible = "cadence,qspi", "cdns,qspi-nor"; + compatible = "cdns,qspi-nor"; status = "okay"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; clock-names = "ref_clk", "pclk"; diff --git a/arch/arm/dts/versal-net-mini-qspi.dtsi b/arch/arm/dts/versal-net-mini-qspi.dtsi index 097b58c633b..e29a3f36d6e 100644 --- a/arch/arm/dts/versal-net-mini-qspi.dtsi +++ b/arch/arm/dts/versal-net-mini-qspi.dtsi @@ -42,7 +42,7 @@ bootph-all; }; - amba: amba { + amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 1727a1cc15c..4de29d5d3ff 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -358,6 +358,7 @@ status = "okay"; rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <10 10>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; assigned-clock-rates = <100000000>; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 5859e6cd8c2..d95a05e2159 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -107,7 +107,7 @@ pwm-fan { compatible = "pwm-fan"; status = "okay"; - pwms = <&ttc0 2 40000 0>; + pwms = <&ttc0 2 40000 1>; }; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 34f592c1a85..6a29f610153 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1025,6 +1025,7 @@ reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; + resets = <&zynqmp_reset ZYNQMP_RESET_UART0>; }; uart1: serial@ff010000 { @@ -1036,6 +1037,7 @@ reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; + resets = <&zynqmp_reset ZYNQMP_RESET_UART1>; }; usb0: usb@ff9d0000 { diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 513cdaca859..7abcd1cb615 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -37,7 +37,6 @@ u32 wait_on_value(u32, u32, void *, u32); #ifdef CONFIG_NOR_BOOT void enable_norboot_pin_mux(void); #endif -void am33xx_spl_board_init(void); int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev); int am335x_get_mpu_vdd(int sil_rev, int frequency); int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency); diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index ef0caed3f7f..b311d176d64 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -129,7 +129,7 @@ DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctre else ifeq ($(CONFIG_ARCH_IMX8M), y) IMAGE_TYPE := imx8mimage DEPFILE_EXISTS := 0 -else ifeq ($(CONFIG_ARCH_IMX9), y) +else ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) IMAGE_TYPE := imx8image DEPFILE_EXISTS := 0 else @@ -215,7 +215,7 @@ flash.bin: spl/u-boot-spl.bin FORCE endif endif -ifeq ($(CONFIG_ARCH_IMX9), y) +ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) quiet_cmd_imx9_check = CHECK $@ cmd_imx9_check = $(srctree)/tools/imx9_image.sh $@ diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index accba502e49..834aca82bcf 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -258,14 +258,14 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) return -EIO; } - if (!power_domain_lookup_name("audio_sai0", &pd)) { + if (!imx8_power_domain_lookup_name("audio_sai0", &pd)) { if (power_domain_on(&pd)) { printf("Error power on SAI0\n"); return -EIO; } } - if (!power_domain_lookup_name("audio_ocram", &pd)) { + if (!imx8_power_domain_lookup_name("audio_ocram", &pd)) { if (power_domain_on(&pd)) { printf("Error power on HIFI RAM\n"); return -EIO; diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig index 49ea25250a3..fbca241e106 100644 --- a/arch/arm/mach-imx/imx8ulp/Kconfig +++ b/arch/arm/mach-imx/imx8ulp/Kconfig @@ -23,6 +23,7 @@ choice config TARGET_IMX8ULP_EVK bool "imx8ulp_evk" + select BINMAN select IMX8ULP select SUPPORT_SPL select IMX8ULP_DRAM diff --git a/arch/arm/mach-imx/imx8ulp/container.cfg b/arch/arm/mach-imx/imx8ulp/container.cfg new file mode 100644 index 00000000000..029b79128c8 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/container.cfg @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +BOOT_FROM SD 0x400 +SOC_TYPE ULP +CONTAINER +IMAGE A35 bl31.bin 0x20040000 +IMAGE A35 u-boot.bin CONFIG_TEXT_BASE diff --git a/arch/arm/mach-imx/imx8ulp/imximage.cfg b/arch/arm/mach-imx/imx8ulp/imximage.cfg new file mode 100644 index 00000000000..a55359fee23 --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/imximage.cfg @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +BOOT_FROM SD 0x400 +SOC_TYPE ULP +APPEND mx8ulpa2-ahab-container.img +CONTAINER +IMAGE PWR upower.bin +IMAGE M40 m33_image.bin 0x1ffc2000 +IMAGE A35 u-boot-spl-ddr.bin 0x22020000 diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 84a60dedd72..abdc1e40335 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -337,14 +337,6 @@ int board_early_init_f(void) return 0; } -/* - * This function is the place to do per-board things such as ramp up the - * MPU clock frequency. - */ -__weak void am33xx_spl_board_init(void) -{ -} - #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) static void rtc32k_enable(void) { diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index e1ea3515ac1..649bc07047a 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -269,7 +269,7 @@ skip_ipu1: debug("%s: IPU2 failed to start (%d)\n", __func__, ret); } -void spl_board_init(void) +void spl_soc_init(void) { /* Prepare console output */ preloader_console_init(); @@ -286,9 +286,6 @@ void spl_board_init(void) #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) hw_watchdog_init(); #endif -#ifdef CONFIG_AM33XX - am33xx_spl_board_init(); -#endif if (IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU)) spl_boot_ipu(); diff --git a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c index 2d7e9711015..e77189eef6c 100644 --- a/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/syscon_rk3308.c @@ -16,4 +16,7 @@ U_BOOT_DRIVER(syscon_rk3308) = { .name = "rk3308_syscon", .id = UCLASS_SYSCON, .of_match = rk3308_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif }; diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 014ebf9f0ba..899cf909fbb 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -32,6 +32,16 @@ config TARGET_QUARTZ64_RK3566 help Pine64 Quartz64 single board computer with a RK3566 SoC. +config TARGET_RADXA_ZERO_3_RK3566 + bool "Radxa ZERO 3W/3E" + help + Radxa ZERO 3W/3E single board computers with a RK3566 SoC. + +config TARGET_ORANGEPI_3B_RK3566 + bool "Xunlong Orange Pi 3B" + help + Xunlong Orange Pi 3B single board computer with a RK3566 SoC. + endchoice config ROCKCHIP_BOOT_MODE_REG @@ -54,5 +64,7 @@ source "board/anbernic/rgxx3_rk3566/Kconfig" source "board/hardkernel/odroid_m1/Kconfig" source "board/pine64/quartz64_rk3566/Kconfig" source "board/powkiddy/x55/Kconfig" +source "board/radxa/zero3-rk3566/Kconfig" +source "board/xunlong/orangepi-3b-rk3566/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index e751d64e1a1..a76a470cc98 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -6,6 +6,29 @@ config TARGET_EVB_RK3588 help RK3588 EVB is a evaluation board for Rockchp RK3588. +config TARGET_CM3588_NAS_RK3588 + bool "FriendlyElec CM3588 NAS" + select BOARD_LATE_INIT + help + The CM3588 NAS by FriendlyElec pairs the CM3588 compute module, based + on the Rockchip RK3588 SoC, with the CM3588 NAS Kit carrier board. + + Hardware features: + - Rockchip RK3588 SoC + - 4GB/8GB/16GB LPDDR4x RAM + - 0GB/64GB HS400 eMMC + - MicroSD card slot + - 1x RTL8125B 2.5G Ethernet + - 4x M.2 M-Key with PCIe 3.0 x1 (via bifurcation) for NVMe SSDs + - 2x USB 3.0 (USB 3.1 Gen1) Type-A, 1x USB 2.0 Type-A + - 1x USB 3.0 Type-C with DP AltMode support + - 2x HDMI 2.1 out, 1x HDMI in + - MIPI-CSI Connector, MIPI-DSI Connector + - 40-pin GPIO header + - 4 buttons: power, reset, recovery, MASK, user button + - 3.5mm Headphone out, 2.0mm PH-2A Mic in + - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector + config TARGET_JAGUAR_RK3588 bool "Theobroma Systems SBC-RK3588-AMR (Jaguar)" select BOARD_LATE_INIT @@ -185,6 +208,34 @@ config TARGET_ROCK5B_RK3588 USB PD over USB Type-C Size: 100mm x 72mm (Pico-ITX form factor) +config TARGET_ROCK_5_ITX_RK3588 + bool "Radxa ROCK-5-ITX RK3588 board" + select BOARD_LATE_INIT + help + Radxa ROCK-5-ITX is a Rockchip RK3588 based SBC (Single Board + Computer) by Radxa in the ITX formfactor. + + There are variants depending on the DRAM size : from 4G up to 32G. + + Specification: + + Rockchip Rk3588 SoC + 4x ARM Cortex-A76, 4x ARM Cortex-A55 + 4/8/16/24/32GB memory LPDDR5 + Mali G610MC4 GPU + 2x MIPI CSI 2 multiple lanes connector + eMMC + uSD slot (up to 128GB) + M.2 M-key and M.2 E-key connector + 4x SATA + 2x USB 2.0 + 4x USB 3.0 Type-A, 2x USB 2.0 Panel, 1x USB 3.0 Type-C + 2x HDMI 2.1 output, 1x HDMI input + DP via Type-C + 2x DSI via PCB connector + 2x 2.5 Gbps Ethernet port + Front-panel connectors for audio and case-power, -leds + Powered by either 12V, ATX power-supply or PoE + config TARGET_SIGE7_RK3588 bool "ArmSoM Sige7 RK3588 board" select BOARD_LATE_INIT @@ -311,6 +362,7 @@ config TEXT_BASE source "board/armsom/sige7-rk3588/Kconfig" source "board/edgeble/neural-compute-module-6/Kconfig" +source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" @@ -319,6 +371,7 @@ source "board/pine64/quartzpro64-rk3588/Kconfig" source "board/turing/turing-rk1-rk3588/Kconfig" source "board/radxa/rock5a-rk3588s/Kconfig" source "board/radxa/rock5b-rk3588/Kconfig" +source "board/radxa/rock-5-itx-rk3588/Kconfig" source "board/rockchip/evb_rk3588/Kconfig" source "board/rockchip/toybrick_rk3588/Kconfig" source "board/theobroma-systems/jaguar_rk3588/Kconfig" diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index c75e453d573..5b6d765099d 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -36,9 +36,11 @@ static const struct { } zynq_fpga_descs[] = { ZYNQ_DESC(7Z007S), ZYNQ_DESC(7Z010), + ZYNQ_DESC(7Z010_LR), ZYNQ_DESC(7Z012S), ZYNQ_DESC(7Z014S), ZYNQ_DESC(7Z015), + ZYNQ_DESC(7Z020_LR), ZYNQ_DESC(7Z020), ZYNQ_DESC(7Z030), ZYNQ_DESC(7Z035), diff --git a/arch/mips/mach-octeon/octeon_fdt.c b/arch/mips/mach-octeon/octeon_fdt.c index c74fe9d9fb8..15ce292be95 100644 --- a/arch/mips/mach-octeon/octeon_fdt.c +++ b/arch/mips/mach-octeon/octeon_fdt.c @@ -687,13 +687,6 @@ int octeon_fdt_i2c_get_bus(const void *fdt, int node_offset) while (node_offset > 0 && !(found = !fdt_node_check_compatible(fdt, node_offset, compat))) { node_offset = fdt_parent_offset(fdt, node_offset); -#ifdef CONFIG_OCTEON_I2C_FDT - bus = i2c_get_bus_num_fdt(node_offset); - if (bus >= 0) { - debug("%s: Found bus 0x%x\n", __func__, bus); - return bus; - } -#endif } if (!found) { printf("Error: node %d in device tree is not a child of the I2C bus\n", diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 0ed85b354cf..4f15a560902 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -340,6 +340,8 @@ void *board_fdt_blob_setup(int *ret) int err; int fd; + if (gd->fdt_blob) + return (void *)gd->fdt_blob; blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0); *ret = 0; if (!state->fdt_fname) { diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 46ff305b536..f5c9a8aecf2 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -47,12 +47,24 @@ struct os_mem_hdr { ssize_t os_read(int fd, void *buf, size_t count) { - return read(fd, buf, count); + ssize_t ret; + + ret = read(fd, buf, count); + if (ret == -1) + return -errno; + + return ret; } ssize_t os_write(int fd, const void *buf, size_t count) { - return write(fd, buf, count); + ssize_t ret; + + ret = write(fd, buf, count); + if (ret == -1) + return -errno; + + return ret; } int os_printf(const char *fmt, ...) @@ -69,6 +81,8 @@ int os_printf(const char *fmt, ...) off_t os_lseek(int fd, off_t offset, int whence) { + off_t ret; + if (whence == OS_SEEK_SET) whence = SEEK_SET; else if (whence == OS_SEEK_CUR) @@ -77,7 +91,11 @@ off_t os_lseek(int fd, off_t offset, int whence) whence = SEEK_END; else os_exit(1); - return lseek(fd, offset, whence); + ret = lseek(fd, offset, whence); + if (ret == -1) + return -errno; + + return ret; } int os_open(const char *pathname, int os_flags) @@ -808,7 +826,7 @@ static int make_exec(char *fname, const void *data, int size) * @count: Number of arguments in @add_args * Return: 0 if OK, -ENOMEM if out of memory */ -static int add_args(char ***argvp, char *add_args[], int count) +static int add_args(char ***argvp, const char *add_args[], int count) { char **argv, **ap; int argc; @@ -859,7 +877,7 @@ static int os_jump_to_file(const char *fname, bool delete_it) struct sandbox_state *state = state_get_current(); char mem_fname[30]; int fd, err; - char *extra_args[5]; + const char *extra_args[5]; char **argv = state->argv; int argc; #ifdef DEBUG @@ -964,7 +982,7 @@ int os_find_u_boot(char *fname, int maxlen, bool use_img, p = strstr(fname, subdir); if (p) { if (*next_prefix) - /* e.g. ".../tpl/u-boot-spl" to "../spl/u-boot-spl" */ + /* e.g. ".../tpl/u-boot-spl" to ".../spl/u-boot-spl" */ memcpy(p + 1, next_prefix, strlen(next_prefix)); else /* e.g. ".../spl/u-boot" to ".../u-boot" */ diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index 9ad9da686c6..bcb1ca10a51 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -3,13 +3,18 @@ * Copyright (c) 2016 Google, Inc */ +#define LOG_CATEGORY LOGC_BOOT + #include <dm.h> #include <hang.h> #include <handoff.h> +#include <image.h> #include <init.h> #include <log.h> +#include <mapmem.h> #include <os.h> #include <spl.h> +#include <upl.h> #include <asm/global_data.h> #include <asm/spl.h> #include <asm/state.h> @@ -51,7 +56,8 @@ void board_init_f(ulong flag) void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = BOOT_DEVICE_VBE; - spl_boot_list[1] = BOOT_DEVICE_BOARD; + spl_boot_list[1] = BOOT_DEVICE_UPL; + spl_boot_list[2] = BOOT_DEVICE_BOARD; } static int spl_board_load_file(struct spl_image_info *spl_image, @@ -179,3 +185,115 @@ int handoff_arch_save(struct spl_handoff *ho) return 0; } + +/* Context used to hold file descriptor */ +struct load_ctx { + int fd; +}; + +static ulong read_fit_image(struct spl_load_info *load, ulong offset, + ulong size, void *buf) +{ + struct load_ctx *load_ctx = load->priv; + off_t ret; + ssize_t res; + + ret = os_lseek(load_ctx->fd, offset, OS_SEEK_SET); + if (ret < 0) { + printf("Failed to seek to %zx, got %zx\n", offset, ret); + return log_msg_ret("lse", ret); + } + + res = os_read(load_ctx->fd, buf, size); + if (res < 0) { + printf("Failed to read %lx bytes, got %ld\n", size, res); + return log_msg_ret("osr", res); + } + + return size; +} + +int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image) +{ + struct legacy_img_hdr *header; + struct load_ctx load_ctx; + struct spl_load_info load; + int ret; + int fd; + + memset(&load, '\0', sizeof(load)); + spl_set_bl_len(&load, IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) ? 512 : 1); + load.read = read_fit_image; + + ret = sandbox_find_next_phase(fname, maxlen, true); + if (ret) { + printf("%s not found, error %d\n", fname, ret); + return log_msg_ret("nph", ret); + } + + header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + + log_debug("reading from %s\n", fname); + fd = os_open(fname, OS_O_RDONLY); + if (fd < 0) { + printf("Failed to open '%s'\n", fname); + return log_msg_ret("ope", -errno); + } + ret = os_read(fd, header, sizeof(*header)); + if (ret != sizeof(*header)) { + printf("Failed to read %lx bytes, got %d\n", sizeof(*header), + ret); + return log_msg_ret("rea", ret); + } + load_ctx.fd = fd; + + load.priv = &load_ctx; + + ret = spl_load_simple_fit(image, &load, 0, header); + if (ret) + return log_msg_ret("slf", ret); + + return 0; +} + +static int upl_load_from_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + long long size; + char *fname; + int ret, fd; + ulong addr; + + if (!CONFIG_IS_ENABLED(UPL_OUT)) + return -ENOTSUPP; + + spl_upl_init(); + fname = os_malloc(256); + + ret = sandbox_spl_load_fit(fname, 256, spl_image); + if (ret) + return log_msg_ret("fit", ret); + spl_image->flags = SPL_SANDBOXF_ARG_IS_BUF; + spl_image->arg = map_sysmem(spl_image->load_addr, 0); + /* size is set by load_simple_fit(), offset is left as 0 */ + + /* now read the whole FIT into memory */ + fd = os_open(fname, OS_O_RDONLY); + if (fd < 0) + return log_msg_ret("op2", -ENOENT); + if (os_get_filesize(fname, &size)) + return log_msg_ret("fis", -ENOENT); + + /* place it after the loaded image, allowing plenty of space */ + addr = ALIGN(spl_image->load_addr + size, 0x1000); + log_debug("Loading whole FIT to %lx\n", addr); + if (os_read(fd, map_sysmem(addr, 0), size) != size) + return log_msg_ret("rea", -EIO); + os_close(fd); + + /* tell UPL where it is */ + upl_set_fit_addr(addr); + + return 0; +} +SPL_LOAD_IMAGE_METHOD("upl", 4, BOOT_DEVICE_UPL, upl_load_from_image); diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index dce80416529..9ad5d46271a 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -431,6 +431,14 @@ static int sandbox_cmdline_cb_autoboot_keyed(struct sandbox_state *state, } SANDBOX_CMDLINE_OPT(autoboot_keyed, 0, "Allow keyed autoboot"); +static int sandbox_cmdline_cb_upl(struct sandbox_state *state, const char *arg) +{ + state->upl = true; + + return 0; +} +SANDBOX_CMDLINE_OPT(upl, 0, "Enable Universal Payload (UPL)"); + static void setup_ram_buf(struct sandbox_state *state) { /* Zero the RAM buffer if we didn't read it, to keep valgrind happy */ @@ -483,6 +491,9 @@ int sandbox_main(int argc, char *argv[]) text_base = os_find_text_base(); + memset(&data, '\0', sizeof(data)); + gd = &data; + /* * This must be the first invocation of os_malloc() to have * state->ram_buf in the low 4 GiB. @@ -501,8 +512,6 @@ int sandbox_main(int argc, char *argv[]) os_exit(1); memcpy(os_argv, argv, size); - memset(&data, '\0', sizeof(data)); - gd = &data; gd->arch.text_base = text_base; state = state_get_current(); @@ -539,6 +548,9 @@ int sandbox_main(int argc, char *argv[]) goto err; } + if (state->upl) + gd->flags |= GD_FLG_UPL; + #if CONFIG_IS_ENABLED(SYS_MALLOC_F) gd->malloc_base = CFG_MALLOC_F_ADDR; #endif @@ -557,7 +569,7 @@ int sandbox_main(int argc, char *argv[]) log_debug("debug: %s\n", __func__); /* Do pre- and post-relocation init */ - board_init_f(0); + board_init_f(gd->flags); board_init_r(gd->new_gd, 0); diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h index 4fab24cd156..d824b2123a2 100644 --- a/arch/sandbox/include/asm/spl.h +++ b/arch/sandbox/include/asm/spl.h @@ -6,6 +6,8 @@ #ifndef __asm_spl_h #define __asm_spl_h +struct spl_image_info; + enum { BOOT_DEVICE_MMC1, BOOT_DEVICE_MMC2, @@ -16,6 +18,7 @@ enum { BOOT_DEVICE_NOR, BOOT_DEVICE_SPI, BOOT_DEVICE_NAND, + BOOT_DEVICE_UPL, }; /** @@ -31,4 +34,16 @@ enum { */ int sandbox_find_next_phase(char *fname, int maxlen, bool use_img); +/** + * sandbox_spl_load_fit() - Load the next phase from a FIT + * + * Loads a FIT containing the next phase and sets it up for booting + * + * @fname: Returns filename loaded + * @maxlen: Maximum length for @fname including \0 + * @image: Place to put SPL-image information + * Return: 0 if OK, -ve on error + */ +int sandbox_spl_load_fit(char *fname, int maxlen, struct spl_image_info *image); + #endif diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index c84a1f7060f..6b50473ed41 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -97,6 +97,7 @@ struct sandbox_state { bool autoboot_keyed; /* Use keyed-autoboot feature */ bool disable_eth; /* Disable Ethernet devices */ bool disable_sf_bootdevs; /* Don't bind SPI flash bootdevs */ + bool upl; /* Enable Universal Payload (UPL) */ /* Pointer to information for each SPI bus/cs */ struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS] diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index dbcea7f47ff..e1ed9bcabc7 100644 --- a/arch/x86/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h @@ -20,11 +20,12 @@ typedef unsigned short __kernel_gid_t; #if defined(__x86_64__) typedef unsigned long __kernel_size_t; typedef long __kernel_ssize_t; +typedef long __kernel_ptrdiff_t; #else typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; -#endif typedef int __kernel_ptrdiff_t; +#endif typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index 192a2fa6327..80e0ca805b5 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -79,7 +79,7 @@ static const struct ctrl_ioregs ddr3_ioregs = { #define OSC (V_OSCK/1000000) static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { int rc; diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c index 2d3f593d0ab..bfb6adf6d5c 100644 --- a/board/BuR/brsmarc1/board.c +++ b/board/BuR/brsmarc1/board.c @@ -72,7 +72,7 @@ static const struct ctrl_ioregs ddr3_ioregs = { #define OSC (V_OSCK / 1000000) const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index b9b595cb156..510d2af3147 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -79,7 +79,7 @@ static const struct ctrl_ioregs ddr3_ioregs = { #define OSC (V_OSCK / 1000000) const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { int rc; diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS index 1cc9aaa29a8..ede4b007540 100644 --- a/board/armltd/corstone1000/MAINTAINERS +++ b/board/armltd/corstone1000/MAINTAINERS @@ -1,6 +1,6 @@ CORSTONE1000 BOARD M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> -M: Xueliang Zhong <xueliang.zhong@arm.com> +M: Hugues Kamba Mpiana <hugues.kambampiana@arm.com> S: Maintained F: board/armltd/corstone1000/ F: include/configs/corstone1000.h diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 41d7567ad21..33ba7a7751c 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -75,7 +75,7 @@ static struct emif_regs ddr3_emif_reg_data = { const struct dpll_params dpll_ddr = { 400, OSC - 1, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { int mpu_vdd; int usb_cur_lim; diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index ab688745938..1f9dc2d8df1 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -34,6 +34,7 @@ #include <asm/emif.h> #include <asm/gpio.h> #include <i2c.h> +#include <i2c_eeprom.h> #include <miiphy.h> #include <cpsw.h> #include <linux/delay.h> @@ -51,21 +52,21 @@ static int shc_eeprom_valid; /* * Read header information from EEPROM into global structure. */ -#define EEPROM_ADDR 0x50 static int read_eeprom(void) { + struct udevice *dev; + int ret; + /* Check if baseboard eeprom is available */ - if (i2c_probe(EEPROM_ADDR)) { - puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); - return -ENODEV; + ret = uclass_first_device_err(UCLASS_I2C_EEPROM, &dev); + if (ret) { + puts("Could not find EEPROM.\n"); + return ret; } - /* read the eeprom using i2c */ - if (i2c_read(EEPROM_ADDR, 0, 2, (uchar *)&header, - sizeof(header))) { - puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); - return -EIO; - } + ret = i2c_eeprom_read(dev, 0, (uint8_t *)&header, sizeof(header)); + if (ret) + return ret; if (header.magic != HDR_MAGIC) { printf("Incorrect magic number (0x%x) in EEPROM\n", @@ -310,7 +311,7 @@ const struct dpll_params *get_dpll_ddr_params(void) const struct dpll_params dpll_mpu_shc_opp100 = { 99, MPUPLL_N, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { int sil_rev; int mpu_vdd; @@ -445,7 +446,6 @@ int board_init(void) #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (read_eeprom() < 0) puts("EEPROM Content Invalid.\n"); diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index c6d33c32ccd..40047cf6783 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -14,6 +14,7 @@ #include <env.h> #include <fsl_esdhc_imx.h> #include <init.h> +#include <i2c.h> #include <miiphy.h> #include <mtd_node.h> #include <net.h> @@ -256,7 +257,7 @@ static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads) { int ret; - ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads); + ret = setup_i2c(busnum, I2C_SPEED_STANDARD_RATE, 0x7f, pads); if (ret) printf("Warning: I2C%d setup failed: %d\n", busnum, ret); diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index 181581926c3..983991ea462 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -48,8 +48,6 @@ int board_init(void) gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_probe(TPS65218_CHIP_PM); return 0; } diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index 7c8226e6e16..c7b2237e5c1 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -4,6 +4,12 @@ # # Author: Igor Grinberg <grinberg@compulab.co.il> +CL_EEPROM=y + +ifdef CONFIG_TARGET_TRIMSLICE +CL_EEPROM= +endif + obj-y += common.o -obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += eeprom.o +obj-$(CL_EEPROM) += eeprom.o obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index efdaf342d5c..1b12d096041 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -34,19 +34,15 @@ static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */ static int cl_eeprom_read(uint offset, uchar *buf, int len) { + struct udevice *eeprom; int res; - unsigned int current_i2c_bus = i2c_get_bus_num(); - res = i2c_set_bus_num(cl_eeprom_bus); - if (res < 0) + res = i2c_get_chip_for_busnum(cl_eeprom_bus, CONFIG_SYS_I2C_EEPROM_ADDR, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &eeprom); + if (res) return res; - res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); - - i2c_set_bus_num(current_i2c_bus); - - return res; + return dm_i2c_read(eeprom, offset, (uint8_t *)buf, len); } static int cl_eeprom_setup(uint eeprom_bus) diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h index 9bd7604a999..0a44926ebd1 100644 --- a/board/compulab/common/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -10,7 +10,7 @@ #define _EEPROM_ #include <errno.h> -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) +#if !CONFIG_IS_ENABLED(TARGET_TRIMSLICE) int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus); u32 cl_eeprom_get_board_rev(uint eeprom_bus); int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus); diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 2ad256f8635..00f9a5ef341 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -56,10 +56,10 @@ DECLARE_GLOBAL_DATA_PTR; * boot device save register * ------------------------- * The boot device can be quired by 'spl_boot_device()' in - * 'am33xx_spl_board_init'. However it can't be saved in the u-boot + * 'spl_board_init'. However it can't be saved in the u-boot * environment here. In turn 'spl_boot_device' can't be called in * 'board_late_init' which allows writing to u-boot environment. - * To get the boot device from 'am33xx_spl_board_init' to + * To get the boot device from 'spl_board_init' to * 'board_late_init' we therefore use a scratch register from the RTC. */ #define CFG_SYS_RTC_SCRATCH0 0x60 @@ -192,7 +192,7 @@ const struct dpll_params dpll_ddr_evm_sk = { const struct dpll_params dpll_ddr_bone_black = { 400, OSC - 1, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; diff --git a/board/friendlyelec/cm3588-nas-rk3588/Kconfig b/board/friendlyelec/cm3588-nas-rk3588/Kconfig new file mode 100644 index 00000000000..fdc458a4264 --- /dev/null +++ b/board/friendlyelec/cm3588-nas-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_CM3588_NAS_RK3588 + +config SYS_BOARD + default "cm3588-nas-rk3588" + +config SYS_VENDOR + default "friendlyelec" + +config SYS_CONFIG_NAME + default "nanopc-t6-rk3588" + +endif diff --git a/board/friendlyelec/cm3588-nas-rk3588/MAINTAINERS b/board/friendlyelec/cm3588-nas-rk3588/MAINTAINERS new file mode 100644 index 00000000000..92b958ada6f --- /dev/null +++ b/board/friendlyelec/cm3588-nas-rk3588/MAINTAINERS @@ -0,0 +1,6 @@ +CM3588-NAS-RK3588 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: board/friendlyelec/cm3588-nas-rk3588 +F: configs/cm3588-nas-rk3588_defconfig +F: arch/arm/dts/rk3588-friendlyelec-cm3588-nas* diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 8313b37655f..e0eb8aa9f2b 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -80,7 +80,7 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } -void am33xx_spl_board_init(void) +void spl_board_init(void) { chilisom_spl_board_init(); } diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c index 3220727f236..f65551ece5e 100644 --- a/board/kosagi/novena/novena.c +++ b/board/kosagi/novena/novena.c @@ -137,23 +137,23 @@ struct novena_eeprom_data { int misc_init_r(void) { struct novena_eeprom_data data; - uchar *datap = (uchar *)&data; + uint8_t *datap = (uint8_t *)&data; const char *signature = "Novena"; + struct udevice *eeprom; int ret; /* If 'ethaddr' is already set, do nothing. */ if (env_get("ethaddr")) return 0; - /* EEPROM is at bus 2. */ - ret = i2c_set_bus_num(2); + /* EEPROM is at bus 2, address 0x56 */ + ret = i2c_get_chip_for_busnum(2, 0x56, 1, &eeprom); if (ret) { puts("Cannot select EEPROM I2C bus.\n"); return 0; } - /* EEPROM is at address 0x56. */ - ret = eeprom_read(0x56, 0, datap, sizeof(data)); + ret = dm_i2c_read(eeprom, 0, datap, sizeof(data)); if (ret) { puts("Cannot read I2C EEPROM.\n"); return 0; diff --git a/board/kosagi/novena/video.c b/board/kosagi/novena/video.c index be5a737a31d..67f98431b58 100644 --- a/board/kosagi/novena/video.c +++ b/board/kosagi/novena/video.c @@ -58,28 +58,29 @@ #define IT6521_RETRY_MAX 20 +static struct udevice *it6251_chip; +static struct udevice *it6251_lvds; + static int it6251_is_stable(void) { - const unsigned int caddr = NOVENA_IT6251_CHIPADDR; - const unsigned int laddr = NOVENA_IT6251_LVDSADDR; int status; int clkcnt; int rpclkcnt; int refstate; - rpclkcnt = (i2c_reg_read(caddr, 0x13) & 0xff) | - ((i2c_reg_read(caddr, 0x14) << 8) & 0x0f00); + rpclkcnt = (dm_i2c_reg_read(it6251_chip, 0x13) & 0xff) | + ((dm_i2c_reg_read(it6251_chip, 0x14) << 8) & 0x0f00); debug("RPCLKCnt: %d\n", rpclkcnt); - status = i2c_reg_read(caddr, IT6251_SYSTEM_STATUS); + status = dm_i2c_reg_read(it6251_chip, IT6251_SYSTEM_STATUS); debug("System status: 0x%02x\n", status); - clkcnt = (i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_LOW) & 0xff) | - ((i2c_reg_read(laddr, IT6251_REG_PCLK_CNT_HIGH) << 8) & + clkcnt = (dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_LOW) & 0xff) | + ((dm_i2c_reg_read(it6251_lvds, IT6251_REG_PCLK_CNT_HIGH) << 8) & 0x0f00); debug("Clock: 0x%02x\n", clkcnt); - refstate = i2c_reg_read(laddr, IT6251_REF_STATE); + refstate = dm_i2c_reg_read(it6251_lvds, IT6251_REF_STATE); debug("Ref Link State: 0x%02x\n", refstate); if ((refstate & 0x1f) != 0) @@ -97,16 +98,14 @@ static int it6251_is_stable(void) static int it6251_ready(void) { - const unsigned int caddr = NOVENA_IT6251_CHIPADDR; - /* Test if the IT6251 came out of reset by reading ID regs. */ - if (i2c_reg_read(caddr, IT6251_VENDOR_ID_LOW) != 0x15) + if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_LOW) != 0x15) return 0; - if (i2c_reg_read(caddr, IT6251_VENDOR_ID_HIGH) != 0xca) + if (dm_i2c_reg_read(it6251_chip, IT6251_VENDOR_ID_HIGH) != 0xca) return 0; - if (i2c_reg_read(caddr, IT6251_DEVICE_ID_LOW) != 0x51) + if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_LOW) != 0x51) return 0; - if (i2c_reg_read(caddr, IT6251_DEVICE_ID_HIGH) != 0x62) + if (dm_i2c_reg_read(it6251_chip, IT6251_DEVICE_ID_HIGH) != 0x62) return 0; return 1; @@ -114,116 +113,112 @@ static int it6251_ready(void) static void it6251_program_regs(void) { - const unsigned int caddr = NOVENA_IT6251_CHIPADDR; - const unsigned int laddr = NOVENA_IT6251_LVDSADDR; - - i2c_reg_write(caddr, 0x05, 0x00); + dm_i2c_reg_write(it6251_chip, 0x05, 0x00); mdelay(1); /* set LVDSRX address, and enable */ - i2c_reg_write(caddr, 0xfd, 0xbc); - i2c_reg_write(caddr, 0xfe, 0x01); + dm_i2c_reg_write(it6251_chip, 0xfd, 0xbc); + dm_i2c_reg_write(it6251_chip, 0xfe, 0x01); /* * LVDSRX */ /* This write always fails, because the chip goes into reset */ /* reset LVDSRX */ - i2c_reg_write(laddr, 0x05, 0xff); - i2c_reg_write(laddr, 0x05, 0x00); + dm_i2c_reg_write(it6251_lvds, 0x05, 0xff); + dm_i2c_reg_write(it6251_lvds, 0x05, 0x00); /* reset LVDSRX PLL */ - i2c_reg_write(laddr, 0x3b, 0x42); - i2c_reg_write(laddr, 0x3b, 0x43); + dm_i2c_reg_write(it6251_lvds, 0x3b, 0x42); + dm_i2c_reg_write(it6251_lvds, 0x3b, 0x43); /* something with SSC PLL */ - i2c_reg_write(laddr, 0x3c, 0x08); + dm_i2c_reg_write(it6251_lvds, 0x3c, 0x08); /* don't swap links, but writing reserved registers */ - i2c_reg_write(laddr, 0x0b, 0x88); + dm_i2c_reg_write(it6251_lvds, 0x0b, 0x88); /* JEIDA, 8-bit depth 0x11, orig 0x42 */ - i2c_reg_write(laddr, 0x2c, 0x01); + dm_i2c_reg_write(it6251_lvds, 0x2c, 0x01); /* "reserved" */ - i2c_reg_write(laddr, 0x32, 0x04); + dm_i2c_reg_write(it6251_lvds, 0x32, 0x04); /* "reserved" */ - i2c_reg_write(laddr, 0x35, 0xe0); + dm_i2c_reg_write(it6251_lvds, 0x35, 0xe0); /* "reserved" + clock delay */ - i2c_reg_write(laddr, 0x2b, 0x24); + dm_i2c_reg_write(it6251_lvds, 0x2b, 0x24); /* reset LVDSRX pix clock */ - i2c_reg_write(laddr, 0x05, 0x02); - i2c_reg_write(laddr, 0x05, 0x00); + dm_i2c_reg_write(it6251_lvds, 0x05, 0x02); + dm_i2c_reg_write(it6251_lvds, 0x05, 0x00); /* * DPTX */ /* set for two lane mode, normal op, no swapping, no downspread */ - i2c_reg_write(caddr, 0x16, 0x02); + dm_i2c_reg_write(it6251_chip, 0x16, 0x02); /* some AUX channel EDID magic */ - i2c_reg_write(caddr, 0x23, 0x40); + dm_i2c_reg_write(it6251_chip, 0x23, 0x40); /* power down lanes 3-0 */ - i2c_reg_write(caddr, 0x5c, 0xf3); + dm_i2c_reg_write(it6251_chip, 0x5c, 0xf3); /* enable DP scrambling, change EQ CR phase */ - i2c_reg_write(caddr, 0x5f, 0x06); + dm_i2c_reg_write(it6251_chip, 0x5f, 0x06); /* color mode RGB, pclk/2 */ - i2c_reg_write(caddr, 0x60, 0x02); + dm_i2c_reg_write(it6251_chip, 0x60, 0x02); /* dual pixel input mode, no EO swap, no RGB swap */ - i2c_reg_write(caddr, 0x61, 0x04); + dm_i2c_reg_write(it6251_chip, 0x61, 0x04); /* M444B24 video format */ - i2c_reg_write(caddr, 0x62, 0x01); + dm_i2c_reg_write(it6251_chip, 0x62, 0x01); /* vesa range / not interlace / vsync high / hsync high */ - i2c_reg_write(caddr, 0xa0, 0x0F); + dm_i2c_reg_write(it6251_chip, 0xa0, 0x0F); /* hpd event timer set to 1.6-ish ms */ - i2c_reg_write(caddr, 0xc9, 0xf5); + dm_i2c_reg_write(it6251_chip, 0xc9, 0xf5); /* more reserved magic */ - i2c_reg_write(caddr, 0xca, 0x4d); - i2c_reg_write(caddr, 0xcb, 0x37); + dm_i2c_reg_write(it6251_chip, 0xca, 0x4d); + dm_i2c_reg_write(it6251_chip, 0xcb, 0x37); /* enhanced framing mode, auto video fifo reset, video mute disable */ - i2c_reg_write(caddr, 0xd3, 0x03); + dm_i2c_reg_write(it6251_chip, 0xd3, 0x03); /* "vidstmp" and some reserved stuff */ - i2c_reg_write(caddr, 0xd4, 0x45); + dm_i2c_reg_write(it6251_chip, 0xd4, 0x45); /* queue number -- reserved */ - i2c_reg_write(caddr, 0xe7, 0xa0); + dm_i2c_reg_write(it6251_chip, 0xe7, 0xa0); /* info frame packets and reserved */ - i2c_reg_write(caddr, 0xe8, 0x33); + dm_i2c_reg_write(it6251_chip, 0xe8, 0x33); /* more AVI stuff */ - i2c_reg_write(caddr, 0xec, 0x00); + dm_i2c_reg_write(it6251_chip, 0xec, 0x00); /* select PC master reg for aux channel? */ - i2c_reg_write(caddr, 0x23, 0x42); + dm_i2c_reg_write(it6251_chip, 0x23, 0x42); /* send PC request commands */ - i2c_reg_write(caddr, 0x24, 0x00); - i2c_reg_write(caddr, 0x25, 0x00); - i2c_reg_write(caddr, 0x26, 0x00); + dm_i2c_reg_write(it6251_chip, 0x24, 0x00); + dm_i2c_reg_write(it6251_chip, 0x25, 0x00); + dm_i2c_reg_write(it6251_chip, 0x26, 0x00); /* native aux read */ - i2c_reg_write(caddr, 0x2b, 0x00); + dm_i2c_reg_write(it6251_chip, 0x2b, 0x00); /* back to internal */ - i2c_reg_write(caddr, 0x23, 0x40); + dm_i2c_reg_write(it6251_chip, 0x23, 0x40); /* voltage swing level 3 */ - i2c_reg_write(caddr, 0x19, 0xff); + dm_i2c_reg_write(it6251_chip, 0x19, 0xff); /* pre-emphasis level 3 */ - i2c_reg_write(caddr, 0x1a, 0xff); + dm_i2c_reg_write(it6251_chip, 0x1a, 0xff); /* start link training */ - i2c_reg_write(caddr, 0x17, 0x01); + dm_i2c_reg_write(it6251_chip, 0x17, 0x01); } static int it6251_init(void) { - const unsigned int caddr = NOVENA_IT6251_CHIPADDR; int reg; int tries, retries = 0; @@ -233,7 +228,7 @@ static int it6251_init(void) /* Wait for video stable. */ for (tries = 0; tries < 100; tries++) { - reg = i2c_reg_read(caddr, 0x17); + reg = dm_i2c_reg_read(it6251_chip, 0x17); /* Test Link CFG, STS, LCS read done. */ if ((reg & 0xe0) != 0xe0) { /* Not yet, wait a bit more. */ @@ -285,10 +280,14 @@ static int detect_lvds(struct display_info_t const *dev) enable_lvds(dev); - ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); - if (ret) { - puts("Cannot select IT6251 I2C bus.\n"); - return 0; + if (!it6251_chip) { + ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS, + NOVENA_IT6251_CHIPADDR, + 1, &it6251_chip); + if (ret) { + puts("Cannot select IT6251 I2C bus.\n"); + return 0; + } } /* Wait up-to ~250 mS for the LVDS to come up. */ @@ -435,9 +434,20 @@ void setup_display_lvds(void) { int ret; - ret = i2c_set_bus_num(NOVENA_IT6251_I2C_BUS); + if (!it6251_chip) { + ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS, + NOVENA_IT6251_CHIPADDR, + 1, &it6251_chip); + if (ret) { + puts("Cannot select LVDS-to-eDP I2C bus.\n"); + return; + } + } + + ret = i2c_get_chip_for_busnum(NOVENA_IT6251_I2C_BUS, + NOVENA_IT6251_LVDSADDR, 1, &it6251_lvds); if (ret) { - puts("Cannot select LVDS-to-eDP I2C bus.\n"); + puts("Cannot find IT6251 LVDS bus.\n"); return; } diff --git a/board/lg/sniper/sniper.c b/board/lg/sniper/sniper.c index 88d5d088143..9d0959f294e 100644 --- a/board/lg/sniper/sniper.c +++ b/board/lg/sniper/sniper.c @@ -14,11 +14,9 @@ #include <linux/ctype.h> #include <linux/usb/musb.h> #include <asm/omap_musb.h> -#include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> #include <asm/io.h> -#include <ns16550.h> #include <twl4030.h> #include "sniper.h" @@ -30,18 +28,6 @@ const omap3_sysinfo sysinfo = { .nand_string = "MMC" }; -static const struct ns16550_plat serial_omap_plat = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DRVINFO(sniper_serial) = { - .name = "ns16550_serial", - .plat = &serial_omap_plat -}; - #if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_USB_MUSB_GADGET) static struct musb_hdrc_config musb_config = { .multipoint = 1, @@ -77,6 +63,11 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; timings->mr = MICRON_V_MR_165; } + +void spl_board_init(void) +{ + twl4030_power_mmc_init(1); +} #endif int board_init(void) @@ -188,13 +179,3 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) return omap_reboot_mode_store("b"); } - -int board_mmc_init(struct bd_info *bis) -{ - return omap_mmc_init(1, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(1); -} diff --git a/board/radxa/rock-5-itx-rk3588/Kconfig b/board/radxa/rock-5-itx-rk3588/Kconfig new file mode 100644 index 00000000000..f7a7666d531 --- /dev/null +++ b/board/radxa/rock-5-itx-rk3588/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ROCK_5_ITX_RK3588 + +config SYS_BOARD + default "rock-5-itx-rk3588" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock-5-itx-rk3588" + +endif diff --git a/board/radxa/rock-5-itx-rk3588/MAINTAINERS b/board/radxa/rock-5-itx-rk3588/MAINTAINERS new file mode 100644 index 00000000000..1c4f24306a0 --- /dev/null +++ b/board/radxa/rock-5-itx-rk3588/MAINTAINERS @@ -0,0 +1,8 @@ +ROCK-5-ITX-RK3588 +M: Heiko Stuebner <heiko@sntech.de> +R: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: board/radxa/rock-5-itx-rk3588 +F: include/configs/rock-5-itx-rk3588.h +F: configs/rock-5-itx-rk3588_defconfig +F: arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi diff --git a/board/radxa/zero3-rk3566/Kconfig b/board/radxa/zero3-rk3566/Kconfig new file mode 100644 index 00000000000..7d46efc9c40 --- /dev/null +++ b/board/radxa/zero3-rk3566/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RADXA_ZERO_3_RK3566 + +config SYS_BOARD + default "zero3-rk3566" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "evb_rk3568" + +endif diff --git a/board/radxa/zero3-rk3566/MAINTAINERS b/board/radxa/zero3-rk3566/MAINTAINERS new file mode 100644 index 00000000000..e5a5d856113 --- /dev/null +++ b/board/radxa/zero3-rk3566/MAINTAINERS @@ -0,0 +1,6 @@ +RADXA-ZERO-3-RK3566 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: board/radxa/zero3-rk3566 +F: configs/radxa-zero-3-rk3566_defconfig +F: arch/arm/dts/rk3566-radxa-zero-3* diff --git a/board/radxa/zero3-rk3566/Makefile b/board/radxa/zero3-rk3566/Makefile new file mode 100644 index 00000000000..b28b58ed5d8 --- /dev/null +++ b/board/radxa/zero3-rk3566/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += zero3-rk3566.o diff --git a/board/radxa/zero3-rk3566/zero3-rk3566.c b/board/radxa/zero3-rk3566/zero3-rk3566.c new file mode 100644 index 00000000000..cf30c4e3898 --- /dev/null +++ b/board/radxa/zero3-rk3566/zero3-rk3566.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <linux/errno.h> +#include <linux/kernel.h> +#include <adc.h> +#include <env.h> + +#define HW_ID_CHANNEL 1 + +struct board_model { + unsigned int low; + unsigned int high; + const char *fdtfile; +}; + +static const struct board_model board_models[] = { + { 230, 270, "rockchip/rk3566-radxa-zero-3w.dtb" }, + { 400, 450, "rockchip/rk3566-radxa-zero-3e.dtb" }, +}; + +static const struct board_model *get_board_model(void) +{ + unsigned int val; + int i, ret; + + ret = adc_channel_single_shot("saradc@fe720000", HW_ID_CHANNEL, &val); + if (ret) + return NULL; + + for (i = 0; i < ARRAY_SIZE(board_models); i++) { + unsigned int min = board_models[i].low; + unsigned int max = board_models[i].high; + + if (min <= val && val <= max) + return &board_models[i]; + } + + return NULL; +} + +int rk_board_late_init(void) +{ + const struct board_model *model = get_board_model(); + + if (model) + env_set("fdtfile", model->fdtfile); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + const struct board_model *model = get_board_model(); + + if (model && !strcmp(name, model->fdtfile)) + return 0; + + return -EINVAL; +} diff --git a/board/rockchip/evb_rk3308/MAINTAINERS b/board/rockchip/evb_rk3308/MAINTAINERS index abffbb1eb0a..cd219c65f27 100644 --- a/board/rockchip/evb_rk3308/MAINTAINERS +++ b/board/rockchip/evb_rk3308/MAINTAINERS @@ -12,3 +12,9 @@ R: Jonas Karlman <jonas@kwiboo.se> S: Maintained F: configs/rock-pi-s-rk3308_defconfig F: arch/arm/dts/rk3308-rock-pi-s* + +ROCK-S0 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/rock-s0-rk3308_defconfig +F: arch/arm/dts/rk3308-rock-s0* diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index e5b0986ead9..588134ecb27 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -69,3 +69,16 @@ S: Maintained F: configs/rock-3a-rk3568_defconfig F: arch/arm/dts/rk3568-rock-3a.dts F: arch/arm/dts/rk3568-rock-3a-u-boot.dtsi + +ROCK-3B +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: configs/rock-3b-rk3568_defconfig +F: arch/arm/dts/rk3568-rock-3b* + +ROCK-3C +M: Jonas Karlman <jonas@kwiboo.se> +M: Maxim Moskalets <maximmosk4@gmail.com> +S: Maintained +F: arch/arm/dts/rk3566-rock-3c-u-boot.dtsi +F: configs/rock-3c-rk3566_defconfig diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index a0dbf97524b..bd430cfaa7f 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -18,7 +18,6 @@ #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/io.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/sections.h> #include <env.h> #include <linux/bitops.h> @@ -27,7 +26,6 @@ #include <config.h> #include <fsl_esdhc_imx.h> #include <mmc.h> -#include <i2c.h> #include <miiphy.h> #include <netdev.h> #include <power/pmic.h> @@ -53,10 +51,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \ PAD_CTL_SRE_FAST) -#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm) - #define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST) @@ -120,21 +114,6 @@ eth_fail: return ret; } -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, - .gp = IMX_GPIO_NR(1, 0), - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, - .gp = IMX_GPIO_NR(1, 1), - }, -}; - static struct pmic *pfuze_init(unsigned char i2cbus) { struct pmic *p; @@ -400,10 +379,6 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); -#endif - return board_net_init(); } diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 4bcd9b9af7f..4ad77c75f5e 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -549,6 +549,12 @@ S: Maintained F: configs/Sunchip_CX-A99_defconfig W: https://linux-sunxi.org/Sunchip_CX-A99 +TANIX TX1 BOARD +M: Andre Przywara <andre.przywara@arm.com> +S: Maintained +F: configs/tanix_tx1_defconfig +W: https://linux-sunxi.org/Tanix_TX1 + TANIX TX6 BOARD M: Jernej Skrabec <jernej.skrabec@siol.net> S: Maintained diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index 484b4e24428..6c60c70b7b4 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -92,7 +92,7 @@ int spl_start_uboot(void) const struct dpll_params dpll_ddr_sl50 = { 400, OSC-1, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { int mpu_vdd; diff --git a/board/tq/tqma6/Kconfig b/board/tq/tqma6/Kconfig index e7f23367afd..b42c8e24ade 100644 --- a/board/tq/tqma6/Kconfig +++ b/board/tq/tqma6/Kconfig @@ -72,6 +72,7 @@ config MBA6 select PHY_MICREL select PHY_MICREL_KSZ90X1 select MXC_UART + imply OF_UPSTREAM help Select the MBa6 starterkit. This features a GigE Phy, USB, SD-Card etc. diff --git a/board/tq/tqma6/tqma6.c b/board/tq/tqma6/tqma6.c index 92142c10ae5..445ce987b68 100644 --- a/board/tq/tqma6/tqma6.c +++ b/board/tq/tqma6/tqma6.c @@ -19,11 +19,9 @@ #include <linux/errno.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/spi.h> #include <fsl_esdhc_imx.h> #include <linux/libfdt.h> -#include <i2c.h> #include <mmc.h> #include <power/pfuze100_pmic.h> #include <power/pmic.h> @@ -48,10 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -170,38 +164,6 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) #endif #endif -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) -static struct i2c_pads_info tqma6_i2c3_pads = { - /* I2C3: on board LM75, M24C64, */ - .scl = { - .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL, - I2C_PAD_CTRL), - .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05, - I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA, - I2C_PAD_CTRL), - .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, - I2C_PAD_CTRL), - .gp = IMX_GPIO_NR(1, 6) - } -}; - -static void tqma6_setup_i2c(void) -{ - int ret; - /* - * use logical index for bus, e.g. I2C1 -> 0 - * warn on error - */ - ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads); - if (ret) - printf("setup I2C3 failed: %d\n", ret); -} -#endif - int board_early_init_f(void) { return tqma6_bb_board_early_init_f(); @@ -215,10 +177,6 @@ int board_init(void) #ifndef CONFIG_DM_SPI tqma6_iomuxc_spi(); #endif -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - tqma6_setup_i2c(); -#endif - tqma6_bb_board_init(); return 0; @@ -246,21 +204,22 @@ static const char *tqma6_get_boardname(void) }; } -#if CONFIG_IS_ENABLED(POWER_LEGACY) +#if CONFIG_IS_ENABLED(DM_PMIC) /* setup board specific PMIC */ int power_init_board(void) { - struct pmic *p; + struct udevice *dev; u32 reg, rev; + int ret; - power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS); - p = pmic_get("PFUZE100"); - if (p && !pmic_probe(p)) { - pmic_reg_read(p, PFUZE100_DEVICEID, ®); - pmic_reg_read(p, PFUZE100_REVID, &rev); - printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev); - } + ret = pmic_get("pmic@8", &dev); + if (ret < 0) + return 0; + + reg = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev); return 0; } #endif @@ -271,11 +230,6 @@ int board_late_init(void) tqma6_bb_board_late_init(); - return 0; -} - -int checkboard(void) -{ printf("Board: %s on a %s\n", tqma6_get_boardname(), tqma6_bb_get_boardname()); return 0; diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index cea25f8c900..f54f183038b 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -177,7 +177,7 @@ const struct dpll_params dpll_ddr_evm_sk = { const struct dpll_params dpll_ddr_baltos = { 400, OSC-1, 1, -1, -1, -1, -1}; -void am33xx_spl_board_init(void) +void spl_board_init(void) { int sil_rev, mpu_vdd; int freq; diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 88e10fa7a7f..1d67e3f3185 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -193,6 +193,51 @@ static u8 versal_net_get_bootmode(void) return bootmode; } +int spi_get_env_dev(void) +{ + struct udevice *dev; + const char *mode = NULL; + int bootseq = -1; + + switch (versal_net_get_bootmode()) { + case QSPI_MODE_24BIT: + puts("QSPI_MODE_24\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case QSPI_MODE_32BIT: + puts("QSPI_MODE_32\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1030000", &dev)) { + debug("QSPI driver for QSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + case OSPI_MODE: + puts("OSPI_MODE\n"); + if (uclass_get_device_by_name(UCLASS_SPI, + "spi@f1010000", &dev)) { + debug("OSPI driver for OSPI device is not present\n"); + break; + } + mode = "xspi"; + bootseq = dev_seq(dev); + break; + default: + break; + } + + debug("bootseq %d\n", bootseq); + return bootseq; +} + static int boot_targets_setup(void) { u8 bootmode; diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index b4c15b041cc..e6331c0e4d8 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -152,20 +152,7 @@ int board_init(void) if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, zynqmp_pm_cfg_obj_size); -#endif - -#if defined(CONFIG_ZYNQMP_FIRMWARE) - struct udevice *dev; - uclass_get_device_by_name(UCLASS_FIRMWARE, "power-management", &dev); - if (!dev) { - uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev); - if (!dev) - panic("PMU Firmware device not found - Enable it"); - } -#endif - -#if defined(CONFIG_SPL_BUILD) printf("Silicon version:\t%d\n", zynqmp_get_silicon_version()); /* the CSU disables the JTAG interface when secure boot is enabled */ diff --git a/board/xilinx/zynqmp/zynqmp_kria.env b/board/xilinx/zynqmp/zynqmp_kria.env index 69e333c5388..49ef3e7d753 100644 --- a/board/xilinx/zynqmp/zynqmp_kria.env +++ b/board/xilinx/zynqmp/zynqmp_kria.env @@ -63,10 +63,13 @@ kr260_setup=i2c dev 1 && run usb_hub_init; i2c dev 2 && run usb_hub_init; kd240_setup=i2c dev 1 && run usb_hub_init;zynqmp pmufw node 33; zynqmp pmufw node 47 tpm_setup=tpm autostart; +tpm_reset=echo "!!! For TPM reset a full power cycle or pressing the POR_B button is required !!!"; +tpm_kv260=if test ${card1_rev} = A -o ${card1_rev} = B -o ${card1_rev} = Y -o ${card1_rev} = Z -o ${card1_rev} = 1; then run tpm_reset; fi +tpm_kd240=if test ${card1_rev} = A; then run tpm_reset; fi board_setup=\ zynqmp mmio_write 0xFFCA0010 0xfff 0; \ -if test ${card1_name} = SCK-KV-G; then run kv260_setup; fi;\ -if test ${card1_name} = SCK-KR-G; then run kr260_setup; fi;\ -if test ${card1_name} = SCK-KD-G; then run kd240_setup; fi;\ +if test ${card1_name} = SCK-KV-G; then run kv260_setup; run tpm_kv260; fi;\ +if test ${card1_name} = SCK-KR-G; then run kr260_setup; run tpm_reset; fi;\ +if test ${card1_name} = SCK-KD-G; then run kd240_setup; run tpm_kd240; fi;\ run tpm_setup diff --git a/board/xunlong/orangepi-3b-rk3566/Kconfig b/board/xunlong/orangepi-3b-rk3566/Kconfig new file mode 100644 index 00000000000..36ccc056c62 --- /dev/null +++ b/board/xunlong/orangepi-3b-rk3566/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ORANGEPI_3B_RK3566 + +config SYS_BOARD + default "orangepi-3b-rk3566" + +config SYS_VENDOR + default "xunlong" + +config SYS_CONFIG_NAME + default "evb_rk3568" + +endif diff --git a/board/xunlong/orangepi-3b-rk3566/MAINTAINERS b/board/xunlong/orangepi-3b-rk3566/MAINTAINERS new file mode 100644 index 00000000000..6e1df1052ba --- /dev/null +++ b/board/xunlong/orangepi-3b-rk3566/MAINTAINERS @@ -0,0 +1,6 @@ +ORANGEPI-3B-RK3566 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: board/xunlong/orangepi-3b-rk3566 +F: configs/orangepi-3b-rk3566_defconfig +F: arch/arm/dts/rk3566-orangepi-3b* diff --git a/board/xunlong/orangepi-3b-rk3566/Makefile b/board/xunlong/orangepi-3b-rk3566/Makefile new file mode 100644 index 00000000000..9ce25549e21 --- /dev/null +++ b/board/xunlong/orangepi-3b-rk3566/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += orangepi-3b-rk3566.o diff --git a/board/xunlong/orangepi-3b-rk3566/orangepi-3b-rk3566.c b/board/xunlong/orangepi-3b-rk3566/orangepi-3b-rk3566.c new file mode 100644 index 00000000000..d05c33adefa --- /dev/null +++ b/board/xunlong/orangepi-3b-rk3566/orangepi-3b-rk3566.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <env.h> +#include <asm/gpio.h> + +struct board_model { + int value; + const char *fdtfile; + const char *config; +}; + +static const struct board_model board_models[] = { + { 0, "rockchip/rk3566-orangepi-3b-v1.1.dtb", "rk3566-orangepi-3b-v1.1.dtb" }, + { 1, "rockchip/rk3566-orangepi-3b-v2.1.dtb", "rk3566-orangepi-3b-v2.1.dtb" }, +}; + +static int get_board_value(void) +{ + struct gpio_desc desc; + int ret; + + /* + * GPIO4_C4 (E20): + * v1.1.1: x (internal pull-down) + * v2.1: PHY_RESET (external pull-up) + */ + ret = dm_gpio_lookup_name("E20", &desc); + if (ret) + return ret; + + ret = dm_gpio_request(&desc, "phy_reset"); + if (ret && ret != -EBUSY) + return ret; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + ret = dm_gpio_get_value(&desc); + dm_gpio_free(desc.dev, &desc); + + return ret; +} + +static const struct board_model *get_board_model(void) +{ + int i, val; + + val = get_board_value(); + if (val < 0) + return NULL; + + for (i = 0; i < ARRAY_SIZE(board_models); i++) { + if (val == board_models[i].value) + return &board_models[i]; + } + + return NULL; +} + +int rk_board_late_init(void) +{ + const struct board_model *model = get_board_model(); + + if (model) + env_set("fdtfile", model->fdtfile); + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + const struct board_model *model = get_board_model(); + + if (model && (!strcmp(name, model->fdtfile) || + !strcmp(name, model->config))) + return 0; + + return -EINVAL; +} diff --git a/boot/Kconfig b/boot/Kconfig index 940389d4882..7ac34574079 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -745,6 +745,76 @@ config BOOTMETH_SCRIPT This provides a way to try out standard boot on an existing boot flow. It is not enabled by default to save space. +config UPL + bool "upl - Universal Payload Specification" + imply CMD_UPL + imply UPL_READ + imply UPL_WRITE + imply SPL_UPL if SPL + help + Provides support for UPL payloads and handoff information. U-Boot + supports generating and accepting handoff information. The mkimage + tool will eventually support creating payloads. + +if UPL + +config UPL_READ + bool "upl - Support reading a Universal Payload handoff" + help + Provides support for decoding a UPL-format payload into a C structure + which can be used elsewhere in U-Boot. This is just the reading + implementation, useful for trying it out. See UPL_IN for how + to tell U-Boot to actually read it on startup and use it for memory + and device information, etc. + +config UPL_WRITE + bool "upl - Support writing a Universal Payload handoff" + help + Provides support for encoding a UPL-format payload from a C structure + so it can be passed to another program. This is just the writing + implementation, useful for trying it out. See SPL_UPL_OUT + for how to tell U-Boot SPL to actually write it before jumping to + the next phase. + +config UPL_IN + bool "upl - Read the UPL handoff on startup" + select UPL_READ + help + Read an SPL handoff when U-Boot starts and use it to provide + devices, memory layout, etc. required by U-Boot. This allows U-Boot + to function as a payload in the meaning of the specification. + +if SPL + +config SPL_UPL + bool "Write a UPL handoff in SPL" + imply SPL_UPL_OUT + help + This tells SPL to write a UPL handoff and pass it to the next phase + (e.g. to U-Boot or another program which SPL loads and runs). THis + provides information to help that program run correctly and + efficiently on the machine. + +config SPL_UPL_WRITE + bool # upl - Support writing a Universal Payload handoff in SPL + select SPL_BLOBLIST + help + Provides support for encoding a UPL-format payload from a C structure + so it can be passed to another program. This is just the writing + implementation, useful for trying it out. + +config SPL_UPL_OUT + bool "upl - Support writing a Universal Payload handoff in SPL" + select SPL_UPL_WRITE + help + Provides support for encoding a UPL-format payload and passing it to + the next firmware phase. This allows U-Boot SPL to function as + Platform Init in the meaning of the specification. + +endif # SPL + +endif # UPL + endif # BOOTSTD config LEGACY_IMAGE_FORMAT diff --git a/boot/Makefile b/boot/Makefile index dff6f99081a..f4675d6ffd5 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -43,6 +43,10 @@ endif obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o obj-$(CONFIG_$(SPL_TPL_)FDT_SIMPLEFB) += fdt_simplefb.o +obj-$(CONFIG_$(SPL_TPL_)UPL) += upl_common.o +obj-$(CONFIG_$(SPL_TPL_)UPL_READ) += upl_read.o +obj-$(CONFIG_$(SPL_TPL_)UPL_WRITE) += upl_write.o + obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += fdt_region.o obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o diff --git a/boot/bootmeth_efi.c b/boot/bootmeth_efi.c index 39232eb2e25..6b41c0999f1 100644 --- a/boot/bootmeth_efi.c +++ b/boot/bootmeth_efi.c @@ -100,11 +100,10 @@ static void set_efi_bootdev(struct blk_desc *desc, struct bootflow *bflow) if (last_slash) *last_slash = '\0'; - log_debug("setting bootdev %s, %s, %s, %p, %x\n", - dev_get_uclass_name(media_dev), devnum_str, bflow->fname, - bflow->buf, size); dev_name = device_get_uclass_id(media_dev) == UCLASS_MASS_STORAGE ? - "usb" : dev_get_uclass_name(media_dev); + "usb" : blk_get_uclass_name(device_get_uclass_id(media_dev)); + log_debug("setting bootdev %s, %s, %s, %p, %x\n", + dev_name, devnum_str, bflow->fname, bflow->buf, size); efi_set_bootdev(dev_name, devnum_str, bflow->fname, bflow->buf, size); } diff --git a/boot/image-fit.c b/boot/image-fit.c index 9253f81fff5..7d56f0b5e6e 100644 --- a/boot/image-fit.c +++ b/boot/image-fit.c @@ -36,6 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; #include <bootm.h> #include <image.h> #include <bootstage.h> +#include <upl.h> #include <u-boot/crc.h> /*****************************************************************************/ @@ -2294,6 +2295,8 @@ int fit_image_load(struct bootm_headers *images, ulong addr, bootstage_mark(bootstage_id + BOOTSTAGE_SUB_LOAD); + upl_add_image(fit, noffset, load, len); + *datap = load; *lenp = len; if (fit_unamep) diff --git a/boot/upl_common.c b/boot/upl_common.c new file mode 100644 index 00000000000..3924423abd5 --- /dev/null +++ b/boot/upl_common.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * UPL handoff command functions + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY UCLASS_BOOTSTD + +#include <string.h> +#include <upl.h> + +/* Names of bootmodes */ +const char *const bootmode_names[UPLBM_COUNT] = { + [UPLBM_FULL] = "full", + [UPLBM_MINIMAL] = "minimal", + [UPLBM_FAST] = "fast", + [UPLBM_DIAG] = "diag", + [UPLBM_DEFAULT] = "default", + [UPLBM_S2] = "s2", + [UPLBM_S3] = "s3", + [UPLBM_S4] = "s4", + [UPLBM_S5] = "s5", + [UPLBM_FACTORY] = "factory", + [UPLBM_FLASH] = "flash", + [UPLBM_RECOVERY] = "recovery", +}; + +/* Names of memory usages */ +const char *const usage_names[UPLUS_COUNT] = { + [UPLUS_ACPI_RECLAIM] = "acpi-reclaim", + [UPLUS_ACPI_NVS] = "acpi-nvs", + [UPLUS_BOOT_CODE] = "boot-code", + [UPLUS_BOOT_DATA] = "boot-data", + [UPLUS_RUNTIME_CODE] = "runtime-code", + [UPLUS_RUNTIME_DATA] = "runtime-data", +}; + +/* Names of access types */ +const char *const access_types[UPLUS_COUNT] = { + [UPLAT_MMIO] = "mmio", + [UPLAT_IO] = "io", +}; + +/* Names of graphics formats */ +const char *const graphics_formats[UPLUS_COUNT] = { + [UPLGF_ARGB32] = "a8r8g8b8", + [UPLGF_ABGR32] = "a8b8g8r8", + [UPLGF_ABGR64] = "a16b16g16r16", +}; + +void upl_init(struct upl *upl) +{ + memset(upl, '\0', sizeof(struct upl)); + alist_init_struct(&upl->image, struct upl_image); + alist_init_struct(&upl->mem, struct upl_mem); + alist_init_struct(&upl->memmap, struct upl_memmap); + alist_init_struct(&upl->memres, struct upl_memres); +} diff --git a/boot/upl_common.h b/boot/upl_common.h new file mode 100644 index 00000000000..cc517dc1de9 --- /dev/null +++ b/boot/upl_common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * UPL handoff command functions + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __UPL_COMMON_H +#define __UPL_COMMON_H + +/* Names of bootmodes */ +extern const char *const bootmode_names[UPLBM_COUNT]; + +/* Names of memory usages */ +extern const char *const usage_names[UPLUS_COUNT]; + +/* Names of access types */ +extern const char *const access_types[UPLUS_COUNT]; + +/* Names of graphics formats */ +extern const char *const graphics_formats[UPLUS_COUNT]; + +#endif /* __UPL_COMMON_H */ diff --git a/boot/upl_read.c b/boot/upl_read.c new file mode 100644 index 00000000000..5063897a132 --- /dev/null +++ b/boot/upl_read.c @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * UPL handoff parsing + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY UCLASS_BOOTSTD + +#include <log.h> +#include <upl.h> +#include <dm/ofnode.h> +#include "upl_common.h" + +/** + * read_addr() - Read an address + * + * Reads an address in the correct format, either 32- or 64-bit + * + * @upl: UPL state + * @node: Node to read from + * @prop: Property name to read + * @addr: Place to put the address + * Return: 0 if OK, -ve on error + */ +static int read_addr(const struct upl *upl, ofnode node, const char *prop, + ulong *addrp) +{ + int ret; + + if (upl->addr_cells == 1) { + u32 val; + + ret = ofnode_read_u32(node, prop, &val); + if (!ret) + *addrp = val; + } else { + u64 val; + + ret = ofnode_read_u64(node, prop, &val); + if (!ret) + *addrp = val; + } + + return ret; +} + +/** + * read_size() - Read a size + * + * Reads a size in the correct format, either 32- or 64-bit + * + * @upl: UPL state + * @node: Node to read from + * @prop: Property name to read + * @addr: Place to put the size + * Return: 0 if OK, -ve on error + */ +static int read_size(const struct upl *upl, ofnode node, const char *prop, + ulong *sizep) +{ + int ret; + + if (upl->size_cells == 1) { + u32 val; + + ret = ofnode_read_u32(node, prop, &val); + if (!ret) + *sizep = val; + } else { + u64 val; + + ret = ofnode_read_u64(node, prop, &val); + if (!ret) + *sizep = val; + } + + return ret; +} + +/** + * ofnode_read_bitmask() - Read a bit mask from a string list + * + * @node: Node to read from + * @prop: Property name to read + * @names: Array of names for each bit + * @count: Number of array entries + * @value: Returns resulting bit-mask value on success + * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the + * string is too long for the (internal) buffer, -EINVAL if no such property + */ +static int ofnode_read_bitmask(ofnode node, const char *prop, + const char *const names[], uint count, + uint *valuep) +{ + const char **list; + const char **strp; + uint val; + uint bit; + int ret; + + ret = ofnode_read_string_list(node, prop, &list); + if (ret < 0) + return log_msg_ret("rea", ret); + + val = 0; + for (strp = list; *strp; strp++) { + const char *str = *strp; + bool found = false; + + for (bit = 0; bit < count; bit++) { + if (!strcmp(str, names[bit])) { + found = true; + break; + } + } + if (found) + val |= BIT(bit); + else + log_warning("%s/%s: Invalid value '%s'\n", + ofnode_get_name(node), prop, str); + } + *valuep = val; + + return 0; +} + +/** + * ofnode_read_value() - Read a string value as an int using a lookup + * + * @node: Node to read from + * @prop: Property name to read + * @names: Array of names for each int value + * @count: Number of array entries + * @valuep: Returns int value read + * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOENT if the + * property does not exist + */ +static int ofnode_read_value(ofnode node, const char *prop, + const char *const names[], uint count, + uint *valuep) +{ + const char *str; + int i; + + str = ofnode_read_string(node, prop); + if (!str) + return log_msg_ret("rd", -ENOENT); + + for (i = 0; i < count; i++) { + if (!strcmp(names[i], str)) { + *valuep = i; + return 0; + } + } + + log_debug("Unnamed value '%s'\n", str); + return log_msg_ret("val", -EINVAL); +} + +static int read_uint(ofnode node, const char *prop, uint *valp) +{ + u32 val; + int ret; + + ret = ofnode_read_u32(node, prop, &val); + if (ret) + return ret; + *valp = val; + + return 0; +} + +/** + * decode_root_props() - Decode root properties from the tree + * + * @upl: UPL state + * @node: Node to decode + * Return 0 if OK, -ve on error + */ +static int decode_root_props(struct upl *upl, ofnode node) +{ + int ret; + + ret = read_uint(node, UPLP_ADDRESS_CELLS, &upl->addr_cells); + if (!ret) + ret = read_uint(node, UPLP_SIZE_CELLS, &upl->size_cells); + if (ret) + return log_msg_ret("cel", ret); + + return 0; +} + +/** + * decode_root_props() - Decode UPL parameters from the tree + * + * @upl: UPL state + * @node: Node to decode + * Return 0 if OK, -ve on error + */ +static int decode_upl_params(struct upl *upl, ofnode options) +{ + ofnode node; + int ret; + + node = ofnode_find_subnode(options, UPLN_UPL_PARAMS); + if (!ofnode_valid(node)) + return log_msg_ret("par", -EINVAL); + log_debug("decoding '%s'\n", ofnode_get_name(node)); + + ret = read_addr(upl, node, UPLP_SMBIOS, &upl->smbios); + if (ret) + return log_msg_ret("smb", ret); + ret = read_addr(upl, node, UPLP_ACPI, &upl->acpi); + if (ret) + return log_msg_ret("acp", ret); + ret = ofnode_read_bitmask(node, UPLP_BOOTMODE, bootmode_names, + UPLBM_COUNT, &upl->bootmode); + if (ret) + return log_msg_ret("boo", ret); + ret = read_uint(node, UPLP_ADDR_WIDTH, &upl->addr_width); + if (ret) + return log_msg_ret("add", ret); + ret = read_uint(node, UPLP_ACPI_NVS_SIZE, &upl->acpi_nvs_size); + if (ret) + return log_msg_ret("nvs", ret); + + return 0; +} + +/** + * decode_upl_images() - Decode /options/upl-image nodes + * + * @node: /options node in which to look for the node + * Return 0 if OK, -ve on error + */ +static int decode_upl_images(struct upl *upl, ofnode options) +{ + ofnode node, images; + int ret; + + images = ofnode_find_subnode(options, UPLN_UPL_IMAGE); + if (!ofnode_valid(images)) + return log_msg_ret("img", -EINVAL); + log_debug("decoding '%s'\n", ofnode_get_name(images)); + + ret = read_addr(upl, images, UPLP_FIT, &upl->fit); + if (!ret) + ret = read_uint(images, UPLP_CONF_OFFSET, &upl->conf_offset); + if (ret) + return log_msg_ret("cnf", ret); + + ofnode_for_each_subnode(node, images) { + struct upl_image img; + + ret = read_addr(upl, node, UPLP_LOAD, &img.load); + if (!ret) + ret = read_size(upl, node, UPLP_SIZE, &img.size); + if (!ret) + ret = read_uint(node, UPLP_OFFSET, &img.offset); + img.description = ofnode_read_string(node, UPLP_DESCRIPTION); + if (!img.description) + return log_msg_ret("sim", ret); + if (!alist_add(&upl->image, img)) + return log_msg_ret("img", -ENOMEM); + } + + return 0; +} + +/** + * decode_addr_size() - Decide a set of addr/size pairs + * + * Each base/size value from the devicetree is written to the region list + * + * @upl: UPL state + * @buf: Bytes to decode + * @size: Number of bytes to decode + * @regions: List of regions to process (struct memregion) + * Returns: number of regions found, if OK, else -ve on error + */ +static int decode_addr_size(const struct upl *upl, const char *buf, int size, + struct alist *regions) +{ + const char *ptr, *end = buf + size; + int i; + + alist_init_struct(regions, struct memregion); + ptr = buf; + for (i = 0; ptr < end; i++) { + struct memregion reg; + + if (upl->addr_cells == 1) + reg.base = fdt32_to_cpu(*(u32 *)ptr); + else + reg.base = fdt64_to_cpu(*(u64 *)ptr); + ptr += upl->addr_cells * sizeof(u32); + + if (upl->size_cells == 1) + reg.size = fdt32_to_cpu(*(u32 *)ptr); + else + reg.size = fdt64_to_cpu(*(u64 *)ptr); + ptr += upl->size_cells * sizeof(u32); + if (ptr > end) + return -ENOSPC; + + if (!alist_add(regions, reg)) + return log_msg_ret("reg", -ENOMEM); + } + + return i; +} + +/** + * node_matches_at() - Check if a node name matches "base@..." + * + * Return: true if the node name matches the base string followed by an @ sign; + * false otherwise + */ +static bool node_matches_at(ofnode node, const char *base) +{ + const char *name = ofnode_get_name(node); + int len = strlen(base); + + return !strncmp(base, name, len) && name[len] == '@'; +} + +/** + * decode_upl_memory_node() - Decode a /memory node from the tree + * + * @upl: UPL state + * @node: Node to decode + * Return 0 if OK, -ve on error + */ +static int decode_upl_memory_node(struct upl *upl, ofnode node) +{ + struct upl_mem mem; + const char *buf; + int size, len; + + buf = ofnode_read_prop(node, UPLP_REG, &size); + if (!buf) { + log_warning("Node '%s': Missing '%s' property\n", + ofnode_get_name(node), UPLP_REG); + return log_msg_ret("reg", -EINVAL); + } + len = decode_addr_size(upl, buf, size, &mem.region); + if (len < 0) + return log_msg_ret("buf", len); + mem.hotpluggable = ofnode_read_bool(node, UPLP_HOTPLUGGABLE); + if (!alist_add(&upl->mem, mem)) + return log_msg_ret("mem", -ENOMEM); + + return 0; +} + +/** + * decode_upl_memmap() - Decode memory-map nodes from the tree + * + * @upl: UPL state + * @root: Parent node containing the /memory-map nodes + * Return 0 if OK, -ve on error + */ +static int decode_upl_memmap(struct upl *upl, ofnode root) +{ + ofnode node; + + ofnode_for_each_subnode(node, root) { + struct upl_memmap memmap; + int size, len, ret; + const char *buf; + + memmap.name = ofnode_get_name(node); + memmap.usage = 0; + + buf = ofnode_read_prop(node, UPLP_REG, &size); + if (!buf) { + log_warning("Node '%s': Missing '%s' property\n", + ofnode_get_name(node), UPLP_REG); + continue; + } + + len = decode_addr_size(upl, buf, size, &memmap.region); + if (len < 0) + return log_msg_ret("buf", len); + ret = ofnode_read_bitmask(node, UPLP_USAGE, usage_names, + UPLUS_COUNT, &memmap.usage); + if (ret && ret != -EINVAL) /* optional property */ + return log_msg_ret("bit", ret); + + if (!alist_add(&upl->memmap, memmap)) + return log_msg_ret("mmp", -ENOMEM); + } + + return 0; +} + +/** + * decode_upl_memres() - Decode reserved-memory nodes from the tree + * + * @upl: UPL state + * @root: Parent node containing the reserved-memory nodes + * Return 0 if OK, -ve on error + */ +static int decode_upl_memres(struct upl *upl, ofnode root) +{ + ofnode node; + + ofnode_for_each_subnode(node, root) { + struct upl_memres memres; + const char *buf; + int size, len; + + log_debug("decoding '%s'\n", ofnode_get_name(node)); + memres.name = ofnode_get_name(node); + + buf = ofnode_read_prop(node, UPLP_REG, &size); + if (!buf) { + log_warning("Node '%s': Missing 'reg' property\n", + ofnode_get_name(node)); + continue; + } + + len = decode_addr_size(upl, buf, size, &memres.region); + if (len < 0) + return log_msg_ret("buf", len); + memres.no_map = ofnode_read_bool(node, UPLP_NO_MAP); + + if (!alist_add(&upl->memres, memres)) + return log_msg_ret("mre", -ENOMEM); + } + + return 0; +} + +/** + * decode_upl_serial() - Decode the serial node + * + * @upl: UPL state + * @root: Parent node contain node + * Return 0 if OK, -ve on error + */ +static int decode_upl_serial(struct upl *upl, ofnode node) +{ + struct upl_serial *ser = &upl->serial; + const char *buf; + int len, size; + int ret; + + ser->compatible = ofnode_read_string(node, UPLP_COMPATIBLE); + if (!ser->compatible) { + log_warning("Node '%s': Missing compatible string\n", + ofnode_get_name(node)); + return log_msg_ret("com", -EINVAL); + } + ret = read_uint(node, UPLP_CLOCK_FREQUENCY, &ser->clock_frequency); + if (!ret) + ret = read_uint(node, UPLP_CURRENT_SPEED, &ser->current_speed); + if (ret) + return log_msg_ret("spe", ret); + + buf = ofnode_read_prop(node, UPLP_REG, &size); + if (!buf) { + log_warning("Node '%s': Missing 'reg' property\n", + ofnode_get_name(node)); + return log_msg_ret("reg", -EINVAL); + } + + len = decode_addr_size(upl, buf, sizeof(buf), &ser->reg); + if (len < 0) + return log_msg_ret("buf", len); + + /* set defaults */ + ser->reg_io_shift = UPLD_REG_IO_SHIFT; + ser->reg_offset = UPLD_REG_OFFSET; + ser->reg_io_width = UPLD_REG_IO_WIDTH; + read_uint(node, UPLP_REG_IO_SHIFT, &ser->reg_io_shift); + read_uint(node, UPLP_REG_OFFSET, &ser->reg_offset); + read_uint(node, UPLP_REG_IO_WIDTH, &ser->reg_io_width); + read_addr(upl, node, UPLP_VIRTUAL_REG, &ser->virtual_reg); + ret = ofnode_read_value(node, UPLP_ACCESS_TYPE, access_types, + ARRAY_SIZE(access_types), &ser->access_type); + if (ret && ret != -ENOENT) + return log_msg_ret("ser", ret); + + return 0; +} + +/** + * decode_upl_graphics() - Decode graphics node + * + * @upl: UPL state + * @root: Node to decode + * Return 0 if OK, -ve on error + */ +static int decode_upl_graphics(struct upl *upl, ofnode node) +{ + struct upl_graphics *gra = &upl->graphics; + const char *buf, *compat; + int len, size; + int ret; + + compat = ofnode_read_string(node, UPLP_COMPATIBLE); + if (!compat) { + log_warning("Node '%s': Missing compatible string\n", + ofnode_get_name(node)); + return log_msg_ret("com", -EINVAL); + } + if (strcmp(UPLC_GRAPHICS, compat)) { + log_warning("Node '%s': Ignoring compatible '%s'\n", + ofnode_get_name(node), compat); + return 0; + } + + buf = ofnode_read_prop(node, UPLP_REG, &size); + if (!buf) { + log_warning("Node '%s': Missing 'reg' property\n", + ofnode_get_name(node)); + return log_msg_ret("reg", -EINVAL); + } + + len = decode_addr_size(upl, buf, sizeof(buf), &gra->reg); + if (len < 0) + return log_msg_ret("buf", len); + + ret = read_uint(node, UPLP_WIDTH, &gra->width); + if (!ret) + ret = read_uint(node, UPLP_HEIGHT, &gra->height); + if (!ret) + ret = read_uint(node, UPLP_STRIDE, &gra->stride); + if (!ret) { + ret = ofnode_read_value(node, UPLP_GRAPHICS_FORMAT, + graphics_formats, + ARRAY_SIZE(graphics_formats), + &gra->format); + } + if (ret) + return log_msg_ret("pro", ret); + + return 0; +} + +int upl_read_handoff(struct upl *upl, oftree tree) +{ + ofnode root, node; + int ret; + + if (!oftree_valid(tree)) + return log_msg_ret("tre", -EINVAL); + + root = oftree_root(tree); + + upl_init(upl); + ret = decode_root_props(upl, root); + if (ret) + return log_msg_ret("roo", ret); + + ofnode_for_each_subnode(node, root) { + const char *name = ofnode_get_name(node); + + log_debug("decoding '%s'\n", name); + if (!strcmp(UPLN_OPTIONS, name)) { + ret = decode_upl_params(upl, node); + if (ret) + return log_msg_ret("opt", ret); + + ret = decode_upl_images(upl, node); + } else if (node_matches_at(node, UPLN_MEMORY)) { + ret = decode_upl_memory_node(upl, node); + } else if (!strcmp(UPLN_MEMORY_MAP, name)) { + ret = decode_upl_memmap(upl, node); + } else if (!strcmp(UPLN_MEMORY_RESERVED, name)) { + ret = decode_upl_memres(upl, node); + } else if (node_matches_at(node, UPLN_SERIAL)) { + ret = decode_upl_serial(upl, node); + } else if (node_matches_at(node, UPLN_GRAPHICS)) { + ret = decode_upl_graphics(upl, node); + } else { + log_debug("Unknown node '%s'\n", name); + ret = 0; + } + if (ret) + return log_msg_ret("err", ret); + } + + return 0; +} diff --git a/boot/upl_write.c b/boot/upl_write.c new file mode 100644 index 00000000000..7d637c15ba0 --- /dev/null +++ b/boot/upl_write.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * UPL handoff generation + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY UCLASS_BOOTSTD + +#include <log.h> +#include <upl.h> +#include <dm/ofnode.h> +#include "upl_common.h" + +/** + * write_addr() - Write an address + * + * Writes an address in the correct format, either 32- or 64-bit + * + * @upl: UPL state + * @node: Node to write to + * @prop: Property name to write + * @addr: Address to write + * Return: 0 if OK, -ve on error + */ +static int write_addr(const struct upl *upl, ofnode node, const char *prop, + ulong addr) +{ + int ret; + + if (upl->addr_cells == 1) + ret = ofnode_write_u32(node, prop, addr); + else + ret = ofnode_write_u64(node, prop, addr); + + return ret; +} + +/** + * write_size() - Write a size + * + * Writes a size in the correct format, either 32- or 64-bit + * + * @upl: UPL state + * @node: Node to write to + * @prop: Property name to write + * @size: Size to write + * Return: 0 if OK, -ve on error + */ +static int write_size(const struct upl *upl, ofnode node, const char *prop, + ulong size) +{ + int ret; + + if (upl->size_cells == 1) + ret = ofnode_write_u32(node, prop, size); + else + ret = ofnode_write_u64(node, prop, size); + + return ret; +} + +/** + * ofnode_write_bitmask() - Write a bit mask as a string list + * + * @node: Node to write to + * @prop: Property name to write + * @names: Array of names for each bit + * @count: Number of array entries + * @value: Bit-mask value to write + * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the + * string is too long for the (internal) buffer + */ +static int ofnode_write_bitmask(ofnode node, const char *prop, + const char *const names[], uint count, + uint value) +{ + char buf[128]; + char *ptr, *end = buf + sizeof(buf); + uint bit; + int ret; + + ptr = buf; + for (bit = 0; bit < count; bit++) { + if (value & BIT(bit)) { + const char *str = names[bit]; + uint len; + + if (!str) { + log_debug("Unnamed bit number %d\n", bit); + return log_msg_ret("bit", -EINVAL); + } + len = strlen(str) + 1; + if (ptr + len > end) { + log_debug("String array too long\n"); + return log_msg_ret("bit", -ENOSPC); + } + + memcpy(ptr, str, len); + ptr += len; + } + } + + ret = ofnode_write_prop(node, prop, buf, ptr - buf, true); + if (ret) + return log_msg_ret("wri", ret); + + return 0; +} + +/** + * ofnode_write_value() - Write an int as a string value using a lookup + * + * @node: Node to write to + * @prop: Property name to write + * @names: Array of names for each int value + * @count: Number of array entries + * @value: Int value to write + * Return: 0 if OK, -EINVAL if a bit number is not defined, -ENOSPC if the + * string is too long for the (internal) buffer + */ +static int ofnode_write_value(ofnode node, const char *prop, + const char *const names[], uint count, + uint value) +{ + const char *str; + int ret; + + if (value >= count) { + log_debug("Value of range %d\n", value); + return log_msg_ret("val", -ERANGE); + } + str = names[value]; + if (!str) { + log_debug("Unnamed value %d\n", value); + return log_msg_ret("val", -EINVAL); + } + ret = ofnode_write_string(node, prop, str); + if (ret) + return log_msg_ret("wri", ret); + + return 0; +} + +/** + * add_root_props() - Add root properties to the tree + * + * @node: Node to add to + * Return 0 if OK, -ve on error + */ +static int add_root_props(const struct upl *upl, ofnode node) +{ + int ret; + + ret = ofnode_write_u32(node, UPLP_ADDRESS_CELLS, upl->addr_cells); + if (!ret) + ret = ofnode_write_u32(node, UPLP_SIZE_CELLS, upl->size_cells); + if (ret) + return log_msg_ret("cel", ret); + + return 0; +} + +/** + * add_upl_params() - Add UPL parameters node + * + * @upl: UPL state + * @options: /options node to add to + * Return 0 if OK, -ve on error + */ +static int add_upl_params(const struct upl *upl, ofnode options) +{ + ofnode node; + int ret; + + ret = ofnode_add_subnode(options, UPLN_UPL_PARAMS, &node); + if (ret) + return log_msg_ret("img", ret); + + ret = write_addr(upl, node, UPLP_SMBIOS, upl->smbios); + if (!ret) + ret = write_addr(upl, node, UPLP_ACPI, upl->acpi); + if (!ret && upl->bootmode) + ret = ofnode_write_bitmask(node, UPLP_BOOTMODE, bootmode_names, + UPLBM_COUNT, upl->bootmode); + if (!ret) + ret = ofnode_write_u32(node, UPLP_ADDR_WIDTH, upl->addr_width); + if (!ret) + ret = ofnode_write_u32(node, UPLP_ACPI_NVS_SIZE, + upl->acpi_nvs_size); + if (ret) + return log_msg_ret("cnf", ret); + + return 0; +} + +/** + * add_upl_image() - Add /options/upl-image nodes and properties to the tree + * + * @upl: UPL state + * @node: /options node to add to + * Return 0 if OK, -ve on error + */ +static int add_upl_image(const struct upl *upl, ofnode options) +{ + ofnode node; + int ret, i; + + ret = ofnode_add_subnode(options, UPLN_UPL_IMAGE, &node); + if (ret) + return log_msg_ret("img", ret); + + if (upl->fit) + ret = ofnode_write_u32(node, UPLP_FIT, upl->fit); + if (!ret && upl->conf_offset) + ret = ofnode_write_u32(node, UPLP_CONF_OFFSET, + upl->conf_offset); + if (ret) + return log_msg_ret("cnf", ret); + + for (i = 0; i < upl->image.count; i++) { + const struct upl_image *img = alist_get(&upl->image, i, + struct upl_image); + ofnode subnode; + char name[10]; + + snprintf(name, sizeof(name), UPLN_IMAGE "-%d", i + 1); + ret = ofnode_add_subnode(node, name, &subnode); + if (ret) + return log_msg_ret("sub", ret); + + ret = write_addr(upl, subnode, UPLP_LOAD, img->load); + if (!ret) + ret = write_size(upl, subnode, UPLP_SIZE, img->size); + if (!ret && img->offset) + ret = ofnode_write_u32(subnode, UPLP_OFFSET, + img->offset); + ret = ofnode_write_string(subnode, UPLP_DESCRIPTION, + img->description); + if (ret) + return log_msg_ret("sim", ret); + } + + return 0; +} + +/** + * buffer_addr_size() - Generate a set of addr/size pairs + * + * Each base/size value from each region is written to the buffer in a suitable + * format to be written to the devicetree + * + * @upl: UPL state + * @buf: Buffer to write to + * @size: Buffer size + * @num_regions: Number of regions to process + * @region: List of regions to process (struct memregion) + * Returns: Number of bytes written, or -ENOSPC if the buffer is too small + */ +static int buffer_addr_size(const struct upl *upl, char *buf, int size, + uint num_regions, const struct alist *region) +{ + char *ptr, *end = buf + size; + int i; + + ptr = buf; + for (i = 0; i < num_regions; i++) { + const struct memregion *reg = alist_get(region, i, + struct memregion); + + if (upl->addr_cells == 1) + *(u32 *)ptr = cpu_to_fdt32(reg->base); + else + *(u64 *)ptr = cpu_to_fdt64(reg->base); + ptr += upl->addr_cells * sizeof(u32); + + if (upl->size_cells == 1) + *(u32 *)ptr = cpu_to_fdt32(reg->size); + else + *(u64 *)ptr = cpu_to_fdt64(reg->size); + ptr += upl->size_cells * sizeof(u32); + if (ptr > end) + return -ENOSPC; + } + + return ptr - buf; +} + +/** + * add_upl_memory() - Add /memory nodes to the tree + * + * @upl: UPL state + * @root: Parent node to contain the new /memory nodes + * Return 0 if OK, -ve on error + */ +static int add_upl_memory(const struct upl *upl, ofnode root) +{ + int i; + + for (i = 0; i < upl->mem.count; i++) { + const struct upl_mem *mem = alist_get(&upl->mem, i, + struct upl_mem); + char buf[mem->region.count * sizeof(64) * 2]; + const struct memregion *first; + char name[26]; + int ret, len; + ofnode node; + + if (!mem->region.count) { + log_debug("Memory %d has no regions\n", i); + return log_msg_ret("reg", -EINVAL); + } + first = alist_get(&mem->region, 0, struct memregion); + sprintf(name, UPLN_MEMORY "@0x%lx", first->base); + ret = ofnode_add_subnode(root, name, &node); + if (ret) + return log_msg_ret("mem", ret); + + len = buffer_addr_size(upl, buf, sizeof(buf), mem->region.count, + &mem->region); + if (len < 0) + return log_msg_ret("buf", len); + + ret = ofnode_write_prop(node, UPLP_REG, buf, len, true); + if (!ret && mem->hotpluggable) + ret = ofnode_write_bool(node, UPLP_HOTPLUGGABLE, + mem->hotpluggable); + if (ret) + return log_msg_ret("lst", ret); + } + + return 0; +} + +/** + * add_upl_memmap() - Add memory-map nodes to the tree + * + * @upl: UPL state + * @root: Parent node to contain the new /memory-map node and its subnodes + * Return 0 if OK, -ve on error + */ +static int add_upl_memmap(const struct upl *upl, ofnode root) +{ + ofnode mem_node; + int i, ret; + + if (!upl->memmap.count) + return 0; + ret = ofnode_add_subnode(root, UPLN_MEMORY_MAP, &mem_node); + if (ret) + return log_msg_ret("img", ret); + + for (i = 0; i < upl->memmap.count; i++) { + const struct upl_memmap *memmap = alist_get(&upl->memmap, i, + struct upl_memmap); + char buf[memmap->region.count * sizeof(64) * 2]; + const struct memregion *first; + char name[26]; + int ret, len; + ofnode node; + + if (!memmap->region.count) { + log_debug("Memory %d has no regions\n", i); + return log_msg_ret("reg", -EINVAL); + } + first = alist_get(&memmap->region, 0, struct memregion); + sprintf(name, "%s@0x%lx", memmap->name, first->base); + ret = ofnode_add_subnode(mem_node, name, &node); + if (ret) + return log_msg_ret("memmap", ret); + + len = buffer_addr_size(upl, buf, sizeof(buf), + memmap->region.count, &memmap->region); + if (len < 0) + return log_msg_ret("buf", len); + ret = ofnode_write_prop(node, UPLP_REG, buf, len, true); + if (!ret && memmap->usage) + ret = ofnode_write_bitmask(node, UPLP_USAGE, + usage_names, + UPLUS_COUNT, memmap->usage); + if (ret) + return log_msg_ret("lst", ret); + } + + return 0; +} + +/** + * add_upl_memres() - Add /memory-reserved nodes to the tree + * + * @upl: UPL state + * @root: Parent node to contain the new node + * Return 0 if OK, -ve on error + */ +static int add_upl_memres(const struct upl *upl, ofnode root, + bool skip_existing) +{ + ofnode mem_node; + int i, ret; + + if (!upl->memmap.count) + return 0; + ret = ofnode_add_subnode(root, UPLN_MEMORY_RESERVED, &mem_node); + if (ret) { + if (skip_existing && ret == -EEXIST) + return 0; + return log_msg_ret("img", ret); + } + + for (i = 0; i < upl->memres.count; i++) { + const struct upl_memres *memres = alist_get(&upl->memres, i, + struct upl_memres); + char buf[memres->region.count * sizeof(64) * 2]; + const struct memregion *first; + char name[26]; + int ret, len; + ofnode node; + + if (!memres->region.count) { + log_debug("Memory %d has no regions\n", i); + return log_msg_ret("reg", -EINVAL); + } + first = alist_get(&memres->region, 0, struct memregion); + sprintf(name, "%s@0x%lx", memres->name, first->base); + ret = ofnode_add_subnode(mem_node, name, &node); + if (ret) + return log_msg_ret("memres", ret); + + len = buffer_addr_size(upl, buf, sizeof(buf), + memres->region.count, &memres->region); + ret = ofnode_write_prop(node, UPLP_REG, buf, len, true); + if (!ret && memres->no_map) + ret = ofnode_write_bool(node, UPLP_NO_MAP, + memres->no_map); + if (ret) + return log_msg_ret("lst", ret); + } + + return 0; +} + +/** + * add_upl_serial() - Add serial node + * + * @upl: UPL state + * @root: Parent node to contain the new node + * Return 0 if OK, -ve on error + */ +static int add_upl_serial(const struct upl *upl, ofnode root, + bool skip_existing) +{ + const struct upl_serial *ser = &upl->serial; + const struct memregion *first; + char name[26]; + ofnode node; + int ret; + + if (!ser->compatible || skip_existing) + return 0; + if (!ser->reg.count) + return log_msg_ret("ser", -EINVAL); + first = alist_get(&ser->reg, 0, struct memregion); + sprintf(name, UPLN_SERIAL "@0x%lx", first->base); + ret = ofnode_add_subnode(root, name, &node); + if (ret) + return log_msg_ret("img", ret); + ret = ofnode_write_string(node, UPLP_COMPATIBLE, ser->compatible); + if (!ret) + ret = ofnode_write_u32(node, UPLP_CLOCK_FREQUENCY, + ser->clock_frequency); + if (!ret) + ret = ofnode_write_u32(node, UPLP_CURRENT_SPEED, + ser->current_speed); + if (!ret) { + char buf[16]; + int len; + + len = buffer_addr_size(upl, buf, sizeof(buf), 1, &ser->reg); + if (len < 0) + return log_msg_ret("buf", len); + + ret = ofnode_write_prop(node, UPLP_REG, buf, len, true); + } + if (!ret && ser->reg_io_shift != UPLD_REG_IO_SHIFT) + ret = ofnode_write_u32(node, UPLP_REG_IO_SHIFT, + ser->reg_io_shift); + if (!ret && ser->reg_offset != UPLD_REG_OFFSET) + ret = ofnode_write_u32(node, UPLP_REG_OFFSET, ser->reg_offset); + if (!ret && ser->reg_io_width != UPLD_REG_IO_WIDTH) + ret = ofnode_write_u32(node, UPLP_REG_IO_WIDTH, + ser->reg_io_width); + if (!ret && ser->virtual_reg) + ret = write_addr(upl, node, UPLP_VIRTUAL_REG, ser->virtual_reg); + if (!ret) { + ret = ofnode_write_value(node, UPLP_ACCESS_TYPE, access_types, + ARRAY_SIZE(access_types), + ser->access_type); + } + if (ret) + return log_msg_ret("ser", ret); + + return 0; +} + +/** + * add_upl_graphics() - Add graphics node + * + * @upl: UPL state + * @root: Parent node to contain the new node + * Return 0 if OK, -ve on error + */ +static int add_upl_graphics(const struct upl *upl, ofnode root) +{ + const struct upl_graphics *gra = &upl->graphics; + const struct memregion *first; + char name[36]; + ofnode node; + int ret; + + if (!gra->reg.count) + return log_msg_ret("gra", -ENOENT); + first = alist_get(&gra->reg, 0, struct memregion); + sprintf(name, UPLN_GRAPHICS "@0x%lx", first->base); + ret = ofnode_add_subnode(root, name, &node); + if (ret) + return log_msg_ret("gra", ret); + + ret = ofnode_write_string(node, UPLP_COMPATIBLE, UPLC_GRAPHICS); + if (!ret) { + char buf[16]; + int len; + + len = buffer_addr_size(upl, buf, sizeof(buf), 1, &gra->reg); + if (len < 0) + return log_msg_ret("buf", len); + + ret = ofnode_write_prop(node, UPLP_REG, buf, len, true); + } + if (!ret) + ret = ofnode_write_u32(node, UPLP_WIDTH, gra->width); + if (!ret) + ret = ofnode_write_u32(node, UPLP_HEIGHT, gra->height); + if (!ret) + ret = ofnode_write_u32(node, UPLP_STRIDE, gra->stride); + if (!ret) { + ret = ofnode_write_value(node, UPLP_GRAPHICS_FORMAT, + graphics_formats, + ARRAY_SIZE(graphics_formats), + gra->format); + } + if (ret) + return log_msg_ret("pro", ret); + + return 0; +} + +int upl_write_handoff(const struct upl *upl, ofnode root, bool skip_existing) +{ + ofnode options; + int ret; + + ret = add_root_props(upl, root); + if (ret) + return log_msg_ret("ad1", ret); + ret = ofnode_add_subnode(root, UPLN_OPTIONS, &options); + if (ret && ret != -EEXIST) + return log_msg_ret("opt", -EINVAL); + + ret = add_upl_params(upl, options); + if (ret) + return log_msg_ret("ad1", ret); + + ret = add_upl_image(upl, options); + if (ret) + return log_msg_ret("ad2", ret); + + ret = add_upl_memory(upl, root); + if (ret) + return log_msg_ret("ad3", ret); + + ret = add_upl_memmap(upl, root); + if (ret) + return log_msg_ret("ad4", ret); + + ret = add_upl_memres(upl, root, skip_existing); + if (ret) + return log_msg_ret("ad5", ret); + + ret = add_upl_serial(upl, root, skip_existing); + if (ret) + return log_msg_ret("ad6", ret); + + ret = add_upl_graphics(upl, root); + if (ret && ret != -ENOENT) + return log_msg_ret("ad6", ret); + + return 0; +} + +int upl_create_handoff_tree(const struct upl *upl, oftree *treep) +{ + ofnode root; + oftree tree; + int ret; + + ret = oftree_new(&tree); + if (ret) + return log_msg_ret("new", ret); + + root = oftree_root(tree); + if (!ofnode_valid(root)) + return log_msg_ret("roo", -EINVAL); + + ret = upl_write_handoff(upl, root, false); + if (ret) + return log_msg_ret("wr", ret); + + *treep = tree; + + return 0; +} diff --git a/cmd/Kconfig b/cmd/Kconfig index 978f44eda42..43f78a5aeb1 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -388,6 +388,13 @@ config CMD_SEAMA help Support reading NAND Seattle Image (SEAMA) images. +config CMD_UPL + bool "upl - Universal Payload Specification" + help + Provides commands to deal with UPL payloads and handoff information. + U-Boot supports generating and accepting handoff information. The + mkimage tool will eventually support creating payloads. + config CMD_VBE bool "vbe - Verified Boot for Embedded" depends on BOOTMETH_VBE @@ -2003,6 +2010,7 @@ config SYS_DISABLE_AUTOLOAD config CMD_WGET bool "wget" select PROT_TCP + default y if SANDBOX help wget is a simple command to download kernel, or other files, from a http server over TCP. diff --git a/cmd/Makefile b/cmd/Makefile index 87133cc27a8..91227f1249c 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -189,6 +189,7 @@ obj-$(CONFIG_CMD_UBIFS) += ubifs.o obj-$(CONFIG_CMD_UNIVERSE) += universe.o obj-$(CONFIG_CMD_UNLZ4) += unlz4.o obj-$(CONFIG_CMD_UNZIP) += unzip.o +obj-$(CONFIG_CMD_UPL) += upl.o obj-$(CONFIG_CMD_VIRTIO) += virtio.o obj-$(CONFIG_CMD_WDT) += wdt.o obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o diff --git a/cmd/date.c b/cmd/date.c index 755adec1e71..8614f022761 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -31,7 +31,6 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, int old_bus __maybe_unused; /* switch to correct I2C bus */ -#ifdef CONFIG_DM_RTC struct udevice *dev; rcode = uclass_get_device_by_seq(UCLASS_RTC, 0, &dev); @@ -42,35 +41,19 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } } -#elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM); -#else - old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM); -#endif switch (argc) { case 2: /* set date & time */ if (strcmp(argv[1],"reset") == 0) { puts ("Reset RTC...\n"); -#ifdef CONFIG_DM_RTC rcode = dm_rtc_reset(dev); if (!rcode) rcode = dm_rtc_set(dev, &default_tm); -#else - rtc_reset(); - rcode = rtc_set(&default_tm); -#endif if (rcode) puts("## Failed to set date after RTC reset\n"); } else { /* initialize tm with current time */ -#ifdef CONFIG_DM_RTC rcode = dm_rtc_get(dev, &tm); -#else - rcode = rtc_get(&tm); -#endif if (!rcode) { /* insert new date & time */ if (mk_date(argv[1], &tm) != 0) { @@ -78,11 +61,7 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, break; } /* and write to RTC */ -#ifdef CONFIG_DM_RTC rcode = dm_rtc_set(dev, &tm); -#else - rcode = rtc_set(&tm); -#endif if (rcode) { printf("## Set date failed: err=%d\n", rcode); @@ -93,11 +72,7 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, } fallthrough; case 1: /* get date & time */ -#ifdef CONFIG_DM_RTC rcode = dm_rtc_get(dev, &tm); -#else - rcode = rtc_get(&tm); -#endif if (rcode) { puts("## Get date failed\n"); break; @@ -114,13 +89,6 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, rcode = CMD_RET_USAGE; } - /* switch back to original I2C bus */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - i2c_set_bus_num(old_bus); -#elif !defined(CONFIG_DM_RTC) - I2C_SET_BUS(old_bus); -#endif - return rcode ? CMD_RET_FAILURE : 0; } diff --git a/cmd/i2c.c b/cmd/i2c.c index 7dac0a9fb6c..7246c4fa3e7 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -1698,18 +1698,6 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) { printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); -#ifndef CFG_SYS_I2C_DIRECT_BUS - int j; - - for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { - if (i2c_bus[i].next_hop[j].chip == 0) - break; - printf("->%s@0x%2x:%d", - i2c_bus[i].next_hop[j].mux.name, - i2c_bus[i].next_hop[j].chip, - i2c_bus[i].next_hop[j].channel); - } -#endif printf("\n"); } #endif @@ -1734,17 +1722,6 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, return -1; } printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); -#ifndef CFG_SYS_I2C_DIRECT_BUS - int j; - for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { - if (i2c_bus[i].next_hop[j].chip == 0) - break; - printf("->%s@0x%2x:%d", - i2c_bus[i].next_hop[j].mux.name, - i2c_bus[i].next_hop[j].chip, - i2c_bus[i].next_hop[j].channel); - } -#endif printf("\n"); #endif } diff --git a/cmd/led.c b/cmd/led.c index 2f786f34c67..91fb856ee59 100644 --- a/cmd/led.c +++ b/cmd/led.c @@ -118,7 +118,7 @@ int do_led(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return 0; } -#ifdef CONFIG_LED_BLINK +#if defined(CONFIG_LED_BLINK) || defined(CONFIG_LED_SW_BLINK) #define BLINK "|blink [blink-freq in ms]" #else #define BLINK "" diff --git a/cmd/ubi.c b/cmd/ubi.c index 92998af2b02..0e62e449327 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -423,18 +423,84 @@ int ubi_volume_begin_write(char *volume, void *buf, size_t size, return ubi_volume_continue_write(volume, buf, size); } -int ubi_volume_write(char *volume, void *buf, size_t size) +static int ubi_volume_offset_write(char *volume, void *buf, loff_t offset, + size_t size) { - return ubi_volume_begin_write(volume, buf, size, size); + int len, tbuf_size, ret; + u64 lnum; + struct ubi_volume *vol; + loff_t off = offset; + void *tbuf; + + vol = ubi_find_volume(volume); + if (!vol) + return -ENODEV; + + if (size > vol->reserved_pebs * (ubi->leb_size - vol->data_pad)) + return -EINVAL; + + tbuf_size = vol->usable_leb_size; + tbuf = malloc_cache_aligned(tbuf_size); + if (!tbuf) + return -ENOMEM; + + lnum = off; + off = do_div(lnum, vol->usable_leb_size); + + do { + struct ubi_volume_desc desc = { + .vol = vol, + .mode = UBI_READWRITE, + }; + + len = size > tbuf_size ? tbuf_size : size; + if (off + len >= vol->usable_leb_size) + len = vol->usable_leb_size - off; + + ret = ubi_read(&desc, (int)lnum, tbuf, 0, tbuf_size); + if (ret) { + pr_err("Failed to read leb %lld (%d)\n", lnum, ret); + goto exit; + } + + memcpy(tbuf + off, buf, len); + + ret = ubi_leb_change(&desc, (int)lnum, tbuf, tbuf_size); + if (ret) { + pr_err("Failed to write leb %lld (%d)\n", lnum, ret); + goto exit; + } + + off += len; + if (off >= vol->usable_leb_size) { + lnum++; + off -= vol->usable_leb_size; + } + + buf += len; + size -= len; + } while (size); + +exit: + free(tbuf); + return ret; +} + +int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size) +{ + if (!offset) + return ubi_volume_begin_write(volume, buf, size, size); + + return ubi_volume_offset_write(volume, buf, offset, size); } -int ubi_volume_read(char *volume, char *buf, size_t size) +int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size) { int err, lnum, off, len, tbuf_size; void *tbuf; unsigned long long tmp; struct ubi_volume *vol; - loff_t offp = 0; + loff_t offp = offset; size_t len_read; vol = ubi_find_volume(volume); @@ -769,7 +835,7 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) (void *)addr, size, full_size); } } else { - ret = ubi_volume_write(argv[3], (void *)addr, size); + ret = ubi_volume_write(argv[3], (void *)addr, 0, size); } if (!ret) { printf("%lld bytes written to volume %s\n", size, @@ -795,7 +861,7 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } if (argc == 3) { - return ubi_volume_read(argv[3], (char *)addr, size); + return ubi_volume_read(argv[3], (char *)addr, 0, size); } } diff --git a/cmd/upl.c b/cmd/upl.c new file mode 100644 index 00000000000..c9745886507 --- /dev/null +++ b/cmd/upl.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Commands for UPL handoff generation + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY UCLASS_BOOTSTD + +#include <abuf.h> +#include <alist.h> +#include <command.h> +#include <display_options.h> +#include <mapmem.h> +#include <string.h> +#include <upl.h> +#include <dm/ofnode.h> +#include <test/ut.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int do_upl_info(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + const struct upl *upl = gd_upl(); + + printf("UPL state: %sactive\n", upl ? "" : "in"); + if (!upl) + return 0; + if (argc > 1 && !strcmp("-v", argv[1])) { + int i; + + printf("fit %lx\n", upl->fit); + printf("conf_offset %x\n", upl->conf_offset); + for (i = 0; i < upl->image.count; i++) { + const struct upl_image *img = + alist_get(&upl->image, i, struct upl_image); + + printf("image %d: load %lx size %lx offset %x: %s\n", i, + img->load, img->size, img->offset, + img->description); + } + } + + return 0; +} + +static int do_upl_write(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct upl s_upl, *upl = &s_upl; + struct unit_test_state uts; + struct abuf buf; + oftree tree; + ulong addr; + int ret; + + upl_get_test_data(&uts, upl); + + log_debug("Writing UPL\n"); + ret = upl_create_handoff_tree(upl, &tree); + if (ret) { + log_err("Failed to write (err=%dE)\n", ret); + return CMD_RET_FAILURE; + } + + log_debug("Flattening\n"); + ret = oftree_to_fdt(tree, &buf); + if (ret) { + log_err("Failed to write (err=%dE)\n", ret); + return CMD_RET_FAILURE; + } + addr = map_to_sysmem(abuf_data(&buf)); + printf("UPL handoff written to %lx size %lx\n", addr, abuf_size(&buf)); + if (env_set_hex("upladdr", addr) || + env_set_hex("uplsize", abuf_size(&buf))) { + printf("Cannot set env var\n"); + return CMD_RET_FAILURE; + } + + log_debug("done\n"); + + return 0; +} + +static int do_upl_read(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct upl s_upl, *upl = &s_upl; + oftree tree; + ulong addr; + int ret; + + if (argc < 1) + return CMD_RET_USAGE; + addr = hextoul(argv[1], NULL); + + printf("Reading UPL at %lx\n", addr); + tree = oftree_from_fdt(map_sysmem(addr, 0)); + ret = upl_read_handoff(upl, tree); + if (ret) { + log_err("Failed to read (err=%dE)\n", ret); + return CMD_RET_FAILURE; + } + + return 0; +} + +U_BOOT_LONGHELP(upl, + "info [-v] - Check UPL status\n" + "upl read <addr> - Read handoff information\n" + "upl write - Write handoff information"); + +U_BOOT_CMD_WITH_SUBCMDS(upl, "Universal Payload support", upl_help_text, + U_BOOT_SUBCMD_MKENT(info, 2, 1, do_upl_info), + U_BOOT_SUBCMD_MKENT(read, 2, 1, do_upl_read), + U_BOOT_SUBCMD_MKENT(write, 1, 1, do_upl_write)); diff --git a/common/board_f.c b/common/board_f.c index 29e185137ad..454426d921c 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -40,6 +40,7 @@ #include <sysreset.h> #include <timer.h> #include <trace.h> +#include <upl.h> #include <video.h> #include <watchdog.h> #include <asm/cache.h> @@ -683,13 +684,7 @@ static int reloc_bootstage(void) if (gd->flags & GD_FLG_SKIP_RELOC) return 0; if (gd->new_bootstage) { - int size = bootstage_get_size(); - - debug("Copying bootstage from %p to %p, size %x\n", - gd->bootstage, gd->new_bootstage, size); - memcpy(gd->new_bootstage, gd->bootstage, size); - gd->bootstage = gd->new_bootstage; - bootstage_relocate(); + bootstage_relocate(gd->new_bootstage); } #endif @@ -859,6 +854,26 @@ __weak int clear_bss(void) return 0; } +static int initf_upl(void) +{ + struct upl *upl; + int ret; + + if (!IS_ENABLED(CONFIG_UPL_IN) || !(gd->flags & GD_FLG_UPL)) + return 0; + + upl = malloc(sizeof(struct upl)); + if (upl) + ret = upl_read_handoff(upl, oftree_default()); + if (ret) { + printf("UPL handoff: read failure (err=%dE)\n", ret); + return ret; + } + gd_set_upl(upl); + + return 0; +} + static const init_fnc_t init_sequence_f[] = { setup_mon_len, #ifdef CONFIG_OF_CONTROL @@ -868,6 +883,7 @@ static const init_fnc_t init_sequence_f[] = { trace_early_init, #endif initf_malloc, + initf_upl, log_init, initf_bootstage, /* uses its own timer, so does not need DM */ event_init, diff --git a/common/board_r.c b/common/board_r.c index d4ba245ac69..f445803d7a4 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -521,6 +521,8 @@ static int dm_announce(void) uclass_count); if (CONFIG_IS_ENABLED(OF_REAL)) printf(", devicetree: %s", fdtdec_get_srcname()); + if (CONFIG_IS_ENABLED(UPL)) + printf(", universal payload active"); printf("\n"); if (IS_ENABLED(CONFIG_OF_HAS_PRIOR_STAGE) && (gd->fdt_src == FDTSRC_SEPARATE || diff --git a/common/bootstage.c b/common/bootstage.c index b6c268d9f47..49acc9078a6 100644 --- a/common/bootstage.c +++ b/common/bootstage.c @@ -54,12 +54,16 @@ struct bootstage_hdr { u32 next_id; /* Next ID to use for bootstage */ }; -int bootstage_relocate(void) +int bootstage_relocate(void *to) { - struct bootstage_data *data = gd->bootstage; + struct bootstage_data *data; int i; char *ptr; + debug("Copying bootstage from %p to %p\n", gd->bootstage, to); + memcpy(to, gd->bootstage, sizeof(struct bootstage_data)); + data = gd->bootstage = to; + /* Figure out where to relocate the strings to */ ptr = (char *)(data + 1); diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 62e8557daa7..1ac7ce3f43c 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -386,8 +386,8 @@ nextchunk-> +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ /* pad request bytes into a usable size */ #define request2size(req) \ - (((long)((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \ - (long)(MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \ + ((((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) < \ + (MINSIZE + MALLOC_ALIGN_MASK)) ? MINSIZE : \ (((req) + (SIZE_SZ + MALLOC_ALIGN_MASK)) & ~(MALLOC_ALIGN_MASK))) /* Check if m has acceptable alignment */ @@ -581,6 +581,9 @@ void *sbrk(ptrdiff_t increment) ulong old = mem_malloc_brk; ulong new = old + increment; + if ((new < mem_malloc_start) || (new > mem_malloc_end)) + return (void *)MORECORE_FAILURE; + /* * if we are giving memory back make sure we clear it out since * we set MORECORE_CLEARS to 1 @@ -588,9 +591,6 @@ void *sbrk(ptrdiff_t increment) if (increment < 0) memset((void *)new, 0, -increment); - if ((new < mem_malloc_start) || (new > mem_malloc_end)) - return (void *)MORECORE_FAILURE; - mem_malloc_brk = new; return (void *)old; @@ -1274,7 +1274,8 @@ Void_t* mALLOc_impl(bytes) size_t bytes; return NULL; } - if ((long)bytes < 0) return NULL; + if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0) + return NULL; nb = request2size(bytes); /* padded request size; */ @@ -1687,7 +1688,8 @@ Void_t* rEALLOc_impl(oldmem, bytes) Void_t* oldmem; size_t bytes; } #endif - if ((long)bytes < 0) return NULL; + if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0) + return NULL; /* realloc of null is supposed to be same as malloc */ if (oldmem == NULL) return mALLOc_impl(bytes); @@ -1698,6 +1700,10 @@ Void_t* rEALLOc_impl(oldmem, bytes) Void_t* oldmem; size_t bytes; panic("pre-reloc realloc() is not supported"); } #endif + if (CONFIG_IS_ENABLED(UNIT_TEST) && malloc_testing) { + if (--malloc_max_allocs < 0) + return NULL; + } newp = oldp = mem2chunk(oldmem); newsize = oldsize = chunksize(oldp); @@ -1907,7 +1913,8 @@ Void_t* mEMALIGn_impl(alignment, bytes) size_t alignment; size_t bytes; mchunkptr remainder; /* spare room at end to split off */ long remainder_size; /* its size */ - if ((long)bytes < 0) return NULL; + if (bytes > CONFIG_SYS_MALLOC_LEN || (long)bytes < 0) + return NULL; #if CONFIG_IS_ENABLED(SYS_MALLOC_F) if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) { diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 6f56ca911c1..44a68abce60 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -78,6 +78,7 @@ config SPL_MAX_SIZE hex "Maximum size of the SPL image, excluding BSS" default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB default 0x1b000 if AM33XX && !TI_SECURE_DEVICE + default 0xec00 if OMAP34XX default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000 default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616 @@ -206,7 +207,7 @@ config SPL_BINMAN_SYMBOLS config SPL_BINMAN_UBOOT_SYMBOLS bool "Declare binman symbols for U-Boot phases in SPL" depends on SPL_BINMAN_SYMBOLS - default n if ARCH_IMX8M || ARCH_IMX9 + default n if ARCH_IMX8M || ARCH_IMX8ULP || ARCH_IMX9 default y help This enables use of symbols in SPL which refer to U-Boot phases, @@ -261,6 +262,7 @@ config SPL_LDSCRIPT config SPL_TEXT_BASE hex "SPL Text Base" + default 0x40200000 if OMAP34XX default 0x402F4000 if AM43XX default 0x402F0400 if AM33XX default 0x40301350 if OMAP54XX diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl index 4ee3b9b826d..92d4d43ec87 100644 --- a/common/spl/Kconfig.tpl +++ b/common/spl/Kconfig.tpl @@ -23,7 +23,7 @@ config TPL_BINMAN_SYMBOLS config TPL_BINMAN_UBOOT_SYMBOLS bool "Declare binman symbols for U-Boot phases in TPL" depends on TPL_BINMAN_SYMBOLS - default n if ARCH_IMX8M || ARCH_IMX9 + default n if ARCH_IMX8M || ARCH_IMX8ULP || ARCH_IMX9 default y help This enables use of symbols in TPL which refer to U-Boot phases, diff --git a/common/spl/Kconfig.vpl b/common/spl/Kconfig.vpl index f1993026bba..d06f36d4ee4 100644 --- a/common/spl/Kconfig.vpl +++ b/common/spl/Kconfig.vpl @@ -243,7 +243,7 @@ config VPL_BINMAN_SYMBOLS config VPL_BINMAN_UBOOT_SYMBOLS bool "Declare binman symbols for U-Boot phases in VPL" depends on VPL_BINMAN_SYMBOLS - default n if ARCH_IMX8M || ARCH_IMX9 + default n if ARCH_IMX8M || ARCH_IMX8ULP || ARCH_IMX9 default y help This enables use of symbols in VPL which refer to U-Boot phases, diff --git a/common/spl/Makefile b/common/spl/Makefile index 4809f9c3ec1..137b18428bd 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -37,3 +37,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o endif + +obj-$(CONFIG_$(SPL_TPL_)UPL) += spl_upl.o diff --git a/common/spl/spl.c b/common/spl/spl.c index 7794ddccade..d6a364de6ee 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -810,6 +810,14 @@ void board_init_r(gd_t *dummy1, ulong dummy2) printf(SPL_TPL_PROMPT "SPL hand-off write failed (err=%d)\n", ret); } + if (CONFIG_IS_ENABLED(UPL_OUT) && (gd->flags & GD_FLG_UPL)) { + ret = spl_write_upl_handoff(&spl_image); + if (ret) { + printf(SPL_TPL_PROMPT + "UPL hand-off write failed (err=%d)\n", ret); + hang(); + } + } if (CONFIG_IS_ENABLED(BLOBLIST)) { ret = bloblist_finish(); if (ret) diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 2a097f4464c..1ad5a69d807 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -12,6 +12,7 @@ #include <memalign.h> #include <mapmem.h> #include <spl.h> +#include <upl.h> #include <sysinfo.h> #include <asm/global_data.h> #include <asm/io.h> @@ -336,6 +337,8 @@ static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, image_info->entry_point = FDT_ERROR; } + upl_add_image(fit, node, load_addr, length); + return 0; } @@ -847,6 +850,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, spl_image->entry_point = spl_image->load_addr; spl_image->flags |= SPL_FIT_FOUND; + upl_set_fit_info(map_to_sysmem(ctx.fit), ctx.conf_node, + spl_image->entry_point); return 0; } @@ -941,6 +946,10 @@ int spl_load_fit_image(struct spl_image_info *spl_image, if (ret < 0) return ret; } + spl_image->flags |= SPL_FIT_FOUND; + + upl_set_fit_info(map_to_sysmem(header), conf_noffset, + spl_image->entry_point); return 0; } diff --git a/common/spl/spl_upl.c b/common/spl/spl_upl.c new file mode 100644 index 00000000000..067d437150f --- /dev/null +++ b/common/spl/spl_upl.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * UPL handoff parsing + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#define LOG_CATEGORY UCLASS_BOOTSTD + +#include <alist.h> +#include <bloblist.h> +#include <dm.h> +#include <image.h> +#include <mapmem.h> +#include <serial.h> +#include <spl.h> +#include <upl.h> +#include <video.h> +#include <asm/global_data.h> +#include <dm/read.h> +#include <dm/uclass-internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct upl s_upl; + +void upl_set_fit_addr(ulong fit) +{ + struct upl *upl = &s_upl; + + upl->fit = fit; +} + +void upl_set_fit_info(ulong fit, int conf_offset, ulong entry_addr) +{ + struct upl *upl = &s_upl; + + upl->fit = fit; + upl->conf_offset = conf_offset; + log_debug("upl: add fit %lx conf %x\n", fit, conf_offset); +} + +int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc) +{ + struct upl *upl = &s_upl; + struct upl_image img; + + img.load = load_addr; + img.size = size; + img.offset = node; + img.description = desc; + if (!alist_add(&upl->image, img)) + return -ENOMEM; + log_debug("upl: add image %s at %lx size %lx\n", desc, load_addr, size); + + return 0; +} + +static int write_serial(struct upl_serial *ser) +{ + struct udevice *dev = gd->cur_serial_dev; + struct serial_device_info info; + struct memregion region; + int ret; + + if (!dev) + return log_msg_ret("ser", -ENOENT); + ret = serial_getinfo(dev, &info); + if (ret) + return log_msg_ret("inf", ret); + + ser->compatible = ofnode_read_string(dev_ofnode(dev), "compatible"); + ser->clock_frequency = info.clock; + ser->current_speed = gd->baudrate; + region.base = info.addr; + region.size = info.size; + alist_init_struct(&ser->reg, struct memregion); + if (!alist_add(&ser->reg, region)) + return -ENOMEM; + ser->reg_io_shift = info.reg_shift; + ser->reg_offset = info.reg_offset; + ser->reg_io_width = info.reg_width; + ser->virtual_reg = 0; + ser->access_type = info.addr_space; + + return 0; +} + +static int write_graphics(struct upl_graphics *gra) +{ + struct video_uc_plat *plat; + struct video_priv *priv; + struct memregion region; + struct udevice *dev; + + alist_init_struct(&gra->reg, struct memregion); + uclass_find_first_device(UCLASS_VIDEO, &dev); + if (!dev || !device_active(dev)) + return log_msg_ret("vid", -ENOENT); + + plat = dev_get_uclass_plat(dev); + region.base = plat->base; + region.size = plat->size; + if (!alist_add(&gra->reg, region)) + return log_msg_ret("reg", -ENOMEM); + + priv = dev_get_uclass_priv(dev); + gra->width = priv->xsize; + gra->height = priv->ysize; + gra->stride = priv->line_length; /* private field */ + switch (priv->format) { + case VIDEO_RGBA8888: + case VIDEO_X8R8G8B8: + gra->format = UPLGF_ARGB32; + break; + case VIDEO_X8B8G8R8: + gra->format = UPLGF_ABGR32; + break; + case VIDEO_X2R10G10B10: + log_debug("device '%s': VIDEO_X2R10G10B10 not supported\n", + dev->name); + return log_msg_ret("for", -EPROTO); + case VIDEO_UNKNOWN: + log_debug("device '%s': Unknown video format\n", dev->name); + return log_msg_ret("for", -EPROTO); + } + + return 0; +} + +int spl_write_upl_handoff(struct spl_image_info *spl_image) +{ + struct upl *upl = &s_upl; + struct abuf buf; + ofnode root; + void *ptr; + int ret; + + log_debug("UPL: Writing handoff - image_count=%d\n", upl->image.count); + upl->addr_cells = IS_ENABLED(CONFIG_PHYS_64BIT) ? 2 : 1; + upl->size_cells = IS_ENABLED(CONFIG_PHYS_64BIT) ? 2 : 1; + upl->bootmode = UPLBM_DEFAULT; + ret = write_serial(&upl->serial); + if (ret) + return log_msg_ret("ser", ret); + ret = write_graphics(&upl->graphics); + if (ret && ret != -ENOENT) + return log_msg_ret("gra", ret); + + root = ofnode_root(); + ret = upl_write_handoff(upl, root, true); + if (ret) + return log_msg_ret("wr", ret); + + ret = oftree_to_fdt(oftree_default(), &buf); + if (ret) + return log_msg_ret("fdt", ret); + log_debug("FDT size %zx\n", abuf_size(&buf)); + + ptr = bloblist_add(BLOBLISTT_CONTROL_FDT, abuf_size(&buf), 0); + if (!ptr) + return log_msg_ret("blo", -ENOENT); + memcpy(ptr, abuf_data(&buf), abuf_size(&buf)); + + return 0; +} + +void spl_upl_init(void) +{ + upl_init(&s_upl); +} diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 9eac43a0fcb..dd30e8d30da 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -139,7 +139,6 @@ CONFIG_CMD_USB=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index f8dfd1d2060..3fcebc6aa7d 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_DEFAULT_DEVICE_TREE="am335x-baltos" CONFIG_AM33XX=y CONFIG_TARGET_AM335X_BALTOS=y @@ -19,6 +17,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;" CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index cabc181460a..5dd0b328835 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -2,8 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_AM33XX=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 8239f5f84da..a55aace0246 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -2,8 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 75138542431..7c7041c23b0 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian" @@ -31,6 +29,7 @@ CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index 3694cc32db9..d780239715f 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_SPL_TEXT_BASE=0x40300350 diff --git a/configs/am335x_hs_evm_spi_defconfig b/configs/am335x_hs_evm_spi_defconfig new file mode 100644 index 00000000000..df009844def --- /dev/null +++ b/configs/am335x_hs_evm_spi_defconfig @@ -0,0 +1,26 @@ +#include <configs/am335x_hs_evm_defconfig> + +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y + +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y + +CONFIG_SPI_BOOT=y + +CONFIG_SPL_MTD_SUPPORT=y + +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_EXT4_WRITE=y + +CONFIG_BLK=n + +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_OF_LIBFDT=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index a99b7b46cfb..bd979941b7a 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" CONFIG_SPL_TEXT_BASE=0x40301950 diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index ddffd4f46f0..19943881973 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x18000 CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033" CONFIG_AM33XX=y @@ -76,7 +74,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig index febe5ebaabb..a0163f16f36 100644 --- a/configs/am335x_pdu001_defconfig +++ b/configs/am335x_pdu001_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x1200 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001" @@ -24,6 +22,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOOTCOMMAND="run eval_boot_device;part uuid mmc ${mmc_boot}:${root_fs_partition} root_fs_partuuid;setenv bootargs console=${console} vt.global_cursor_default=0 root=PARTUUID=${root_fs_partuuid} rootfstype=ext4 rootwait rootdelay=1;fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};bootz ${loadaddr} - ${fdtaddr}" CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 47c08e5054b..72933ba1a64 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" @@ -33,6 +31,7 @@ CONFIG_BOOTCOMMAND="if mmc dev 1; mmc rescan; then run emmc_setup; else echo ERR CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 @@ -66,10 +65,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_OMAP_HS=y CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index c7618c5c799..b8a3227557d 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" @@ -31,6 +29,7 @@ CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 @@ -64,10 +63,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_OMAP_HS=y CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index 934265815be..b25a4de30c7 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" @@ -34,6 +32,7 @@ CONFIG_BOOTCOMMAND="run fusecmd; if run netboot; then echo Booting from network; CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 @@ -67,10 +66,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_OMAP_HS=y CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 439f9b8188a..8486ccb6d52 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x1000 CONFIG_ENV_OFFSET=0x7000 CONFIG_DEFAULT_DEVICE_TREE="am335x-shc" @@ -34,6 +32,7 @@ CONFIG_BOOTCOMMAND="if mmc dev 0; mmc rescan; then run sd_setup; else echo ERROR CONFIG_DEFAULT_FDT_FILE="am335x-shc" CONFIG_SYS_PBSIZE=1049 CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 @@ -66,10 +65,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_MMC_OMAP_HS=y CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 88122bd052c..7444e55b6f7 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_OFFSET=0x0 CONFIG_DEFAULT_DEVICE_TREE="am335x-sl50" CONFIG_AM33XX=y @@ -24,6 +22,7 @@ CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n" CONFIG_AUTOBOOT_DELAY_STR="d" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_ENV_SUPPORT=y @@ -66,7 +65,7 @@ CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 3236f1dd672..4eb406673ff 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -5,15 +5,10 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SOURCE_FILE="am3517evm" -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_DEFAULT_DEVICE_TREE="ti/omap/am3517-evm" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_AM3517_EVM=y CONFIG_EMIF4=y -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL_SYS_MALLOC_F_LEN=0x2500 CONFIG_SPL=y CONFIG_LTO=y @@ -21,7 +16,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi" CONFIG_SYS_PBSIZE=1054 -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index d73b1cb804b..0fc4c0f269a 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -3,8 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_ENV_SIZE=0x10000 CONFIG_DM_GPIO=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 89e212595af..c538c1ae352 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TEXT_BASE=0x30000000 CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x110000 diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 2ff01193285..0fe5479757b 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -3,8 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_ENV_SIZE=0x10000 CONFIG_DM_GPIO=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 845b686ac93..c4693bc9824 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -2,8 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_ENV_SIZE=0x10000 CONFIG_DM_GPIO=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index ff5073cbb2b..980ef13f104 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_ENV_SIZE=0x10000 CONFIG_DM_GPIO=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index 5ef59d830e5..75725e179d7 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_CPU_INIT=y # CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x110000 diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 7c3ceeb07db..587af53acb6 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -1,9 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 1f7eca4691e..b790897645f 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -2,9 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 807e1d66a6d..450751b354f 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -2,9 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037ff00 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/amd_versal2_mini_defconfig b/configs/amd_versal2_mini_defconfig new file mode 100644 index 00000000000..0dd2305bfb2 --- /dev/null +++ b/configs/amd_versal2_mini_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="amd_versal2_mini" +# CONFIG_ARM64_CRC32 is not set +CONFIG_COUNTER_FREQUENCY=100000000 +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_VERSAL2=y +CONFIG_TEXT_BASE=0xBBF00000 +CONFIG_SYS_MALLOC_LEN=0x20000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" +CONFIG_DEBUG_UART_BASE=0xf1920000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_DEBUG_UART=y +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_AUTOBOOT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="versal2> " +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +# CONFIG_CMD_SLEEP is not set +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +# CONFIG_POWER is not set +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_ARM_DCC=y +CONFIG_PL01X_SERIAL=y +# CONFIG_GZIP is not set diff --git a/configs/amd_versal2_mini_emmc_defconfig b/configs/amd_versal2_mini_emmc_defconfig new file mode 100644 index 00000000000..7ad44386a6d --- /dev/null +++ b/configs/amd_versal2_mini_emmc_defconfig @@ -0,0 +1,69 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="amd_versal2_mini" +CONFIG_COUNTER_FREQUENCY=100000000 +CONFIG_ARCH_VERSAL2=y +CONFIG_TEXT_BASE=0x10000 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" +CONFIG_DEBUG_UART_BASE=0xf1920000 +CONFIG_DEBUG_UART_CLOCK=100000000 +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_DEBUG_UART=y +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="versal2> " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_ARM_DCC=y +CONFIG_PL01X_SERIAL=y +CONFIG_FAT_WRITE=y +# CONFIG_GZIP is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_LMB is not set diff --git a/configs/amd_versal2_mini_ospi_defconfig b/configs/amd_versal2_mini_ospi_defconfig new file mode 100644 index 00000000000..2242960392f --- /dev/null +++ b/configs/amd_versal2_mini_ospi_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="amd_versal2_mini" +# CONFIG_ARM64_CRC32 is not set +CONFIG_COUNTER_FREQUENCY=100000000 +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_VERSAL2=y +CONFIG_TEXT_BASE=0xBBF00000 +CONFIG_SYS_MALLOC_LEN=0x20000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" +CONFIG_DEBUG_UART_BASE=0xf1920000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_DEBUG_UART=y +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_AUTOBOOT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="versal2> " +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +# CONFIG_CMD_SLEEP is not set +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +# CONFIG_SPI_FLASH_LOCK is not set +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +# CONFIG_POWER is not set +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_ARM_DCC=y +CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_HAS_CQSPI_REF_CLK=y +CONFIG_CQSPI_REF_CLK=200000000 +CONFIG_CADENCE_OSPI_VERSAL=y +# CONFIG_GZIP is not set diff --git a/configs/amd_versal2_mini_qspi_defconfig b/configs/amd_versal2_mini_qspi_defconfig new file mode 100644 index 00000000000..3360c1546a2 --- /dev/null +++ b/configs/amd_versal2_mini_qspi_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="amd_versal2_mini" +# CONFIG_ARM64_CRC32 is not set +CONFIG_COUNTER_FREQUENCY=100000000 +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_VERSAL2=y +CONFIG_TEXT_BASE=0xBBF00000 +CONFIG_SYS_MALLOC_LEN=0x20000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF20000 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="amd-versal2-mini" +CONFIG_DEBUG_UART_BASE=0xf1920000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0xBBF80000 +CONFIG_DEBUG_UART=y +# CONFIG_EXPERT is not set +CONFIG_REMAKE_ELF=y +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_AUTOBOOT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="versal2> " +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +# CONFIG_CMD_SLEEP is not set +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +# CONFIG_SPI_FLASH_LOCK is not set +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_POWER is not set +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_ARM_DCC=y +CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y +# CONFIG_GZIP is not set diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 2d611f84cd9..c4bf77186cd 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -46,6 +46,7 @@ CONFIG_CMD_USB=y CONFIG_BOOTP_MAY_FAIL=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y @@ -59,6 +60,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_BOARD=y CONFIG_DTB_RESELECT=y @@ -119,7 +121,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y -CONFIG_XILINX_UARTLITE=y CONFIG_SOC_DEVICE=y CONFIG_SOC_AMD_VERSAL2=y CONFIG_SPI=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 0b2ee74b003..8947b76e11f 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -6,8 +6,6 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_DM_GPIO=y @@ -39,6 +37,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index f584b8d30b1..dc868b72b21 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -4,8 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x20000 @@ -39,6 +37,7 @@ CONFIG_BOARD_TYPES=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 6c27f07fc79..fc801f26740 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -4,8 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x500000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x40000 CONFIG_DM_GPIO=y @@ -35,6 +33,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index c574d93806a..8cb6b34ce76 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030fef0 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x20000 CONFIG_DM_GPIO=y @@ -24,6 +22,7 @@ CONFIG_BOOTCOMMAND="run mmcboot; run nandboot; run netboot" CONFIG_DEFAULT_FDT_FILE="am335x-chiliboard.dtb" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y @@ -53,7 +52,7 @@ CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MISC=y CONFIG_MMC_OMAP_HS=y diff --git a/configs/cm3588-nas-rk3588_defconfig b/configs/cm3588-nas-rk3588_defconfig new file mode 100644 index 00000000000..d6d82757a2d --- /dev/null +++ b/configs/cm3588-nas-rk3588_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-friendlyelec-cm3588-nas" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_CM3588_NAS_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-friendlyelec-cm3588-nas.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_BUTTON=y +CONFIG_BUTTON_ADC=y +CONFIG_BUTTON_GPIO=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 386616cc420..81a39f70735 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -80,7 +80,7 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y # CONFIG_DWC_AHSATA_AHCI is not set CONFIG_LBA48=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_SYS_MXC_I2C3_SPEED=400000 diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 32f126a5174..eabeee8b8da 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -5,8 +5,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0xC0000 @@ -38,6 +36,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y +# CONFIG_SPL_DM_I2C is not set CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y @@ -72,7 +71,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_SYS_RX_ETH_BUFFER=64 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_HSMMC2_8BIT=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 7653fbbe7e5..33201cec772 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -3,13 +3,8 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_DEFAULT_DEVICE_TREE="omap3-devkit8000" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_DEVKIT8000=y -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL_BSS_START_ADDR=0x80000500 CONFIG_SPL=y @@ -17,7 +12,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run autoboot" CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 0cea5504364..6264d9fa7ad 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -2,9 +2,6 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x18000 CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 5f56b187503..4e7929718fd 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -3,9 +3,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x18000 CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 5b67a0e8392..68d342b277c 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -3,9 +3,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_F_LEN=0x18000 CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4037fef0 CONFIG_SF_DEFAULT_SPEED=76800000 CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig index ba3f381f69f..78ee5c1eb66 100644 --- a/configs/draco-etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -5,8 +5,6 @@ CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x980000 CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index 43d29f5b11a..81a349b730c 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -5,8 +5,6 @@ CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index b457b22fc64..265c1138dfe 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -5,8 +5,6 @@ CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_AM33XX=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index cc2f567c8a8..004f1866162 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -46,7 +46,6 @@ CONFIG_CMD_SNTP=y CONFIG_CMD_DNS=y CONFIG_CMD_BSP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 473891607b0..f1d9bb34aba 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -4,14 +4,9 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_ENV_SIZE=0x8000 CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-igep0020" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_IGEP00X0=y -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y @@ -22,7 +17,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index b302df1f351..0f0748b6792 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x400000 -CONFIG_IMX_CONFIG="" +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx8ulp/imximage.cfg" CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk" CONFIG_SPL_TEXT_BASE=0x22020000 @@ -38,6 +38,7 @@ CONFIG_SPL_MAX_SIZE=0x25000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx8ulp/container.cfg" # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 8d6cb240446..f201a175727 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -18,7 +18,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm" CONFIG_SPL_TEXT_BASE=0xC100000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc1223f4 @@ -99,3 +99,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index e3c0ae15071..46501d59e09 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -15,7 +15,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2e-evm" CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y @@ -73,3 +73,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 5d54d75f974..57a3d362a1b 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -17,7 +17,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm" CONFIG_SPL_TEXT_BASE=0xC0A0000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc0c23f4 @@ -57,7 +57,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice" +CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y @@ -109,3 +109,4 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_SDP=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 9adab3af305..392ec5b2a05 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -14,7 +14,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc09ff10 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2g-evm" CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y @@ -33,7 +33,7 @@ CONFIG_BOOTP_DNS2=y CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice" +CONFIG_OF_LIST="ti/keystone/keystone-k2g-evm ti/keystone/keystone-k2g-ice" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y @@ -84,3 +84,4 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_SDP=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 4da75d1ca76..2e29b2f2aeb 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -18,7 +18,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm" CONFIG_SPL_TEXT_BASE=0xC200000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc2223f4 @@ -100,3 +100,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 1a24d7142b8..cf299f2457c 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -15,7 +15,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc1fff10 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2hk-evm" CONFIG_TIMESTAMP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y @@ -74,3 +74,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index c4534f033ac..0cadece4b02 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -18,7 +18,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm" CONFIG_SPL_TEXT_BASE=0xC100000 CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK=0xc1223f4 @@ -100,3 +100,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index c874349e942..5496049d3a3 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -15,7 +15,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0fff10 CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0x100000 -CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" +CONFIG_DEFAULT_DEVICE_TREE="ti/keystone/keystone-k2l-evm" CONFIG_TIMESTAMP=y CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y @@ -78,3 +78,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_OF_UPSTREAM=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 06e41546d67..0066414f0f5 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -61,7 +61,6 @@ CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 0b54bc999e7..44a1459749f 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -43,7 +43,6 @@ CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index f1009e1738b..cbc8d6a5cf4 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -68,7 +68,6 @@ CONFIG_CMD_PCI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index ff371daaa0d..8ac29b9289f 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -27,7 +27,6 @@ CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_IDE_MAXBUS=1 diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 5b130bcde9b..0a71013d5fc 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -29,7 +29,6 @@ CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_IDE_MAXBUS=1 diff --git a/configs/malta_defconfig b/configs/malta_defconfig index ce917a69de5..355292ef950 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -26,7 +26,6 @@ CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_IDE_MAXBUS=1 diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index de29a7a3a5b..ffd27713963 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -28,7 +28,6 @@ CONFIG_CMD_PCI=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y # CONFIG_ISO_PARTITION is not set CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_IDE_MAXBUS=1 diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 1fe68ef93f9..dddb57efd3e 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -32,7 +32,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index e5178fb3d6b..5932a15a33d 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -31,7 +31,6 @@ CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 4a6c320faf5..8e30093ed9d 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_DM_WARN=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 7ab12e619ac..e1865b2e171 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -CONFIG_SPL_DM_WARN=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 322689ef3a2..dd3541bc59a 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -67,7 +67,7 @@ CONFIG_NETCONSOLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_USDHC=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 23b2e503385..843b61dec4a 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -6,14 +6,9 @@ CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO is not set -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-35xx-devkit" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL=y CONFIG_LTO=y CONFIG_ANDROID_BOOT_IMAGE=y @@ -24,7 +19,6 @@ CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb" CONFIG_SYS_PBSIZE=1054 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index a5f242ff40c..bbd1b746cf9 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -6,14 +6,9 @@ CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO is not set -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-35xx-devkit" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL=y CONFIG_LTO=y CONFIG_SYS_MONITOR_BASE=0x10000000 @@ -25,7 +20,6 @@ CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb" CONFIG_SYS_PBSIZE=1054 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 3c8d974fbd0..cc0b61af509 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -3,13 +3,8 @@ CONFIG_ARM=y # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_OMAP2PLUS=y CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_DEFAULT_DEVICE_TREE="omap3-evm" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_EVM=y -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y @@ -18,7 +13,6 @@ CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" CONFIG_SYS_PBSIZE=1053 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index d081d4e0fb4..ed04386cf95 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -6,14 +6,9 @@ CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO is not set -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-torpedo-37xx-devkit" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL=y CONFIG_LTO=y CONFIG_ANDROID_BOOT_IMAGE=y @@ -23,7 +18,6 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_SYS_PBSIZE=1054 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 68e89d245ee..c5d76d0d086 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -6,14 +6,9 @@ CONFIG_TEXT_BASE=0x80100000 CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_TI_COMMON_CMD_OPTIONS=y # CONFIG_SPL_GPIO is not set -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 CONFIG_DEFAULT_DEVICE_TREE="ti/omap/logicpd-som-lv-37xx-devkit" -CONFIG_SPL_TEXT_BASE=0x40200000 CONFIG_TARGET_OMAP3_LOGIC=y # CONFIG_SPL_OMAP3_ID_NAND is not set -CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SPL=y CONFIG_LTO=y CONFIG_SYS_MONITOR_BASE=0x10000000 @@ -25,7 +20,6 @@ CONFIG_PREBOOT="setenv preboot;saveenv;" CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb" CONFIG_SYS_PBSIZE=1054 CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_SPL_MAX_SIZE=0xec00 CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 diff --git a/configs/orangepi-3b-rk3566_defconfig b/configs/orangepi-3b-rk3566_defconfig new file mode 100644 index 00000000000..575dc4340d3 --- /dev/null +++ b/configs/orangepi-3b-rk3566_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-orangepi-3b" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ORANGEPI_3B_RK3566=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-orangepi-3b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_LIST="rk3566-orangepi-3b rk3566-orangepi-3b-v1.1 rk3566-orangepi-3b-v2.1" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 78469814af3..a4e467fa05e 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk" CONFIG_AM33XX=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index ac638c4e321..d5056ccd98e 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_OFFSET=0xA0000 CONFIG_DEFAULT_DEVICE_TREE="am335x-regor-rdk" CONFIG_AM33XX=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 98c62171865..5813d102475 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -4,8 +4,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_OFFSET=0xA0000 CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk" CONFIG_AM33XX=y diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig index e46acf3a3b5..2d075d12174 100644 --- a/configs/pinetab2-rk3566_defconfig +++ b/configs/pinetab2-rk3566_defconfig @@ -5,7 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_SF_DEFAULT_SPEED=24000000 CONFIG_SF_DEFAULT_MODE=0x1000 -CONFIG_DEFAULT_DEVICE_TREE="rk3566-pinetab2-v2.0" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-pinetab2-v2.0" CONFIG_ROCKCHIP_RK3568=y CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y CONFIG_ROCKCHIP_SPI_IMAGE=y @@ -47,8 +47,7 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -# CONFIG_OF_UPSTREAM is not set -CONFIG_OF_LIST="rk3566-pinetab2-v0.1 rk3566-pinetab2-v2.0" +CONFIG_OF_LIST="rockchip/rk3566-pinetab2-v0.1 rockchip/rk3566-pinetab2-v2.0" CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 9e5499a1fec..ccc7f355dbd 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" +CONFIG_CONSOLE_MUX=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 CONFIG_SPL_PAD_TO=0x38000 @@ -40,7 +41,6 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_PMIC=y @@ -102,12 +102,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_BPP8 is not set -CONFIG_DISPLAY=y -CONFIG_VIDEO_ROCKCHIP=y -CONFIG_DISPLAY_ROCKCHIP_HDMI=y -CONFIG_BMP_16BPP=y -CONFIG_BMP_24BPP=y -CONFIG_BMP_32BPP=y CONFIG_ERRNO_STR=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index c2f869391d7..30946b8f6b4 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -6,8 +6,6 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50" diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 7e166f43908..088ba39f18e 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_DFU=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TPM=y CONFIG_CMD_MTDPARTS=y CONFIG_ENV_IS_IN_FLASH=y @@ -68,3 +69,4 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_SEMIHOSTING=y CONFIG_TPM=y +CONFIG_EFI_HTTP_BOOT=y diff --git a/configs/radxa-zero-3-rk3566_defconfig b/configs/radxa-zero-3-rk3566_defconfig new file mode 100644 index 00000000000..7606edf393e --- /dev/null +++ b/configs/radxa-zero-3-rk3566_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-radxa-zero-3w" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_RADXA_ZERO_3_RK3566=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-zero-3w.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_POWER=y +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_LIST="rockchip/rk3566-radxa-zero-3w rockchip/rk3566-radxa-zero-3e" +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_ADC=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock-3b-rk3568_defconfig b/configs/rock-3b-rk3568_defconfig new file mode 100644 index 00000000000..937796811a9 --- /dev/null +++ b/configs/rock-3b-rk3568_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-rock-3b" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3b.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_FAN53555=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig new file mode 100644 index 00000000000..f44b202c8c3 --- /dev/null +++ b/configs/rock-3c-rk3566_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-rock-3c" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHY_REALTEK=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig new file mode 100644 index 00000000000..bb9f148692a --- /dev/null +++ b/configs/rock-5-itx-rk3588_defconfig @@ -0,0 +1,111 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-rock-5-itx" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_SPI_IMAGE=y +CONFIG_SPL_SERIAL=y +CONFIG_TARGET_ROCK5B_RK3588=y +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5-itx.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI_PCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_PHYLIB=y +CONFIG_RTL8169=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_ETHER_LAN78XX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index e450a061802..54f7744c989 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -38,10 +38,14 @@ CONFIG_CLK=y # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y diff --git a/configs/rock-s0-rk3308_defconfig b/configs/rock-s0-rk3308_defconfig new file mode 100644 index 00000000000..074ec4cd66b --- /dev/null +++ b/configs/rock-s0-rk3308_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3308-rock-s0" +CONFIG_DM_RESET=y +CONFIG_ROCKCHIP_RK3308=y +CONFIG_TARGET_EVB_RK3308=y +CONFIG_DEBUG_UART_BASE=0xFF0A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +# CONFIG_DEBUG_UART_BOARD_INIT is not set +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-s0.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_ROCKCHIP_IODOMAIN=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PINCTRL=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_LZO=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index fc118cea7ba..80a2f2fed58 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 7e78f1d6491..2bcbdd6b12a 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -6,8 +6,6 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00 CONFIG_ENV_SIZE=0x2000 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="am335x-rut" @@ -90,7 +88,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y # CONFIG_SPL_DM_MMC is not set CONFIG_MMC_OMAP_HS=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index dc5fcdbd1c9..484f9e1bf8d 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -16,6 +16,7 @@ CONFIG_FIT_RSASSA_PSS=y CONFIG_FIT_CIPHER=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTMETH_ANDROID=y +CONFIG_UPL=y CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_MEASURED_BOOT=y CONFIG_BOOTSTAGE=y diff --git a/configs/sandbox_vpl_defconfig b/configs/sandbox_vpl_defconfig index 72483d8ba10..96e9211bd19 100644 --- a/configs/sandbox_vpl_defconfig +++ b/configs/sandbox_vpl_defconfig @@ -27,6 +27,9 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_BEST_MATCH=y CONFIG_SPL_LOAD_FIT=y +CONFIG_UPL=y +CONFIG_UPL_IN=y +CONFIG_SPL_UPL_OUT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y CONFIG_BOOTSTAGE_FDT=y @@ -35,6 +38,7 @@ CONFIG_BOOTSTAGE_STASH_SIZE=0x4096 CONFIG_CONSOLE_RECORD=y CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000 CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BLOBLIST_SIZE=0x5000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 0243b15f31c..06e9b2ae2fa 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -1,43 +1,33 @@ CONFIG_ARM=y -# CONFIG_SYS_THUMB_BUILD is not set CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TEXT_BASE=0x80100000 -CONFIG_SYS_MALLOC_LEN=0x120000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=2 -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 -CONFIG_SPL_TEXT_BASE=0x40200000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_DEFAULT_DEVICE_TREE="ti/omap/omap3-sniper" CONFIG_TARGET_SNIPER=y -CONFIG_SPL_STACK=0x4020fffc -CONFIG_SPL_BSS_START_ADDR=0x80000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="setenv boot_mmc_part ${kernel_mmc_part}; if test reboot-${reboot-mode} = reboot-r; then echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; if test reboot-${reboot-mode} = reboot-b; then echo fastboot; fastboot 0; fi; part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; mmc dev ${boot_mmc_dev}; mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && bootm ${kernel_addr_r};" -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=538 CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SPL_MAX_SIZE=0xec00 -# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y -CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y -CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80208000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=2 # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SYS_PROMPT="sniper # " CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SPL_DM=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_TWL4030_INPUT=y CONFIG_MMC_OMAP_HS=y -CONFIG_CONS_INDEX=3 -CONFIG_OF_LIBFDT=y diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig new file mode 100644 index 00000000000..9915fff4a00 --- /dev/null +++ b/configs/tanix_tx1_defconfig @@ -0,0 +1,25 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h313-tanix-tx1" +CONFIG_SPL=y +CONFIG_DRAM_SUN50I_H616_DX_ODT=0x06060606 +CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0d0d0d0d +CONFIG_DRAM_SUN50I_H616_CA_DRI=0x1919 +CONFIG_DRAM_SUN50I_H616_ODT_EN=0x9988eeee +CONFIG_DRAM_SUN50I_H616_TPR6=0x2fb08080 +CONFIG_DRAM_SUN50I_H616_TPR10=0x402f4469 +CONFIG_DRAM_SUN50I_H616_TPR11=0x0e0f0d0d +CONFIG_DRAM_SUN50I_H616_TPR12=0x11131213 +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_LPDDR3=y +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SLAVE=0x7f +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_AXP313_POWER=y +CONFIG_AXP_DCDC3_VOLT=1200 +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig index 5a190357e45..12a076aeeae 100644 --- a/configs/toybrick-rk3588_defconfig +++ b/configs/toybrick-rk3588_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y -CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-toybrick-x0" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y CONFIG_TARGET_TOYBRICK_RK3588=y @@ -31,7 +31,6 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -# CONFIG_OF_UPSTREAM is not set CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig index 1a1d253c50e..d0c5db65177 100644 --- a/configs/tqma6dl_mba6_mmc_defconfig +++ b/configs/tqma6dl_mba6_mmc_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6DL=y CONFIG_TARGET_TQMA6=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SUPPORT_RAW_INITRD=y @@ -17,6 +17,7 @@ CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run mmcboot; run netboot; run panicboot" CONFIG_DEFAULT_FDT_FILE="imx6dl-mba6x.dtb" CONFIG_SYS_PBSIZE=532 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_CMD_BOOTZ=y @@ -65,5 +66,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index c6a1c7cf3d7..953ceba6626 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6DL=y CONFIG_TARGET_TQMA6=y CONFIG_TQMA6X_SPI_BOOT=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b" CONFIG_ENV_OFFSET_REDUND=0x90000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -69,5 +69,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig index 27f949c6ef6..d6706afe040 100644 --- a/configs/tqma6q_mba6_mmc_defconfig +++ b/configs/tqma6q_mba6_mmc_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6Q=y CONFIG_TARGET_TQMA6=y -CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-mba6b" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SUPPORT_RAW_INITRD=y @@ -65,5 +65,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 5d3ce79c35d..28b1bfc41f4 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6Q=y CONFIG_TARGET_TQMA6=y CONFIG_TQMA6X_SPI_BOOT=y -CONFIG_DEFAULT_DEVICE_TREE="imx6q-mba6b" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6q-mba6b" CONFIG_ENV_OFFSET_REDUND=0x90000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -18,7 +18,7 @@ CONFIG_BOOTDELAY=3 CONFIG_OF_BOARD_SETUP=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="sf probe; run mmcboot; run netboot; run panicboot" -CONFIG_DEFAULT_FDT_FILE="imx6q-mba6x.dtb" +CONFIG_DEFAULT_FDT_FILE="nxp/imx/imx6q-mba6x.dtb" CONFIG_SYS_PBSIZE=532 CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 @@ -69,5 +69,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig index a9ed0d3fc2c..7bed776507a 100644 --- a/configs/tqma6s_mba6_mmc_defconfig +++ b/configs/tqma6s_mba6_mmc_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_MX6S=y CONFIG_TARGET_TQMA6=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SUPPORT_RAW_INITRD=y @@ -65,5 +65,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index 9cd8c3dd20f..0af80d5c2e1 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -9,7 +9,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6S=y CONFIG_TARGET_TQMA6=y CONFIG_TQMA6X_SPI_BOOT=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-mba6b" +CONFIG_DEFAULT_DEVICE_TREE="nxp/imx/imx6dl-mba6b" CONFIG_ENV_OFFSET_REDUND=0x90000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -69,5 +69,8 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_IMX_WATCHDOG=y diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig index af889ec903f..7713454136b 100644 --- a/configs/vf610twr_defconfig +++ b/configs/vf610twr_defconfig @@ -47,7 +47,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VYBRID_GPIO=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig index c50afc4bec1..2cef8988638 100644 --- a/configs/vf610twr_nand_defconfig +++ b/configs/vf610twr_nand_defconfig @@ -48,7 +48,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VYBRID_GPIO=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index c39597cdf52..e5c9c2861e1 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -70,7 +70,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_BOUNCE_BUFFER=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 4b73e1551ce..e7da0de5df1 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -47,7 +47,6 @@ CONFIG_CMD_NAND=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 53ef81e64d4..40a9b16b9cf 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -58,6 +58,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_BOARD=y CONFIG_DTB_RESELECT=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 915f0b993ce..dc1754f6d18 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_SQUASHFS=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_BOARD=y CONFIG_ENV_IS_NOWHERE=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index b2a1f14eb34..f8b6a3f1aa2 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -81,6 +81,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS_SPREAD=y CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_OF_BOARD=y CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0" CONFIG_ENV_IS_NOWHERE=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index 58e88b25fd6..4c66c536d0f 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -81,6 +81,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_BOOTP_MAY_FAIL=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_NFS=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EFIDEBUG=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index fa912ae3bbd..1133134e3fe 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -101,6 +101,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_MTDPARTS_SPREAD=y CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y CONFIG_CMD_UBI=y +CONFIG_MMC_SPEED_MODE_SET=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_BOARD=y diff --git a/disk/part.c b/disk/part.c index bc932526f90..706d77b3194 100644 --- a/disk/part.c +++ b/disk/part.c @@ -285,6 +285,13 @@ void part_init(struct blk_desc *desc) blkcache_invalidate(desc->uclass_id, desc->devnum); + if (desc->part_type != PART_TYPE_UNKNOWN) { + for (entry = drv; entry != drv + n_ents; entry++) { + if (entry->part_type == desc->part_type && !entry->test(desc)) + return; + } + } + desc->part_type = PART_TYPE_UNKNOWN; for (entry = drv; entry != drv + n_ents; entry++) { int ret; @@ -304,7 +311,8 @@ static void print_part_header(const char *type, struct blk_desc *desc) CONFIG_IS_ENABLED(DOS_PARTITION) || \ CONFIG_IS_ENABLED(ISO_PARTITION) || \ CONFIG_IS_ENABLED(AMIGA_PARTITION) || \ - CONFIG_IS_ENABLED(EFI_PARTITION) + CONFIG_IS_ENABLED(EFI_PARTITION) || \ + CONFIG_IS_ENABLED(MTD_PARTITIONS) printf("\nPartition Map for %s device %d -- Partition Type: %s\n\n", uclass_get_name(desc->uclass_id), desc->devnum, type); #endif /* any CONFIG_..._PARTITION */ diff --git a/doc/I2C_Edge_Conditions b/doc/I2C_Edge_Conditions index f4a99687011..9ccb21c5092 100644 --- a/doc/I2C_Edge_Conditions +++ b/doc/I2C_Edge_Conditions @@ -31,12 +31,10 @@ Notes !!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!! This reset edge condition could possibly be present in every I2C -controller and device available. For boards where a I2C bus reset -function can be implemented a i2c_init_board() function should be -provided and enabled by #define'ing CONFIG_SYS_I2C_INIT_BOARD in your -board's config file. Note that this is NOT necessary when using the -bit-banging I2C driver (common/soft_i2c.c) as this already includes -the I2C bus reset sequence. +controller and device available. + +Note that this problem does not happen when using the bit-banging I2C driver +(common/soft_i2c.c) as this already includes the I2C bus reset sequence. Many thanks to Bill Hunter for finding this serious BUG. diff --git a/doc/board/beagle/am62x_beagleplay.rst b/doc/board/beagle/am62x_beagleplay.rst index 01f04beb55a..bc71aabaac3 100644 --- a/doc/board/beagle/am62x_beagleplay.rst +++ b/doc/board/beagle/am62x_beagleplay.rst @@ -23,7 +23,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: ../ti/img/boot_diagram_k3_current.svg +.. image:: ../ti/img/boot_diagram_am62.svg :alt: Boot flow diagram - On this platform, 'TI Foundational Security' (TIFS) functions as the @@ -38,6 +38,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_tifsstub + Build procedure: ---------------- 0. Setup the environment variables: @@ -86,7 +90,7 @@ Image formats - tispl.bin -.. image:: ../ti/img/dm_tispl.bin.svg +.. image:: ../ti/img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format Additional hardware for U-Boot development diff --git a/doc/board/beagle/j721e_beagleboneai64.rst b/doc/board/beagle/j721e_beagleboneai64.rst index d6b9c8ca606..090b2b3b86a 100644 --- a/doc/board/beagle/j721e_beagleboneai64.rst +++ b/doc/board/beagle/j721e_beagleboneai64.rst @@ -42,6 +42,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_boot_firmwares + Build procedure: ---------------- 0. Setup the environment variables: diff --git a/doc/board/nxp/imx8ulp_evk.rst b/doc/board/nxp/imx8ulp_evk.rst new file mode 100644 index 00000000000..a9f5546311d --- /dev/null +++ b/doc/board/nxp/imx8ulp_evk.rst @@ -0,0 +1,79 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx8ulp_evk +======================= + +U-Boot for the NXP i.MX 8ULP EVK board + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the uPower firmware +- Get the M33 firmware +- Get ahab-container.img +- Build U-Boot +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.10 + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx8ulp bl31 + $ cp build/imx8ulp/release/bl31.bin $(srctree) + +Get the uPower firmware +----------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-upower-1.3.1.bin + $ chmod +x firmware-upower-1.3.1.bin + $ ./firmware-upower-1.3.1.bin + $ cp firmware-upower-1.3.1/upower_a1.bin $(srctree)/upower.bin + +Get the M33 firmware +-------------------- + +.. code-block:: bash + + $ wget http://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx8ulp-m33-demo-2.14.1.bin + $ chmod +x imx8ulp-m33-demo-2.14.1.bin + $ ./imx8ulp-m33-demo-2.14.1.bin + $ cp imx8ulp-m33-demo-2.14.1/imx8ulp_m33_TCM_power_mode_switch.bin $(srctree)/m33_image.bin + +Get ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-0.1.2-4ed450a.bin + $ chmod +x firmware-ele-imx-0.1.2-4ed450a.bin + $ ./firmware-ele-imx-0.1.2-4ed450a.bin + $ cp firmware-ele-imx-0.1.2-4ed450a/mx8ulpa2-ahab-container.img $(srctree) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx8ulp_evk_defconfig + $ make + +Burn the flash.bin to MicroSD card offset 32KB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc + +Boot +---- + +Set Boot switch to SD boot diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 94687730544..5f1e878508e 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -11,6 +11,7 @@ NXP Semiconductors imx8mp_evk imx8mq_evk imx8qxp_mek + imx8ulp_evk imx93_11x11_evk imxrt1020-evk imxrt1050-evk diff --git a/doc/board/phytec/phycore-am62x.rst b/doc/board/phytec/phycore-am62x.rst index a7ce2c58825..56c1fd8354b 100644 --- a/doc/board/phytec/phycore-am62x.rst +++ b/doc/board/phytec/phycore-am62x.rst @@ -30,6 +30,10 @@ Sources :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_tifsstub + Build procedure --------------- diff --git a/doc/board/phytec/phycore-am64x.rst b/doc/board/phytec/phycore-am64x.rst index 68d78ad7c25..01c42b90660 100644 --- a/doc/board/phytec/phycore-am64x.rst +++ b/doc/board/phytec/phycore-am64x.rst @@ -30,6 +30,10 @@ Sources :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares_sysfw + :end-before: .. k3_rst_include_end_boot_firmwares_sysfw + Build procedure --------------- diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index bedc52e03e2..0f9cb404d93 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -54,6 +54,7 @@ List of mainline supported Rockchip boards: - Amarula Vyasa-RK3288 (vyasa-rk3288) * rk3308 - Radxa ROCK Pi S (rock-pi-s-rk3308) + - Radxa ROCK S0 (rock-s0-rk3308) - Rockchip Evb-RK3308 (evb-rk3308) - Roc-cc-RK3308 (roc-cc-rk3308) * rk3326 @@ -105,6 +106,9 @@ List of mainline supported Rockchip boards: - Pine64 SOQuartz on Model A (soquartz-model-a-rk3566) - Powkiddy X55 (powkiddy-x55-rk3566) - Radxa CM3 IO Board (radxa-cm3-io-rk3566) + - Radxa ROCK 3C (rock-3c-rk3566) + - Radxa ZERO 3W/3E (radxa-zero-3-rk3566) + - Xunlong Orange Pi 3B (orangepi-3b-rk3566) * rk3568 - Rockchip Evb-RK3568 (evb-rk3568) @@ -115,19 +119,22 @@ List of mainline supported Rockchip boards: - Generic RK3566/RK3568 (generic-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) - Radxa E25 Carrier Board (radxa-e25-rk3568) - - Radxa ROCK 3 Model A (rock-3a-rk3568) + - Radxa ROCK 3A (rock-3a-rk3568) + - Radxa ROCK 3B (rock-3b-rk3568) * rk3588 - ArmSoM Sige7 (sige7-rk3588) - Rockchip EVB (evb-rk3588) - Edgeble Neural Compute Module 6A SoM - Neu6a (neu6a-io-rk3588) - Edgeble Neural Compute Module 6B SoM - Neu6b (neu6b-io-rk3588) + - FriendlyElec CM3588 NAS (cm3588-nas-rk3588) - FriendlyElec NanoPC-T6 (nanopc-t6-rk3588) - FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s) - FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s) - Generic RK3588S/RK3588 (generic-rk3588) - Indiedroid Nova (nova-rk3588s) - Pine64 QuartzPro64 (quartzpro64-rk3588) + - Radxa ROCK 5 ITX (rock-5-itx-rk3588) - Radxa ROCK 5A (rock5a-rk3588s) - Radxa ROCK 5B (rock5b-rk3588) - Rockchip Toybrick TB-RK3588X (toybrick-rk3588) diff --git a/doc/board/ti/am62ax_sk.rst b/doc/board/ti/am62ax_sk.rst index 60726b6652c..262340ef59a 100644 --- a/doc/board/ti/am62ax_sk.rst +++ b/doc/board/ti/am62ax_sk.rst @@ -47,7 +47,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -60,6 +60,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_tifsstub + Build procedure: ---------------- 0. Setup the environment variables: @@ -144,7 +148,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format Switch Setting for Boot Mode diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst index c80b5068117..99bdc034869 100644 --- a/doc/board/ti/am62px_sk.rst +++ b/doc/board/ti/am62px_sk.rst @@ -55,7 +55,7 @@ Boot Flow: The bootflow is exactly the same as all SoCs in the am62xxx extended SoC family. Below is the pictorial representation: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -68,6 +68,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_tifsstub + Build procedure: ---------------- @@ -153,7 +157,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format OSPI: diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index 2a25e84f6c9..b9d35244d44 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -46,7 +46,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. image:: img/boot_diagram_k3_current.svg +.. image:: img/boot_diagram_am62.svg :alt: Boot flow diagram - Here TIFS acts as master and provides all the critical services. R5/A53 @@ -59,6 +59,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_tifsstub + Build procedure: ---------------- 0. Setup the environment variables: @@ -161,7 +165,7 @@ Image formats: - tispl.bin -.. image:: img/dm_tispl.bin.svg +.. image:: img/tifsstub_dm_tispl.bin.svg :alt: tispl.bin image format OSPI: diff --git a/doc/board/ti/am64x_evm.rst b/doc/board/ti/am64x_evm.rst index 88997b6a283..65c4c456528 100644 --- a/doc/board/ti/am64x_evm.rst +++ b/doc/board/ti/am64x_evm.rst @@ -48,6 +48,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares_sysfw + :end-before: .. k3_rst_include_end_boot_firmwares_sysfw + Build procedure: ---------------- 0. Setup the environment variables: diff --git a/doc/board/ti/am65x_evm.rst b/doc/board/ti/am65x_evm.rst index 89011c08dd4..60b08ceebf0 100644 --- a/doc/board/ti/am65x_evm.rst +++ b/doc/board/ti/am65x_evm.rst @@ -58,6 +58,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares_sysfw + :end-before: .. k3_rst_include_end_boot_firmwares_sysfw + Build procedure: ---------------- 0. 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text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 104px; height: 1px; padding-top: 321px; margin-left: 303px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Cortex-R SPL</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="355" + y="325" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text30">Cortex-R SPL</text> + </switch> + </g> + <rect + x="308.75" + y="190" + width="90" + height="40" + rx="6" + ry="6" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect36" /> + <g + transform="translate(-0.5 -0.5)" + id="g42"> + <switch + id="switch40"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 88px; height: 1px; padding-top: 210px; margin-left: 310px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load and auth tiboot3.bin</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="354" + y="214" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text38">Load and auth t...</text> + </switch> + </g> + <rect + x="309" + y="262" + width="90" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect44" /> + <g + transform="translate(-0.5 -0.5)" + id="g50"> + <switch + id="switch48"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 88px; height: 1px; padding-top: 278px; margin-left: 310px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load system<xhtml:br /> +config data</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="354" + y="282" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text46">Load system...</text> + </switch> + </g> + <rect + x="310" + y="336" + width="90" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect52" /> + <g + transform="translate(-0.5 -0.5)" + id="g58"> + <switch + id="switch56"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 88px; height: 1px; padding-top: 352px; margin-left: 311px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">DDR Config</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="355" + y="356" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text54">DDR Config</text> + </switch> + </g> + <rect + x="310" + y="368" + width="90" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect60" /> + <g + transform="translate(-0.5 -0.5)" + id="g66"> + <switch + id="switch64"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 88px; height: 1px; padding-top: 384px; margin-left: 311px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load tispl.bin</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="355" + y="388" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text62">Load tispl.bin</text> + </switch> + </g> + <rect + x="310" + y="440" + width="90" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect68" /> + <g + transform="translate(-0.5 -0.5)" + id="g74"> + <switch + id="switch72"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 88px; height: 1px; padding-top: 456px; margin-left: 311px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Start Cortex-A</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="355" + y="460" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text70">Start Cortex-A</text> + </switch> + </g> + <rect + x="310" + y="472" + width="90" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect76" /> + <g + transform="translate(-0.5 -0.5)" + id="g82"> + <switch + id="switch80"> + <foreignObject + style="overflow: visible; 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text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 70px; height: 1px; padding-top: 550px; margin-left: 303px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Device Mgr</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="338" + y="554" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text92">Device Mgr</text> + </switch> + </g> + <path + d="M 299 456 L 139.37 456" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path98" /> + <path + d="M 134.12 456 L 141.12 452.5 L 139.37 456 L 141.12 459.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path100" /> + <g + transform="translate(-0.5 -0.5)" + id="g106"> + <switch + id="switch104"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 440px; margin-left: 257px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Start Cortex-A</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="257" + y="443" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + text-anchor="middle" + id="text102">Start Cort...</text> + </switch> + </g> + <path + d="M 481 711 L 139.37 711" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path108" /> + <path + d="M 134.12 711 L 141.12 707.5 L 139.37 711 L 141.12 714.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path110" /> + <path + d="M 482 692 L 317.37 691.04" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path112" /> + <path + d="M 312.12 691.01 L 319.14 687.55 L 317.37 691.04 L 319.1 694.55 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path114" /> + <path + d="M 482 799 L 317.37 798.04" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path116" /> + <path + d="M 312.12 798.01 L 319.14 794.55 L 317.37 798.04 L 319.1 801.55 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path118" /> + <path + d="M 481 791 L 139.37 791" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path120" /> + <path + d="M 134.12 791 L 141.12 787.5 L 139.37 791 L 141.12 794.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path122" /> + <path + d="M 481 890 L 315.37 890.96" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path124" /> + <path + d="M 310.12 890.99 L 317.1 887.45 L 315.37 890.96 L 317.14 894.45 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path126" /> + <path + d="M 481 879 L 139.37 881.95" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path128" /> + <path + d="M 134.12 881.99 L 141.09 878.43 L 139.37 881.95 L 141.15 885.43 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path130" /> + <rect + x="302" + y="580" + width="71.5" + height="30" + fill="#e1d5e7" + stroke="#9673a6" + pointer-events="all" + id="rect132" /> + <g + transform="translate(-0.5 -0.5)" + id="g138"> + <switch + id="switch136"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 70px; height: 1px; padding-top: 595px; margin-left: 303px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load TIFS Stub in TCM</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="338" + y="599" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text134">Load TIFS St...</text> + </switch> + </g> + <path + d="M 482 640 L 315.37 640" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path140" /> + <path + d="M 310.12 640 L 317.12 636.5 L 315.37 640 L 317.12 643.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path142" /> + <rect + x="437" + y="50" + width="116.5" + height="40" + rx="6" + ry="6" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect144" /> + <path + d="M 495.25 90 L 495.25 820" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + stroke-dasharray="3 3" + pointer-events="all" + id="path146" /> + <g + transform="translate(-0.5 -0.5)" + id="g152"> + <switch + id="switch150"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 115px; height: 1px; padding-top: 70px; margin-left: 438px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Verdana; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Cortex-A</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="495" + y="74" + fill="rgb(0, 0, 0)" + font-family="Verdana" + font-size="12px" + text-anchor="middle" + id="text148">Cortex-A</text> + </switch> + </g> + <rect + x="482" + y="510" + width="10" + height="70" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect154" /> + <path + d="M 482 565 L 139.37 565" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path156" /> + <path + d="M 134.12 565 L 141.12 561.5 L 139.37 565 L 141.12 568.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path158" /> + <path + d="M 482 614.97 L 140.37 614.67" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path160" /> + <path + d="M 135.12 614.66 L 142.12 611.17 L 140.37 614.67 L 142.11 618.17 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path162" /> + <rect + x="482" + y="600" + width="71.5" + height="30" + fill="#d5e8d4" + stroke="#82b366" + pointer-events="all" + id="rect164" /> + <g + transform="translate(-0.5 -0.5)" + id="g170"> + <switch + id="switch168"> + <foreignObject + style="overflow: visible; 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text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 115px; height: 1px; padding-top: 70px; margin-left: 578px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Verdana; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Cortex-R/M<xhtml:br /> +C6x/C7x</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="635" + y="74" + fill="rgb(0, 0, 0)" + font-family="Verdana" + font-size="12px" + text-anchor="middle" + id="text176">Cortex-R/M...</text> + </switch> + </g> + <rect + x="631" + y="910" + width="10" + height="38" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect182" /> + <rect + x="633" + y="912" + width="71.5" + height="30" + fill="#e1d5e7" + stroke="#9673a6" + pointer-events="all" + id="rect184" /> + <g + transform="translate(-0.5 -0.5)" + id="g190"> + <switch + id="switch188"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 70px; height: 1px; padding-top: 927px; margin-left: 634px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Aux f/w</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="669" + y="931" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text186">Aux f/w</text> + </switch> + </g> + <rect + x="77" + y="50" + width="100" + height="40" + rx="6" + ry="6" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect192" /> + <path + d="M 127 90 L 127 940" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + stroke-dasharray="3 3" + pointer-events="all" + id="path194" /> + <g + transform="translate(-0.5 -0.5)" + id="g200"> + <switch + id="switch198"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 70px; margin-left: 78px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Verdana; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">TIFS/DMSC</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="127" + y="74" + fill="rgb(0, 0, 0)" + font-family="Verdana" + font-size="12px" + text-anchor="middle" + id="text196">TIFS/DMSC</text> + </switch> + </g> + <rect + x="122" + y="130" + width="10" + height="110" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect202" /> + <rect + x="79" + y="132" + width="50" + height="30" + fill="#ffe6cc" + stroke="#d79b00" + pointer-events="all" + id="rect204" /> + <g + transform="translate(-0.5 -0.5)" + id="g210"> + <switch + id="switch208"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 48px; height: 1px; padding-top: 147px; margin-left: 80px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">ROM</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="104" + y="151" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text206">ROM</text> + </switch> + </g> + <rect + x="122" + y="253" + width="10" + height="687" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect212" /> + <path + d="M 297 238 L 138.37 238" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path214" /> + <path + d="M 133.12 238 L 140.12 234.5 L 138.37 238 L 140.12 241.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path216" /> + <g + transform="translate(-0.5 -0.5)" + id="g222"> + <switch + id="switch220"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 230px; margin-left: 267px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Start TIFS</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="267" + y="233" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + text-anchor="middle" + id="text218">Start TIFS</text> + </switch> + </g> + <rect + x="80" + y="255" + width="50" + height="30" + fill="#f8cecc" + stroke="#b85450" + pointer-events="all" + id="rect224" /> + <g + transform="translate(-0.5 -0.5)" + id="g230"> + <switch + id="switch228"> + <foreignObject + style="overflow: visible; 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text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe flex-start; justify-content: unsafe center; width: 128px; height: 1px; padding-top: 1px; margin-left: 63px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Verdana; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Security Enclave Boot Processor</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="127" + y="13" + fill="rgb(0, 0, 0)" + font-family="Verdana" + font-size="12px" + text-anchor="middle" + id="text236">Security Enclave Boot...</text> + </switch> + </g> + <path + d="M 241 0 L 361 0 L 375 14 L 375 35 L 241 35 L 241 0 Z" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path242" /> + <path + d="M 361 0 L 361 14 L 375 14" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path244" /> + <g + transform="translate(-0.5 -0.5)" + id="g250"> + <switch + id="switch248"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe flex-start; justify-content: unsafe center; width: 132px; height: 1px; padding-top: 1px; margin-left: 242px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Verdana; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Boot Loader <xhtml:br /> +Processor</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="308" + y="13" + fill="rgb(0, 0, 0)" + font-family="Verdana" + font-size="12px" + text-anchor="middle" + id="text246">Boot Loader...</text> + </switch> + </g> + <path + d="M 437 0 L 523 0 L 537 14 L 537 35 L 437 35 L 437 0 Z" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path252" /> + <path + d="M 523 0 L 523 14 L 537 14" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path254" /> + <g + transform="translate(-0.5 -0.5)" + id="g260"> + <switch + id="switch258"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe flex-start; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 1px; margin-left: 438px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Verdana; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Main CPU</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="487" + y="13" + fill="rgb(0, 0, 0)" + font-family="Verdana" + font-size="12px" + text-anchor="middle" + id="text256">Main CPU</text> + </switch> + </g> + <path + d="M 577 0 L 663 0 L 677 14 L 677 35 L 577 35 L 577 0 Z" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path262" /> + <path + d="M 663 0 L 663 14 L 677 14" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path264" /> + <g + transform="translate(-0.5 -0.5)" + id="g270"> + <switch + id="switch268"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe flex-start; justify-content: unsafe center; width: 98px; height: 1px; padding-top: 1px; margin-left: 578px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Verdana; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Auxiliary<xhtml:br /> +Processor</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="627" + y="13" + fill="rgb(0, 0, 0)" + font-family="Verdana" + font-size="12px" + text-anchor="middle" + id="text266">Auxiliary...</text> + </switch> + </g> + <path + d="M 7 120 L 120.63 120" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + stroke-dasharray="12 12" + pointer-events="stroke" + id="path272" /> + <path + d="M 125.88 120 L 118.88 123.5 L 120.63 120 L 118.88 116.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path274" /> + <g + transform="translate(-0.5 -0.5)" + id="g280"> + <switch + id="switch278"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe flex-end; justify-content: unsafe flex-start; width: 1px; height: 1px; padding-top: 118px; margin-left: 9px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: left;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">H/w Seq: Reset rls</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="9" + y="118" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + id="text276">H/w Seq: Reset rls</text> + </switch> + </g> + <path + d="M 298 200 L 138.37 199.98" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path282" /> + <path + d="M 133.12 199.98 L 140.12 196.48 L 138.37 199.98 L 140.12 203.48 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path284" /> + <g + transform="translate(-0.5 -0.5)" + id="g290"> + <switch + id="switch288"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 190px; margin-left: 257px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Auth tiboot3.bin</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="257" + y="193" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + text-anchor="middle" + id="text286">Auth tiboo...</text> + </switch> + </g> + <path + d="M 133 159 L 301.01 159" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path292" /> + <path + d="M 306.26 159 L 299.26 162.5 L 301.01 159 L 299.26 155.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path294" /> + <g + transform="translate(-0.5 -0.5)" + id="g300"> + <switch + id="switch298"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 150px; margin-left: 178px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Release Reset</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="178" + y="153" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + text-anchor="middle" + id="text296">Release Re...</text> + </switch> + </g> + <path + d="M 299 281.94 L 139.37 281.04" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path302" /> + <path + d="M 134.12 281.01 L 141.14 277.55 L 139.37 281.04 L 141.1 284.55 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path304" /> + <g + transform="translate(-0.5 -0.5)" + id="g310"> + <switch + id="switch308"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 270px; margin-left: 237px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Load system config data</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="237" + y="273" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + text-anchor="middle" + id="text306">Load syste...</text> + </switch> + </g> + <rect + x="308.75" + y="230" + width="90" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect312" /> + <g + transform="translate(-0.5 -0.5)" + id="g318"> + <switch + id="switch316"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 88px; height: 1px; padding-top: 246px; margin-left: 310px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Start TIFS</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="354" + y="250" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text314">Start TIFS</text> + </switch> + </g> + <rect + x="310" + y="400" + width="90" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect320" /> + <g + transform="translate(-0.5 -0.5)" + id="g326"> + <switch + id="switch324"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 88px; height: 1px; padding-top: 416px; margin-left: 311px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load DM f/w</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="355" + y="420" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text322">Load DM f/w</text> + </switch> + </g> + <path + d="M 303 510 L 333 510 L 333 530 L 309.12 530" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path328" /> + <path + d="M 302.12 530 L 309.12 526.5 L 309.12 533.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path330" /> + <g + transform="translate(-0.5 -0.5)" + id="g336"> + <switch + id="switch334"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe flex-start; width: 1px; height: 1px; padding-top: 521px; margin-left: 337px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: left;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">branch</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="337" + y="524" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + id="text332">branch</text> + </switch> + </g> + <path + d="M 133 511 L 137 511 L 476.63 511" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path338" /> + <path + d="M 481.88 511 L 474.88 514.5 L 476.63 511 L 474.88 507.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path340" /> + <g + transform="translate(-0.5 -0.5)" + id="g346"> + <switch + id="switch344"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 500px; margin-left: 177px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Release Reset</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="177" + y="503" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + text-anchor="middle" + id="text342">Release Re...</text> + </switch> + </g> + <rect + x="484" + y="513" + width="71.5" + height="30" + fill="#d5e8d4" + stroke="#82b366" + pointer-events="all" + id="rect348" /> + <g + transform="translate(-0.5 -0.5)" + id="g354"> + <switch + id="switch352"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 70px; height: 1px; padding-top: 528px; margin-left: 485px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">TF-A </xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="520" + y="532" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text350">TF-A </text> + </switch> + </g> + <rect + x="482" + y="662" + width="10" + height="78" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect356" /> + <rect + x="484" + y="665" + width="83" + height="30" + fill="#d5e8d4" + stroke="#82b366" + pointer-events="all" + id="rect358" /> + <g + transform="translate(-0.5 -0.5)" + id="g364"> + <switch + id="switch362"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 81px; height: 1px; padding-top: 680px; margin-left: 485px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Cortex-A SPL</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="526" + y="684" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text360">Cortex-A SPL</text> + </switch> + </g> + <rect + x="482" + y="748" + width="10" + height="192" + fill="rgb(255, 255, 255)" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect366" /> + <rect + x="484" + y="751" + width="83" + height="30" + fill="#d5e8d4" + stroke="#82b366" + pointer-events="all" + id="rect368" /> + <g + transform="translate(-0.5 -0.5)" + id="g374"> + <switch + id="switch372"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 81px; height: 1px; padding-top: 766px; margin-left: 485px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">U-Boot</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="526" + y="770" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text370">U-Boot</text> + </switch> + </g> + <rect + x="492" + y="700" + width="103" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect376" /> + <g + transform="translate(-0.5 -0.5)" + id="g382"> + <switch + id="switch380"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 101px; height: 1px; padding-top: 716px; margin-left: 493px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load u-boot.img</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="544" + y="720" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text378">Load u-boot.img</text> + </switch> + </g> + <rect + x="492" + y="820" + width="103" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect384" /> + <g + transform="translate(-0.5 -0.5)" + id="g390"> + <switch + id="switch388"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 101px; height: 1px; padding-top: 836px; margin-left: 493px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Load Aux core f/w<xhtml:br /> +(optional)</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="544" + y="840" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text386">Load Aux core f/w...</text> + </switch> + </g> + <rect + x="492" + y="860" + width="103" + height="32" + rx="4.8" + ry="4.8" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect392" /> + <g + transform="translate(-0.5 -0.5)" + id="g398"> + <switch + id="switch396"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 101px; height: 1px; padding-top: 876px; margin-left: 493px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Start Aux core<xhtml:br /> +(optional)</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="544" + y="880" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text394">Start Aux core...</text> + </switch> + </g> + <path + d="M 311 909 L 628.38 909" + fill="none" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="stroke" + id="path400" /> + <path + d="M 633.63 909 L 626.63 912.5 L 628.38 909 L 626.63 905.5 Z" + fill="rgb(0, 0, 0)" + stroke="rgb(0, 0, 0)" + stroke-miterlimit="10" + pointer-events="all" + id="path402" /> + <g + transform="translate(-0.5 -0.5)" + id="g408"> + <switch + id="switch406"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 1px; height: 1px; padding-top: 900px; margin-left: 357px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); background-color: rgb(255, 255, 255); "> + <xhtml:div + style="display: inline-block; font-size: 11px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; background-color: rgb(255, 255, 255); white-space: nowrap;">Release Reset</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="357" + y="903" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="11px" + text-anchor="middle" + id="text404">Release Re...</text> + </switch> + </g> + </g> + <switch + id="switch418"> + <g + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" + id="g412" /> + <a + transform="translate(0,-5)" + xlink:href="https://www.drawio.com/doc/faq/svg-export-text-problems" + target="_blank" + id="a416"> + <text + text-anchor="middle" + font-size="10px" + x="50%" + y="100%" + id="text414">Text is not SVG - cannot display</text> + </a> + </switch> +</svg> diff --git a/doc/board/ti/img/tifsstub_dm_tispl.bin.svg b/doc/board/ti/img/tifsstub_dm_tispl.bin.svg new file mode 100644 index 00000000000..5d56d81f667 --- /dev/null +++ b/doc/board/ti/img/tifsstub_dm_tispl.bin.svg @@ -0,0 +1,353 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!-- SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause --> + +<!-- Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ --> + +<svg + version="1.1" + width="231px" + height="351px" + viewBox="-0.5 -0.5 231 351" + id="svg72" + sodipodi:docname="tifsstub_dm_tispl.bin.svg" + inkscape:version="1.1.2 (0a00cf5339, 2022-02-04)" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns:xlink="http://www.w3.org/1999/xlink" + xmlns="http://www.w3.org/2000/svg" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:xhtml="http://www.w3.org/1999/xhtml"> + <sodipodi:namedview + id="namedview74" + pagecolor="#ffffff" + bordercolor="#666666" + borderopacity="1.0" + inkscape:pageshadow="2" + inkscape:pageopacity="0.0" + inkscape:pagecheckerboard="0" + showgrid="false" + inkscape:zoom="2.3561254" + inkscape:cx="115.65599" + inkscape:cy="276.72551" + inkscape:window-width="1920" + inkscape:window-height="1008" + inkscape:window-x="0" + inkscape:window-y="0" + inkscape:window-maximized="1" + inkscape:current-layer="svg72" /> + <defs + id="defs2" /> + <g + id="g62"> + <rect + x="0" + y="0" + width="230" + height="350" + rx="34.5" + ry="34.5" + fill="#d5e8d4" + stroke="#82b366" + pointer-events="all" + id="rect4" /> + <rect + x="40" + y="30" + width="160" + height="60" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect6" /> + <g + transform="translate(-0.5 -0.5)" + id="g12"> + <switch + id="switch10"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 60px; margin-left: 41px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">FIT Header</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="120" + y="64" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text8">FIT Header</text> + </switch> + </g> + <rect + x="40" + y="160" + width="160" + height="50" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect14" /> + <g + transform="translate(-0.5 -0.5)" + id="g20"> + <switch + id="switch18"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 185px; margin-left: 41px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">TIFS Stub<xhtml:br /> +(GP, HS-FS, HS-SE)</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="120" + y="189" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text16">TIFS Stub...</text> + </switch> + </g> + <rect + x="40" + y="90" + width="160" + height="30" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect22" /> + <g + transform="translate(-0.5 -0.5)" + id="g28"> + <switch + id="switch26"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 105px; margin-left: 41px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">TF-A</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="120" + y="109" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text24">TF-A</text> + </switch> + </g> + <rect + x="40" + y="120" + width="160" + height="40" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect30" /> + <g + transform="translate(-0.5 -0.5)" + id="g36"> + <switch + id="switch34"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 140px; margin-left: 41px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">OP-TEE</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="120" + y="144" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text32">OP-TEE</text> + </switch> + </g> + <rect + x="40" + y="210" + width="160" + height="40" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect38" /> + <g + transform="translate(-0.5 -0.5)" + id="g44"> + <switch + id="switch42"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 230px; margin-left: 41px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">R5 DM FW</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="120" + y="234" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text40">R5 DM FW</text> + </switch> + </g> + <rect + x="40" + y="250" + width="160" + height="40" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect46" /> + <g + transform="translate(-0.5 -0.5)" + id="g52"> + <switch + id="switch50"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 270px; margin-left: 41px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">Cortex-A SPL</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="120" + y="274" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text48">Cortex-A SPL</text> + </switch> + </g> + <rect + x="40" + y="290" + width="160" + height="40" + fill="none" + stroke="rgb(0, 0, 0)" + pointer-events="all" + id="rect54" /> + <g + transform="translate(-0.5 -0.5)" + id="g60"> + <switch + id="switch58"> + <foreignObject + style="overflow: visible; text-align: left;" + pointer-events="none" + width="100%" + height="100%" + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility"> + <xhtml:div + style="display: flex; align-items: unsafe center; justify-content: unsafe center; width: 158px; height: 1px; padding-top: 310px; margin-left: 41px;"> + <xhtml:div + style="box-sizing: border-box; font-size: 0px; text-align: center;" + data-drawio-colors="color: rgb(0, 0, 0); "> + <xhtml:div + style="display: inline-block; font-size: 12px; font-family: Helvetica; color: rgb(0, 0, 0); line-height: 1.2; pointer-events: all; white-space: normal; overflow-wrap: normal;">SPL DTB 1..N</xhtml:div> + </xhtml:div> + </xhtml:div> + </foreignObject> + <text + x="120" + y="314" + fill="rgb(0, 0, 0)" + font-family="Helvetica" + font-size="12px" + text-anchor="middle" + id="text56">SPL DTB 1..N</text> + </switch> + </g> + </g> + <switch + id="switch70"> + <g + requiredFeatures="http://www.w3.org/TR/SVG11/feature#Extensibility" + id="g64" /> + <a + transform="translate(0,-5)" + xlink:href="https://www.drawio.com/doc/faq/svg-export-text-problems" + target="_blank" + id="a68"> + <text + text-anchor="middle" + font-size="10px" + x="50%" + y="100%" + id="text66">Text is not SVG - cannot display</text> + </a> + </switch> +</svg> diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst index d4a823fa26c..4fd2aff8354 100644 --- a/doc/board/ti/j7200_evm.rst +++ b/doc/board/ti/j7200_evm.rst @@ -47,6 +47,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_boot_firmwares + Build procedure: ---------------- 0. Setup the environment variables: diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index 80d91cafab0..41c8d4c72a8 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -52,6 +52,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_boot_firmwares + Build procedure: ---------------- 0. Setup the environment variables: diff --git a/doc/board/ti/j721s2_evm.rst b/doc/board/ti/j721s2_evm.rst index f5c48c96a83..21683b90b1a 100644 --- a/doc/board/ti/j721s2_evm.rst +++ b/doc/board/ti/j721s2_evm.rst @@ -60,6 +60,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_boot_firmwares + Build procedure: ---------------- diff --git a/doc/board/ti/j722s_evm.rst b/doc/board/ti/j722s_evm.rst index 10b243908a1..e5a1be50c4f 100644 --- a/doc/board/ti/j722s_evm.rst +++ b/doc/board/ti/j722s_evm.rst @@ -45,6 +45,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_boot_firmwares + Build procedure: ---------------- diff --git a/doc/board/ti/j784s4_evm.rst b/doc/board/ti/j784s4_evm.rst index 2ffec3dbd3b..a1e927cb743 100644 --- a/doc/board/ti/j784s4_evm.rst +++ b/doc/board/ti/j784s4_evm.rst @@ -60,6 +60,10 @@ Sources :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_boot_firmwares + Build procedure --------------- 0. Setup the environment variables: diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 67b066a07d3..c3513f0aee2 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -182,24 +182,43 @@ online .. note:: - The TI Firmware required for functionality of the system can be - one of the following combination (see platform specific boot diagram for - further information as to which component runs on which processor): + The TI Firmwares required for functionality of the system are (see + platform specific boot diagram for further information as to which + component runs on which processor): - * **TIFS** - TI Foundational Security Firmware - Consists of purely firmware - meant to run on the security enclave. - * **DM** - Device Management firmware also called TI System Control Interface - server (TISCI Server) - This component purely plays the role of managing - device resources such as power, clock, interrupts, dma etc. This firmware - runs on a dedicated or multi-use microcontroller outside the security - enclave. +.. k3_rst_include_end_boot_sources - OR +.. k3_rst_include_start_boot_firmwares - * **SYSFW** - System firmware - consists of both TIFS and DM both running on - the security enclave. +* **TIFS** - TI Foundational Security Firmware - Consists of purely firmware + meant to run on the security enclave. +* **DM** - Device Management firmware also called TI System Control Interface + server (TISCI Server) - This component purely plays the role of managing + device resources such as power, clock, interrupts, dma etc. This firmware + runs on a dedicated or multi-use microcontroller outside the security + enclave. -.. k3_rst_include_end_boot_sources +.. k3_rst_include_end_boot_firmwares +.. k3_rst_include_start_tifsstub + +* **TIFS Stub** - The TIFS stub is a small piece of binary designed to help + restore the required security context and resume the TIFS firmware when + the system resumes from low-power modes such as suspend-to-RAM/Deep + Sleep. This stub uses the same encryption and customer key signing model + as TIFS and is loaded into the ATCM (Tightly Coupled Memory 'A' of the + DM R5) during DM startup. Due to the independent certificate signing + process, the stub is maintained separately from DM. + +.. k3_rst_include_end_tifsstub + +OR + +.. k3_rst_include_start_boot_firmwares_sysfw + +* **SYSFW** - System firmware - consists of both TIFS and DM both running on + the security enclave. + +.. k3_rst_include_end_boot_firmwares_sysfw Build Procedure --------------- diff --git a/doc/board/toradex/verdin-am62.rst b/doc/board/toradex/verdin-am62.rst index e8d90273288..93912adc896 100644 --- a/doc/board/toradex/verdin-am62.rst +++ b/doc/board/toradex/verdin-am62.rst @@ -29,6 +29,10 @@ Sources: :start-after: .. k3_rst_include_start_boot_sources :end-before: .. k3_rst_include_end_boot_sources +.. include:: ../ti/k3.rst + :start-after: .. k3_rst_include_start_boot_firmwares + :end-before: .. k3_rst_include_end_tifsstub + Build procedure: ---------------- diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 776af601e20..72863756a42 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -71,7 +71,7 @@ For the next scheduled release, release candidates were made on:: * U-Boot v2024.10-rc2 was released on Mon 05 August 2024. -.. * U-Boot v2024.10-rc3 was released on Mon 19 August 2024. +* U-Boot v2024.10-rc3 was released on Mon 19 August 2024. .. * U-Boot v2024.10-rc4 was released on Mon 02 September 2024. diff --git a/doc/device-tree-bindings/spi/soft-spi.txt b/doc/device-tree-bindings/spi/soft-spi.txt index bdf7e86befb..77b01b2fd9a 100644 --- a/doc/device-tree-bindings/spi/soft-spi.txt +++ b/doc/device-tree-bindings/spi/soft-spi.txt @@ -8,14 +8,15 @@ The soft SPI node requires the following properties: Mandatory properties: compatible: "spi-gpio" -cs-gpios: GPIOs to use for SPI chip select (output) +cs-gpios: GPIOs to use for SPI chip select (output), not required if num-chipselects = <0> sck-gpios: GPIO to use for SPI clock (output) And at least one of: mosi-gpios: GPIO to use for SPI MOSI line (output) miso-gpios: GPIO to use for SPI MISO line (input) -Optional propertie: +Optional properties: spi-delay-us: Number of microseconds of delay between each CS transition +num-chipselects: Number of chipselect lines The GPIOs should be specified as required by the GPIO controller referenced. The first cell holds the phandle of the controller and the second cell diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst index 9629f97ffc4..b65d85b6681 100644 --- a/doc/usage/cmd/env.rst +++ b/doc/usage/cmd/env.rst @@ -79,7 +79,8 @@ The *env default* command resets the selected variables in the U-Boot environment to their default values. var - list of variable name. + list of variable names. If variable is not part of default + environment, it is deleted with a warning message on console. \-a all U-Boot environment. \-f @@ -309,6 +310,7 @@ Delete environment variable in memory:: Reset environment variable to default value, in memory:: => env default bootcmd + => env default ipaddr serverip => env default -a Save current environment in persistent storage:: diff --git a/doc/usage/cmd/upl.rst b/doc/usage/cmd/upl.rst new file mode 100644 index 00000000000..8d6ea5daa37 --- /dev/null +++ b/doc/usage/cmd/upl.rst @@ -0,0 +1,186 @@ +.. SPDX-License-Identifier: GPL-2.0+: + +upl command +=========== + +Synopsis +-------- + +:: + + upl write + upl read <addr> + upl info [-v] + +Description +----------- + +The *upl* command is used to test U-Boot's support for the Universal Payload +Specification (UPL) firmware standard (see :doc:`../upl`). It allows creation of +a fake handoff for use in testing. + + +upl write +~~~~~~~~~ + +Write a fake UPL handoff structure. The `upladdr` environment variable is set to +the address of this structure and `uplsize` is set to the size. + + +upl read +~~~~~~~~ + +Read a UPL handoff structure into internal state. This allows testing that the +handoff can be obtained. + +upl info +~~~~~~~~ + +Show basic information about usage of UPL: + + UPL state + active or inactive (indicates whether U-Boot booted from UPL or not) + + fit + Address of the FIT which was loaded + + conf_offset 2a4 + FIT offset of the chosen configuration + +For each image the following information is shown: + + Image number + Images are numbered from 0 + + load + Address to which the image was loaded + + size + Size of the loaded image + + offset + FIT offset of the image + + description + Description of the image + + +Example +------- + +This shows checking whether a UPL handoff was read at start-up:: + + => upl info + UPL state: active + +This shows how to use the command to write and display the handoff:: + + => upl write + UPL handoff written to bc8a5e0 size 662 + => print upladdr + upladdr=bc8a5e0 + => print uplsize + uplsize=662 + + > fdt addr ${upladdr} + Working FDT set to bc8a5e0 + => fdt print + / { + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + options { + upl-params { + smbios = <0x00000123>; + acpi = <0x00000456>; + bootmode = "default", "s3"; + addr-width = <0x0000002e>; + acpi-nvs-size = <0x00000100>; + }; + upl-image { + fit = <0x00000789>; + conf-offset = <0x00000234>; + image-1 { + load = <0x00000001>; + size = <0x00000002>; + offset = <0x00000003>; + description = "U-Boot"; + }; + image-2 { + load = <0x00000004>; + size = <0x00000005>; + offset = <0x00000006>; + description = "ATF"; + }; + }; + }; + memory@0x10 { + reg = <0x00000010 0x00000020 0x00000030 0x00000040 0x00000050 0x00000060>; + }; + memory@0x70 { + reg = <0x00000070 0x00000080>; + hotpluggable; + }; + memory-map { + acpi@0x11 { + reg = <0x00000011 0x00000012 0x00000013 0x00000014 0x00000015 0x00000016 0x00000017 0x00000018 0x00000019 0x0000001a>; + usage = "acpi-reclaim"; + }; + u-boot@0x21 { + reg = <0x00000021 0x00000022>; + usage = "boot-data"; + }; + efi@0x23 { + reg = <0x00000023 0x00000024>; + usage = "runtime-code"; + }; + empty@0x25 { + reg = <0x00000025 0x00000026 0x00000027 0x00000028>; + }; + acpi-things@0x2a { + reg = <0x0000002a 0x00000000>; + usage = "acpi-nvs", "runtime-code"; + }; + }; + reserved-memory { + mmio@0x2b { + reg = <0x0000002b 0x0000002c>; + }; + memory@0x2d { + reg = <0x0000002d 0x0000002e 0x0000002f 0x00000030>; + no-map; + }; + }; + serial@0xf1de0000 { + compatible = "ns16550a"; + clock-frequency = <0x001c2000>; + current-speed = <0x0001c200>; + reg = <0xf1de0000 0x00000100>; + reg-io-shift = <0x00000002>; + reg-offset = <0x00000040>; + virtual-reg = <0x20000000>; + access-type = "mmio"; + }; + framebuffer@0xd0000000 { + compatible = "simple-framebuffer"; + reg = <0xd0000000 0x10000000>; + width = <0x00000500>; + height = <0x00000500>; + stride = <0x00001400>; + format = "a8r8g8b8"; + }; + }; + => + +This showing reading the handoff into internal state:: + + => upl read bc8a5e0 + Reading UPL at bc8a5e0 + => + +This shows getting basic information about UPL: + + => upl info -v + UPL state: active + fit 1264000 + conf_offset 2a4 + image 0: load 200000 size 105f5c8 offset a4: U-Boot 2024.07-00770-g739ee12e8358 for sandbox board diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 1f6518b77c4..b058c2254fb 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -15,6 +15,7 @@ Use U-Boot cmdline semihosting measured_boot + upl Shell commands -------------- @@ -114,6 +115,7 @@ Shell commands cmd/tftpput cmd/trace cmd/true + cmd/upl cmd/ums cmd/unbind cmd/ut diff --git a/doc/usage/upl.rst b/doc/usage/upl.rst new file mode 100644 index 00000000000..3c4a10c862c --- /dev/null +++ b/doc/usage/upl.rst @@ -0,0 +1,46 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Universal Payload +----------------- + +`Universal Payload (UPL) <https://universalpayload.github.io/spec/index.html>`_ +is an Industry Standard for firmware components. UPL +is designed to improve interoperability within the firmware industry, allowing +mixing and matching of projects with less friction and fewer project-specific +implementations. UPL is cross-platform, supporting ARM, x86 and RISC-V +initially. + +UPL is defined in termns of two firmware components: + +`Platform Init` + Perhaps initial setup of the hardware and jumps to the payload. + +`Payload` + Selects the OS to boot + +In practice UPL can be used to handle any number of handoffs through the +firmware startup process, with one program acting as platform init and another +acting as the payload. + +UPL provides a standard for three main pieces: + +- file format for the payload, which may comprise multiple images to load +- handoff format for the information the payload needs, such as serial port, + memory layout, etc. +- machine state and register settings at the point of handoff + +See also the :doc:`cmd/upl`. + +UPL in U-Boot +~~~~~~~~~~~~~ + +U-Boot supports: + +- writing a UPL handoff (devicetree) in SPL +- reading a UPL handoff in U-Boot proper +- creating a FIT + +There are some new FIT features in UPL which are not yet supported in U-Boot. + +.. sectionauthor:: Simon Glass <sjg@chromium.org> +.. July 2024 diff --git a/drivers/Makefile b/drivers/Makefile index 9195dafd37e..1acd94f3c17 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_TPL_)ADC) += adc/ obj-$(CONFIG_$(SPL_TPL_)BIOSEMU) += bios_emulator/ obj-$(CONFIG_$(SPL_TPL_)BLK) += block/ obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ @@ -81,7 +82,6 @@ endif ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) -obj-y += adc/ obj-y += ata/ obj-$(CONFIG_DM_DEMO) += demo/ obj-y += block/ diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index c9cdbe6942d..37235f557a3 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -1,5 +1,6 @@ config ADC bool "Enable ADC drivers using Driver Model" + depends on DM help This enables ADC API for drivers, which allows driving ADC features by single and multi-channel methods for: @@ -11,6 +12,10 @@ config ADC - support supply's phandle with auto-enable - supply polarity setting in fdt +config SPL_ADC + bool "Enable ADC drivers using Driver Model in SPL" + depends on SPL_DM + config ADC_EXYNOS bool "Enable Exynos 54xx ADC driver" depends on ADC diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index 5336c820973..dca0b39c2e2 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -4,7 +4,7 @@ # Przemyslaw Marczak <p.marczak@samsung.com> # -obj-$(CONFIG_ADC) += adc-uclass.o +obj-$(CONFIG_$(SPL_TPL_)ADC) += adc-uclass.o obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o obj-$(CONFIG_ADC_SANDBOX) += sandbox.o obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 512c952f4d7..312e038445c 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -36,6 +36,8 @@ static struct { { UCLASS_PVBLOCK, "pvblock" }, { UCLASS_BLKMAP, "blkmap" }, { UCLASS_RKMTD, "rkmtd" }, + { UCLASS_MTD, "mtd" }, + { UCLASS_MTD, "ubi" }, }; static enum uclass_id uclass_name_to_iftype(const char *uclass_idname) diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index ec34f1ad8c2..6c74d66037e 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -25,7 +25,7 @@ static unsigned long host_block_read(struct udevice *dev, struct udevice *host_dev = dev_get_parent(dev); struct host_sb_plat *plat = dev_get_plat(host_dev); - if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) { + if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { printf("ERROR: Invalid block %lx\n", start); return -1; } @@ -44,7 +44,7 @@ static unsigned long host_block_write(struct udevice *dev, struct udevice *host_dev = dev_get_parent(dev); struct host_sb_plat *plat = dev_get_plat(host_dev); - if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) == -1) { + if (os_lseek(plat->fd, start * desc->blksz, OS_SEEK_SET) < 0) { printf("ERROR: Invalid block %lx\n", start); return -1; } diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 97f3b999d7c..a8239e228cf 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -726,6 +726,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: + case dp_video_ref ... dp_stc_ref: return zynqmp_clk_set_peripheral_rate(priv, id, rate, two_divs); default: diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 2beb63030f2..23b9787612a 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -66,6 +66,24 @@ static const struct mtk_pll_data apmixed_plls[] = { 21, 0x358, 1, 0x35c, 0), }; +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0x8, + .sta_ofs = 0x8, +}; + +#define GATE_APMIXED(_id, _parent, _shift) { \ + .id = _id, \ + .parent = _parent, \ + .regs = &apmixed_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV, \ + } + +static const struct mtk_gate apmixed_cgs[] = { + GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, CLK_APMIXED_MAINPLL, 5), +}; + /* topckgen */ #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -366,6 +384,20 @@ static const struct mtk_composite top_muxes[] = { }; /* infracfg */ +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) + +static const struct mtk_parent infra_mux1_parents[] = { + XTAL_PARENT(CLK_XTAL), + APMIXED_PARENT(CLK_APMIXED_MAINPLL), + APMIXED_PARENT(CLK_APMIXED_MAIN_CORE_EN), + APMIXED_PARENT(CLK_APMIXED_MAINPLL), +}; + +static const struct mtk_composite infra_muxes[] = { + MUX_MIXED(CLK_INFRA_MUX1_SEL, infra_mux1_parents, 0x000, 2, 2), +}; + static const struct mtk_gate_regs infra_cg_regs = { .set_ofs = 0x40, .clr_ofs = 0x44, @@ -382,14 +414,26 @@ static const struct mtk_gate_regs infra_cg_regs = { static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0), - GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5), GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16), GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18), GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22), + GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), }; /* pericfg */ +static const int peribus_ck_parents[] = { + CLK_TOP_SYSPLL1_D8, + CLK_TOP_SYSPLL1_D4, +}; + +#define PERI_MUX(_id, _parents, _reg, _shift, _width) \ + MUX_FLAGS(_id, _parents, _reg, _shift, _width, CLK_PARENT_TOPCKGEN) + +static const struct mtk_composite peri_muxes[] = { + PERI_MUX(CLK_PERIBUS_SEL, peribus_ck_parents, 0x05c, 0, 1), +}; + static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x8, .clr_ofs = 0x10, @@ -402,13 +446,17 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x1C, }; -#define GATE_PERI0(_id, _parent, _shift) { \ +#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \ .id = _id, \ .parent = _parent, \ .regs = &peri0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = _flags, \ } +#define GATE_PERI0(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_PERI0_XTAL(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -421,14 +469,14 @@ static const struct mtk_gate_regs peri1_cg_regs = { static const struct mtk_gate peri_cgs[] = { /* PERI0 */ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), - GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2), - GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3), - GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4), - GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5), - GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6), - GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7), - GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8), - GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9), + GATE_PERI0_XTAL(CLK_PERI_PWM1_PD, CLK_XTAL, 2), + GATE_PERI0_XTAL(CLK_PERI_PWM2_PD, CLK_XTAL, 3), + GATE_PERI0_XTAL(CLK_PERI_PWM3_PD, CLK_XTAL, 4), + GATE_PERI0_XTAL(CLK_PERI_PWM4_PD, CLK_XTAL, 5), + GATE_PERI0_XTAL(CLK_PERI_PWM5_PD, CLK_XTAL, 6), + GATE_PERI0_XTAL(CLK_PERI_PWM6_PD, CLK_XTAL, 7), + GATE_PERI0_XTAL(CLK_PERI_PWM7_PD, CLK_XTAL, 8), + GATE_PERI0_XTAL(CLK_PERI_PWM_PD, CLK_XTAL, 9), GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13), GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14), @@ -436,12 +484,13 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), + GATE_PERI0(CLK_PERI_UART4_PD, CLK_TOP_AXI_SEL, 21), GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22), GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23), GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26), - GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), + GATE_PERI0_XTAL(CLK_PERI_AUXADC_PD, CLK_XTAL, 27), GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28), GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29), GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30), @@ -550,12 +599,33 @@ static const struct mtk_gate ssusb_cgs[] = { GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_HIF_SEL, 8), }; +static const struct mtk_clk_tree mt7622_apmixed_clk_tree = { + .xtal2_rate = 25 * MHZ, + .plls = apmixed_plls, + .gates_offs = CLK_APMIXED_MAIN_CORE_EN, + .gates = apmixed_cgs, +}; + +static const struct mtk_clk_tree mt7622_infra_clk_tree = { + .xtal_rate = 25 * MHZ, + .muxes_offs = CLK_INFRA_MUX1_SEL, + .gates_offs = CLK_INFRA_DBGCLK_PD, + .muxes = infra_muxes, + .gates = infra_cgs, +}; + +static const struct mtk_clk_tree mt7622_peri_clk_tree = { + .xtal_rate = 25 * MHZ, + .muxes_offs = CLK_PERIBUS_SEL, + .gates_offs = CLK_PERI_THERM_PD, + .muxes = peri_muxes, + .gates = peri_cgs, +}; + static const struct mtk_clk_tree mt7622_clk_tree = { .xtal_rate = 25 * MHZ, - .xtal2_rate = 25 * MHZ, .fdivs_offs = CLK_TOP_TO_USB3_SYS, .muxes_offs = CLK_TOP_AXI_SEL, - .plls = apmixed_plls, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, @@ -582,7 +652,7 @@ static int mt7622_apmixedsys_probe(struct udevice *dev) struct mtk_clk_priv *priv = dev_get_priv(dev); int ret; - ret = mtk_common_clk_init(dev, &mt7622_clk_tree); + ret = mtk_common_clk_init(dev, &mt7622_apmixed_clk_tree); if (ret) return ret; @@ -603,12 +673,12 @@ static int mt7622_topckgen_probe(struct udevice *dev) static int mt7622_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7622_infra_clk_tree); } static int mt7622_pericfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7622_peri_clk_tree); } static int mt7622_pciesys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c index 5072c9983c1..d0b80f48b0a 100644 --- a/drivers/clk/mediatek/clk-mt7623.c +++ b/drivers/clk/mediatek/clk-mt7623.c @@ -25,6 +25,22 @@ #define AXI_DIV_SEL(x) (x) /* apmixedsys */ +static const int pll_id_offs_map[] = { + [CLK_APMIXED_ARMPLL] = 0, + [CLK_APMIXED_MAINPLL] = 1, + [CLK_APMIXED_UNIVPLL] = 2, + [CLK_APMIXED_MMPLL] = 3, + [CLK_APMIXED_MSDCPLL] = 4, + [CLK_APMIXED_TVDPLL] = 5, + [CLK_APMIXED_AUD1PLL] = 6, + [CLK_APMIXED_TRGPLL] = 7, + [CLK_APMIXED_ETHPLL] = 8, + [CLK_APMIXED_VDECPLL] = 9, + [CLK_APMIXED_HADDS2PLL] = 10, + [CLK_APMIXED_AUD2PLL] = 11, + [CLK_APMIXED_TVD2PLL] = 12, +}; + #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ _pd_shift, _pcw_reg, _pcw_shift) { \ .id = _id, \ @@ -71,6 +87,176 @@ static const struct mtk_pll_data apmixed_plls[] = { }; /* topckgen */ + +/* Fixed CLK exposed upstream by the hdmi PHY driver */ +#define CLK_TOP_HDMITX_CLKDIG_CTS CLK_TOP_NR + +static const int top_id_offs_map[CLK_TOP_NR + 1] = { + /* Fixed CLK */ + [CLK_TOP_DPI] = 0, + [CLK_TOP_DMPLL] = 1, + [CLK_TOP_VENCPLL] = 2, + [CLK_TOP_HDMI_0_PIX340M] = 3, + [CLK_TOP_HDMI_0_DEEP340M] = 4, + [CLK_TOP_HDMI_0_PLL340M] = 5, + [CLK_TOP_HADDS2_FB] = 6, + [CLK_TOP_WBG_DIG_416M] = 7, + [CLK_TOP_DSI0_LNTC_DSI] = 8, + [CLK_TOP_HDMI_SCL_RX] = 9, + [CLK_TOP_32K_EXTERNAL] = 10, + [CLK_TOP_HDMITX_CLKDIG_CTS] = 11, + [CLK_TOP_AUD_EXT1] = 12, + [CLK_TOP_AUD_EXT2] = 13, + [CLK_TOP_NFI1X_PAD] = 14, + /* Factor CLK */ + [CLK_TOP_SYSPLL] = 15, + [CLK_TOP_SYSPLL_D2] = 16, + [CLK_TOP_SYSPLL_D3] = 17, + [CLK_TOP_SYSPLL_D5] = 18, + [CLK_TOP_SYSPLL_D7] = 19, + [CLK_TOP_SYSPLL1_D2] = 20, + [CLK_TOP_SYSPLL1_D4] = 21, + [CLK_TOP_SYSPLL1_D8] = 22, + [CLK_TOP_SYSPLL1_D16] = 23, + [CLK_TOP_SYSPLL2_D2] = 24, + [CLK_TOP_SYSPLL2_D4] = 25, + [CLK_TOP_SYSPLL2_D8] = 26, + [CLK_TOP_SYSPLL3_D2] = 27, + [CLK_TOP_SYSPLL3_D4] = 28, + [CLK_TOP_SYSPLL4_D2] = 29, + [CLK_TOP_SYSPLL4_D4] = 30, + [CLK_TOP_UNIVPLL] = 31, + [CLK_TOP_UNIVPLL_D2] = 32, + [CLK_TOP_UNIVPLL_D3] = 33, + [CLK_TOP_UNIVPLL_D5] = 34, + [CLK_TOP_UNIVPLL_D7] = 35, + [CLK_TOP_UNIVPLL_D26] = 36, + [CLK_TOP_UNIVPLL_D52] = 37, + [CLK_TOP_UNIVPLL_D108] = 38, + [CLK_TOP_USB_PHY48M] = 39, + [CLK_TOP_UNIVPLL1_D2] = 40, + [CLK_TOP_UNIVPLL1_D4] = 41, + [CLK_TOP_UNIVPLL1_D8] = 42, + [CLK_TOP_UNIVPLL2_D2] = 43, + [CLK_TOP_UNIVPLL2_D4] = 44, + [CLK_TOP_UNIVPLL2_D8] = 45, + [CLK_TOP_UNIVPLL2_D16] = 46, + [CLK_TOP_UNIVPLL2_D32] = 47, + [CLK_TOP_UNIVPLL3_D2] = 48, + [CLK_TOP_UNIVPLL3_D4] = 49, + [CLK_TOP_UNIVPLL3_D8] = 50, + [CLK_TOP_MSDCPLL] = 51, + [CLK_TOP_MSDCPLL_D2] = 52, + [CLK_TOP_MSDCPLL_D4] = 53, + [CLK_TOP_MSDCPLL_D8] = 54, + [CLK_TOP_MMPLL] = 55, + [CLK_TOP_MMPLL_D2] = 56, + [CLK_TOP_DMPLL_D2] = 57, + [CLK_TOP_DMPLL_D4] = 58, + [CLK_TOP_DMPLL_X2] = 59, + [CLK_TOP_TVDPLL] = 60, + [CLK_TOP_TVDPLL_D2] = 61, + [CLK_TOP_TVDPLL_D4] = 62, + [CLK_TOP_VDECPLL] = 63, + [CLK_TOP_TVD2PLL] = 64, + [CLK_TOP_TVD2PLL_D2] = 65, + [CLK_TOP_MIPIPLL] = 66, + [CLK_TOP_MIPIPLL_D2] = 67, + [CLK_TOP_MIPIPLL_D4] = 68, + [CLK_TOP_HDMIPLL] = 69, + [CLK_TOP_HDMIPLL_D2] = 70, + [CLK_TOP_HDMIPLL_D3] = 71, + [CLK_TOP_ARMPLL_1P3G] = 72, + [CLK_TOP_AUDPLL] = 73, + [CLK_TOP_AUDPLL_D4] = 74, + [CLK_TOP_AUDPLL_D8] = 75, + [CLK_TOP_AUDPLL_D16] = 76, + [CLK_TOP_AUDPLL_D24] = 77, + [CLK_TOP_AUD1PLL_98M] = 78, + [CLK_TOP_AUD2PLL_90M] = 79, + [CLK_TOP_HADDS2PLL_98M] = 80, + [CLK_TOP_HADDS2PLL_294M] = 81, + [CLK_TOP_ETHPLL_500M] = 82, + [CLK_TOP_CLK26M_D8] = 83, + [CLK_TOP_32K_INTERNAL] = 84, + [CLK_TOP_AXISEL_D4] = 85, + [CLK_TOP_8BDAC] = 86, + /* MUX CLK */ + [CLK_TOP_AXI_SEL] = 87, + [CLK_TOP_MEM_SEL] = 88, + [CLK_TOP_DDRPHYCFG_SEL] = 89, + [CLK_TOP_MM_SEL] = 90, + [CLK_TOP_PWM_SEL] = 91, + [CLK_TOP_VDEC_SEL] = 92, + [CLK_TOP_MFG_SEL] = 93, + [CLK_TOP_CAMTG_SEL] = 94, + [CLK_TOP_UART_SEL] = 95, + [CLK_TOP_SPI0_SEL] = 96, + [CLK_TOP_USB20_SEL] = 97, + [CLK_TOP_MSDC30_0_SEL] = 98, + [CLK_TOP_MSDC30_1_SEL] = 99, + [CLK_TOP_MSDC30_2_SEL] = 100, + [CLK_TOP_AUDIO_SEL] = 101, + [CLK_TOP_AUDINTBUS_SEL] = 102, + [CLK_TOP_PMICSPI_SEL] = 103, + [CLK_TOP_SCP_SEL] = 104, + [CLK_TOP_DPI0_SEL] = 105, + [CLK_TOP_DPI1_SEL] = 106, + [CLK_TOP_TVE_SEL] = 107, + [CLK_TOP_HDMI_SEL] = 108, + [CLK_TOP_APLL_SEL] = 109, + [CLK_TOP_RTC_SEL] = 110, + [CLK_TOP_NFI2X_SEL] = 111, + [CLK_TOP_EMMC_HCLK_SEL] = 112, + [CLK_TOP_FLASH_SEL] = 113, + [CLK_TOP_DI_SEL] = 114, + [CLK_TOP_NR_SEL] = 115, + [CLK_TOP_OSD_SEL] = 116, + [CLK_TOP_HDMIRX_BIST_SEL] = 117, + [CLK_TOP_INTDIR_SEL] = 118, + [CLK_TOP_ASM_I_SEL] = 119, + [CLK_TOP_ASM_M_SEL] = 120, + [CLK_TOP_ASM_H_SEL] = 121, + [CLK_TOP_MS_CARD_SEL] = 122, + [CLK_TOP_ETHIF_SEL] = 123, + [CLK_TOP_HDMIRX26_24_SEL] = 124, + [CLK_TOP_MSDC30_3_SEL] = 125, + [CLK_TOP_CMSYS_SEL] = 126, + [CLK_TOP_SPI1_SEL] = 127, + [CLK_TOP_SPI2_SEL] = 128, + [CLK_TOP_8BDAC_SEL] = 129, + [CLK_TOP_AUD2DVD_SEL] = 130, + [CLK_TOP_PADMCLK_SEL] = 131, + [CLK_TOP_AUD_MUX1_SEL] = 132, + [CLK_TOP_AUD_MUX2_SEL] = 133, + [CLK_TOP_AUDPLL_MUX_SEL] = 134, + [CLK_TOP_AUD_K1_SRC_SEL] = 135, + [CLK_TOP_AUD_K2_SRC_SEL] = 136, + [CLK_TOP_AUD_K3_SRC_SEL] = 137, + [CLK_TOP_AUD_K4_SRC_SEL] = 138, + [CLK_TOP_AUD_K5_SRC_SEL] = 139, + [CLK_TOP_AUD_K6_SRC_SEL] = 140, + /* Misc CLK only used as parents */ + [CLK_TOP_AUD_EXTCK1_DIV] = 141, + [CLK_TOP_AUD_EXTCK2_DIV] = 142, + [CLK_TOP_AUD_MUX1_DIV] = 143, + [CLK_TOP_AUD_MUX2_DIV] = 144, + [CLK_TOP_AUD_K1_SRC_DIV] = 145, + [CLK_TOP_AUD_K2_SRC_DIV] = 146, + [CLK_TOP_AUD_K3_SRC_DIV] = 147, + [CLK_TOP_AUD_K4_SRC_DIV] = 148, + [CLK_TOP_AUD_K5_SRC_DIV] = 149, + [CLK_TOP_AUD_K6_SRC_DIV] = 150, + [CLK_TOP_AUD_48K_TIMING] = 151, + [CLK_TOP_AUD_44K_TIMING] = 152, + [CLK_TOP_AUD_I2S1_MCLK] = 153, + [CLK_TOP_AUD_I2S2_MCLK] = 154, + [CLK_TOP_AUD_I2S3_MCLK] = 155, + [CLK_TOP_AUD_I2S4_MCLK] = 156, + [CLK_TOP_AUD_I2S5_MCLK] = 157, + [CLK_TOP_AUD_I2S6_MCLK] = 158, +}; + #define FACTOR0(_id, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -586,21 +772,26 @@ static const struct mtk_gate_regs infra_cg_regs = { .sta_ofs = 0x48, }; -#define GATE_INFRA(_id, _parent, _shift) { \ +#define GATE_INFRA_FLAGS(_id, _parent, _shift, _flags) { \ .id = _id, \ .parent = _parent, \ .regs = &infra_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = _flags, \ } +#define GATE_INFRA(_id, _parent, _shift) \ + GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_INFRA_XTAL(_id, _parent, _shift) \ + GATE_INFRA_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) + static const struct mtk_gate infra_cgs[] = { GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0), GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1), GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4), - GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5), - GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6), + GATE_INFRA_XTAL(CLK_INFRA_AUDIO, CLK_XTAL, 5), + GATE_INFRA_XTAL(CLK_INFRA_EFUSE, CLK_XTAL, 6), GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7), GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8), GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12), @@ -616,6 +807,74 @@ static const struct mtk_gate infra_cgs[] = { }; /* pericfg */ +static const int peri_id_offs_map[] = { + /* MUX CLK */ + [CLK_PERI_UART0_SEL] = 1, + [CLK_PERI_UART1_SEL] = 2, + [CLK_PERI_UART2_SEL] = 3, + [CLK_PERI_UART3_SEL] = 4, + /* GATE CLK */ + [CLK_PERI_NFI] = 5, + [CLK_PERI_THERM] = 6, + [CLK_PERI_PWM1] = 7, + [CLK_PERI_PWM2] = 8, + [CLK_PERI_PWM3] = 9, + [CLK_PERI_PWM4] = 10, + [CLK_PERI_PWM5] = 11, + [CLK_PERI_PWM6] = 12, + [CLK_PERI_PWM7] = 13, + [CLK_PERI_PWM] = 14, + [CLK_PERI_USB0] = 15, + [CLK_PERI_USB1] = 16, + [CLK_PERI_AP_DMA] = 17, + [CLK_PERI_MSDC30_0] = 18, + [CLK_PERI_MSDC30_1] = 19, + [CLK_PERI_MSDC30_2] = 20, + [CLK_PERI_MSDC30_3] = 21, + [CLK_PERI_MSDC50_3] = 22, + [CLK_PERI_NLI] = 23, + [CLK_PERI_UART0] = 24, + [CLK_PERI_UART1] = 25, + [CLK_PERI_UART2] = 26, + [CLK_PERI_UART3] = 27, + [CLK_PERI_BTIF] = 28, + [CLK_PERI_I2C0] = 29, + [CLK_PERI_I2C1] = 30, + [CLK_PERI_I2C2] = 31, + [CLK_PERI_I2C3] = 32, + [CLK_PERI_AUXADC] = 33, + [CLK_PERI_SPI0] = 34, + [CLK_PERI_ETH] = 35, + [CLK_PERI_USB0_MCU] = 36, + [CLK_PERI_USB1_MCU] = 37, + [CLK_PERI_USB_SLV] = 38, + [CLK_PERI_GCPU] = 39, + [CLK_PERI_NFI_ECC] = 40, + [CLK_PERI_NFI_PAD] = 41, + [CLK_PERI_FLASH] = 42, + [CLK_PERI_HOST89_INT] = 43, + [CLK_PERI_HOST89_SPI] = 44, + [CLK_PERI_HOST89_DVD] = 45, + [CLK_PERI_SPI1] = 46, + [CLK_PERI_SPI2] = 47, + [CLK_PERI_FCI] = 48, +}; + +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) +#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL) + +static const struct mtk_parent uart_ck_sel_parents[] = { + XTAL_PARENT(CLK_XTAL), + TOP_PARENT(CLK_TOP_UART_SEL), +}; + +static const struct mtk_composite peri_muxes[] = { + MUX_MIXED(CLK_PERI_UART0_SEL, uart_ck_sel_parents, 0x40C, 0, 1), + MUX_MIXED(CLK_PERI_UART1_SEL, uart_ck_sel_parents, 0x40C, 1, 1), + MUX_MIXED(CLK_PERI_UART2_SEL, uart_ck_sel_parents, 0x40C, 2, 1), + MUX_MIXED(CLK_PERI_UART3_SEL, uart_ck_sel_parents, 0x40C, 3, 1), +}; + static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x8, .clr_ofs = 0x10, @@ -628,13 +887,17 @@ static const struct mtk_gate_regs peri1_cg_regs = { .sta_ofs = 0x1C, }; -#define GATE_PERI0(_id, _parent, _shift) { \ +#define GATE_PERI0_FLAGS(_id, _parent, _shift, _flags) { \ .id = _id, \ .parent = _parent, \ .regs = &peri0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ + .flags = _flags, \ } +#define GATE_PERI0(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_PERI0_XTAL(_id, _parent, _shift) \ + GATE_PERI0_FLAGS(_id, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) #define GATE_PERI1(_id, _parent, _shift) { \ .id = _id, \ @@ -672,10 +935,10 @@ static const struct mtk_gate peri_cgs[] = { GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24), GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25), GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26), - GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27), - GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28), + GATE_PERI0_XTAL(CLK_PERI_I2C3, CLK_XTAL, 27), + GATE_PERI0_XTAL(CLK_PERI_AUXADC, CLK_XTAL, 28), GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29), - GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30), + GATE_PERI0_XTAL(CLK_PERI_ETH, CLK_XTAL, 30), GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31), GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0), @@ -730,12 +993,17 @@ static const struct mtk_gate hif_cgs[] = { GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26), }; -static const struct mtk_clk_tree mt7623_clk_tree = { - .xtal_rate = 26 * MHZ, +static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = { .xtal2_rate = 26 * MHZ, - .fdivs_offs = CLK_TOP_SYSPLL, - .muxes_offs = CLK_TOP_AXI_SEL, + .id_offs_map = pll_id_offs_map, .plls = apmixed_plls, +}; + +static const struct mtk_clk_tree mt7623_topckgen_clk_tree = { + .xtal_rate = 26 * MHZ, + .id_offs_map = top_id_offs_map, + .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL], + .muxes_offs = top_id_offs_map[CLK_TOP_AXI_SEL], .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, @@ -760,7 +1028,7 @@ static int mt7623_apmixedsys_probe(struct udevice *dev) struct mtk_clk_priv *priv = dev_get_priv(dev); int ret; - ret = mtk_common_clk_init(dev, &mt7623_clk_tree); + ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree); if (ret) return ret; @@ -774,27 +1042,45 @@ static int mt7623_apmixedsys_probe(struct udevice *dev) static int mt7623_topckgen_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7623_clk_tree); + return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree); } +static const struct mtk_clk_tree mt7623_clk_gate_tree = { + /* Each CLK ID for gates clock starts at index 1 */ + .gates_offs = 1, + .xtal_rate = 26 * MHZ, +}; + static int mt7623_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs); + return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, + infra_cgs); } +static const struct mtk_clk_tree mt7623_clk_peri_tree = { + .id_offs_map = peri_id_offs_map, + .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL], + .gates_offs = peri_id_offs_map[CLK_PERI_NFI], + .muxes = peri_muxes, + .gates = peri_cgs, + .xtal_rate = 26 * MHZ, +}; + static int mt7623_pericfg_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs); + return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree); } static int mt7623_hifsys_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs); + return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, + hif_cgs); } static int mt7623_ethsys_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs); + return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, + eth_cgs); } static int mt7623_ethsys_hifsys_bind(struct udevice *dev) @@ -889,7 +1175,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = { .of_match = mt7623_pericfg_compat, .probe = mt7623_pericfg_probe, .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, + .ops = &mtk_clk_infrasys_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c index 13dc3df0e9e..97073918006 100644 --- a/drivers/clk/mediatek/clk-mt7981.c +++ b/drivers/clk/mediatek/clk-mt7981.c @@ -29,204 +29,204 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk fixed_pll_clks[] = { - FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000), - FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000), - FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), - FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 1300000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), }; /* TOPCKGEN FIXED CLK */ static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), + FIXED_CLK(CLK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ static const struct mtk_fixed_factor top_fixed_divs[] = { - PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3), - PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), - PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), - PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3), - PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15), - PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6), - PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12), - PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, + PLL_FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", CLK_APMIXED_MPLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", CLK_APMIXED_MPLL, 1, 3), + PLL_FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", CLK_APMIXED_MMPLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", CLK_APMIXED_MMPLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", CLK_APMIXED_MMPLL, 1, 3), + PLL_FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CLK_APMIXED_MMPLL, 1, 15), + PLL_FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", CLK_APMIXED_MMPLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", CLK_APMIXED_MMPLL, 1, 6), + PLL_FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", CLK_APMIXED_MMPLL, 1, 12), + PLL_FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", CLK_APMIXED_APLL2, 1, 1), - PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2), - PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), - PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), - PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), - PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), - PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), - PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, + PLL_FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", CLK_APMIXED_APLL2, 1, 2), + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", CLK_APMIXED_NET1PLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", CLK_APMIXED_NET1PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + PLL_FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", CLK_APMIXED_NET2PLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), - PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16), - PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6), - PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", - CK_APMIXED_WEDMCUPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), - TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2), - TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, + PLL_FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", CLK_APMIXED_NET2PLL, 1, 2), + PLL_FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", CLK_APMIXED_NET2PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), + PLL_FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", CLK_APMIXED_NET2PLL, 1, 6), + PLL_FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", + CLK_APMIXED_WEDMCUPLL, 1, 1), + PLL_FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", CLK_APMIXED_SGMPLL, 1, 1), + TOP_FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CLK_TOP_CB_CKSQ_40M, 1, 2), + TOP_FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", CLK_TOP_CB_CKSQ_40M, 1, 1250), - TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CLK_TOP_CB_CKSQ_40M, 1, 1220), - TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", CLK_TOP_CB_CKSQ_40M, 1, 1), + TOP_FACTOR(CLK_TOP_FAUD, "faud", CLK_TOP_AUD_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_NFI1X, "nfi1x", CLK_TOP_NFI1X_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CLK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1), - TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1), - TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1, + TOP_FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", CLK_TOP_CB_CKSQ_40M, 1, 1), + TOP_FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", CLK_TOP_CB_CKSQ_40M, 1, 1), + TOP_FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", CLK_TOP_SPINFI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SPI, "spi", CLK_TOP_SPI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SPIM_MST, "spim_mst", CLK_TOP_SPIM_MST_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_UART_BCK, "uart_bck", CLK_TOP_UART_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", CLK_TOP_PWM_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", CLK_TOP_I2C_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", CLK_TOP_PEXTP_TL_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", CLK_TOP_EMMC_208M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", CLK_TOP_EMMC_400M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", CLK_TOP_DRAMC_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", CLK_TOP_DRAMC_MD32_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1), - TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1, + TOP_FACTOR(CLK_TOP_SYSAXI, "sysaxi", CLK_TOP_SYSAXI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SYSAPB, "sysapb", CLK_TOP_SYSAPB_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", CLK_TOP_ARM_DB_MAIN_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1, + TOP_FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", CLK_TOP_AP2CNN_HOST_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1, + TOP_FACTOR(CLK_TOP_NETSYS, "netsys", CLK_TOP_NETSYS_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", CLK_TOP_NETSYS_500M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", - CK_TOP_NETSYS_MCU_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1), - TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1), - TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1, + TOP_FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", + CLK_TOP_NETSYS_MCU_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", CLK_TOP_NETSYS_2X_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SGM_325M, "sgm_325m", CLK_TOP_SGM_325M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_SGM_REG, "sgm_reg", CLK_TOP_SGM_REG_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_F26M, "csw_f26m", CLK_TOP_F26M_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_EIP97B, "eip97b", CLK_TOP_EIP97B_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", CLK_TOP_USB3_PHY_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_AUD, "aud", CLK_TOP_FAUD, 1, 1), + TOP_FACTOR(CLK_TOP_A1SYS, "a1sys", CLK_TOP_A1SYS_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_AUD_L, "aud_l", CLK_TOP_AUD_L_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", CLK_TOP_U2U3_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", CLK_TOP_U2U3_SYS_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", CLK_TOP_U2U3_XHCI_SEL, 1, 1), + TOP_FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", CLK_TOP_USB_FRMCNT_SEL, 1, 1), }; /* TOPCKGEN MUX PARENTS */ -static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4, - CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, - CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8, - CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; +static const int nfi1x_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D4, + CLK_TOP_NET1_D8_D2, CLK_TOP_CB_NET2_D6, + CLK_TOP_CB_M_D4, CLK_TOP_CB_MM_D8, + CLK_TOP_NET1_D8_D4, CLK_TOP_CB_M_D8 }; -static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, - CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 }; +static const int spinfi_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_CB_CKSQ_40M, + CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, + CLK_TOP_CB_MM_D8, CLK_TOP_NET1_D8_D4, + CLK_TOP_MM_D6_D2, CLK_TOP_CB_M_D8 }; -static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, - CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const int spi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, + CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, + CLK_TOP_CB_NET2_D6, CLK_TOP_NET1_D5_D4, + CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; -static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, - CK_TOP_M_D8_D2 }; +static const int uart_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D8, + CLK_TOP_M_D8_D2 }; -static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; +static const int pwm_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2, + CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, + CLK_TOP_M_D8_D2, CLK_TOP_CB_RTC_32K }; -static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const int i2c_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4, + CLK_TOP_CB_M_D4, CLK_TOP_NET1_D8_D4 }; -static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_CB_RTC_32K }; +static const int pextp_tl_ck_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_NET1_D5_D4, CLK_TOP_CB_M_D4, + CLK_TOP_CB_RTC_32K }; static const int emmc_208m_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4, - CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, - CK_TOP_CB_MM_D6 + CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, CLK_TOP_CB_NET2_D4, + CLK_TOP_CB_APLL2_196M, CLK_TOP_CB_MM_D4, CLK_TOP_NET1_D8_D2, + CLK_TOP_CB_MM_D6 }; -static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2, - CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 }; +static const int emmc_400m_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D2, + CLK_TOP_CB_MM_D2, CLK_TOP_CB_NET2_D2 }; -static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; +static const int csw_f26m_parents[] = { CLK_TOP_CKSQ_40M_D2, CLK_TOP_M_D8_D2 }; -static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_WEDMCU_208M }; +static const int dramc_md32_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_M_D2, + CLK_TOP_CB_WEDMCU_208M }; -static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 }; +static const int sysaxi_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D8_D2 }; -static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 }; +static const int sysapb_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D3_D2 }; -static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D6 }; +static const int arm_db_main_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_NET2_D6 }; -static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D8_D4 }; +static const int ap2cnn_host_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_NET1_D8_D4 }; -static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 }; +static const int netsys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_D2 }; -static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D5 }; +static const int netsys_500m_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_NET1_D5 }; -static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M, - CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, - CK_TOP_CB_M_416M }; +static const int netsys_mcu_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_MM_720M, + CLK_TOP_CB_NET1_D4, CLK_TOP_CB_NET1_D5, + CLK_TOP_CB_M_416M }; -static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M, - CK_TOP_CB_MM_720M }; +static const int netsys_2x_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_NET2_800M, + CLK_TOP_CB_MM_720M }; -static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_SGM_325M }; +static const int sgm_325m_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_SGM_325M }; -static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 }; +static const int sgm_reg_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET2_D4 }; -static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5, - CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2, - CK_TOP_NET1_D5_D2 }; +static const int eip97b_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_NET1_D5, + CLK_TOP_CB_M_416M, CLK_TOP_CB_MM_D2, + CLK_TOP_NET1_D5_D2 }; -static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M }; +static const int aud_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M }; -static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; +static const int a1sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4 }; -static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, - CK_TOP_M_D8_D2 }; +static const int aud_l_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_CB_APLL2_196M, + CLK_TOP_M_D8_D2 }; -static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4, - CK_TOP_M_D8_D2 }; +static const int a_tuner_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_APLL2_D4, + CLK_TOP_M_D8_D2 }; -static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 }; +static const int u2u3_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_M_D8_D2 }; -static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; +static const int u2u3_sys_parents[] = { CLK_TOP_CB_CKSQ_40M, CLK_TOP_NET1_D5_D4 }; -static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_MM_D3_D5 }; +static const int usb_frmcnt_parents[] = { CLK_TOP_CB_CKSQ_40M, + CLK_TOP_CB_MM_D3_D5 }; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -242,174 +242,150 @@ static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, /* TOPCKGEN MUX_GATE */ static const struct mtk_composite top_muxes[] = { - TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0, + TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0, 3, 7, 0x1c0, 0), - TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8, + TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8, 8, 3, 15, 0x1c0, 1), - TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3, + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3, 23, 0x1c0, 2), - TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8, + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8, 24, 3, 31, 0x1c0, 3), - TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0, + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0, 2, 7, 0x1c0, 4), - TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3, + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5), - TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2, + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2, 23, 0x1c0, 6), - TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, 0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7), - TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20, 0x24, 0x28, 0, 3, 7, 0x1c0, 8), - TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, 0x24, 0x28, 8, 2, 15, 0x1c0, 9), - TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24, + TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24, 0x28, 16, 1, 23, 0x1c0, 10), - TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24, + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24, 0x28, 24, 1, 31, 0x1c0, 11), - TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, 0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12), - TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34, 0x38, 8, 1, 15, 0x1c0, 13), - TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34, 0x38, 16, 1, 23, 0x1c0, 14), - TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, + TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, 0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15), - TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents, + TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents, 0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16), - TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44, + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44, 0x48, 8, 1, 15, 0x1c0, 17), - TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18), - TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, + TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19), - TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50, + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50, 0x54, 0x58, 0, 2, 7, 0x1c0, 20), - TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50, + TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50, 0x54, 0x58, 8, 1, 15, 0x1c0, 21), - TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54, + TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54, 0x58, 16, 1, 23, 0x1c0, 22), - TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54, + TOP_MUX(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54, 0x58, 24, 3, 31, 0x1c0, 23), - TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60, + TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60, 0x64, 0x68, 0, 1, 7, 0x1c0, 24), - TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1, + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1, 15, 0x1c0, 25), - TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68, + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26), - TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68, + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68, 24, 2, 31, 0x1c0, 27), - TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74, + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74, 0x78, 0, 2, 7, 0x1c0, 28), - TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8, + TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8, 1, 15, 0x1c0, 29), - TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70, + TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x1c0, 30), - TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70, + TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70, 0x74, 0x78, 24, 1, 31, 0x1c4, 0), - TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, + TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1), }; /* INFRA FIXED DIV */ static const struct mtk_fixed_factor infra_fixed_divs[] = { - TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2), - TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1), - INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), - INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, - 1), - TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1, - 1), - TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL, - 1, 1), - TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1), - TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M, - 1, 1), - TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1), - TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", - CK_TOP_PEXTP_TL, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1), + TOP_FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", CLK_TOP_SYSAXI_SEL, 1, 2), }; /* INFRASYS MUX PARENTS */ -static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART }; +#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) +#define VOID_PARENT PARENT(-1, 0) -static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 }; +static const struct mtk_parent infra_uart0_parents[] = { + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL) +}; + +static const struct mtk_parent infra_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL) +}; -static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 }; +static const struct mtk_parent infra_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPIM_MST_SEL) +}; -static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM }; +static const struct mtk_parent infra_pwm1_parents[] = { + VOID_PARENT, + TOP_PARENT(CLK_TOP_PWM_SEL) +}; -static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM }; +static const struct mtk_parent infra_pwm_bsel_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + INFRA_PARENT(CLK_INFRA_66M_MCK), + TOP_PARENT(CLK_TOP_PWM_SEL) +}; -static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M, - CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK}; +static const struct mtk_parent infra_pcie_parents[] = { + TOP_PARENT(CLK_TOP_CB_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_CB_CKSQ_40M), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL) +}; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ { \ .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ - .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* INFRA MUX */ static const struct mtk_composite infra_muxes[] = { - INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, 0x10, 0, 1), - INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, 0x10, 1, 1), - INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, 0x10, 2, 1), - INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, 4, 1), - INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, 5, 1), - INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10, 6, 1), - INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10, - 9, 2), - INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, - 11, 2), - INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10, + 9, 1), + INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10, + 11, 1), + INFRA_MUX(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", infra_pwm1_parents, 0x10, + 15, 1), + INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), - INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, + INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, 0, 2), }; @@ -431,92 +407,105 @@ static const struct mtk_gate_regs infra_2_cg_regs = { .sta_ofs = 0x68, }; -#define GATE_INFRA0(_id, _name, _parent, _shift) \ +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA1(_id, _name, _parent, _shift) \ +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA2(_id, _name, _parent, _shift) \ +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) /* INFRA GATE */ -static const struct mtk_gate infracfg_ao_gates[] = { - GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0), - GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1), - GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2), - GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3), - GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4), - GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6), - GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8), - GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9), - GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10), - GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK, - 11), - GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK, - 13), - GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M, - 14), - GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15), - GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16), - GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24), - GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25), - GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0), - GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1), - GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2), - GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3), - GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4), - GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6), - GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK, - 7), - GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8), - GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK, +static const struct mtk_gate infracfg_gates[] = { + GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_66M_MCK, 0), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_66M_MCK, 1), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2), + GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3), + GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4), + GATE_INFRA0_INFRA(CLK_INFRA_PWM3_CK, "infra_pwm3", CLK_INFRA_PWM3_SEL, 27), + GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI, 6), + GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI, 8), + GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9), + GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L, 10), + GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS, + 11), + GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER, + 13), + GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL, + 14), + GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_66M_MCK, 15), + GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_66M_MCK, 16), + GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_66M_MCK, 24), + GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25), + GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2c0", CLK_TOP_I2C_BCK, 1), + GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2), + GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3), + GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4), + GATE_INFRA1_INFRA(CLK_INFRA_SPI2_CK, "infra_spi2", CLK_INFRA_SPI2_SEL, 6), + GATE_INFRA1_INFRA(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CLK_INFRA_66M_MCK, + 7), + GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X, 8), + GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_BCK, 9), - GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10), - GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11), - GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12), - GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK, - 13), - GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK, - 14), - GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15), - GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16), - GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", - CK_INFRA_FMSDC_HCK_CK, 17), - GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", - CK_INFRA_PERI_133M, 18), - GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK, - 19), - GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20), - GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21), - GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK, - 23), - GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK, - 25), - GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26), - GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK, - 0), - GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK, - 1), - GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK, - 2), - GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3), - GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", - CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12), - GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14), - GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15), + GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_66M_MCK, 10), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_66M_MCK, + 13), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_66M_MCK, + 14), + GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_CB_RTC_32K, 15), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_400M, 16), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", + CLK_TOP_EMMC_208M, 17), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", + CLK_TOP_SYSAXI, 18), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_TOP_SYSAXI, + 19), + GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20), + GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M, 21), + GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X, + 23), + GATE_INFRA1_TOP(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CLK_TOP_SYSAXI, + 25), + GATE_INFRA1_INFRA(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CLK_INFRA_66M_MCK, 26), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI, + 0), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_TOP_SYSAXI, + 1), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS, + 2), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_REF, 3), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL, 12), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_CB_CKSQ_40M, 13), + GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M, 14), + GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI, 15), }; static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { @@ -526,19 +515,22 @@ static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = { }; static const struct mtk_clk_tree mt7981_topckgen_clk_tree = { - .fdivs_offs = CK_TOP_CB_M_416M, - .muxes_offs = CK_TOP_NFI1X_SEL, + .fdivs_offs = CLK_TOP_CB_M_416M, + .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, - .flags = CLK_BYPASS_XTAL, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, }; static const struct mtk_clk_tree mt7981_infracfg_clk_tree = { - .fdivs_offs = CK_INFRA_CK_F26M, - .muxes_offs = CK_INFRA_UART0_SEL, + .fdivs_offs = CLK_INFRA_66M_MCK, + .muxes_offs = CLK_INFRA_UART0_SEL, + .gates_offs = CLK_INFRA_GPT_STA, .fdivs = infra_fixed_divs, .muxes = infra_muxes, + .gates = infracfg_gates, + .flags = CLK_INFRASYS, }; static const struct udevice_id mt7981_fixed_pll_compat[] = { @@ -592,20 +584,9 @@ static const struct udevice_id mt7981_infracfg_compat[] = { {} }; -static const struct udevice_id mt7981_infracfg_ao_compat[] = { - { .compatible = "mediatek,mt7981-infracfg_ao" }, - {} -}; - static int mt7981_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree); -} - -static int mt7981_infracfg_ao_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree, - infracfg_ao_gates); + return mtk_common_clk_infrasys_init(dev, &mt7981_infracfg_clk_tree); } U_BOOT_DRIVER(mtk_clk_infracfg) = { @@ -618,14 +599,72 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { - .name = "mt7981-clock-infracfg-ao", +/* sgmiisys */ +static const struct mtk_gate_regs sgmii_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII(_id, _name, _parent, _shift) \ + { \ + .id = _id, .parent = _parent, .regs = &sgmii_cg_regs, \ + .shift = _shift, \ + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ + } + +static const struct mtk_gate sgmii0_cgs[] = { + GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_USB_TX250M, 2), + GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_USB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGM0_CK0_EN, "sgm0_ck0_en", CLK_TOP_USB_LN0_CK, 4), + GATE_SGMII(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", CLK_TOP_USB_CDR_CK, 5), +}; + +static int mt7981_sgmii0sys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, + sgmii0_cgs); +} + +static const struct udevice_id mt7981_sgmii0sys_compat[] = { + { .compatible = "mediatek,mt7981-sgmiisys_0", }, + {} +}; + +U_BOOT_DRIVER(mtk_clk_sgmii0sys) = { + .name = "mt7981-clock-sgmii0sys", .id = UCLASS_CLK, - .of_match = mt7981_infracfg_ao_compat, - .probe = mt7981_infracfg_ao_probe, + .of_match = mt7981_sgmii0sys_compat, + .probe = mt7981_sgmii0sys_probe, + .priv_auto = sizeof(struct mtk_cg_priv), + .ops = &mtk_clk_gate_ops, +}; + +static const struct mtk_gate sgmii1_cgs[] = { + GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_USB_TX250M, 2), + GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_USB_EQ_RX250M, 3), + GATE_SGMII(CLK_SGM1_CK1_EN, "sgm1_ck1_en", CLK_TOP_USB_LN0_CK, 4), + GATE_SGMII(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", CLK_TOP_USB_CDR_CK, 5), +}; + +static int mt7981_sgmii1sys_probe(struct udevice *dev) +{ + return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree, + sgmii1_cgs); +} + +static const struct udevice_id mt7981_sgmii1sys_compat[] = { + { .compatible = "mediatek,mt7981-sgmiisys_1", }, + {} +}; + +U_BOOT_DRIVER(mtk_clk_sgmii1sys) = { + .name = "mt7981-clock-sgmii1sys", + .id = UCLASS_CLK, + .of_match = mt7981_sgmii1sys_compat, + .probe = mt7981_sgmii1sys_probe, .priv_auto = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, }; /* ethsys */ @@ -643,10 +682,10 @@ static const struct mtk_gate_regs eth_cg_regs = { } static const struct mtk_gate eth_cgs[] = { - GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6), - GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7), - GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8), - GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15), + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X, 6), + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M, 7), + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M, 8), + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_WED_MCU, 15), }; static int mt7981_ethsys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c index efc3d4120b7..c5cc77243d0 100644 --- a/drivers/clk/mediatek/clk-mt7986.c +++ b/drivers/clk/mediatek/clk-mt7986.c @@ -18,6 +18,11 @@ #define MT7986_CLK_PDN 0x250 #define MT7986_CLK_PDN_EN_WRITE BIT(31) +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) +#define VOID_PARENT PARENT(-1, 0) + #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) @@ -29,177 +34,195 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk fixed_pll_clks[] = { - FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 2000000000), - FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 1440000000), - FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000), - FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_ARMPLL, CLK_XTAL, 2000000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 1440000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 760000000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), }; /* TOPCKGEN FIXED CLK */ static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000), + FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ static const struct mtk_fixed_factor top_fixed_divs[] = { - PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), - PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), - PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_MM_D8_D2, "mm_d8_d2", CK_APMIXED_MMPLL, 1, 16), - PLL_FACTOR(CK_TOP_MM_D3_D8, "mm_d3_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_U2_PHYD_CK, "cb_u2_phyd", CK_APMIXED_MMPLL, 1, 30), - PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, - 1), - PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), - PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), - PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), - PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), - PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, - 1), - PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), - PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET2_D3_D2, "net2_d3_d2", CK_APMIXED_NET2PLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_WEDMCU_760M, "cb_wedmcu_760m", - CK_APMIXED_WEDMCUPLL, 1, 1), - PLL_FACTOR(CK_TOP_WEDMCU_D5_D2, "wedmcu_d5_d2", CK_APMIXED_WEDMCUPLL, 1, - 10), - PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), - TOP_FACTOR(CK_TOP_CB_CKSQ_40M_D2, "cb_cksq_40m_d2", CK_TOP_CB_CKSQ_40M, + /* TOP Factors */ + TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2), - TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1, 1250), - TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1, 1220), - TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1, - 1), - TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1), - TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_416M, "emmc_416m", CK_TOP_EMMC_416M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_F_26M_ADC_CK, "f_26m_adc", CK_TOP_F_26M_ADC_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", - CK_TOP_NETSYS_MCU_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EIP_B, "eip_b", CK_TOP_EIP_B_SEL, 1, 1), - TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 2, 1), - TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1, - 1), + /* Not defined upstream and not used */ + /* TOP_FACTOR(CLK_TOP_A_TUNER, "a_tuner", CLK_TOP_A_TUNER_SEL, 2, 1), */ + /* MPLL */ + PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2), + /* MMPLL */ + PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MMPLL_D8_D2, "mmpll_d8_d2", CLK_APMIXED_MMPLL, 1, 16), + PLL_FACTOR(CLK_TOP_MMPLL_D3_D8, "mmpll_d3_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MMPLL_U2PHYD, "mmpll_u2phy", CLK_APMIXED_MMPLL, 1, 30), + /* APLL2 */ + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), + /* NET1PLL */ + PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + /* NET2PLL */ + PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D2, "net2pll_d4_d2", CLK_APMIXED_NET2PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET2PLL_D3_D2, "net2pll_d3_d2", CLK_APMIXED_NET2PLL, 1, 2), + /* WEDMCUPLL */ + PLL_FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "wedmcupll_d5_d2", CLK_APMIXED_WEDMCUPLL, 1, + 10), }; /* TOPCKGEN MUX PARENTS */ -static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D8, - CK_TOP_NET1_D8_D2, CK_TOP_NET2_D3_D2, - CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, - CK_TOP_WEDMCU_D5_D2, CK_TOP_CB_M_D8 }; +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D8), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8_D2), + TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), TOP_PARENT(CLK_TOP_MPLL_D8), +}; -static const int spinfi_parents[] = { - CK_TOP_CB_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_MM_D8_D2, CK_TOP_WEDMCU_D5_D2, - CK_TOP_MM_D3_D8, CK_TOP_CB_M_D8 +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D8_D2), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D3_D8), TOP_PARENT(CLK_TOP_MPLL_D8), }; -static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D2, - CK_TOP_NET2_D3_D2, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_WEDMCU_D5_D2 }; +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_WEDMCUPLL_D5_D2), +}; -static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4 }; +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), +}; -static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_NET2_D4_D2, - CK_TOP_CB_RTC_32K }; +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), TOP_PARENT(CLK_TOP_RTC_32K), +}; -static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D2 }; +static const struct mtk_parent emmc_250m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), +}; -static const int emmc_416m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_416M }; +static const struct mtk_parent emmc_416m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MPLL), +}; -static const int f_26m_adc_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 }; +static const struct mtk_parent f_26m_adc_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2 }; +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), +}; -static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_CB_NET2_D4 }; +static const struct mtk_parent sysaxi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D4), +}; -static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2, - CK_TOP_NET2_D4_D2 }; +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D4_D2), +}; -static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET2_D3_D2 }; +static const struct mtk_parent arm_db_main_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D3_D2), +}; -static const int arm_db_jtsel_parents[] = { -1, CK_TOP_CB_CKSQ_40M }; +static const struct mtk_parent arm_db_jtsel_parents[] = { + VOID_PARENT, TOP_PARENT(CLK_TOP_XTAL), +}; -static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4 }; +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4), +}; -static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_WEDMCU_760M, - CK_TOP_CB_MM_D2, CK_TOP_CB_NET1_D4, - CK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_mcu_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), + TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M, - CK_TOP_CB_WEDMCU_760M, - CK_TOP_CB_MM_D2 }; +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_APMIXED_NET2PLL), + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), TOP_PARENT(CLK_TOP_MMPLL_D2), +}; -static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_SGM_325M }; +static const struct mtk_parent sgm_325m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL), +}; -static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent sgm_reg_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 }; +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4), +}; -static const int conn_mcusys_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_MM_D2 }; +static const struct mtk_parent conn_mcusys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D2), +}; -static const int eip_b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M }; +static const struct mtk_parent eip_b_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), +}; -static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent a_tuner_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; +static const struct mtk_parent u2u3_sys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), +}; -static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_U2_PHYD_CK }; +static const struct mtk_parent da_u2_refsel_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_U2PHYD), +}; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -208,199 +231,167 @@ static const int da_u2_refsel_parents[] = { CK_TOP_CB_CKSQ_40M, .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent = _parents, \ + .gate_shift = _gate, .parent_flags = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* TOPCKGEN MUX_GATE */ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ - TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004, + TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), - TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004, + TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), - TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16, + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), - TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004, + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), /* CLK_CFG_1 */ - TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018, + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), - TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8, + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x1C0, 5), - TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16, + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), - TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, 0x1C0, 7), /* CLK_CFG_2 */ - TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7, 0x1C0, 8), - TOP_MUX(CK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020, + TOP_MUX(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel", emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15, 0x1C0, 9), - TOP_MUX(CK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020, + TOP_MUX(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 0x1C0, 10), - TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024, + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), /* CLK_CFG_3 */ - TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, 0x1C0, 12), - TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034, + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), - TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034, + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), - TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, + TOP_MUX(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15), /* CLK_CFG_4 */ - TOP_MUX(CK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents, + TOP_MUX(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel", arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7, 0x1C0, 16), - TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044, + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), - TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), - TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, + TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x1C0, 19), /* CLK_CFG_5 */ - TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050, + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, 0x1C0, 20), - TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, + TOP_MUX(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 0x1C0, 21), - TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050, + TOP_MUX(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), - TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054, + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), /* CLK_CFG_6 */ - TOP_MUX(CK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents, + TOP_MUX(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel", conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7, 0x1C0, 24), - TOP_MUX(CK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064, + TOP_MUX(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents, 0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25), - TOP_MUX(CK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060, + TOP_MUX(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel", f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), - TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060, + TOP_MUX(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), /* CLK_CFG_7 */ - TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070, + TOP_MUX(CLK_TOP_F26M_SEL, "csw_f26m_sel", f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, 0x1C0, 28), - TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), - TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070, + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x1C0, 30), - TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074, + TOP_MUX(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents, 0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0), /* CLK_CFG_8 */ - TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080, + TOP_MUX(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7, 0x1C4, 1), - TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080, + TOP_MUX(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15, 0x1C4, 2), - TOP_MUX(CK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents, + TOP_MUX(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel", da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1, 23, 0x1C4, 3), - TOP_MUX(CK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents, + TOP_MUX(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel", da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1, 31, 0x1C4, 4), /* CLK_CFG_9 */ - TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents, + TOP_MUX(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7, 0x1C4, 5), }; /* INFRA FIXED DIV */ static const struct mtk_fixed_factor infra_fixed_divs[] = { - TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2), - TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1), - INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_EIP_CK, "infra_eip", CK_TOP_EIP_B, 1, 1), - INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, - 1), - TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1, - 1), - TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL, - 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL, - 1, 1), - TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1), - TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1, - 1), - INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_416M, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_250M, - 1, 1), - TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1), - TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1, - 1), - TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux", - CK_TOP_PEXTP_TL, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_HD_133M, "infra_hd_133m", CK_TOP_SYSAXI, 1, 1), + TOP_FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", CLK_TOP_SYSAXI_SEL, 1, 2), }; /* INFRASYS MUX PARENTS */ -static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART }; -static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 }; -static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 }; +static const struct mtk_parent infra_uart0_parents[] = { + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_UART_SEL) +}; + +static const struct mtk_parent infra_spi0_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPI_SEL) +}; + +static const struct mtk_parent infra_spi1_parents[] = { + TOP_PARENT(CLK_TOP_I2C_SEL), + TOP_PARENT(CLK_TOP_SPINFI_SEL) +}; -static const int infra_pwm_bsel_parents[] = { CK_INFRA_CK_F32K, - CK_INFRA_CK_F26M, - CK_INFRA_66M_MCK, CK_INFRA_PWM }; +static const struct mtk_parent infra_pwm_bsel_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + INFRA_PARENT(CLK_INFRA_SYSAXI_D2), + TOP_PARENT(CLK_TOP_PWM_SEL) +}; -static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M, - -1, CK_INFRA_PCIE_CK }; +static const struct mtk_parent infra_pcie_parents[] = { + TOP_PARENT(CLK_TOP_RTC_32P7K), + TOP_PARENT(CLK_TOP_F26M_SEL), + TOP_PARENT(CLK_TOP_XTAL), + TOP_PARENT(CLK_TOP_PEXTP_TL_SEL) +}; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ { \ .id = _id, .mux_reg = (_reg) + 0x8, \ .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ - .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* INFRA MUX */ static const struct mtk_composite infra_muxes[] = { /* MODULE_CLK_SEL_0 */ - INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents, 0x10, 0, 1), - INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents, 0x10, 1, 1), - INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, + INFRA_MUX(CLK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents, 0x10, 2, 1), - INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10, 4, 1), - INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, + INFRA_MUX(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10, 5, 1), - INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm_bsel_parents, 0x10, 9, 2), - INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm_bsel_parents, 0x10, 11, 2), - INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, + INFRA_MUX(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents, 0x10, 13, 2), /* MODULE_CLK_SEL_1 */ - INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, + INFRA_MUX(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20, 0, 2), }; @@ -422,113 +413,131 @@ static const struct mtk_gate_regs infra_2_cg_regs = { .sta_ofs = 0x68, }; -#define GATE_INFRA0(_id, _name, _parent, _shift) \ +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA1(_id, _name, _parent, _shift) \ +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA2(_id, _name, _parent, _shift) \ +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) /* INFRA GATE */ -static const struct mtk_gate infracfg_ao_gates[] = { +static const struct mtk_gate infracfg_gates[] = { /* INFRA0 */ - GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0), - GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1), - GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2), - GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3), - GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4), - GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6), - GATE_INFRA0(CK_INFRA_EIP97_CK, "infra_eip97", CK_INFRA_EIP_CK, 7), - GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8), - GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9), - GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10), - GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK, - 11), - GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK, - 13), - GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M, - 14), - GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15), - GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16), - GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24), - GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25), - GATE_INFRA0(CK_INFRA_TRNG_CK, "infra_trng", CK_INFRA_HD_133M, 26), + GATE_INFRA0_INFRA(CLK_INFRA_GPT_STA, "infra_gpt_sta", CLK_INFRA_SYSAXI_D2, 0), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_HCK, "infra_pwm_hck", CLK_INFRA_SYSAXI_D2, 1), + GATE_INFRA0_INFRA(CLK_INFRA_PWM_STA, "infra_pwm_sta", CLK_INFRA_PWM_BSEL, 2), + GATE_INFRA0_INFRA(CLK_INFRA_PWM1_CK, "infra_pwm1", CLK_INFRA_PWM1_SEL, 3), + GATE_INFRA0_INFRA(CLK_INFRA_PWM2_CK, "infra_pwm2", CLK_INFRA_PWM2_SEL, 4), + GATE_INFRA0_TOP(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", CLK_TOP_SYSAXI_SEL, 6), + GATE_INFRA0_TOP(CLK_INFRA_EIP97_CK, "infra_eip97", CLK_TOP_EIP_B_SEL, 7), + GATE_INFRA0_TOP(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", CLK_TOP_SYSAXI_SEL, 8), + GATE_INFRA0_TOP(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", CLK_TOP_F26M_SEL, 9), + GATE_INFRA0_TOP(CLK_INFRA_AUD_L_CK, "infra_aud_l", CLK_TOP_AUD_L_SEL, 10), + GATE_INFRA0_TOP(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", CLK_TOP_A1SYS_SEL, + 11), + GATE_INFRA0_TOP(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CLK_TOP_A_TUNER_SEL, + 13), + GATE_INFRA0_TOP(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CLK_TOP_F26M_SEL, + 14), + GATE_INFRA0_INFRA(CLK_INFRA_DBG_CK, "infra_dbg", CLK_INFRA_SYSAXI_D2, 15), + GATE_INFRA0_INFRA(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", CLK_INFRA_SYSAXI_D2, 16), + GATE_INFRA0_INFRA(CLK_INFRA_SEJ_CK, "infra_sej", CLK_INFRA_SYSAXI_D2, 24), + GATE_INFRA0_TOP(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", CLK_TOP_F26M_SEL, 25), /* INFRA1 */ - GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0), - GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1), - GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2), - GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3), - GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4), - GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8), - GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK, - 9), - GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10), - GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11), - GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12), - GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK, - 13), - GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK, - 14), - GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15), - GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16), - GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", - CK_INFRA_FMSDC_HCK_CK, 17), - GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m", - CK_INFRA_PERI_133M, 18), - GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK, - 19), - GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_INFRA_CK_F26M, 20), - GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_INFRA_CK_F26M, 21), - GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK, - 23), + GATE_INFRA1_TOP(CLK_INFRA_THERM_CK, "infra_therm", CLK_TOP_F26M_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_I2C0_CK, "infra_i2co", CLK_TOP_I2C_SEL, 1), + GATE_INFRA1_INFRA(CLK_INFRA_UART0_CK, "infra_uart0", CLK_INFRA_UART0_SEL, 2), + GATE_INFRA1_INFRA(CLK_INFRA_UART1_CK, "infra_uart1", CLK_INFRA_UART1_SEL, 3), + GATE_INFRA1_INFRA(CLK_INFRA_UART2_CK, "infra_uart2", CLK_INFRA_UART2_SEL, 4), + GATE_INFRA1_TOP(CLK_INFRA_NFI1_CK, "infra_nfi1", CLK_TOP_NFI1X_SEL, 8), + GATE_INFRA1_TOP(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", CLK_TOP_SPINFI_SEL, + 9), + GATE_INFRA1_INFRA(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CLK_INFRA_SYSAXI_D2, 10), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_CK, "infra_spi0", CLK_INFRA_SPI0_SEL, 11), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_CK, "infra_spi1", CLK_INFRA_SPI1_SEL, 12), + GATE_INFRA1_INFRA(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CLK_INFRA_SYSAXI_D2, + 13), + GATE_INFRA1_INFRA(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CLK_INFRA_SYSAXI_D2, + 14), + GATE_INFRA1_TOP(CLK_INFRA_FRTC_CK, "infra_frtc", CLK_TOP_RTC_32K, 15), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_CK, "infra_msdc", CLK_TOP_EMMC_416M_SEL, 16), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", + CLK_TOP_EMMC_250M_SEL, 17), + GATE_INFRA1_TOP(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", + CLK_TOP_SYSAXI_SEL, 18), + GATE_INFRA1_INFRA(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CLK_INFRA_SYSAXI_D2, + 19), + GATE_INFRA1_INFRA(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", CLK_INFRA_ADC_FRC_CK, 20), + GATE_INFRA1_TOP(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", CLK_TOP_F26M_SEL, 21), + GATE_INFRA1_TOP(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CLK_TOP_NFI1X_SEL, + 23), /* INFRA2 */ - GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK, - 0), - GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK, - 1), - GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK, - 2), - GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3), - GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13), - GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15), - GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", CLK_TOP_SYSAXI_SEL, + 0), + GATE_INFRA2_INFRA(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CLK_INFRA_SYSAXI_D2, + 1), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CLK_TOP_U2U3_SYS_SEL, + 2), + GATE_INFRA2_TOP(CLK_INFRA_IUSB_CK, "infra_iusb", CLK_TOP_U2U3_SEL, 3), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_CK, "infra_ipcie", CLK_TOP_PEXTP_TL_SEL, 12), + GATE_INFRA2_TOP(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", CLK_TOP_XTAL, 13), + GATE_INFRA2_TOP(CLK_INFRA_IPCIER_CK, "infra_ipcier", CLK_TOP_F26M_SEL, 14), + GATE_INFRA2_TOP(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", CLK_TOP_SYSAXI_SEL, 15), + /* upstream linux unordered */ + GATE_INFRA0_TOP(CLK_INFRA_TRNG_CK, "infra_trng", CLK_TOP_SYSAXI_SEL, 26), }; static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = { .fdivs_offs = CLK_APMIXED_NR_CLK, .xtal_rate = 40 * MHZ, .fclks = fixed_pll_clks, + .flags = CLK_APMIXED, }; static const struct mtk_clk_tree mt7986_topckgen_clk_tree = { - .fdivs_offs = CK_TOP_CB_M_416M, - .muxes_offs = CK_TOP_NFI1X_SEL, + .fdivs_offs = CLK_TOP_XTAL_D2, + .muxes_offs = CLK_TOP_NFI1X_SEL, .fclks = top_fixed_clks, .fdivs = top_fixed_divs, .muxes = top_muxes, - .flags = CLK_BYPASS_XTAL, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, }; static const struct mtk_clk_tree mt7986_infracfg_clk_tree = { - .fdivs_offs = CK_INFRA_CK_F26M, - .muxes_offs = CK_INFRA_UART0_SEL, + .fdivs_offs = CLK_INFRA_SYSAXI_D2, + .muxes_offs = CLK_INFRA_UART0_SEL, + .gates_offs = CLK_INFRA_GPT_STA, .fdivs = infra_fixed_divs, .muxes = infra_muxes, + .gates = infracfg_gates, + .flags = CLK_INFRASYS, }; static const struct udevice_id mt7986_fixed_pll_compat[] = { @@ -582,20 +591,9 @@ static const struct udevice_id mt7986_infracfg_compat[] = { {} }; -static const struct udevice_id mt7986_infracfg_ao_compat[] = { - { .compatible = "mediatek,mt7986-infracfg_ao" }, - {} -}; - static int mt7986_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree); -} - -static int mt7986_infracfg_ao_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7986_infracfg_clk_tree, - infracfg_ao_gates); + return mtk_common_clk_infrasys_init(dev, &mt7986_infracfg_clk_tree); } U_BOOT_DRIVER(mtk_clk_infracfg) = { @@ -608,16 +606,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_infracfg_ao) = { - .name = "mt7986-clock-infracfg-ao", - .id = UCLASS_CLK, - .of_match = mt7986_infracfg_ao_compat, - .probe = mt7986_infracfg_ao_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - /* ethsys */ static const struct mtk_gate_regs eth_cg_regs = { .sta_ofs = 0x30, @@ -631,11 +619,11 @@ static const struct mtk_gate_regs eth_cg_regs = { } static const struct mtk_gate eth_cgs[] = { - GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 7), - GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 8), - GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8), - GATE_ETH(CK_ETH_WOCPU1_EN, "eth_wocpu1_en", CK_TOP_NETSYS_WED_MCU, 14), - GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15), + GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", CLK_TOP_NETSYS_2X_SEL, 7), + GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", CLK_TOP_SGM_325M_SEL, 8), + GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", CLK_TOP_SGM_325M_SEL, 8), + GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", CLK_TOP_NETSYS_MCU_SEL, 14), + GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", CLK_TOP_NETSYS_MCU_SEL, 15), }; static int mt7986_ethsys_probe(struct udevice *dev) diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c index 32b04511781..8f4e8f4e8c9 100644 --- a/drivers/clk/mediatek/clk-mt7988.c +++ b/drivers/clk/mediatek/clk-mt7988.c @@ -35,225 +35,243 @@ /* FIXED PLLS */ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = { - FIXED_CLK(CK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000), - FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000), - FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000), - FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000), - FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), - FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000), - FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), - FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000), - FIXED_CLK(CK_APMIXED_ARM_B, CLK_XTAL, 1500000000), - FIXED_CLK(CK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000), - FIXED_CLK(CK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000), - FIXED_CLK(CK_APMIXED_MSDCPLL, CLK_XTAL, 400000000), + FIXED_CLK(CLK_APMIXED_NETSYSPLL, CLK_XTAL, 850000000), + FIXED_CLK(CLK_APMIXED_MPLL, CLK_XTAL, 416000000), + FIXED_CLK(CLK_APMIXED_MMPLL, CLK_XTAL, 720000000), + FIXED_CLK(CLK_APMIXED_APLL2, CLK_XTAL, 196608000), + FIXED_CLK(CLK_APMIXED_NET1PLL, CLK_XTAL, 2500000000), + FIXED_CLK(CLK_APMIXED_NET2PLL, CLK_XTAL, 800000000), + FIXED_CLK(CLK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000), + FIXED_CLK(CLK_APMIXED_SGMPLL, CLK_XTAL, 325000000), + FIXED_CLK(CLK_APMIXED_ARM_B, CLK_XTAL, 1500000000), + FIXED_CLK(CLK_APMIXED_CCIPLL2_B, CLK_XTAL, 960000000), + FIXED_CLK(CLK_APMIXED_USXGMIIPLL, CLK_XTAL, 644533000), + FIXED_CLK(CLK_APMIXED_MSDCPLL, CLK_XTAL, 400000000), +}; + +/* TOPCKGEN FIXED CLK */ +static const struct mtk_fixed_clk topckgen_mtk_fixed_clks[] = { + FIXED_CLK(CLK_TOP_XTAL, CLK_XTAL, 40000000), }; /* TOPCKGEN FIXED DIV */ static const struct mtk_fixed_factor topckgen_mtk_fixed_factors[] = { - XTAL_FACTOR(CK_TOP_CB_CKSQ_40M, "cb_cksq_40m", CLK_XTAL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8), - PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16), - PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15), - PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4), - PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12), - PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1, - 1), - PLL_FACTOR(CK_TOP_CB_APLL2_D4, "cb_apll2_d4", CK_APMIXED_APLL2, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4), - PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5), - PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10), - PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20), - PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8), - PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32), - PLL_FACTOR(CK_TOP_NET1_D8_D8, "net1_d8_d8", CK_APMIXED_NET1PLL, 1, 64), - PLL_FACTOR(CK_TOP_NET1_D8_D16, "net1_d8_d16", CK_APMIXED_NET1PLL, 1, - 128), - PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1, - 1), - PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2), - PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4), - PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16), - PLL_FACTOR(CK_TOP_NET2_D4_D8, "net2_d4_d8", CK_APMIXED_NET2PLL, 1, 32), - PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6), - PLL_FACTOR(CK_TOP_CB_NET2_D8, "cb_net2_d8", CK_APMIXED_NET2PLL, 1, 8), - PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", - CK_APMIXED_WEDMCUPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_NETSYS_850M, "cb_netsys_850m", - CK_APMIXED_NETSYSPLL, 1, 1), - PLL_FACTOR(CK_TOP_CB_MSDC_400M, "cb_msdc_400m", CK_APMIXED_MSDCPLL, 1, - 1), - TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2), - TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_XTAL_D2, "xtal_d2", CLK_TOP_XTAL, 1, 2), + TOP_FACTOR(CLK_TOP_RTC_32K, "rtc_32k", CLK_TOP_XTAL, 1, 1250), - TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1, + TOP_FACTOR(CLK_TOP_RTC_32P7K, "rtc_32p7k", CLK_TOP_XTAL, 1, 1220), - TOP_FACTOR(CK_TOP_INFRA_F32K, "csw_infra_f32k", CK_TOP_CB_RTC_32P7K, 1, - 1), - XTAL_FACTOR(CK_TOP_CKSQ_SRC, "cksq_src", CLK_XTAL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NETSYS_GSW, "netsys_gsw", CK_TOP_NETSYS_GSW_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", - CK_TOP_NETSYS_MCU_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EIP197, "eip197", CK_TOP_EIP197_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_250M, "emmc_250m", CK_TOP_EMMC_250M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1), - TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_SYS, "usb_sys", CK_TOP_USB_SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_SYS_P1, "usb_sys_p1", CK_TOP_USB_SYS_P1_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_USB_XHCI, "usb_xhci", CK_TOP_USB_XHCI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_USB_XHCI_P1, "usb_xhci_p1", CK_TOP_USB_XHCI_P1_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1, - 1), - TOP_FACTOR(CK_TOP_USB_FRMCNT_P1, "usb_frmcnt_p1", - CK_TOP_USB_FRMCNT_P1_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_AUD_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1), - TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1), - TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1), - TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1), - TOP_FACTOR(CK_TOP_INFRA_F26M, "csw_infra_f26m", CK_TOP_INFRA_F26M_SEL, - 1, 1), - TOP_FACTOR(CK_TOP_USB_REF, "usb_ref", CK_TOP_CKSQ_SRC, 1, 1), - TOP_FACTOR(CK_TOP_USB_CK_P1, "usb_ck_p1", CK_TOP_CKSQ_SRC, 1, 1), + PLL_FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", CLK_APMIXED_MPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", CLK_APMIXED_MPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", CLK_APMIXED_MPLL, 1, 8), + PLL_FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", CLK_APMIXED_MPLL, 1, 16), + PLL_FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", CLK_APMIXED_MMPLL, 1, 2), + PLL_FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", CLK_APMIXED_MMPLL, 1, 15), + PLL_FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", CLK_APMIXED_MMPLL, 1, 4), + PLL_FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", CLK_APMIXED_MMPLL, 1, 12), + PLL_FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", CLK_APMIXED_MMPLL, 1, 8), + PLL_FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", CLK_APMIXED_APLL2, 1, 4), + PLL_FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", CLK_APMIXED_NET1PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", CLK_APMIXED_NET1PLL, 1, 5), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", CLK_APMIXED_NET1PLL, 1, 10), + PLL_FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", CLK_APMIXED_NET1PLL, 1, 20), + PLL_FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", CLK_APMIXED_NET1PLL, 1, 8), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", CLK_APMIXED_NET1PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", CLK_APMIXED_NET1PLL, 1, 32), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", CLK_APMIXED_NET1PLL, 1, 64), + PLL_FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", CLK_APMIXED_NET1PLL, 1, + 128), + PLL_FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", CLK_APMIXED_NET2PLL, 1, 2), + PLL_FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", CLK_APMIXED_NET2PLL, 1, 4), + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", CLK_APMIXED_NET2PLL, 1, 16), + PLL_FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", CLK_APMIXED_NET2PLL, 1, 32), + PLL_FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", CLK_APMIXED_NET2PLL, 1, 6), + PLL_FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", CLK_APMIXED_NET2PLL, 1, 8), }; /* TOPCKGEN MUX PARENTS */ -static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2, - CK_TOP_CB_MM_D2 }; +#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED) +#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN) -static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D5, - CK_TOP_NET1_D5_D2 }; +static const struct mtk_parent netsys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D2), +}; -static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M, - CK_TOP_CB_MM_720M }; +static const struct mtk_parent netsys_500m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), +}; -static const int netsys_gsw_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D4, - CK_TOP_CB_NET1_D5 }; +static const struct mtk_parent netsys_2x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), + APMIXED_PARENT(CLK_APMIXED_MMPLL), +}; -static const int eth_gmii_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 }; +static const struct mtk_parent netsys_gsw_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int netsys_mcu_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_800M, CK_TOP_CB_MM_720M, - CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5, CK_TOP_CB_M_416M +static const struct mtk_parent eth_gmii_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), }; -static const int eip197_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NETSYS_850M, CK_TOP_CB_NET2_800M, - CK_TOP_CB_MM_720M, CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5 +static const struct mtk_parent netsys_mcu_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), + APMIXED_PARENT(CLK_APMIXED_MMPLL), TOP_PARENT(CLK_TOP_NET1PLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D5), APMIXED_PARENT(CLK_APMIXED_MPLL), }; -static const int axi_infra_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D8_D2 }; +static const struct mtk_parent eip197_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NETSYSPLL), + APMIXED_PARENT(CLK_APMIXED_NET2PLL), APMIXED_PARENT(CLK_APMIXED_MMPLL), + TOP_PARENT(CLK_TOP_NET1PLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D5), +}; -static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent axi_infra_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), +}; -static const int emmc_250m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D2, - CK_TOP_CB_MM_D4 }; +static const struct mtk_parent uart_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D8), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int emmc_400m_parents[] = { - CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MSDC_400M, CK_TOP_CB_MM_D2, - CK_TOP_CB_M_D2, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2 +static const struct mtk_parent emmc_250m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4), }; -static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2, - CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent emmc_400m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_MSDCPLL), + TOP_PARENT(CLK_TOP_MMPLL_D2), TOP_PARENT(CLK_TOP_MPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), +}; -static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4, - CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6, - CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8, - CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 }; +static const struct mtk_parent spi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), + TOP_PARENT(CLK_TOP_MMPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET2PLL_D6), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4, - CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 }; +static const struct mtk_parent nfi1x_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D4), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), TOP_PARENT(CLK_TOP_NET2PLL_D6), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_MMPLL_D8), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), TOP_PARENT(CLK_TOP_MPLL_D8), +}; -static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2, - CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4, - CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; +static const struct mtk_parent spinfi_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_XTAL), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), + TOP_PARENT(CLK_TOP_MMPLL_D6_D2), TOP_PARENT(CLK_TOP_MPLL_D8), +}; -static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4, - CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent pwm_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D2), + TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), TOP_PARENT(CLK_TOP_MPLL_D4), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), TOP_PARENT(CLK_TOP_RTC_32K), +}; -static const int pcie_mbist_250m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D5_D2 }; +static const struct mtk_parent i2c_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D4), + TOP_PARENT(CLK_TOP_MPLL_D4), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D6, CK_TOP_CB_MM_D8, - CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K }; +static const struct mtk_parent pcie_mbist_250m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5_D2), +}; -static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_MM_D3_D5 }; +static const struct mtk_parent pextp_tl_ck_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D6), + TOP_PARENT(CLK_TOP_MMPLL_D8), TOP_PARENT(CLK_TOP_MPLL_D8_D2), + TOP_PARENT(CLK_TOP_RTC_32K), +}; -static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M }; +static const struct mtk_parent usb_frmcnt_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MMPLL_D3_D5), +}; -static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_D4 }; +static const struct mtk_parent aud_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2), +}; -static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M, - CK_TOP_M_D8_D2 }; +static const struct mtk_parent a1sys_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_APLL2_D4), +}; + +static const struct mtk_parent aud_l_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_APLL2), + TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int sspxtp_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 }; +static const struct mtk_parent sspxtp_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_MPLL_D8_D2), +}; -static const int usxgmii_sbus_0_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET1_D8_D4 }; +static const struct mtk_parent usxgmii_sbus_0_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D8_D4), +}; -static const int sgm_0_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M }; +static const struct mtk_parent sgm_0_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL), +}; -static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 }; +static const struct mtk_parent sysapb_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D3_D2), +}; -static const int eth_refck_50m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_NET2_D4_D4 }; +static const struct mtk_parent eth_refck_50m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4_D4), +}; -static const int eth_sys_200m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D4 }; +static const struct mtk_parent eth_sys_200m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D4), +}; -static const int eth_xgmii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET1_D8_D8, - CK_TOP_NET1_D8_D16 }; +static const struct mtk_parent eth_xgmii_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET1PLL_D8_D8), + TOP_PARENT(CLK_TOP_NET1PLL_D8_D16), +}; -static const int bus_tops_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5, - CK_TOP_CB_NET2_D2 }; +static const struct mtk_parent bus_tops_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D5), + TOP_PARENT(CLK_TOP_NET2PLL_D2), +}; -static const int npu_tops_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_800M }; +static const struct mtk_parent npu_tops_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_NET2PLL), +}; -static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, - CK_TOP_CB_WEDMCU_208M }; +static const struct mtk_parent dramc_md32_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_MPLL_D2), + APMIXED_PARENT(CLK_APMIXED_WEDMCUPLL), +}; -static const int da_xtp_glb_p0_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D8 }; +static const struct mtk_parent da_xtp_glb_p0_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D8), +}; -static const int mcusys_backup_625m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET1_D4 }; +static const struct mtk_parent mcusys_backup_625m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET1PLL_D4), +}; -static const int macsec_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_SGM_325M, - CK_TOP_CB_NET1_D8 }; +static const struct mtk_parent macsec_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), APMIXED_PARENT(CLK_APMIXED_SGMPLL), + TOP_PARENT(CLK_TOP_NET1PLL_D8), +}; -static const int netsys_tops_400m_parents[] = { CK_TOP_CB_CKSQ_40M, - CK_TOP_CB_NET2_D2 }; +static const struct mtk_parent netsys_tops_400m_parents[] = { + TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2), +}; -static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 }; +static const struct mtk_parent eth_mii_parents[] = { + TOP_PARENT(CLK_TOP_XTAL_D2), TOP_PARENT(CLK_TOP_NET2PLL_D4_D8), +}; #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ _shift, _width, _gate, _upd_ofs, _upd) \ @@ -262,278 +280,204 @@ static const int eth_mii_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_NET2_D4_D8 }; .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \ .upd_shift = _upd, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \ - .gate_shift = _gate, .parent = _parents, \ + .gate_shift = _gate, .parent_flags = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ } /* TOPCKGEN MUX_GATE */ static const struct mtk_composite topckgen_mtk_muxes[] = { - TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8, + TOP_MUX(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x0, 0x4, 0x8, 0, 2, 7, 0x1c0, 0), - TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, + TOP_MUX(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x0, 0x4, 0x8, 8, 2, 15, 0x1c0, 1), - TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0, + TOP_MUX(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x0, 0x4, 0x8, 16, 2, 23, 0x1c0, 2), - TOP_MUX(CK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, + TOP_MUX(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x0, 0x4, 0x8, 24, 2, 31, 0x1c0, 3), - TOP_MUX(CK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10, + TOP_MUX(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x10, 0x14, 0x18, 0, 1, 7, 0x1c0, 4), - TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, + TOP_MUX(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents, 0x10, 0x14, 0x18, 8, 3, 15, 0x1c0, 5), - TOP_MUX(CK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", + TOP_MUX(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", netsys_mcu_parents, 0x10, 0x14, 0x18, 16, 3, 23, 0x1c0, 6), - TOP_MUX(CK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14, + TOP_MUX(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, 0x10, 0x14, 0x18, 24, 3, 31, 0x1c0, 7), - TOP_MUX(CK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20, + TOP_MUX(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", axi_infra_parents, 0x20, 0x24, 0x28, 0, 1, 7, 0x1c0, 8), - TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8, + TOP_MUX(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x20, 0x24, 0x28, 8, 2, 15, 0x1c0, 9), - TOP_MUX(CK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", emmc_250m_parents, 0x20, 0x24, 0x28, 16, 2, 23, 0x1c0, 10), - TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, + TOP_MUX(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20, 0x24, 0x28, 24, 3, 31, 0x1c0, 11), - TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3, + TOP_MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x30, 0x34, 0x38, 0, 3, 7, 0x1c0, 12), - TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x30, 0x34, 0x38, 8, 3, 15, 0x1c0, 13), - TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38, + TOP_MUX(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x30, 0x34, 0x38, 16, 3, 23, 0x1c0, 14), - TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34, + TOP_MUX(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x30, 0x34, 0x38, 24, 3, 31, 0x1c0, 15), - TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3, + TOP_MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x40, 0x44, 0x48, 0, 3, 7, 0x1c0, 16), - TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2, + TOP_MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x40, 0x44, 0x48, 8, 2, 15, 0x1c0, 17), - TOP_MUX(CK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", + TOP_MUX(CLK_TOP_PCIE_MBIST_250M_SEL, "pcie_mbist_250m_sel", pcie_mbist_250m_parents, 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18), - TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, + TOP_MUX(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents, 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19), - TOP_MUX(CK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", + TOP_MUX(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_ck_p1_sel", pextp_tl_ck_parents, 0x50, 0x54, 0x58, 0, 3, 7, 0x1c0, 20), - TOP_MUX(CK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel", + TOP_MUX(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_ck_p2_sel", pextp_tl_ck_parents, 0x50, 0x54, 0x58, 8, 3, 15, 0x1c0, 21), - TOP_MUX(CK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel", + TOP_MUX(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_ck_p3_sel", pextp_tl_ck_parents, 0x50, 0x54, 0x58, 16, 3, 23, 0x1c0, 22), - TOP_MUX(CK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54, + TOP_MUX(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", eth_gmii_parents, 0x50, 0x54, 0x58, 24, 1, 31, 0x1c0, 23), - TOP_MUX(CK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60, + TOP_MUX(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", eth_gmii_parents, 0x60, 0x64, 0x68, 0, 1, 7, 0x1c0, 24), - TOP_MUX(CK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60, + TOP_MUX(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", eth_gmii_parents, 0x60, 0x64, 0x68, 8, 1, 15, 0x1c0, 25), - TOP_MUX(CK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, + TOP_MUX(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", eth_gmii_parents, 0x60, 0x64, 0x68, 16, 1, 23, 0x1c0, 26), - TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, + TOP_MUX(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents, 0x60, 0x64, 0x68, 24, 1, 31, 0x1c0, 27), - TOP_MUX(CK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", + TOP_MUX(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", usb_frmcnt_parents, 0x70, 0x74, 0x78, 0, 1, 7, 0x1c0, 28), - TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1, + TOP_MUX(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x70, 0x74, 0x78, 8, 1, 15, 0x1c0, 29), - TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78, + TOP_MUX(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x70, 0x74, 0x78, 16, 1, 23, 0x1c0, 30), - TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78, + TOP_MUX(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x70, 0x74, 0x78, 24, 2, 31, 0x1c4, 0), - TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84, + TOP_MUX(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1), - TOP_MUX(CK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84, + TOP_MUX(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, 0x80, 0x84, 0x88, 8, 1, 15, 0x1c4, 2), - TOP_MUX(CK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84, + TOP_MUX(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", sspxtp_parents, 0x80, 0x84, 0x88, 16, 1, 23, 0x1c4, 3), - TOP_MUX(CK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", + TOP_MUX(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", usxgmii_sbus_0_parents, 0x80, 0x84, 0x88, 24, 1, 31, 0x1c4, 4), - TOP_MUX(CK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", + TOP_MUX(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 0, 1, 7, 0x1c4, 5), - TOP_MUX(CK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98, + TOP_MUX(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, 0x90, 0x94, 0x98, 8, 1, 15, 0x1c4, 6), - TOP_MUX(CK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, + TOP_MUX(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", usxgmii_sbus_0_parents, 0x90, 0x94, 0x98, 16, 1, 23, 0x1c4, 7), - TOP_MUX(CK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98, + TOP_MUX(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, 0x90, 0x94, 0x98, 24, 1, 31, 0x1c4, 8), - TOP_MUX(CK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, + TOP_MUX(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", usxgmii_sbus_0_parents, 0xa0, 0xa4, 0xa8, 0, 1, 7, 0x1c4, 9), - TOP_MUX(CK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", sspxtp_parents, 0xa0, 0xa4, 0xa8, 8, 1, 15, 0x1c4, 10), - TOP_MUX(CK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", sspxtp_parents, 0xa0, 0xa4, 0xa8, 16, 1, 23, 0x1c4, 11), - TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4, + TOP_MUX(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", axi_infra_parents, 0xa0, 0xa4, 0xa8, 24, 1, 31, 0x1c4, 12), - TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4, + TOP_MUX(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0xb0, 0xb4, 0xb8, 0, 1, 7, 0x1c4, 13), - TOP_MUX(CK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", + TOP_MUX(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", eth_refck_50m_parents, 0xb0, 0xb4, 0xb8, 8, 1, 15, 0x1c4, 14), - TOP_MUX(CK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", + TOP_MUX(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", eth_sys_200m_parents, 0xb0, 0xb4, 0xb8, 16, 1, 23, 0x1c4, 15), - TOP_MUX(CK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, + TOP_MUX(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", pcie_mbist_250m_parents, 0xb0, 0xb4, 0xb8, 24, 1, 31, 0x1c4, 16), - TOP_MUX(CK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0, + TOP_MUX(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", eth_xgmii_parents, 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x1c4, 17), - TOP_MUX(CK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0, + TOP_MUX(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", bus_tops_parents, 0xc0, 0xc4, 0xc8, 8, 2, 15, 0x1c4, 18), - TOP_MUX(CK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0, + TOP_MUX(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", npu_tops_parents, 0xc0, 0xc4, 0xc8, 16, 1, 23, 0x1c4, 19), - TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8, + TOP_MUX(CLK_TOP_DRAMC_SEL, "dramc_sel", sspxtp_parents, 0xc0, 0xc4, 0xc8, 24, 1, 31, 0x1c4, 20), - TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, + TOP_MUX(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents, 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x1c4, 21), - TOP_MUX(CK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x1c4, 22), - TOP_MUX(CK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4, + TOP_MUX(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", sspxtp_parents, 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x1c4, 23), - TOP_MUX(CK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4, + TOP_MUX(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", sspxtp_parents, 0xd0, 0xd4, 0xd8, 24, 1, 31, 0x1c4, 24), - TOP_MUX(CK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4, + TOP_MUX(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", sspxtp_parents, 0xe0, 0xe4, 0xe8, 0, 1, 7, 0x1c4, 25), - TOP_MUX(CK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4, + TOP_MUX(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", sspxtp_parents, 0xe0, 0xe4, 0xe8, 8, 1, 15, 0x1c4, 26), - TOP_MUX(CK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 16, 1, 23, 0x1c4, 27), - TOP_MUX(CK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", da_xtp_glb_p0_parents, 0xe0, 0xe4, 0xe8, 24, 1, 31, 0x1c4, 28), - TOP_MUX(CK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x1c4, 29), - TOP_MUX(CK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", + TOP_MUX(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", da_xtp_glb_p0_parents, 0xf0, 0xf4, 0xf8, 8, 1, 15, 0x1c4, 30), - TOP_MUX(CK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16, + TOP_MUX(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 16, 1, 23, 0x1c8, 0), - TOP_MUX(CK_TOP_DA_SELM_XTAL_SEL, "da_selm_xtal_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0xf0, 0xf4, 0xf8, 24, 1, 31, 0x1c8, 1), - TOP_MUX(CK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104, + TOP_MUX(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, 0x100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), - TOP_MUX(CK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, + TOP_MUX(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", sspxtp_parents, 0x100, 0x104, 0x108, 8, 1, 15, 0x1c8, 3), - TOP_MUX(CK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", + TOP_MUX(CLK_TOP_MCUSYS_BACKUP_625M_SEL, "mcusys_backup_625m_sel", mcusys_backup_625m_parents, 0x100, 0x104, 0x108, 16, 1, 23, 0x1c8, 4), - TOP_MUX(CK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", + TOP_MUX(CLK_TOP_NETSYS_SYNC_250M_SEL, "netsys_sync_250m_sel", pcie_mbist_250m_parents, 0x100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), - TOP_MUX(CK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114, + TOP_MUX(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), - TOP_MUX(CK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", + TOP_MUX(CLK_TOP_NETSYS_TOPS_400M_SEL, "netsys_tops_400m_sel", netsys_tops_400m_parents, 0x110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), - TOP_MUX(CK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", + TOP_MUX(CLK_TOP_NETSYS_PPEFB_250M_SEL, "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, 0x110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), - TOP_MUX(CK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, + TOP_MUX(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", netsys_parents, 0x110, 0x114, 0x118, 24, 2, 31, 0x1c8, 9), - TOP_MUX(CK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120, + TOP_MUX(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", eth_mii_parents, 0x120, 0x124, 0x128, 0, 1, 7, 0x1c8, 10), - TOP_MUX(CK_TOP_CK_NPU_SEL_CM_TOPS_SEL, "ck_npu_sel_cm_tops_sel", + TOP_MUX(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, 0x120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), }; -/* INFRA FIXED DIV */ -static const struct mtk_fixed_factor infracfg_mtk_fixed_factor[] = { - TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_INFRA_F26M_SEL, 1, - 1), - TOP_FACTOR(CK_INFRA_PWM_O, "infra_pwm_o", CK_TOP_PWM_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P0, "infra_pcie_ck_occ_p0", - CK_TOP_PEXTP_TL_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P1, "infra_pcie_ck_occ_p1", - CK_TOP_PEXTP_TL_P1_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P2, "infra_pcie_ck_occ_p2", - CK_TOP_PEXTP_TL_P2_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_PCIE_OCC_P3, "infra_pcie_ck_occ_p3", - CK_TOP_PEXTP_TL_P3_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1), - INFRA_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_INFRA_133M_HCK, - 1, 1), - INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1, - 1), - TOP_FACTOR(CK_INFRA_FAUD_L_O, "infra_faud_l_o", CK_TOP_AUD_L, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_AUD_O, "infra_faud_aud_o", CK_TOP_A1SYS, 1, 1), - TOP_FACTOR(CK_INFRA_FAUD_EG2_O, "infra_faud_eg2_o", CK_TOP_A_TUNER, 1, - 1), - TOP_FACTOR(CK_INFRA_I2C_O, "infra_i2c_o", CK_TOP_I2C_BCK, 1, 1), - TOP_FACTOR(CK_INFRA_UART_O0, "infra_uart_o0", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART_O1, "infra_uart_o1", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_UART_O2, "infra_uart_o2", CK_TOP_UART_SEL, 1, 1), - TOP_FACTOR(CK_INFRA_NFI_O, "infra_nfi_o", CK_TOP_NFI1X, 1, 1), - TOP_FACTOR(CK_INFRA_SPINFI_O, "infra_spinfi_o", CK_TOP_SPINFI_BCK, 1, - 1), - TOP_FACTOR(CK_INFRA_SPI0_O, "infra_spi0_o", CK_TOP_SPI, 1, 1), - TOP_FACTOR(CK_INFRA_SPI1_O, "infra_spi1_o", CK_TOP_SPIM_MST, 1, 1), - INFRA_FACTOR(CK_INFRA_LB_MUX_FRTC, "infra_lb_mux_frtc", CK_INFRA_FRTC, - 1, 1), - TOP_FACTOR(CK_INFRA_FRTC, "infra_frtc", CK_TOP_CB_RTC_32K, 1, 1), - TOP_FACTOR(CK_INFRA_FMSDC400_O, "infra_fmsdc400_o", CK_TOP_EMMC_400M, 1, - 1), - TOP_FACTOR(CK_INFRA_FMSDC2_HCK_OCC, "infra_fmsdc2_hck_occ", - CK_TOP_EMMC_250M, 1, 1), - TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_USB_O, "infra_usb_o", CK_TOP_USB_REF, 1, 1), - TOP_FACTOR(CK_INFRA_USB_O_P1, "infra_usb_o_p1", CK_TOP_USB_CK_P1, 1, 1), - TOP_FACTOR(CK_INFRA_USB_FRMCNT_O, "infra_usb_frmcnt_o", - CK_TOP_USB_FRMCNT, 1, 1), - TOP_FACTOR(CK_INFRA_USB_FRMCNT_O_P1, "infra_usb_frmcnt_o_p1", - CK_TOP_USB_FRMCNT_P1, 1, 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_O, "infra_usb_xhci_o", CK_TOP_USB_XHCI, 1, - 1), - TOP_FACTOR(CK_INFRA_USB_XHCI_O_P1, "infra_usb_xhci_o_p1", - CK_TOP_USB_XHCI_P1, 1, 1), - XTAL_FACTOR(CK_INFRA_USB_PIPE_O, "infra_usb_pipe_o", CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_USB_PIPE_O_P1, "infra_usb_pipe_o_p1", CLK_XTAL, 1, - 1), - XTAL_FACTOR(CK_INFRA_USB_UTMI_O, "infra_usb_utmi_o", CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_USB_UTMI_O_P1, "infra_usb_utmi_o_p1", CLK_XTAL, 1, - 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P0, "infra_pcie_pipe_ck_occ_p0", - CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P1, "infra_pcie_pipe_ck_occ_p1", - CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P2, "infra_pcie_pipe_ck_occ_p2", - CLK_XTAL, 1, 1), - XTAL_FACTOR(CK_INFRA_PCIE_PIPE_OCC_P3, "infra_pcie_pipe_ck_occ_p3", - CLK_XTAL, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_O0, "infra_f26m_o0", CK_TOP_INFRA_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_F26M_O1, "infra_f26m_o1", CK_TOP_INFRA_F26M, 1, 1), - TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI, 1, 1), - TOP_FACTOR(CK_INFRA_PERI_66M_O, "infra_peri_66m_o", CK_TOP_SYSAXI, 1, - 1), - TOP_FACTOR(CK_INFRA_USB_SYS_O, "infra_usb_sys_o", CK_TOP_USB_SYS, 1, 1), - TOP_FACTOR(CK_INFRA_USB_SYS_O_P1, "infra_usb_sys_o_p1", - CK_TOP_USB_SYS_P1, 1, 1), -}; - /* INFRASYS MUX PARENTS */ -static const int infra_mux_uart0_parents[] = { CK_INFRA_CK_F26M, - CK_INFRA_UART_O0 }; +static const int infra_mux_uart0_parents[] = { CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL }; -static const int infra_mux_uart1_parents[] = { CK_INFRA_CK_F26M, - CK_INFRA_UART_O1 }; +static const int infra_mux_uart1_parents[] = { CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL }; -static const int infra_mux_uart2_parents[] = { CK_INFRA_CK_F26M, - CK_INFRA_UART_O2 }; +static const int infra_mux_uart2_parents[] = { CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_UART_SEL }; -static const int infra_mux_spi0_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI0_O }; +static const int infra_mux_spi0_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPI_SEL }; -static const int infra_mux_spi1_parents[] = { CK_INFRA_I2C_O, CK_INFRA_SPI1_O }; +static const int infra_mux_spi1_parents[] = { CLK_TOP_I2C_SEL, CLK_TOP_SPIM_MST_SEL }; -static const int infra_pwm_bck_parents[] = { CK_TOP_INFRA_F32K, - CK_INFRA_CK_F26M, CK_INFRA_66M_MCK, - CK_INFRA_PWM_O }; +static const int infra_pwm_bck_parents[] = { CLK_TOP_RTC_32P7K, + CLK_TOP_INFRA_F26M_SEL, CLK_TOP_SYSAXI_SEL, + CLK_TOP_PWM_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p0_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P0 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p1_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P1 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P1_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p2_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P2 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P2_SEL }; static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { - CK_TOP_INFRA_F32K, CK_INFRA_CK_F26M, CK_INFRA_CK_F26M, - CK_INFRA_PCIE_OCC_P3 + CLK_TOP_RTC_32P7K, CLK_TOP_INFRA_F26M_SEL, CLK_TOP_INFRA_F26M_SEL, + CLK_TOP_PEXTP_TL_P3_SEL }; #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ @@ -542,51 +486,51 @@ static const int infra_pcie_gfmux_tl_ck_o_p3_parents[] = { .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ .mux_mask = BIT(_width) - 1, .parent = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ - .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ } /* INFRA MUX */ static const struct mtk_composite infracfg_mtk_mux[] = { - INFRA_MUX(CK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", + INFRA_MUX(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", infra_mux_uart0_parents, 0x10, 0, 1), - INFRA_MUX(CK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", + INFRA_MUX(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", infra_mux_uart1_parents, 0x10, 1, 1), - INFRA_MUX(CK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", + INFRA_MUX(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", infra_mux_uart2_parents, 0x10, 2, 1), - INFRA_MUX(CK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", + INFRA_MUX(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents, 0x10, 4, 1), - INFRA_MUX(CK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", + INFRA_MUX(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents, 0x10, 5, 1), - INFRA_MUX(CK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", + INFRA_MUX(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents, 0x10, 6, 1), - INFRA_MUX(CK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, + INFRA_MUX(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x10, 14, 2), - INFRA_MUX(CK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", + INFRA_MUX(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents, 0x10, 16, 2), - INFRA_MUX(CK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", + INFRA_MUX(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents, 0x10, 18, 2), - INFRA_MUX(CK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", + INFRA_MUX(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents, 0x10, 20, 2), - INFRA_MUX(CK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", + INFRA_MUX(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents, 0x10, 22, 2), - INFRA_MUX(CK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", + INFRA_MUX(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents, 0x10, 24, 2), - INFRA_MUX(CK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", + INFRA_MUX(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents, 0x10, 26, 2), - INFRA_MUX(CK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", + INFRA_MUX(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents, 0x10, 28, 2), - INFRA_MUX(CK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", + INFRA_MUX(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents, 0x10, 30, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel", infra_pcie_gfmux_tl_ck_o_p0_parents, 0x20, 0, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel", infra_pcie_gfmux_tl_ck_o_p1_parents, 0x20, 2, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel", infra_pcie_gfmux_tl_ck_o_p2_parents, 0x20, 4, 2), - INFRA_MUX(CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, + INFRA_MUX(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel", infra_pcie_gfmux_tl_ck_o_p3_parents, 0x20, 6, 2), }; @@ -615,218 +559,238 @@ static const struct mtk_gate_regs infra_3_cg_regs = { .sta_ofs = 0x68, }; -#define GATE_INFRA0(_id, _name, _parent, _shift) \ +#define GATE_INFRA0(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA0_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA0_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA0(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA1(_id, _name, _parent, _shift) \ +#define GATE_INFRA1(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA1_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA1_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA1(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA2(_id, _name, _parent, _shift) \ +#define GATE_INFRA2(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA2_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA2_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA2(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) -#define GATE_INFRA3(_id, _name, _parent, _shift) \ +#define GATE_INFRA3(_id, _name, _parent, _shift, _flags) \ { \ .id = _id, .parent = _parent, .regs = &infra_3_cg_regs, \ .shift = _shift, \ - .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \ + .flags = _flags, \ } +#define GATE_INFRA3_INFRA(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_INFRASYS) +#define GATE_INFRA3_TOP(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN) +#define GATE_INFRA3_XTAL(_id, _name, _parent, _shift) \ + GATE_INFRA3(_id, _name, _parent, _shift, CLK_GATE_SETCLR | CLK_PARENT_XTAL) /* INFRA GATE */ static const struct mtk_gate infracfg_mtk_gates[] = { - GATE_INFRA1(CK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", - CK_INFRA_66M_MCK, 0), - GATE_INFRA1(CK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", - CK_INFRA_66M_MCK, 1), - GATE_INFRA1(CK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", - CK_INFRA_PWM_SEL, 2), - GATE_INFRA1(CK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", - CK_INFRA_PWM_CK1_SEL, 3), - GATE_INFRA1(CK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", - CK_INFRA_PWM_CK2_SEL, 4), - GATE_INFRA1(CK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", - CK_INFRA_PWM_CK3_SEL, 5), - GATE_INFRA1(CK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", - CK_INFRA_PWM_CK4_SEL, 6), - GATE_INFRA1(CK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", - CK_INFRA_PWM_CK5_SEL, 7), - GATE_INFRA1(CK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", - CK_INFRA_PWM_CK6_SEL, 8), - GATE_INFRA1(CK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", - CK_INFRA_PWM_CK7_SEL, 9), - GATE_INFRA1(CK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", - CK_INFRA_PWM_CK8_SEL, 10), - GATE_INFRA1(CK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", - CK_INFRA_133M_MCK, 12), - GATE_INFRA1(CK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", - CK_INFRA_66M_PHCK, 13), - GATE_INFRA1(CK_INFRA_AUD_26M, "infra_f_faud_26m", CK_INFRA_CK_F26M, 14), - GATE_INFRA1(CK_INFRA_AUD_L, "infra_f_faud_l", CK_INFRA_FAUD_L_O, 15), - GATE_INFRA1(CK_INFRA_AUD_AUD, "infra_f_aud_aud", CK_INFRA_FAUD_AUD_O, - 16), - GATE_INFRA1(CK_INFRA_AUD_EG2, "infra_f_faud_eg2", CK_INFRA_FAUD_EG2_O, - 18), - GATE_INFRA1(CK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CK_INFRA_CK_F26M, - 19), - GATE_INFRA1(CK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", - CK_INFRA_133M_MCK, 20), - GATE_INFRA1(CK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", - CK_INFRA_66M_MCK, 21), - GATE_INFRA1(CK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", - CK_INFRA_66M_MCK, 29), - GATE_INFRA1(CK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", - CK_INFRA_CK_F26M, 30), - GATE_INFRA1(CK_INFRA_66M_TRNG, "infra_hf_66m_trng", CK_INFRA_PERI_66M_O, - 31), - GATE_INFRA2(CK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", - CK_INFRA_CK_F26M, 0), - GATE_INFRA2(CK_INFRA_I2C_BCK, "infra_i2c_bck", CK_INFRA_I2C_O, 1), - GATE_INFRA2(CK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck", - CK_INFRA_66M_MCK, 3), - GATE_INFRA2(CK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck", - CK_INFRA_66M_MCK, 4), - GATE_INFRA2(CK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck", - CK_INFRA_66M_MCK, 5), - GATE_INFRA2(CK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", - CK_INFRA_MUX_UART0_SEL, 3), - GATE_INFRA2(CK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", - CK_INFRA_MUX_UART1_SEL, 4), - GATE_INFRA2(CK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", - CK_INFRA_MUX_UART2_SEL, 5), - GATE_INFRA2(CK_INFRA_NFI, "infra_f_fnfi", CK_INFRA_NFI_O, 9), - GATE_INFRA2(CK_INFRA_SPINFI, "infra_f_fspinfi", CK_INFRA_SPINFI_O, 10), - GATE_INFRA2(CK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", - CK_INFRA_66M_MCK, 11), - GATE_INFRA2(CK_INFRA_104M_SPI0, "infra_hf_104m_spi0", - CK_INFRA_MUX_SPI0_SEL, 12), - GATE_INFRA2(CK_INFRA_104M_SPI1, "infra_hf_104m_spi1", - CK_INFRA_MUX_SPI1_SEL, 13), - GATE_INFRA2(CK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", - CK_INFRA_MUX_SPI2_SEL, 14), - GATE_INFRA2(CK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", - CK_INFRA_66M_MCK, 15), - GATE_INFRA2(CK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", - CK_INFRA_66M_MCK, 16), - GATE_INFRA2(CK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", - CK_INFRA_66M_MCK, 17), - GATE_INFRA2(CK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", - CK_INFRA_66M_MCK, 18), - GATE_INFRA2(CK_INFRA_RTC, "infra_f_frtc", CK_INFRA_LB_MUX_FRTC, 19), - GATE_INFRA2(CK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", - CK_INFRA_F26M_O1, 20), - GATE_INFRA2(CK_INFRA_RC_ADC, "infra_f_frc_adc", CK_INFRA_26M_ADC_BCK, - 21), - GATE_INFRA2(CK_INFRA_MSDC400, "infra_f_fmsdc400", CK_INFRA_FMSDC400_O, - 22), - GATE_INFRA2(CK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", - CK_INFRA_FMSDC2_HCK_OCC, 23), - GATE_INFRA2(CK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", - CK_INFRA_PERI_133M, 24), - GATE_INFRA2(CK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", - CK_INFRA_66M_PHCK, 25), - GATE_INFRA2(CK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", - CK_INFRA_133M_MCK, 26), - GATE_INFRA2(CK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CK_INFRA_NFI_O, - 27), - GATE_INFRA2(CK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", - CK_INFRA_133M_MCK, 29), - GATE_INFRA2(CK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", - CK_INFRA_66M_PHCK, 31), - GATE_INFRA3(CK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", - CK_INFRA_133M_PHCK, 0), - GATE_INFRA3(CK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", - CK_INFRA_133M_PHCK, 1), - GATE_INFRA3(CK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", - CK_INFRA_66M_PHCK, 2), - GATE_INFRA3(CK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", - CK_INFRA_66M_PHCK, 3), - GATE_INFRA3(CK_INFRA_USB_SYS, "infra_usb_sys", CK_INFRA_USB_SYS_O, 4), - GATE_INFRA3(CK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", - CK_INFRA_USB_SYS_O_P1, 5), - GATE_INFRA3(CK_INFRA_USB_REF, "infra_usb_ref", CK_INFRA_USB_O, 6), - GATE_INFRA3(CK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CK_INFRA_USB_O_P1, - 7), - GATE_INFRA3(CK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", - CK_INFRA_USB_FRMCNT_O, 8), - GATE_INFRA3(CK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", - CK_INFRA_USB_FRMCNT_O_P1, 9), - GATE_INFRA3(CK_INFRA_USB_PIPE, "infra_usb_pipe", CK_INFRA_USB_PIPE_O, - 10), - GATE_INFRA3(CK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - CK_INFRA_USB_PIPE_O_P1, 11), - GATE_INFRA3(CK_INFRA_USB_UTMI, "infra_usb_utmi", CK_INFRA_USB_UTMI_O, - 12), - GATE_INFRA3(CK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - CK_INFRA_USB_UTMI_O_P1, 13), - GATE_INFRA3(CK_INFRA_USB_XHCI, "infra_usb_xhci", CK_INFRA_USB_XHCI_O, - 14), - GATE_INFRA3(CK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", - CK_INFRA_USB_XHCI_O_P1, 15), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", - CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", - CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", - CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), - GATE_INFRA3(CK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", - CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - CK_INFRA_PCIE_PIPE_OCC_P0, 24), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - CK_INFRA_PCIE_PIPE_OCC_P1, 25), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - CK_INFRA_PCIE_PIPE_OCC_P2, 26), - GATE_INFRA3(CK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - CK_INFRA_PCIE_PIPE_OCC_P3, 27), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", - CK_INFRA_133M_PHCK, 28), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", - CK_INFRA_133M_PHCK, 29), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", - CK_INFRA_133M_PHCK, 30), - GATE_INFRA3(CK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", - CK_INFRA_133M_PHCK, 31), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P0, - "infra_pcie_peri_ck_26m_ck_p0", CK_INFRA_F26M_O0, 7), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P1, - "infra_pcie_peri_ck_26m_ck_p1", CK_INFRA_F26M_O0, 8), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P2, - "infra_pcie_peri_ck_26m_ck_p2", CK_INFRA_F26M_O0, 9), - GATE_INFRA0(CK_INFRA_PCIE_PERI_26M_CK_P3, - "infra_pcie_peri_ck_26m_ck_p3", CK_INFRA_F26M_O0, 10), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P0, + "infra_pcie_peri_ck_26m_ck_p0", CLK_TOP_INFRA_F26M_SEL, 7), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P1, + "infra_pcie_peri_ck_26m_ck_p1", CLK_TOP_INFRA_F26M_SEL, 8), + GATE_INFRA0_INFRA(CLK_INFRA_PCIE_PERI_26M_CK_P2, + "infra_pcie_peri_ck_26m_ck_p2", CLK_INFRA_PCIE_PERI_26M_CK_P3, 9), + GATE_INFRA0_TOP(CLK_INFRA_PCIE_PERI_26M_CK_P3, + "infra_pcie_peri_ck_26m_ck_p3", CLK_TOP_INFRA_F26M_SEL, 10), + GATE_INFRA1_TOP(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", + CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA1_TOP(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", + CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", + CLK_INFRA_PWM_SEL, 2), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", + CLK_INFRA_PWM_CK1_SEL, 3), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", + CLK_INFRA_PWM_CK2_SEL, 4), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", + CLK_INFRA_PWM_CK3_SEL, 5), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", + CLK_INFRA_PWM_CK4_SEL, 6), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", + CLK_INFRA_PWM_CK5_SEL, 7), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", + CLK_INFRA_PWM_CK6_SEL, 8), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", + CLK_INFRA_PWM_CK7_SEL, 9), + GATE_INFRA1_INFRA(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", + CLK_INFRA_PWM_CK8_SEL, 10), + GATE_INFRA1_TOP(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", + CLK_TOP_SYSAXI_SEL, 12), + GATE_INFRA1_TOP(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", + CLK_TOP_SYSAXI_SEL, 13), + GATE_INFRA1_TOP(CLK_INFRA_AUD_26M, "infra_f_faud_26m", CLK_TOP_INFRA_F26M_SEL, 14), + GATE_INFRA1_TOP(CLK_INFRA_AUD_L, "infra_f_faud_l", CLK_TOP_AUD_L_SEL, 15), + GATE_INFRA1_TOP(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", CLK_TOP_A1SYS_SEL, + 16), + GATE_INFRA1_TOP(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", CLK_TOP_A_TUNER_SEL, + 18), + GATE_INFRA1_TOP(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", CLK_TOP_INFRA_F26M_SEL, + 19), + GATE_INFRA1_TOP(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", + CLK_TOP_SYSAXI_SEL, 20), + GATE_INFRA1_TOP(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", + CLK_TOP_SYSAXI_SEL, 21), + GATE_INFRA1_TOP(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", + CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA1_TOP(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", + CLK_TOP_INFRA_F26M_SEL, 30), + /* GATE_INFRA1_TOP(CLK_INFRA_66M_TRNG, "infra_hf_66m_trng", CLK_TOP_SYSAXI_SEL, + 31), */ + GATE_INFRA2_TOP(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", + CLK_TOP_INFRA_F26M_SEL, 0), + GATE_INFRA2_TOP(CLK_INFRA_I2C_BCK, "infra_i2c_bck", CLK_TOP_I2C_SEL, 1), + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART0_PCK, "infra_hf_66m_uart0_pck", + CLK_TOP_SYSAXI_SEL, 3), */ + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART1_PCK, "infra_hf_66m_uart1_pck", + CLK_TOP_SYSAXI_SEL, 4), */ + /* GATE_INFRA2_TOP(CLK_INFRA_66M_UART2_PCK, "infra_hf_66m_uart2_pck", + CLK_TOP_SYSAXI_SEL, 5), */ + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", + CLK_INFRA_MUX_UART0_SEL, 3), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", + CLK_INFRA_MUX_UART1_SEL, 4), + GATE_INFRA2_INFRA(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", + CLK_INFRA_MUX_UART2_SEL, 5), + GATE_INFRA2_TOP(CLK_INFRA_NFI, "infra_f_fnfi", CLK_TOP_NFI1X_SEL, 9), + GATE_INFRA2_TOP(CLK_INFRA_SPINFI, "infra_f_fspinfi", CLK_TOP_SPINFI_SEL, 10), + GATE_INFRA2_TOP(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", + CLK_TOP_SYSAXI_SEL, 11), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", + CLK_INFRA_MUX_SPI0_SEL, 12), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", + CLK_INFRA_MUX_SPI1_SEL, 13), + GATE_INFRA2_INFRA(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", + CLK_INFRA_MUX_SPI2_SEL, 14), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", + CLK_TOP_SYSAXI_SEL, 15), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", + CLK_TOP_SYSAXI_SEL, 16), + GATE_INFRA2_TOP(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", + CLK_TOP_SYSAXI_SEL, 17), + GATE_INFRA2_TOP(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", + CLK_TOP_SYSAXI_SEL, 18), + GATE_INFRA2_TOP(CLK_INFRA_RTC, "infra_f_frtc", CLK_TOP_RTC_32K, 19), + GATE_INFRA2_TOP(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", + CLK_TOP_INFRA_F26M_SEL, 20), + GATE_INFRA2_INFRA(CLK_INFRA_RC_ADC, "infra_f_frc_adc", CLK_INFRA_26M_ADC_BCK, + 21), + GATE_INFRA2_TOP(CLK_INFRA_MSDC400, "infra_f_fmsdc400", CLK_TOP_EMMC_400M_SEL, + 22), + GATE_INFRA2_TOP(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", + CLK_TOP_EMMC_250M_SEL, 23), + GATE_INFRA2_TOP(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", + CLK_TOP_SYSAXI_SEL, 24), + GATE_INFRA2_TOP(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", + CLK_TOP_SYSAXI_SEL, 25), + GATE_INFRA2_TOP(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", + CLK_TOP_SYSAXI_SEL, 26), + GATE_INFRA2_TOP(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", CLK_TOP_NFI1X_SEL, + 27), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_MCK_CK_P1, "infra_hf_i2c_x16w_mck_ck_p1", + CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA2_TOP(CLK_INFRA_I2C_X16W_PCK_CK_P1, "infra_hf_i2c_x16w_pck_ck_p1", + CLK_TOP_SYSAXI_SEL, 31), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", + CLK_TOP_SYSAXI_SEL, 0), + GATE_INFRA3_TOP(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", + CLK_TOP_SYSAXI_SEL, 1), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", + CLK_TOP_SYSAXI_SEL, 2), + GATE_INFRA3_TOP(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", + CLK_TOP_SYSAXI_SEL, 3), + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS, "infra_usb_sys", CLK_TOP_USB_SYS_SEL, 4), + GATE_INFRA3_TOP(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", + CLK_TOP_USB_SYS_P1_SEL, 5), + GATE_INFRA3_XTAL(CLK_INFRA_USB_REF, "infra_usb_ref", CLK_XTAL, 6), + GATE_INFRA3_XTAL(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", CLK_XTAL, + 7), + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", + CLK_TOP_USB_FRMCNT_SEL, 8), + GATE_INFRA3_TOP(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", + CLK_TOP_USB_FRMCNT_P1_SEL, 9), + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE, "infra_usb_pipe", CLK_XTAL, + 10), + GATE_INFRA3_XTAL(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", + CLK_XTAL, 11), + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI, "infra_usb_utmi", CLK_XTAL, + 12), + GATE_INFRA3_XTAL(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", + CLK_XTAL, 13), + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI, "infra_usb_xhci", CLK_TOP_USB_XHCI_SEL, + 14), + GATE_INFRA3_TOP(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", + CLK_TOP_USB_XHCI_P1_SEL, 15), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", + CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, 20), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", + CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, 21), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", + CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, 22), + GATE_INFRA3_INFRA(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", + CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, 23), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", + CLK_XTAL, 24), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", + CLK_XTAL, 25), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", + CLK_XTAL, 26), + GATE_INFRA3_XTAL(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", + CLK_XTAL, 27), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", + CLK_TOP_SYSAXI_SEL, 28), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", + CLK_TOP_SYSAXI_SEL, 29), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", + CLK_TOP_SYSAXI_SEL, 30), + GATE_INFRA3_TOP(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", + CLK_TOP_SYSAXI_SEL, 31), }; static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = { .fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls), .fclks = apmixedsys_mtk_plls, + .flags = CLK_APMIXED, .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_topckgen_clk_tree = { - .fdivs_offs = CK_TOP_CB_CKSQ_40M, - .muxes_offs = CK_TOP_NETSYS_SEL, + .fdivs_offs = CLK_TOP_XTAL_D2, + .muxes_offs = CLK_TOP_NETSYS_SEL, + .fclks = topckgen_mtk_fixed_clks, .fdivs = topckgen_mtk_fixed_factors, .muxes = topckgen_mtk_muxes, - .flags = CLK_BYPASS_XTAL, + .flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN, .xtal_rate = 40 * MHZ, }; static const struct mtk_clk_tree mt7988_infracfg_clk_tree = { - .fdivs_offs = CK_INFRA_CK_F26M, - .muxes_offs = CK_INFRA_MUX_UART0_SEL, - .fdivs = infracfg_mtk_fixed_factor, + .muxes_offs = CLK_INFRA_MUX_UART0_SEL, + .gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0, .muxes = infracfg_mtk_mux, + .gates = infracfg_mtk_gates, .flags = CLK_BYPASS_XTAL, .xtal_rate = 40 * MHZ, }; @@ -884,20 +848,9 @@ static const struct udevice_id mt7988_infracfg_compat[] = { {} }; -static const struct udevice_id mt7988_infracfg_ao_cgs_compat[] = { - { .compatible = "mediatek,mt7988-infracfg_ao_cgs" }, - {} -}; - static int mt7988_infracfg_probe(struct udevice *dev) { - return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree); -} - -static int mt7988_infracfg_ao_cgs_probe(struct udevice *dev) -{ - return mtk_common_clk_gate_init(dev, &mt7988_infracfg_clk_tree, - infracfg_mtk_gates); + return mtk_common_clk_infrasys_init(dev, &mt7988_infracfg_clk_tree); } U_BOOT_DRIVER(mtk_clk_infracfg) = { @@ -910,16 +863,6 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRIVER(mtk_clk_infracfg_ao_cgs) = { - .name = "mt7988-clock-infracfg_ao_cgs", - .id = UCLASS_CLK, - .of_match = mt7988_infracfg_ao_cgs_compat, - .probe = mt7988_infracfg_ao_cgs_probe, - .priv_auto = sizeof(struct mtk_cg_priv), - .ops = &mtk_clk_gate_ops, - .flags = DM_FLAG_PRE_RELOC, -}; - /* ETHDMA */ static const struct mtk_gate_regs ethdma_cg_regs = { @@ -936,7 +879,7 @@ static const struct mtk_gate_regs ethdma_cg_regs = { } static const struct mtk_gate ethdma_mtk_gate[] = { - GATE_ETHDMA(CK_ETHDMA_FE_EN, "ethdma_fe_en", CK_TOP_NETSYS_2X, 6), + GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6), }; static int mt7988_ethdma_probe(struct udevice *dev) @@ -991,10 +934,10 @@ static const struct mtk_gate_regs sgmii0_cg_regs = { } static const struct mtk_gate sgmiisys_0_mtk_gate[] = { - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII0(CK_SGM0_TX_EN, "sgm0_tx_en", CK_TOP_CB_CKSQ_40M, 2), - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII0(CK_SGM0_RX_EN, "sgm0_rx_en", CK_TOP_CB_CKSQ_40M, 3), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", CLK_TOP_XTAL, 2), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3), }; static int mt7988_sgmiisys_0_probe(struct udevice *dev) @@ -1035,10 +978,10 @@ static const struct mtk_gate_regs sgmii1_cg_regs = { } static const struct mtk_gate sgmiisys_1_mtk_gate[] = { - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII1(CK_SGM1_TX_EN, "sgm1_tx_en", CK_TOP_CB_CKSQ_40M, 2), - /* connect to fake clock, so use CK_TOP_CB_CKSQ_40M as the clock parent */ - GATE_SGMII1(CK_SGM1_RX_EN, "sgm1_rx_en", CK_TOP_CB_CKSQ_40M, 3), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", CLK_TOP_XTAL, 2), + /* connect to fake clock, so use CLK_TOP_XTAL as the clock parent */ + GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3), }; static int mt7988_sgmiisys_1_probe(struct udevice *dev) @@ -1079,12 +1022,12 @@ static const struct mtk_gate_regs ethwarp_cg_regs = { } static const struct mtk_gate ethwarp_mtk_gate[] = { - GATE_ETHWARP(CK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", - CK_TOP_NETSYS_WED_MCU, 13), - GATE_ETHWARP(CK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", - CK_TOP_NETSYS_WED_MCU, 14), - GATE_ETHWARP(CK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", - CK_TOP_NETSYS_WED_MCU, 15), + GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", + CLK_TOP_NETSYS_MCU_SEL, 13), + GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", + CLK_TOP_NETSYS_MCU_SEL, 14), + GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", + CLK_TOP_NETSYS_MCU_SEL, 15), }; static int mt7988_ethwarp_probe(struct udevice *dev) diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 31091bb4495..888dfb7ff33 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -111,7 +111,7 @@ static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr, #if CONFIG_IS_ENABLED(DM_I2C) ret = dm_i2c_read(dev, 0, buf, len); #else - ret = i2c_read(dev->chip, addr, alen, buf, len); + ret = 0; #endif return ret; @@ -162,7 +162,6 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) }; dev = &ldev; - i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); #endif #ifdef CONFIG_SYS_FSL_DDR4 diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index cba7f848942..52067fa7c1f 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -650,7 +650,7 @@ config SYS_I2C_GENI config SYS_I2C_S3C24X0 bool "Samsung I2C driver" - depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C + depends on DM_I2C help Support for Samsung I2C controller as Samsung SoCs. diff --git a/drivers/i2c/exynos_hs_i2c.c b/drivers/i2c/exynos_hs_i2c.c index 2ab0bae4499..fa0d1c8f64a 100644 --- a/drivers/i2c/exynos_hs_i2c.c +++ b/drivers/i2c/exynos_hs_i2c.c @@ -9,11 +9,15 @@ #include <dm.h> #include <i2c.h> #include <log.h> +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) #include <asm/arch/clk.h> #include <asm/arch/cpu.h> #include <asm/arch/pinmux.h> +#endif #include <asm/global_data.h> +#include <asm/io.h> #include <linux/delay.h> +#include <clk.h> #include "s3c24x0_i2c.h" DECLARE_GLOBAL_DATA_PTR; @@ -137,18 +141,25 @@ static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) return I2C_NOK_TOUT; } -static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) +static int hsi2c_get_clk_details(struct udevice *dev) { + struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; ulong clkin; unsigned int op_clk = i2c_bus->clock_frequency; unsigned int i = 0, utemp0 = 0, utemp1 = 0; unsigned int t_ftl_cycle; -#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) clkin = get_i2c_clk(); #else - clkin = get_PCLK(); + struct clk clk; + int ret; + + ret = clk_get_by_name(dev, "hsi2c", &clk); + if (ret < 0) + return ret; + clkin = clk_get_rate(&clk); #endif /* FPCLK / FI2C = * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE @@ -491,7 +502,7 @@ static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) i2c_bus->clock_frequency = speed; - if (hsi2c_get_clk_details(i2c_bus)) + if (hsi2c_get_clk_details(dev)) return -EFAULT; hsi2c_ch_init(i2c_bus); @@ -518,7 +529,9 @@ static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) static int s3c_i2c_of_to_plat(struct udevice *dev) { +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) const void *blob = gd->fdt_blob; +#endif struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); int node; @@ -526,7 +539,9 @@ static int s3c_i2c_of_to_plat(struct udevice *dev) i2c_bus->hsregs = dev_read_addr_ptr(dev); +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) i2c_bus->id = pinmux_decode_periph_id(blob, node); +#endif i2c_bus->clock_frequency = dev_read_u32_default(dev, "clock-frequency", @@ -534,7 +549,9 @@ static int s3c_i2c_of_to_plat(struct udevice *dev) i2c_bus->node = node; i2c_bus->bus_num = dev_seq(dev); +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE); +#endif i2c_bus->active = true; diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 7c43a5546d3..cccd45027db 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -33,137 +33,8 @@ struct i2c_adapter *i2c_get_adapter(int index) return i2c_adap_p; } -#if !defined(CFG_SYS_I2C_DIRECT_BUS) -struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = - CFG_SYS_I2C_BUSES; -#endif - DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_SYS_I2C_DIRECT_BUS -/* - * i2c_mux_set() - * ------------- - * - * This turns on the given channel on I2C multiplexer chip connected to - * a given I2C adapter directly or via other multiplexers. In the latter - * case the entire multiplexer chain must be initialized first starting - * with the one connected directly to the adapter. When disabling a chain - * muxes must be programmed in reverse order, starting with the one - * farthest from the adapter. - * - * mux_id is the multiplexer chip type from defined in i2c.h. So far only - * NXP (Philips) PCA954x multiplexers are supported. Switches are NOT - * supported (anybody uses them?) - */ - -static int i2c_mux_set(struct i2c_adapter *adap, int mux_id, int chip, - int channel) -{ - uint8_t buf; - int ret; - - /* channel < 0 - turn off the mux */ - if (channel < 0) { - buf = 0; - ret = adap->write(adap, chip, 0, 0, &buf, 1); - if (ret) - printf("%s: Could not turn off the mux.\n", __func__); - return ret; - } - - switch (mux_id) { - case I2C_MUX_PCA9540_ID: - case I2C_MUX_PCA9542_ID: - if (channel > 1) - return -1; - buf = (uint8_t)((channel & 0x01) | (1 << 2)); - break; - case I2C_MUX_PCA9544_ID: - if (channel > 3) - return -1; - buf = (uint8_t)((channel & 0x03) | (1 << 2)); - break; - case I2C_MUX_PCA9547_ID: - if (channel > 7) - return -1; - buf = (uint8_t)((channel & 0x07) | (1 << 3)); - break; - case I2C_MUX_PCA9548_ID: - if (channel > 7) - return -1; - buf = (uint8_t)(0x01 << channel); - break; - default: - printf("%s: wrong mux id: %d\n", __func__, mux_id); - return -1; - } - - ret = adap->write(adap, chip, 0, 0, &buf, 1); - if (ret) - printf("%s: could not set mux: id: %d chip: %x channel: %d\n", - __func__, mux_id, chip, channel); - return ret; -} - -static int i2c_mux_set_all(void) -{ - struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS]; - int i; - - /* Connect requested bus if behind muxes */ - if (i2c_bus_tmp->next_hop[0].chip != 0) { - /* Set all muxes along the path to that bus */ - for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) { - int ret; - - if (i2c_bus_tmp->next_hop[i].chip == 0) - break; - - ret = i2c_mux_set(I2C_ADAP, - i2c_bus_tmp->next_hop[i].mux.id, - i2c_bus_tmp->next_hop[i].chip, - i2c_bus_tmp->next_hop[i].channel); - if (ret != 0) - return ret; - } - } - return 0; -} - -static int i2c_mux_disconnect_all(void) -{ - struct i2c_bus_hose *i2c_bus_tmp = &i2c_bus[I2C_BUS]; - int i; - uint8_t buf = 0; - - if (I2C_ADAP->init_done == 0) - return 0; - - /* Disconnect current bus (turn off muxes if any) */ - if ((i2c_bus_tmp->next_hop[0].chip != 0) && - (I2C_ADAP->init_done != 0)) { - i = CFG_SYS_I2C_MAX_HOPS; - do { - uint8_t chip; - int ret; - - chip = i2c_bus_tmp->next_hop[--i].chip; - if (chip == 0) - continue; - - ret = I2C_ADAP->write(I2C_ADAP, chip, 0, 0, &buf, 1); - if (ret != 0) { - printf("i2c: mux disconnect error\n"); - return ret; - } - } while (i > 0); - } - - return 0; -} -#endif - /* * i2c_init_bus(): * --------------- @@ -237,11 +108,6 @@ int i2c_set_bus_num(unsigned int bus) if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0)) return 0; -#ifndef CFG_SYS_I2C_DIRECT_BUS - if (bus >= CFG_SYS_NUM_I2C_BUSES) - return -1; -#endif - max = ll_entry_count(struct i2c_adapter, i2c); if (I2C_ADAPTER(bus) >= max) { printf("Error, wrong i2c adapter %d max %d possible\n", @@ -249,17 +115,10 @@ int i2c_set_bus_num(unsigned int bus) return -2; } -#ifndef CFG_SYS_I2C_DIRECT_BUS - i2c_mux_disconnect_all(); -#endif - gd->cur_i2c_bus = bus; if (I2C_ADAP->init_done == 0) i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr); -#ifndef CFG_SYS_I2C_DIRECT_BUS - i2c_mux_set_all(); -#endif return 0; } diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index a1be841b119..4636da9f301 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -19,7 +19,10 @@ #define LPI2C_NACK_TOUT_MS 1 #define LPI2C_TIMEOUT_MS 100 -static int bus_i2c_init(struct udevice *bus, int speed); +#define LPI2C_CHUNK_DATA 256U +#define LPI2C_CHUNK_LEN_MIN 1U + +static int bus_i2c_init(struct udevice *bus); /* Weak linked function for overridden by some SoC power function */ int __weak init_i2c_power(unsigned i2c_num) @@ -118,8 +121,10 @@ static int bus_i2c_send(struct udevice *bus, u8 *txbuf, int len) static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) { + struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus); struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); + unsigned int chunk_len, rx_remain, timeout; lpi2c_status_t result = LPI2C_SUCESS; u32 val; ulong start_time = get_timer(0); @@ -128,33 +133,50 @@ static int bus_i2c_receive(struct udevice *bus, u8 *rxbuf, int len) if (!len) return result; - result = bus_i2c_wait_for_tx_ready(regs); - if (result) { - debug("i2c: receive wait fot tx ready: %d\n", result); - return result; - } + /* + * Extend the timeout for a bulk read if needed. + * The calculated timeout is the result of multiplying the + * transfer length with 8 bit + ACK + one clock of extra time, + * considering the I2C bus frequency. + */ + timeout = max(len * 10 * 1000 / i2c->speed_hz, LPI2C_TIMEOUT_MS); - /* clear all status flags */ - writel(0x7f00, ®s->msr); - /* send receive command */ - val = LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(len - 1); - writel(val, ®s->mtdr); + rx_remain = len; + while (rx_remain > 0) { + chunk_len = clamp(rx_remain, LPI2C_CHUNK_LEN_MIN, LPI2C_CHUNK_DATA) - 1; - while (len--) { - do { - result = imx_lpci2c_check_clear_error(regs); - if (result) { - debug("i2c: receive check clear error: %d\n", - result); - return result; - } - if (get_timer(start_time) > LPI2C_TIMEOUT_MS) { - debug("i2c: receive mrdr: timeout\n"); - return -1; - } - val = readl(®s->mrdr); - } while (val & LPI2C_MRDR_RXEMPTY_MASK); - *rxbuf++ = LPI2C_MRDR_DATA(val); + result = bus_i2c_wait_for_tx_ready(regs); + if (result) { + debug("i2c: receive wait for tx ready: %d\n", result); + return result; + } + + /* clear all status flags */ + writel(0x7f00, ®s->msr); + /* send receive command */ + writel(LPI2C_MTDR_CMD(0x1) | LPI2C_MTDR_DATA(chunk_len), ®s->mtdr); + rx_remain = rx_remain - (chunk_len & 0xff) - 1; + + while (len--) { + do { + result = imx_lpci2c_check_clear_error(regs); + if (result) { + debug("i2c: receive check clear error: %d\n", + result); + return result; + } + if (get_timer(start_time) > timeout) { + debug("i2c: receive mrdr: timeout\n"); + return -1; + } + val = readl(®s->mrdr); + } while (val & LPI2C_MRDR_RXEMPTY_MASK); + *rxbuf++ = LPI2C_MRDR_DATA(val); + + /* send next receive command before controller NACKs last byte */ + if ((len - rx_remain) < 2 && rx_remain > 0) + break; + } } return result; @@ -172,7 +194,7 @@ static int bus_i2c_start(struct udevice *bus, u8 addr, u8 dir) debug("i2c: start check busy bus: 0x%x\n", result); /* Try to init the lpi2c then check the bus busy again */ - bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE); + bus_i2c_init(bus); result = imx_lpci2c_check_busy_bus(regs); if (result) { printf("i2c: Error check busy bus: 0x%x\n", result); @@ -344,11 +366,14 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed) return 0; } -static int bus_i2c_init(struct udevice *bus, int speed) +static int bus_i2c_init(struct udevice *bus) { u32 val; int ret; + struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus); + int speed = i2c->speed_hz; + struct imx_lpi2c_bus *i2c_bus = dev_get_priv(bus); struct imx_lpi2c_reg *regs = (struct imx_lpi2c_reg *)(i2c_bus->base); /* reset peripheral */ @@ -388,13 +413,13 @@ static int imx_lpi2c_probe_chip(struct udevice *bus, u32 chip, result = bus_i2c_start(bus, chip, 0); if (result) { bus_i2c_stop(bus); - bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE); + bus_i2c_init(bus); return result; } result = bus_i2c_stop(bus); if (result) - bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE); + bus_i2c_init(bus); return result; } @@ -489,7 +514,7 @@ static int imx_lpi2c_probe(struct udevice *bus) return ret; } - ret = bus_i2c_init(bus, I2C_SPEED_STANDARD_RATE); + ret = bus_i2c_init(bus); if (ret < 0) return ret; diff --git a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c index a83d7cb0829..3d2ce0ca705 100644 --- a/drivers/i2c/muxes/i2c-arb-gpio-challenge.c +++ b/drivers/i2c/muxes/i2c-arb-gpio-challenge.c @@ -54,7 +54,7 @@ int i2c_arbitrator_select(struct udevice *mux, struct udevice *bus, /* Indicate that we want to claim the bus */ ret = dm_gpio_set_value(&priv->ap_claim, 1); if (ret) - goto err; + return ret; udelay(priv->slew_delay_us); /* Wait for the EC to release it */ @@ -62,7 +62,7 @@ int i2c_arbitrator_select(struct udevice *mux, struct udevice *bus, while (get_timer(start_retry) < priv->wait_retry_ms) { ret = dm_gpio_get_value(&priv->ec_claim); if (ret < 0) { - goto err; + return ret; } else if (!ret) { /* We got it, so return */ return 0; @@ -75,17 +75,14 @@ int i2c_arbitrator_select(struct udevice *mux, struct udevice *bus, /* It didn't release, so give up, wait, and try again */ ret = dm_gpio_set_value(&priv->ap_claim, 0); if (ret) - goto err; + return ret; mdelay(priv->wait_retry_ms); } while (get_timer(start) < priv->wait_free_ms); /* Give up, release our claim */ printf("I2C: Could not claim bus, timeout %lu\n", get_timer(start)); - ret = -ETIMEDOUT; - ret = 0; -err: - return ret; + return -ETIMEDOUT; } static int i2c_arbitrator_probe(struct udevice *dev) diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index b4e3e16a976..795288fe2e9 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -10,12 +10,9 @@ #include <i2c.h> #include <log.h> #include <malloc.h> -#include <asm/global_data.h> #include <asm-generic/gpio.h> -DECLARE_GLOBAL_DATA_PTR; - enum pca_type { PCA9543, PCA9544, diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 84c0050eac0..2f3cb5908c9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -620,6 +620,7 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) __attribute__((weak, alias("__enable_i2c_clk"))); #if !CONFIG_IS_ENABLED(DM_I2C) + /* * Read data from I2C device * diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 72d2ab0f73d..ade1ad6cef7 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -8,17 +8,16 @@ #include <dm.h> #include <fdtdec.h> #include <time.h> -#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) #include <log.h> +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) #include <asm/arch/clk.h> #include <asm/arch/cpu.h> #include <asm/arch/pinmux.h> -#else -#include <asm/arch/s3c24x0_cpu.h> #endif #include <asm/global_data.h> #include <asm/io.h> #include <i2c.h> +#include <clk.h> #include "s3c24x0_i2c.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,13 +49,22 @@ static void read_write_byte(struct s3c24x0_i2c *i2c) clrbits_le32(&i2c->iiccon, I2CCON_IRPND); } -static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) +static int i2c_ch_init(struct udevice *dev, int speed, int slaveadd) { + struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); + struct s3c24x0_i2c *i2c = i2c_bus->regs; ulong freq, pres = 16, div; -#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) + +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) freq = get_i2c_clk(); #else - freq = get_PCLK(); + struct clk clk; + int ret; + + ret = clk_get_by_name(dev, "i2c", &clk); + if (ret < 0) + return ret; + freq = clk_get_rate(&clk); #endif /* calculate prescaler and divisor values */ if ((freq / pres / (16 + 1)) > speed) @@ -75,6 +83,7 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) writel(slaveadd, &i2c->iicadd); /* program Master Transmit (and implicit STOP) */ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); + return 0; } #define SYS_I2C_S3C24X0_SLAVE_ADDR 0 @@ -85,8 +94,9 @@ static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) i2c_bus->clock_frequency = speed; - i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, - SYS_I2C_S3C24X0_SLAVE_ADDR); + if (i2c_ch_init(dev, i2c_bus->clock_frequency, + SYS_I2C_S3C24X0_SLAVE_ADDR)) + return -EFAULT; return 0; } @@ -301,7 +311,9 @@ static int s3c24x0_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, static int s3c_i2c_of_to_plat(struct udevice *dev) { +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) const void *blob = gd->fdt_blob; +#endif struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); int node; @@ -309,7 +321,9 @@ static int s3c_i2c_of_to_plat(struct udevice *dev) i2c_bus->regs = dev_read_addr_ptr(dev); +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) i2c_bus->id = pinmux_decode_periph_id(blob, node); +#endif i2c_bus->clock_frequency = dev_read_u32_default(dev, "clock-frequency", @@ -317,7 +331,9 @@ static int s3c_i2c_of_to_plat(struct udevice *dev) i2c_bus->node = node; i2c_bus->bus_num = dev_seq(dev); +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) exynos_pinmux_config(i2c_bus->id, 0); +#endif i2c_bus->active = true; diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h index ec8f1acaef5..12249d5c141 100644 --- a/drivers/i2c/s3c24x0_i2c.h +++ b/drivers/i2c/s3c24x0_i2c.h @@ -54,7 +54,9 @@ struct s3c24x0_i2c_bus { struct exynos5_hsi2c *hsregs; int is_highspeed; /* High speed type, rather than I2C */ unsigned clock_frequency; +#if IS_ENABLED(CONFIG_ARCH_EXYNOS4) || IS_ENABLED(CONFIG_ARCH_EXYNOS5) int id; +#endif unsigned clk_cycle; unsigned clk_div; }; diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 89ddf821063..79f7a320502 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -107,16 +107,13 @@ DECLARE_GLOBAL_DATA_PTR; /*----------------------------------------------------------------------- * Local functions */ -#if !defined(CONFIG_SYS_I2C_INIT_BOARD) static void send_reset (void); -#endif static void send_start (void); static void send_stop (void); static void send_ack (int); static int write_byte (uchar byte); static uchar read_byte (int); -#if !defined(CONFIG_SYS_I2C_INIT_BOARD) /*----------------------------------------------------------------------- * Send a reset sequence consisting of 9 clocks with the data signal high * to clock any confused device back into an idle state. Also send a @@ -144,7 +141,6 @@ static void send_reset(void) send_stop(); I2C_TRISTATE; } -#endif /*----------------------------------------------------------------------- * START: High -> Low on SDA while SCL is High @@ -277,12 +273,6 @@ static uchar read_byte(int ack) */ static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { -#if defined(CONFIG_SYS_I2C_INIT_BOARD) - /* call board specific i2c bus reset routine before accessing the */ - /* environment, which might be in a chip on that bus. For details */ - /* about this problem see doc/I2C_Edge_Conditions. */ - i2c_init_board(); -#else /* * WARNING: Do NOT save speed in a static variable: if the * I2C routines are called before RAM is initialized (to read @@ -290,7 +280,6 @@ static void soft_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) * system will crash. */ send_reset (); -#endif } /*----------------------------------------------------------------------- diff --git a/drivers/misc/rockchip-io-domain.c b/drivers/misc/rockchip-io-domain.c index cf4f7c3984c..025b6049a9f 100644 --- a/drivers/misc/rockchip-io-domain.c +++ b/drivers/misc/rockchip-io-domain.c @@ -31,6 +31,10 @@ #define PX30_IO_VSEL_VCCIO6_SRC BIT(0) #define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1 +#define RK3308_SOC_CON0 0x300 +#define RK3308_SOC_CON0_VCCIO3 BIT(8) +#define RK3308_SOC_VCCIO3_SUPPLY_NUM 3 + #define RK3328_SOC_CON4 0x410 #define RK3328_SOC_CON4_VCCIO2 BIT(7) #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1 @@ -119,6 +123,22 @@ static int px30_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) return ret; } +static int rk3308_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) +{ + int ret = rockchip_iodomain_write(grf, offset, idx, uV); + + if (!ret && idx == RK3308_SOC_VCCIO3_SUPPLY_NUM) { + /* + * set vccio3 iodomain to also use this framework + * instead of a special gpio. + */ + u32 val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16); + ret = regmap_write(grf, RK3308_SOC_CON0, val); + } + + return ret; +} + static int rk3328_iodomain_write(struct regmap *grf, uint offset, int idx, int uV) { int ret = rockchip_iodomain_write(grf, offset, idx, uV); @@ -189,6 +209,19 @@ static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = { .write = rockchip_iodomain_write, }; +static const struct rockchip_iodomain_soc_data soc_data_rk3308 = { + .grf_offset = 0x300, + .supply_names = { + "vccio0-supply", + "vccio1-supply", + "vccio2-supply", + "vccio3-supply", + "vccio4-supply", + "vccio5-supply", + }, + .write = rk3308_iodomain_write, +}; + static const struct rockchip_iodomain_soc_data soc_data_rk3328 = { .grf_offset = 0x410, .supply_names = { @@ -257,6 +290,10 @@ static const struct udevice_id rockchip_iodomain_ids[] = { .data = (ulong)&soc_data_px30_pmu, }, { + .compatible = "rockchip,rk3308-io-voltage-domain", + .data = (ulong)&soc_data_rk3308, + }, + { .compatible = "rockchip,rk3328-io-voltage-domain", .data = (ulong)&soc_data_rk3328, }, diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 1a10b7057a4..549fb80f198 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -159,6 +159,10 @@ static int rockchip_dwmmc_probe(struct udevice *dev) host->mmc->dev = dev; upriv->mmc = host->mmc; + /* Hosts capable of 8-bit can also do 4 bits */ + if (host->buswidth == 8) + plat->cfg.host_caps |= MMC_MODE_4BIT; + return dwmci_probe(dev); } diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 4fdc9645d08..3764e2567c1 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -2,6 +2,7 @@ menu "MTD Support" config MTD_PARTITIONS bool + select PARTITIONS config MTD bool "Enable MTD layer" @@ -31,6 +32,13 @@ config MTD_CONCAT into a single logical device. The larger logical device can then be partitioned. +config MTD_BLOCK + bool "Enable block device access to MTD devices" + depends on BLK + help + Enable support for block device access to MTD devices + using blk_ops abstraction. + config SYS_MTDPARTS_RUNTIME bool "Allow MTDPARTS to be configured at runtime" help diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index c2fc80b10f0..10d575e9f93 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -26,6 +26,7 @@ obj-y += onenand/ obj-y += spi/ obj-$(CONFIG_MTD_UBI) += ubi/ obj-$(CONFIG_NVMXIP) += nvmxip/ +obj-$(CONFIG_MTD_BLOCK) += mtdblock.o #SPL/TPL build else diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c new file mode 100644 index 00000000000..66a79b8c56a --- /dev/null +++ b/drivers/mtd/mtdblock.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * MTD block - abstraction over MTD subsystem, allowing + * to read and write in blocks using BLK UCLASS. + * + * - Read algorithm: + * + * 1. Convert start block number to start address. + * 2. Read block_dev->blksz bytes using mtd_read() and + * add to start address pointer block_dev->blksz bytes, + * until the requested number of blocks have been read. + * + * - Write algorithm: + * + * 1. Convert start block number to start address. + * 2. Round this address down by mtd->erasesize. + * + * Erase addr Start addr + * | | + * v v + * +----------------+----------------+----------------+ + * | blksz | blksz | blksz | + * +----------------+----------------+----------------+ + * + * 3. Calculate offset between this two addresses. + * 4. Read mtd->erasesize bytes using mtd_read() into + * temporary buffer from erase address. + * + * Erase addr Start addr + * | | + * v v + * +----------------+----------------+----------------+ + * | blksz | blksz | blksz | + * +----------------+----------------+----------------+ + * ^ + * | + * | + * mtd_read() + * from here + * + * 5. Copy data from user buffer to temporary buffer with offset, + * calculated at step 3. + * 6. Erase and write mtd->erasesize bytes at erase address + * pointer using mtd_erase/mtd_write(). + * 7. Add to erase address pointer mtd->erasesize bytes. + * 8. goto 1 until the requested number of blocks have + * been written. + * + * (C) Copyright 2024 SaluteDevices, Inc. + * + * Author: Alexey Romanov <avromanov@salutedevices.com> + */ + +#include <blk.h> +#include <part.h> +#include <dm/device.h> +#include <dm/device-internal.h> +#include <linux/mtd/mtd.h> + +int mtd_bind(struct udevice *dev, struct mtd_info **mtd) +{ + struct blk_desc *bdesc; + struct udevice *bdev; + int ret; + + ret = blk_create_devicef(dev, "mtd_blk", "blk", UCLASS_MTD, + -1, 512, 0, &bdev); + if (ret) { + pr_err("Cannot create block device\n"); + return ret; + } + + bdesc = dev_get_uclass_plat(bdev); + dev_set_priv(bdev, mtd); + bdesc->bdev = bdev; + bdesc->part_type = PART_TYPE_MTD; + + return 0; +} + +static ulong mtd_blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, + void *dst) +{ + struct blk_desc *block_dev = dev_get_uclass_plat(dev); + struct mtd_info *mtd = blk_desc_to_mtd(block_dev); + unsigned int sect_size = block_dev->blksz; + lbaint_t cur = start; + ulong read_cnt = 0; + + while (read_cnt < blkcnt) { + int ret; + loff_t sect_start = cur * sect_size; + size_t retlen; + + ret = mtd_read(mtd, sect_start, sect_size, &retlen, dst); + if (ret) + return ret; + + if (retlen != sect_size) { + pr_err("mtdblock: failed to read block 0x" LBAF "\n", cur); + return -EIO; + } + + cur++; + dst += sect_size; + read_cnt++; + } + + return read_cnt; +} + +static int mtd_erase_write(struct mtd_info *mtd, uint64_t start, const void *src) +{ + int ret; + size_t retlen; + struct erase_info erase = { 0 }; + + erase.mtd = mtd; + erase.addr = start; + erase.len = mtd->erasesize; + + ret = mtd_erase(mtd, &erase); + if (ret) + return ret; + + ret = mtd_write(mtd, start, mtd->erasesize, &retlen, src); + if (ret) + return ret; + + if (retlen != mtd->erasesize) { + pr_err("mtdblock: failed to read block at 0x%llx\n", start); + return -EIO; + } + + return 0; +} + +static ulong mtd_blk_write(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, + const void *src) +{ + struct blk_desc *block_dev = dev_get_uclass_plat(dev); + struct mtd_info *mtd = blk_desc_to_mtd(block_dev); + unsigned int sect_size = block_dev->blksz; + lbaint_t cur = start, blocks_todo = blkcnt; + ulong write_cnt = 0; + u8 *buf; + int ret = 0; + + buf = malloc(mtd->erasesize); + if (!buf) + return -ENOMEM; + + while (blocks_todo > 0) { + loff_t sect_start = cur * sect_size; + loff_t erase_start = ALIGN_DOWN(sect_start, mtd->erasesize); + u32 offset = sect_start - erase_start; + size_t cur_size = min_t(size_t, mtd->erasesize - offset, + blocks_todo * sect_size); + size_t retlen; + lbaint_t written; + + ret = mtd_read(mtd, erase_start, mtd->erasesize, &retlen, buf); + if (ret) + goto out; + + if (retlen != mtd->erasesize) { + pr_err("mtdblock: failed to read block 0x" LBAF "\n", cur); + ret = -EIO; + goto out; + } + + memcpy(buf + offset, src, cur_size); + + ret = mtd_erase_write(mtd, erase_start, buf); + if (ret) + goto out; + + written = cur_size / sect_size; + + blocks_todo -= written; + cur += written; + src += cur_size; + write_cnt += written; + } + +out: + free(buf); + + if (ret) + return ret; + + return write_cnt; +} + +static int mtd_blk_probe(struct udevice *dev) +{ + struct blk_desc *bdesc; + struct mtd_info *mtd; + int ret; + + ret = device_probe(dev); + if (ret) { + pr_err("Probing %s failed (err=%d)\n", dev->name, ret); + return ret; + } + + bdesc = dev_get_uclass_plat(dev); + mtd = blk_desc_to_mtd(bdesc); + + if (mtd_type_is_nand(mtd)) + pr_warn("MTD device '%s' is NAND, please use UBI devices instead\n", + mtd->name); + + return 0; +} + +static const struct blk_ops mtd_blk_ops = { + .read = mtd_blk_read, + .write = mtd_blk_write, +}; + +U_BOOT_DRIVER(mtd_blk) = { + .name = "mtd_blk", + .id = UCLASS_BLK, + .ops = &mtd_blk_ops, + .probe = mtd_blk_probe, +}; diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index be1d19b4ffa..88094b81e7a 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -20,6 +20,8 @@ #endif #include <malloc.h> +#include <memalign.h> +#include <part.h> #include <linux/bug.h> #include <linux/errno.h> #include <linux/compat.h> @@ -1054,3 +1056,77 @@ uint64_t mtd_get_device_size(const struct mtd_info *mtd) return mtd->size; } EXPORT_SYMBOL_GPL(mtd_get_device_size); + +static struct mtd_info *mtd_get_partition_by_index(struct mtd_info *mtd, int index) +{ + struct mtd_info *part; + int i = 0; + + list_for_each_entry(part, &mtd->partitions, node) + if (i++ == index) + return part; + + debug("Partition with idx=%d not found on MTD device %s\n", index, mtd->name); + return NULL; +} + +static int __maybe_unused part_get_info_mtd(struct blk_desc *dev_desc, int part_idx, + struct disk_partition *info) +{ + struct mtd_info *master = blk_desc_to_mtd(dev_desc); + struct mtd_info *part; + + if (!master) { + debug("MTD device is NULL\n"); + return -EINVAL; + } + + part = mtd_get_partition_by_index(master, part_idx); + if (!part) { + debug("Failed to find partition with idx=%d\n", part_idx); + return -EINVAL; + } + + snprintf(info->name, PART_NAME_LEN, part->name); + info->start = part->offset / dev_desc->blksz; + info->size = part->size / dev_desc->blksz; + info->blksz = dev_desc->blksz; + + return 0; +} + +static void __maybe_unused part_print_mtd(struct blk_desc *dev_desc) +{ + struct mtd_info *master = blk_desc_to_mtd(dev_desc); + struct mtd_info *part; + + if (!master) + return; + + list_for_each_entry(part, &master->partitions, node) + printf("- 0x%012llx-0x%012llx : \"%s\"\n", + part->offset, part->offset + part->size, part->name); +} + +static int part_test_mtd(struct blk_desc *dev_desc) +{ + struct mtd_info *master = blk_desc_to_mtd(dev_desc); + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); + + if (!master) + return -1; + + if (blk_dread(dev_desc, 0, 1, (ulong *)buffer) != 1) + return -1; + + return 0; +} + +U_BOOT_PART_TYPE(mtd) = { + .name = "MTD", + .part_type = PART_TYPE_MTD, + .max_entries = MTD_ENTRY_NUMBERS, + .get_info = part_get_info_ptr(part_get_info_mtd), + .print = part_print_ptr(part_print_mtd), + .test = part_test_mtd, +}; diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index ef50237f10e..f5ddfbf4b83 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -25,6 +25,7 @@ #include <watchdog.h> #include <spi.h> #include <spi-mem.h> +#include <ubi_uboot.h> #include <dm/device_compat.h> #include <dm/devres.h> #include <linux/bitops.h> @@ -33,6 +34,10 @@ #include <linux/printk.h> #endif +struct spinand_plat { + struct mtd_info *mtd; +}; + /* SPI NAND index visible in MTD names */ static int spi_nand_idx; @@ -1172,12 +1177,32 @@ static void spinand_cleanup(struct spinand_device *spinand) kfree(spinand->scratchbuf); } +static int spinand_bind(struct udevice *dev) +{ + if (blk_enabled()) { + struct spinand_plat *plat = dev_get_plat(dev); + int ret; + + if (CONFIG_IS_ENABLED(MTD_BLOCK)) { + ret = mtd_bind(dev, &plat->mtd); + if (ret) + return ret; + } + + if (CONFIG_IS_ENABLED(UBI_BLOCK)) + return ubi_bind(dev); + } + + return 0; +} + static int spinand_probe(struct udevice *dev) { struct spinand_device *spinand = dev_get_priv(dev); struct spi_slave *slave = dev_get_parent_priv(dev); struct mtd_info *mtd = dev_get_uclass_priv(dev); struct nand_device *nand = spinand_to_nand(spinand); + struct spinand_plat *plat = dev_get_plat(dev); int ret; #ifndef __UBOOT__ @@ -1217,6 +1242,8 @@ static int spinand_probe(struct udevice *dev) if (ret) goto err_spinand_cleanup; + plat->mtd = mtd; + return 0; err_spinand_cleanup: @@ -1286,4 +1313,6 @@ U_BOOT_DRIVER(spinand) = { .of_match = spinand_ids, .priv_auto = sizeof(struct spinand_device), .probe = spinand_probe, + .bind = spinand_bind, + .plat_auto = sizeof(struct spinand_plat), }; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2206d734810..88709a52b3a 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -241,6 +241,8 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) }, + { INFO("is25lp01gg", 0x9d6021, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index fd446d6efb3..c027d898a64 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -114,5 +114,11 @@ config MTD_UBI_FM_DEBUG help Enable UBI fastmap debug +config UBI_BLOCK + bool "Enable UBI block device support" + depends on BLK + help + Enable UBI block device support using blk_ops abstraction. + endif # MTD_UBI endmenu # "Enable UBI - Unsorted block images" diff --git a/drivers/mtd/ubi/Makefile b/drivers/mtd/ubi/Makefile index 30d00fbdfe9..690ef9e901a 100644 --- a/drivers/mtd/ubi/Makefile +++ b/drivers/mtd/ubi/Makefile @@ -7,3 +7,4 @@ obj-y += attach.o build.o vtbl.o vmt.o upd.o kapi.o eba.o io.o wl.o crc32.o obj-$(CONFIG_MTD_UBI_FASTMAP) += fastmap.o obj-y += misc.o obj-y += debug.o +obj-$(CONFIG_UBI_BLOCK) += block.o part.o diff --git a/drivers/mtd/ubi/block.c b/drivers/mtd/ubi/block.c new file mode 100644 index 00000000000..99d55282cd7 --- /dev/null +++ b/drivers/mtd/ubi/block.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 SaluteDevices, Inc. + * + * Author: Alexey Romanov <avromanov@salutedevices.com> + */ + +#include <blk.h> +#include <part.h> +#include <ubi_uboot.h> +#include <dm/device.h> +#include <dm/device-internal.h> + +int ubi_bind(struct udevice *dev) +{ + struct blk_desc *bdesc; + struct udevice *bdev; + int ret; + + ret = blk_create_devicef(dev, "ubi_blk", "blk", UCLASS_MTD, + -1, 512, 0, &bdev); + if (ret) { + pr_err("Cannot create block device"); + return ret; + } + + bdesc = dev_get_uclass_plat(bdev); + + bdesc->bdev = bdev; + bdesc->part_type = PART_TYPE_UBI; + + return 0; +} + +static struct ubi_device *get_ubi_device(void) +{ + return ubi_devices[0]; +} + +static char *get_volume_name(int vol_id) +{ + struct ubi_device *ubi = get_ubi_device(); + int i; + + for (i = 0; i < (ubi->vtbl_slots + 1); i++) { + struct ubi_volume *volume = ubi->volumes[i]; + + if (!volume) + continue; + + if (volume->vol_id >= UBI_INTERNAL_VOL_START) + continue; + + if (volume->vol_id == vol_id) + return volume->name; + } + + return NULL; +} + +static ulong ubi_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, + void *dst) +{ + struct blk_desc *block_dev = dev_get_uclass_plat(dev); + char *volume_name = get_volume_name(block_dev->hwpart); + unsigned int size = blkcnt * block_dev->blksz; + loff_t offset = start * block_dev->blksz; + int ret; + + if (!volume_name) { + pr_err("%s: failed to find volume name for blk=" LBAF "\n", __func__, start); + return -EINVAL; + } + + ret = ubi_volume_read(volume_name, dst, offset, size); + if (ret) { + pr_err("%s: failed to read from %s UBI volume\n", __func__, volume_name); + return ret; + } + + return blkcnt; +} + +static ulong ubi_bwrite(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, + const void *src) +{ + struct blk_desc *block_dev = dev_get_uclass_plat(dev); + char *volume_name = get_volume_name(block_dev->hwpart); + unsigned int size = blkcnt * block_dev->blksz; + loff_t offset = start * block_dev->blksz; + int ret; + + if (!volume_name) { + pr_err("%s: failed to find volume for blk=" LBAF "\n", __func__, start); + return -EINVAL; + } + + ret = ubi_volume_write(volume_name, (void *)src, offset, size); + if (ret) { + pr_err("%s: failed to write from %s UBI volume\n", __func__, volume_name); + return ret; + } + + return blkcnt; +} + +static int ubi_blk_probe(struct udevice *dev) +{ + int ret; + + ret = device_probe(dev); + if (ret) { + pr_err("Probing %s failed (err=%d)\n", dev->name, ret); + return ret; + } + + return 0; +} + +static const struct blk_ops ubi_blk_ops = { + .read = ubi_bread, + .write = ubi_bwrite, +}; + +U_BOOT_DRIVER(ubi_blk) = { + .name = "ubi_blk", + .id = UCLASS_BLK, + .ops = &ubi_blk_ops, + .probe = ubi_blk_probe, +}; diff --git a/drivers/mtd/ubi/part.c b/drivers/mtd/ubi/part.c new file mode 100644 index 00000000000..13d1f165c30 --- /dev/null +++ b/drivers/mtd/ubi/part.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2024 SaluteDevices, Inc. + * + * Author: Alexey Romanov <avromanov@salutedevices.com> + */ + +#include <memalign.h> +#include <part.h> +#include <ubi_uboot.h> + +static inline struct ubi_device *get_ubi_device(void) +{ + return ubi_devices[0]; +} + +static struct ubi_volume *ubi_get_volume_by_index(int vol_id) +{ + struct ubi_device *ubi = get_ubi_device(); + int i; + + for (i = 0; i < (ubi->vtbl_slots + 1); i++) { + struct ubi_volume *volume = ubi->volumes[i]; + + if (!volume) + continue; + + if (volume->vol_id >= UBI_INTERNAL_VOL_START) + continue; + + if (volume->vol_id == vol_id) + return volume; + } + + return NULL; +} + +static int __maybe_unused part_get_info_ubi(struct blk_desc *dev_desc, int part_idx, + struct disk_partition *info) +{ + struct ubi_volume *vol; + + /* + * We must use part_idx - 1 instead of part_idx, because + * part_get_info_by_name() start indexing at 1, not 0. + * ubi volumes idexed starting at 0 + */ + vol = ubi_get_volume_by_index(part_idx - 1); + if (!vol) + return 0; + + snprintf(info->name, PART_NAME_LEN, vol->name); + + info->start = 0; + info->size = (unsigned long)vol->used_bytes / dev_desc->blksz; + info->blksz = dev_desc->blksz; + + /* Save UBI volume ID in blk device descriptor */ + dev_desc->hwpart = vol->vol_id; + + return 0; +} + +static void __maybe_unused part_print_ubi(struct blk_desc *dev_desc) +{ + struct ubi_device *ubi = get_ubi_device(); + int i; + + for (i = 0; i < (ubi->vtbl_slots + 1); i++) { + struct ubi_volume *volume = ubi->volumes[i]; + + if (!volume) + continue; + + if (volume->vol_id >= UBI_INTERNAL_VOL_START) + continue; + + printf("%d: %s\n", volume->vol_id, volume->name); + } +} + +static int part_test_ubi(struct blk_desc *dev_desc) +{ + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); + + if (blk_dread(dev_desc, 0, 1, (ulong *)buffer) != 1) + return -1; + + return 0; +} + +U_BOOT_PART_TYPE(ubi) = { + .name = "ubi", + .part_type = PART_TYPE_UBI, + .max_entries = UBI_ENTRY_NUMBERS, + .get_info = part_get_info_ptr(part_get_info_ubi), + .print = part_print_ptr(part_print_ubi), + .test = part_test_ubi, +}; diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 1b85cbcce8d..5145b517aa4 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -67,12 +67,15 @@ struct rockchip_combphy_grfcfg { }; struct rockchip_combphy_cfg { + unsigned int num_phys; + unsigned int phy_ids[3]; const struct rockchip_combphy_grfcfg *grfcfg; int (*combphy_cfg)(struct rockchip_combphy_priv *priv); }; struct rockchip_combphy_priv { u32 mode; + int id; void __iomem *mmio; struct udevice *dev; struct regmap *pipe_grf; @@ -270,8 +273,13 @@ static int rockchip_combphy_probe(struct udevice *udev) { struct rockchip_combphy_priv *priv = dev_get_priv(udev); const struct rockchip_combphy_cfg *phy_cfg; + fdt_addr_t addr = dev_read_addr(udev); + if (addr == FDT_ADDR_T_NONE) { + dev_err(udev, "No valid device address found\n"); + return -EINVAL; + } - priv->mmio = (void __iomem *)dev_read_addr(udev); + priv->mmio = (void __iomem *)addr; if (IS_ERR(priv->mmio)) return PTR_ERR(priv->mmio); @@ -281,6 +289,20 @@ static int rockchip_combphy_probe(struct udevice *udev) return -EINVAL; } + /* Find the phy-id based on the device's I/O-address */ + priv->id = -ENODEV; + for (int id = 0; id < phy_cfg->num_phys; id++) { + if (addr == phy_cfg->phy_ids[id]) { + priv->id = id; + break; + } + } + + if (priv->id == -ENODEV) { + dev_err(udev, "Failed to find PHY ID\n"); + return -ENODEV; + } + priv->dev = udev; priv->mode = PHY_TYPE_SATA; priv->cfg = phy_cfg; @@ -421,6 +443,12 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { }; static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { + .num_phys = 3, + .phy_ids = { + 0xfe820000, + 0xfe830000, + 0xfe840000, + }, .grfcfg = &rk3568_combphy_grfcfgs, .combphy_cfg = rk3568_combphy_cfg, }; @@ -436,8 +464,14 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) param_write(priv->phy_grf, &cfg->con1_for_pcie, true); param_write(priv->phy_grf, &cfg->con2_for_pcie, true); param_write(priv->phy_grf, &cfg->con3_for_pcie, true); - param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); - param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); + switch (priv->id) { + case 1: + param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); + break; + case 2: + param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); + break; + } break; case PHY_TYPE_USB3: param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); @@ -515,6 +549,12 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { }; static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { + .num_phys = 3, + .phy_ids = { + 0xfee00000, + 0xfee10000, + 0xfee20000, + }, .grfcfg = &rk3588_combphy_grfcfgs, .combphy_cfg = rk3588_combphy_cfg, }; diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c index 2464acf0b85..81a9327eb35 100644 --- a/drivers/pinctrl/pinctrl-generic.c +++ b/drivers/pinctrl/pinctrl-generic.c @@ -22,7 +22,7 @@ static int pinctrl_pin_name_to_selector(struct udevice *dev, const char *pin) if (!ops->get_pins_count || !ops->get_pin_name) { dev_dbg(dev, "get_pins_count or get_pin_name missing\n"); - return -ENOSYS; + return -ENOENT; } npins = ops->get_pins_count(dev); @@ -35,7 +35,7 @@ static int pinctrl_pin_name_to_selector(struct udevice *dev, const char *pin) return selector; } - return -ENOSYS; + return -ENOENT; } /** @@ -53,7 +53,7 @@ static int pinctrl_group_name_to_selector(struct udevice *dev, if (!ops->get_groups_count || !ops->get_group_name) { dev_dbg(dev, "get_groups_count or get_group_name missing\n"); - return -ENOSYS; + return -ENOENT; } ngroups = ops->get_groups_count(dev); @@ -66,7 +66,7 @@ static int pinctrl_group_name_to_selector(struct udevice *dev, return selector; } - return -ENOSYS; + return -ENOENT; } #if CONFIG_IS_ENABLED(PINMUX) @@ -86,7 +86,7 @@ static int pinmux_func_name_to_selector(struct udevice *dev, if (!ops->get_functions_count || !ops->get_function_name) { dev_dbg(dev, "get_functions_count or get_function_name missing\n"); - return -ENOSYS; + return -ENOENT; } nfuncs = ops->get_functions_count(dev); @@ -99,7 +99,7 @@ static int pinmux_func_name_to_selector(struct udevice *dev, return selector; } - return -ENOSYS; + return -ENOENT; } /** @@ -119,14 +119,14 @@ static int pinmux_enable_setting(struct udevice *dev, bool is_group, if (is_group) { if (!ops->pinmux_group_set) { dev_dbg(dev, "pinmux_group_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinmux_group_set(dev, selector, func_selector); } else { if (!ops->pinmux_set) { dev_dbg(dev, "pinmux_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinmux_set(dev, selector, func_selector); } @@ -162,7 +162,7 @@ static int pinconf_prop_name_to_param(struct udevice *dev, if (!ops->pinconf_num_params || !ops->pinconf_params) { dev_dbg(dev, "pinconf_num_params or pinconf_params missing\n"); - return -ENOSYS; + return -ENOENT; } p = ops->pinconf_params; @@ -176,7 +176,7 @@ static int pinconf_prop_name_to_param(struct udevice *dev, } } - return -ENOSYS; + return -ENOENT; } /** @@ -198,7 +198,7 @@ static int pinconf_enable_setting(struct udevice *dev, bool is_group, if (is_group) { if (!ops->pinconf_group_set) { dev_dbg(dev, "pinconf_group_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinconf_group_set(dev, selector, param, @@ -206,7 +206,7 @@ static int pinconf_enable_setting(struct udevice *dev, bool is_group, } else { if (!ops->pinconf_set) { dev_dbg(dev, "pinconf_set op missing\n"); - return -ENOSYS; + return -ENOENT; } return ops->pinconf_set(dev, selector, param, argument); } @@ -215,7 +215,7 @@ static int pinconf_enable_setting(struct udevice *dev, bool is_group, static int pinconf_prop_name_to_param(struct udevice *dev, const char *property, u32 *default_value) { - return -ENOSYS; + return -ENOENT; } static int pinconf_enable_setting(struct udevice *dev, bool is_group, diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index a871fc41987..c2fc1c6b42f 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -33,8 +33,6 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) p->bus); return -ENXIO; } -#else /* Non DM I2C support - will be removed */ - I2C_SET_BUS(p->bus); #endif switch (pmic_i2c_tx_num) { @@ -93,9 +91,6 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) return -ENXIO; } ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num); -#else /* Non DM I2C support - will be removed */ - I2C_SET_BUS(p->bus); - ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num); #endif if (ret) return ret; diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index a2d5b82fd34..0c45c781fef 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -44,6 +44,7 @@ enum { ZYNQMP_VARIANT_DR_SE = BIT(4), ZYNQMP_VARIANT_EG_SE = BIT(5), ZYNQMP_VARIANT_TEG = BIT(6), + ZYNQMP_VARIANT_EG_LR = BIT(7), }; struct zynqmp_device { @@ -65,6 +66,11 @@ static const struct zynqmp_device zynqmp_devices[] = { .variants = ZYNQMP_VARIANT_EG, }, { + .id = 0x04689093, + .device = 1, + .variants = ZYNQMP_VARIANT_EG_LR, + }, + { .id = 0x04711093, .device = 2, .variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG, @@ -300,6 +306,8 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, strlcat(priv->machine, "eg", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_EG_SE) { strlcat(priv->machine, "eg_SE", sizeof(priv->machine)); + } else if (device->variants & ZYNQMP_VARIANT_EG_LR) { + strlcat(priv->machine, "eg_LR", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_DR) { strlcat(priv->machine, "dr", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_DR_SE) { diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 9bdb4a5bff9..a8ec2f4f7b4 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -237,6 +237,18 @@ static int soft_spi_of_to_plat(struct udevice *dev) return 0; } +static int retrieve_num_chipselects(struct udevice *dev) +{ + int chipselects; + int ret; + + ret = ofnode_read_u32(dev_ofnode(dev), "num-chipselects", &chipselects); + if (ret) + return ret; + + return chipselects; +} + static int soft_spi_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); @@ -249,7 +261,15 @@ static int soft_spi_probe(struct udevice *dev) ret = gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, GPIOD_IS_OUT | cs_flags); - if (ret) + /* + * If num-chipselects is zero we're ignoring absence of cs-gpios. This + * code relies on the fact that `gpio_request_by_name` call above + * initiailizes plat->cs to correct value with invalid GPIO even when + * there is no cs-gpios node in dts. All other functions which work + * with plat->cs verify it via `dm_gpio_is_valid` before using it, so + * such value doesn't cause any problems. + */ + if (ret && retrieve_num_chipselects(dev) != 0) return -EINVAL; ret = gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, @@ -271,7 +291,7 @@ static int soft_spi_probe(struct udevice *dev) ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso, GPIOD_IS_IN); if (ret) - ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso, + ret = gpio_request_by_name(dev, "miso-gpios", 0, &plat->miso, GPIOD_IS_IN); if (ret) plat->flags |= SPI_MASTER_NO_RX; diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index a7333d8d9c0..88550b8ea84 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -233,7 +233,7 @@ err_ahb: static void sun4i_spi_set_speed_mode(struct udevice *dev) { struct sun4i_spi_priv *priv = dev_get_priv(dev); - unsigned int div; + unsigned int div, div_cdr2; u32 reg; /* @@ -249,6 +249,8 @@ static void sun4i_spi_set_speed_mode(struct udevice *dev) * We have two choices there. Either we can use the clock * divide rate 1, which is calculated thanks to this formula: * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) + * Or for sun6i/sun8i variants: + * SPI_CLK = MOD_CLK / (2 ^ cdr) * Or we can use CDR2, which is calculated with the formula: * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) * Whether we use the former or the latter is set through the @@ -256,18 +258,18 @@ static void sun4i_spi_set_speed_mode(struct udevice *dev) * * First try CDR2, and if we can't reach the expected * frequency, fall back to CDR1. + * There is one exception if the requested clock is the input + * clock. In that case we always use CDR1 because we'll get a + * 1:1 ration for sun6i/sun8i variants. */ div = DIV_ROUND_UP(SUNXI_INPUT_CLOCK, priv->freq); + div_cdr2 = DIV_ROUND_UP(div, 2); reg = readl(SPI_REG(priv, SPI_CCR)); - if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { - div /= 2; - if (div > 0) - div--; - + if (div != 1 && (div_cdr2 <= (SUN4I_CLK_CTL_CDR2_MASK + 1))) { reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); - reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; + reg |= SUN4I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN4I_CLK_CTL_DRS; } else { div = fls(div - 1); /* The F1C100s encodes the divider as 2^(n+1) */ diff --git a/drivers/tpm/tpm2_tis_core.c b/drivers/tpm/tpm2_tis_core.c index 680a6409433..1fdf8cfa319 100644 --- a/drivers/tpm/tpm2_tis_core.c +++ b/drivers/tpm/tpm2_tis_core.c @@ -419,6 +419,28 @@ static bool tis_check_ops(struct tpm_tis_phy_ops *phy_ops) return true; } +static int tpm_tis_wait_init(struct udevice *dev, int loc) +{ + struct tpm_chip *chip = dev_get_priv(dev); + unsigned long start, stop; + u8 status; + int ret; + + start = get_timer(0); + stop = chip->timeout_b; + do { + mdelay(TPM_TIMEOUT_MS); + ret = chip->phy_ops->read_bytes(dev, TPM_ACCESS(loc), 1, &status); + if (ret) + break; + + if (status & TPM_ACCESS_VALID) + return 0; + } while (get_timer(start) < stop); + + return -EIO; +} + int tpm_tis_init(struct udevice *dev) { struct tpm_chip *chip = dev_get_priv(dev); @@ -436,6 +458,12 @@ int tpm_tis_init(struct udevice *dev) chip->timeout_c = TIS_SHORT_TIMEOUT_MS; chip->timeout_d = TIS_SHORT_TIMEOUT_MS; + ret = tpm_tis_wait_init(dev, chip->locality); + if (ret) { + log(LOGC_DM, LOGL_ERR, "%s: no device found\n", __func__); + return ret; + } + ret = tpm_tis_request_locality(dev, 0); if (ret) return ret; diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index d35a4dd3a36..c433e8088ac 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -187,29 +187,6 @@ static int tpm_tis_spi_write32(struct udevice *dev, u32 addr, u32 value) return tpm_tis_spi_write(dev, addr, sizeof(value), (u8 *)&value_le); } -static int tpm_tis_wait_init(struct udevice *dev, int loc) -{ - struct tpm_chip *chip = dev_get_priv(dev); - unsigned long start, stop; - u8 status; - int ret; - - start = get_timer(0); - stop = chip->timeout_b; - do { - mdelay(TPM_TIMEOUT_MS); - - ret = tpm_tis_spi_read(dev, TPM_ACCESS(loc), 1, &status); - if (ret) - break; - - if (status & TPM_ACCESS_VALID) - return 0; - } while (get_timer(start) < stop); - - return -EIO; -} - static struct tpm_tis_phy_ops phy_ops = { .read_bytes = tpm_tis_spi_read, .write_bytes = tpm_tis_spi_write, @@ -221,7 +198,6 @@ static int tpm_tis_spi_probe(struct udevice *dev) { struct tpm_tis_chip_data *drv_data = (void *)dev_get_driver_data(dev); struct tpm_chip_priv *priv = dev_get_uclass_priv(dev); - struct tpm_chip *chip = dev_get_priv(dev); int ret; /* Use the TPM v2 stack */ @@ -255,12 +231,6 @@ static int tpm_tis_spi_probe(struct udevice *dev) /* Ensure a minimum amount of time elapsed since reset of the TPM */ mdelay(drv_data->time_before_first_cmd_ms); - ret = tpm_tis_wait_init(dev, chip->locality); - if (ret) { - log(LOGC_DM, LOGL_ERR, "%s: no device found\n", __func__); - return ret; - } - tpm_tis_ops_register(dev, &phy_ops); ret = tpm_tis_init(dev); if (ret) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index c443d56746d..a35b8c2f646 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -594,7 +594,8 @@ static int dwc3_core_init(struct dwc3 *dwc) reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); /* This should read as U3 followed by revision number */ - if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { + if ((reg & DWC3_GSNPSID_MASK) != 0x55330000 && + (reg & DWC3_GSNPSID_MASK) != 0x33310000) { dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); ret = -ENODEV; goto err0; diff --git a/drivers/usb/emul/sandbox_flash.c b/drivers/usb/emul/sandbox_flash.c index 24420e3d51e..b5176bb30ce 100644 --- a/drivers/usb/emul/sandbox_flash.c +++ b/drivers/usb/emul/sandbox_flash.c @@ -196,7 +196,7 @@ static int handle_ufi_command(struct sandbox_flash_priv *priv, const void *buff, priv->fd != -1) { offset = os_lseek(priv->fd, info->seek_block * info->block_size, OS_SEEK_SET); - if (offset == (off_t)-1) + if (offset < 0) setup_fail_response(priv); else setup_response(priv); diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index ed04cae7afe..bf89bf8ab49 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -94,10 +94,6 @@ static int isp1301_set_value(struct udevice *dev, int reg, u8 value) static void isp1301_configure(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_set_bus_num(I2C_2); -#endif - /* * LPC32XX only supports DAT_SE0 USB mode * This sequence is important diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts index 079101cddd6..62d18ca769a 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts +++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-pi-s.dts @@ -17,6 +17,7 @@ ethernet0 = &gmac; mmc0 = &emmc; mmc1 = &sdmmc; + mmc2 = &sdio; }; chosen { @@ -144,11 +145,25 @@ &gmac { clock_in_out = "output"; + phy-handle = <&rtl8201f>; phy-supply = <&vcc_io>; - snps,reset-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 50000 50000>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8201f: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mac_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + }; + }; }; &gpio0 { @@ -217,10 +232,40 @@ status = "okay"; }; +&io_domains { + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_io>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_io>; + status = "okay"; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&rtc_32k>; + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + mac_rst: mac-rst { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { green_led: green-led { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; @@ -264,15 +309,31 @@ cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; - max-frequency = <1000000>; + max-frequency = <100000000>; mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; non-removable; - sd-uhs-sdr104; + sd-uhs-sdr50; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_1v8>; status = "okay"; + + rtl8723ds: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + }; }; &sdmmc { + cap-mmc-highspeed; cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_io>; status = "okay"; }; @@ -291,16 +352,22 @@ }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; status = "okay"; }; &uart4 { + uart-has-rtscts; status = "okay"; bluetooth { - compatible = "realtek,rtl8723bs-bt"; - device-wake-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + compatible = "realtek,rtl8723ds-bt"; + device-wake-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; host-wake-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; }; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts new file mode 100644 index 00000000000..bd6419a5c20 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3308-rock-s0.dts @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "rk3308.dtsi" + +/ { + model = "Radxa ROCK S0"; + compatible = "radxa,rock-s0", "rockchip,rk3308"; + + aliases { + ethernet0 = &gmac; + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led>; + + led-green { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_log: regulator-1v04-vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1040000>; + regulator-max-microvolt = <1040000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v5-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_io: regulator-3v3-vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_core: regulator-vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_core"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-settling-time-up-us = <250>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_pwren>; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-handle = <&rtl8201f>; + phy-supply = <&vcc_io>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8201f: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mac_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&io_domains { + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_io>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_io>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&rtc_32k>; + + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + mac_rst: mac-rst { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + pwr_led: pwr-led { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>; + }; +}; + +&sdmmc { + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart4 { + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + clocks = <&cru SCLK_RTC32K>; + clock-names = "lpo"; + interrupt-parent = <&gpio4>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + vbat-supply = <&vcc_io>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3308.dtsi b/dts/upstream/src/arm64/rockchip/rk3308.dtsi index c00da150a22..31c25de2d68 100644 --- a/dts/upstream/src/arm64/rockchip/rk3308.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3308.dtsi @@ -173,6 +173,11 @@ compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; reg = <0x0 0xff000000 0x0 0x08000>; + io_domains: io-domains { + compatible = "rockchip,rk3308-io-voltage-domain"; + status = "disabled"; + }; + reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x500>; @@ -556,6 +561,30 @@ status = "disabled"; }; + otp: efuse@ff210000 { + compatible = "rockchip,rk3308-otp"; + reg = <0x0 0xff210000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, + <&cru PCLK_OTP_PHY>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTP_PHY>; + reset-names = "phy"; + + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + logic_leakage: logic-leakage@18 { + reg = <0x18 0x1>; + }; + }; + dmac0: dma-controller@ff2c0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff2c0000 0x0 0x4000>; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v1.1.dts b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v1.1.dts new file mode 100644 index 00000000000..074e93bd4b8 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v1.1.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v1.1"; + compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio5-supply = <&vcc_3v3>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v2.1.dts b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v2.1.dts new file mode 100644 index 00000000000..d894bff41e6 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b-v2.1.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v2.1"; + compatible = "xunlong,orangepi-3b-v2.1", "xunlong,orangepi-3b", "rockchip,rk3566"; + + vccio_phy1: regulator-1v8-vccio-phy { + compatible = "regulator-fixed"; + regulator-name = "vccio_phy1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; +}; + +&pmu_io_domains { + vccio5-supply = <&vccio_phy1>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + }; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&uart1 { + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + interrupt-parent = <&gpio2>; + interrupts = <RK_PC0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b.dtsi new file mode 100644 index 00000000000..d539570f531 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-orangepi-3b.dtsi @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "Xunlong Orange Pi 3B"; + compatible = "xunlong,orangepi-3b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc3v3_pcie30: regulator-3v3-vcc-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-5v0-vcc-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pins>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led: work-led { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_pins: pcie20-pins { + rockchip,pins = + <1 RK_PB0 4 &pcfg_pull_none>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + pcie20_pwren: pcie20-pwren { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3.dtsi new file mode 100644 index 00000000000..9cc7aa3298d --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3.dtsi @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led2>; + + led-green { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcca_1v8: regulator-1v8-vcca { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcca1v8_image: regulator-1v8-vcca-image { + compatible = "regulator-fixed"; + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_p>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpio0 { + gpio-line-names = + /* GPIO0_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO0_D0 - D7 */ + "pin-10 [GPIO0_D0]", "pin-08 [GPIO0_D1]", "", + "", "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1_A0 - A7 */ + "pin-03 [GPIO1_A0]", "pin-05 [GPIO1_A1]", "", + "", "pin-37 [GPIO1_A4]", "", + "", "", + /* GPIO1_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO1_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_B0 - B7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_C0 - C7 */ + "", "", "", "", "", "", "", "", + /* GPIO2_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3_A0 - A7 */ + "", "pin-11 [GPIO3_A1]", "pin-13 [GPIO3_A2]", + "pin-12 [GPIO3_A3]", "pin-35 [GPIO3_A4]", "pin-40 [GPIO3_A5]", + "pin-38 [GPIO3_A6]", "pin-36 [GPIO3_A7]", + /* GPIO3_B0 - B7 */ + "pin-15 [GPIO3_B0]", "pin-16 [GPIO3_B1]", "pin-18 [GPIO3_B2]", + "pin-29 [GPIO3_B3]", "pin-31 [GPIO3_B4]", "", + "", "", + /* GPIO3_C0 - C7 */ + "", "pin-22 [GPIO3_C1]", "pin-32 [GPIO3_C2]", + "pin-33 [GPIO3_C3]", "pin-07 [GPIO3_C4]", "", + "", "", + /* GPIO3_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4_A0 - A7 */ + "", "", "", "", "", "", "", "", + /* GPIO4_B0 - B7 */ + "", "", "pin-27 [GPIO4_B2]", + "pin-28 [GPIO4_B3]", "", "", "", "", + /* GPIO4_C0 - C7 */ + "", "", "pin-23 [GPIO4_C2]", + "pin-19 [GPIO4_C3]", "", "pin-21 [GPIO4_C5]", + "pin-24 [GPIO4_C6]", "", + /* GPIO4_D0 - D7 */ + "", "", "", "", "", "", "", ""; +}; + +&gpu { + mali-supply = <&vdd_gpu_npu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "rk817-clkout1", "rk817-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc5v_midu>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-name = "vdd_gpu_npu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8_p: LDO_REG7 { + regulator-name = "vcc_1v8_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-name = "vcc2v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_midu: BOOST { + regulator-name = "vcc5v_midu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbus: OTG_SWITCH { + regulator-name = "vbus"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "rockchip,rk8600"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pinctrl { + leds { + user_led2: user-led2 { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3e.dts b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3e.dts new file mode 100644 index 00000000000..4a830eb09f0 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3e.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-radxa-zero-3.dtsi" + +/ { + model = "Radxa ZERO 3E"; + compatible = "radxa,zero-3e", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac1 { + gmac1_rstn: gmac1-rstn { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3w.dts b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3w.dts new file mode 100644 index 00000000000..f92475c59de --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3566-radxa-zero-3w.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-radxa-zero-3.dtsi" + +/ { + model = "Radxa ZERO 3W"; + compatible = "radxa,zero-3w", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts index b242409d378..f2cc086e500 100644 --- a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts +++ b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts @@ -633,7 +633,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; - spi-max-frequency = <120000000>; + spi-max-frequency = <104000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3568-rock-3b.dts b/dts/upstream/src/arm64/rockchip/rk3568-rock-3b.dts new file mode 100644 index 00000000000..3d0c1ccfaa7 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3568-rock-3b.dts @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Radxa ROCK 3B"; + compatible = "radxa,rock-3b", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_ir>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pi6c_03"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <10000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys2: regulator-3v3-vcc-sys2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-5v0-vcc-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&rtcic_int_l>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20m1_pins>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys2>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir-receiver { + pwm3_ir: pwm3-ir { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led: led { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie20 { + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + <2 RK_PD0 4 &pcfg_pull_none>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + <2 RK_PD4 4 &pcfg_pull_none>, + <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtc { + rtcic_int_l: rtcic-int-l { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys2>; + vqmmc-supply = <&vcc_1v8>; + status = "disabled"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + uart-has-rtscts; + status = "disabled"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi index 30db12c4fc8..30db12c4fc8 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s-pinctrl.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-base-pinctrl.dtsi diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi new file mode 100644 index 00000000000..78bc9dc9704 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi @@ -0,0 +1,2823 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/power/rk3588-power.h> +#include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "rockchip,rk3588"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu_b2>; + }; + core1 { + cpu = <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_b0: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b0>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b1: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b1>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b2: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b2>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b3: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b3>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <100>; + exit-latency-us = <120>; + min-residency-us = <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-level = <3>; + cache-unified; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + spll: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <702000000>; + clock-output-names = "spll"; + #clock-cells = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; + + xin24m: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: clock-2 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + pmu_sram: sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + ranges = <0 0x0 0x0010f000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gpu: gpu@fb000000 { + compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; + reg = <0x0 0xfb000000 0x0 0x200000>; + #cooling-cells = <2>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + clock-names = "core", "coregroup", "stacks"; + dynamic-power-coefficient = <2982>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3588_PD_GPU>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>; + }; + }; + }; + + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + pmu1grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58a000 0x0 0x10000>; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&cru PCLK_VO1GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + }; + + system_sram1: sram@fd600000 { + compatible = "mmio-sram"; + reg = <0x0 0xfd600000 0x0 0x100000>; + ranges = <0x0 0x0 0xfd600000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + assigned-clocks = + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>; + assigned-clock-rates = + <1100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <800000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, <500000000>, + <375000000>, <150000000>, + <200000000>; + rockchip,grf = <&php_grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@fd880000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart0m1_xfer>; + pinctrl-names = "default"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0000 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0020 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0030 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible = "rockchip,rk3588-power-controller"; + #address-cells = <1>; + #power-domain-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg = <RK3588_PD_NPU>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPUTOP { + reg = <RK3588_PD_NPUTOP>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>, + <&cru HCLK_NPU_CM0_ROOT>; + pm_qos = <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPU1 { + reg = <RK3588_PD_NPU1>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_NPU2 { + reg = <RK3588_PD_NPU2>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu2>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg = <RK3588_PD_GPU>; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + pm_qos = <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + #power-domain-cells = <0>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg = <RK3588_PD_VCODEC>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg = <RK3588_PD_RKVDEC0>; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>, + <&cru ACLK_RKVDEC_CCU>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = <RK3588_PD_RKVDEC1>; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC1>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VENC0 { + reg = <RK3588_PD_VENC0>; + clocks = <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>; + pm_qos = <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VENC1 { + reg = <RK3588_PD_VENC1>; + clocks = <&cru HCLK_RKVENC1>, + <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>, + <&cru ACLK_RKVENC1>; + pm_qos = <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg = <RK3588_PD_VDPU>; + clocks = <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_LOW_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_JPEG_DECODER_ROOT>, + <&cru ACLK_IEP2P0>, + <&cru HCLK_IEP2P0>, + <&cru ACLK_JPEG_ENCODER0>, + <&cru HCLK_JPEG_ENCODER0>, + <&cru ACLK_JPEG_ENCODER1>, + <&cru HCLK_JPEG_ENCODER1>, + <&cru ACLK_JPEG_ENCODER2>, + <&cru HCLK_JPEG_ENCODER2>, + <&cru ACLK_JPEG_ENCODER3>, + <&cru HCLK_JPEG_ENCODER3>, + <&cru ACLK_JPEG_DECODER>, + <&cru HCLK_JPEG_DECODER>, + <&cru ACLK_RGA2>, + <&cru HCLK_RGA2>; + pm_qos = <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + + power-domain@RK3588_PD_AV1 { + reg = <RK3588_PD_AV1>; + clocks = <&cru PCLK_AV1>, + <&cru ACLK_AV1>, + <&cru HCLK_VDPU_ROOT>; + pm_qos = <&qos_av1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC0 { + reg = <RK3588_PD_RKVDEC0>; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = <RK3588_PD_RKVDEC1>; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RGA30 { + reg = <RK3588_PD_RGA30>; + clocks = <&cru ACLK_RGA3_0>, + <&cru HCLK_RGA3_0>; + pm_qos = <&qos_rga3_0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VOP { + reg = <RK3588_PD_VOP>; + clocks = <&cru PCLK_VOP_ROOT>, + <&cru HCLK_VOP_ROOT>, + <&cru ACLK_VOP>; + pm_qos = <&qos_vop_m0>, + <&qos_vop_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VO0 { + reg = <RK3588_PD_VO0>; + clocks = <&cru PCLK_VO0_ROOT>, + <&cru PCLK_VO0_S_ROOT>, + <&cru HCLK_VO0_S_ROOT>, + <&cru ACLK_VO0_ROOT>, + <&cru HCLK_HDCP0>, + <&cru ACLK_HDCP0>, + <&cru HCLK_VOP_ROOT>; + pm_qos = <&qos_hdcp0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VO1 { + reg = <RK3588_PD_VO1>; + clocks = <&cru PCLK_VO1_ROOT>, + <&cru PCLK_VO1_S_ROOT>, + <&cru HCLK_VO1_S_ROOT>, + <&cru HCLK_HDCP1>, + <&cru ACLK_HDCP1>, + <&cru ACLK_HDMIRX_ROOT>, + <&cru HCLK_VO1USB_TOP_ROOT>; + pm_qos = <&qos_hdcp1>, + <&qos_hdmirx>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VI { + reg = <RK3588_PD_VI>; + clocks = <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>, + <&cru HCLK_ISP0>, + <&cru ACLK_ISP0>, + <&cru HCLK_VICAP>, + <&cru ACLK_VICAP>; + pm_qos = <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_ISP1 { + reg = <RK3588_PD_ISP1>; + clocks = <&cru HCLK_ISP1>, + <&cru ACLK_ISP1>, + <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_isp1_mwo>, + <&qos_isp1_mro>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_FEC { + reg = <RK3588_PD_FEC>; + clocks = <&cru HCLK_FISHEYE0>, + <&cru ACLK_FISHEYE0>, + <&cru HCLK_FISHEYE1>, + <&cru ACLK_FISHEYE1>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_fisheye0>, + <&qos_fisheye1>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg = <RK3588_PD_RGA31>; + clocks = <&cru HCLK_RGA3_1>, + <&cru ACLK_RGA3_1>; + pm_qos = <&qos_rga3_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_USB { + reg = <RK3588_PD_USB>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_USB_ROOT>, + <&cru ACLK_USB>, + <&cru HCLK_USB_ROOT>, + <&cru HCLK_HOST0>, + <&cru HCLK_HOST_ARB0>, + <&cru HCLK_HOST1>, + <&cru HCLK_HOST_ARB1>; + pm_qos = <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_GMAC { + reg = <RK3588_PD_GMAC>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_PCIE { + reg = <RK3588_PD_PCIE>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDIO { + reg = <RK3588_PD_SDIO>; + clocks = <&cru HCLK_SDIO>, + <&cru HCLK_NVM_ROOT>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_AUDIO { + reg = <RK3588_PD_AUDIO>; + clocks = <&cru HCLK_AUDIO_ROOT>, + <&cru PCLK_AUDIO_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDMMC { + reg = <RK3588_PD_SDMMC>; + pm_qos = <&qos_sdmmc>; + #power-domain-cells = <0>; + }; + }; + }; + + av1d: video-codec@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3588_PD_AV1>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + }; + + dfi: dfi@fe060000 { + reg = <0x00 0xfe060000 0x00 0x10000>; + compatible = "rockchip,rk3588-dfi"; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; + rockchip,pmu = <&pmu1grf>; + }; + + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power RK3588_PD_SDMMC>; + status = "disabled"; + }; + + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-controller; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; + ranges; + #address-cells = <2>; + #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + ppi-partitions { + ppi_partition0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + ppi_partition1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; + }; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dma-controller@fea30000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fea90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c1m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeaa0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfead0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + spi0: spi@feb00000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@feb10000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb10000 0x0 0x1000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@feb20000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@feb30000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb30000 0x0 0x1000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 17>, <&dmac1 18>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@feb40000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb40000 0x0 0x100>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart1m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb50000 0x0 0x100>; + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart2m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart3m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@feb70000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 9>, <&dmac1 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart4m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@feb80000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb80000 0x0 0x100>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 11>, <&dmac1 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart5m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@feb90000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb90000 0x0 0x100>; + interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 13>, <&dmac1 14>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart6m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@feba0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 7>, <&dmac2 8>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart7m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@febb0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebb0000 0x0 0x100>; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 9>, <&dmac2 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart8m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@febc0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebc0000 0x0 0x100>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 11>, <&dmac2 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart9m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore0_alert: bigcore0-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore0_crit: bigcore0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore0_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + bigcore2_alert: bigcore2-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore2_crit: bigcore2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore2_alert>; + cooling-device = + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 6>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c6m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec90000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c7m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeca0000 0x0 0x1000>; + clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c8m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@fecb0000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfecb0000 0x0 0x1000>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac2 13>, <&dmac2 14>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + hdptxphy_hdmi0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + status = "disabled"; + }; + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + + system_sram2: sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + ranges = <0x0 0x0 0xff001000 0xef000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + ranges; + rockchip,grf = <&ioc>; + #address-cells = <2>; + #size-cells = <2>; + + gpio0: gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3588-base-pinctrl.dtsi" diff --git a/dts/upstream/src/arm64/rockchip/rk3588-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra-pinctrl.dtsi index 244c66faa16..244c66faa16 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588-pinctrl.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588-extra-pinctrl.dtsi diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi new file mode 100644 index 00000000000..37101768999 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588-base.dtsi" +#include "rk3588-extra-pinctrl.dtsi" + +/ { + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + #clock-cells = <0>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts new file mode 100644 index 00000000000..83103e4c721 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -0,0 +1,778 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * Copyright (c) 2024 Sebastian Kropatsch + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588-friendlyelec-cm3588.dtsi" + +/ { + model = "FriendlyElec CM3588 NAS"; + compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588"; + + adc_key_recovery: adc-key-recovery { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = <KEY_VENDOR>; + press-threshold-microvolt = <17000>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&headphone_detect>; + + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "realtek,rt5616-codec"; + + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Microphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + buzzer: pwm-beeper { + compatible = "pwm-beeper"; + amp-supply = <&vcc_5v0_sys>; + beeper-hz = <500>; + pwms = <&pwm8 0 500000 0>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 80 120 160 220>; + fan-supply = <&vcc_5v0_sys>; + pwms = <&pwm1 0 50000 0>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button-user { + debounce-interval = <50>; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; + label = "User Button"; + linux,code = <BTN_1>; + wakeup-source; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + vcc_12v_dcin: regulator-vcc-12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_3v3_m2_a: regulator-vcc-3v3-m2-a { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_b: regulator-vcc-3v3-m2-b { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_c: regulator-vcc-3v3-m2-c { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_c"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + vcc_3v3_m2_d: regulator-vcc-3v3-m2-d { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_m2_d"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_12v_dcin>; + }; + + /* vcc_5v0_sys powers the peripherals */ + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_12v_dcin>; + }; + + /* SY6280AAC power switch (U14 in schematics) */ + vcc_5v0_host_20: regulator-vcc-5v0-host-20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host20_en>; + regulator-name = "vcc_5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U8 in schematics) */ + vcc_5v0_host_30_p1: regulator-vcc-5v0-host-30-p1 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host30p1_en>; + regulator-name = "vcc_5v0_host_30_p1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U9 in schematics) */ + vcc_5v0_host_30_p2: regulator-vcc-5v0-host-30-p2 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_host30p2_en>; + regulator-name = "vcc_5v0_host_30_p2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* SY6280AAC power switch (U10 in schematics) */ + vbus_5v0_typec: regulator-vbus-5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec_5v_pwr_en>; + regulator-name = "vbus_5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_sys>; + }; +}; + +/* vcc_4v0_sys powers the RK806 and RK860's */ +&vcc_4v0_sys { + vin-supply = <&vcc_12v_dcin>; +}; + +/* Combo PHY 1 is configured to act as as PCIe 2.0 PHY */ +/* Used by PCIe controller 2 (pcie2x1l0) */ +&combphy1_ps { + status = "okay"; +}; + +/* Combo PHY 2 is configured to act as USB3 PHY */ +/* Used by USB 3.0 OTG 2 controller (USB 3.0 Type-A port 2) */ +/* CM3588 USB Controller Config Table: USB30 HOST2 */ +&combphy2_psu { + status = "okay"; +}; + +/* GPIO names are in the format "Human-readable-name [SIGNAL_LABEL]" */ +/* Signal labels match the official CM3588 NAS SDK schematic revision 2309 */ +&gpio0 { + gpio-line-names = + /* GPIO0 A0-A7 */ + "", "", "", "", + "MicroSD detect [SDMMC_DET_L]", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "Pin 10 [UART0_RX_M0]", "Pin 08 [UART0_TX_M0/PWM4_M0]", "Pin 32 [PWM5_M1]", "", + /* GPIO0 D0-D7 */ + "", "", "", "USB3 Type-C [CC_INT_L]", + "IR receiver [PWM3_IR_M0]", "User Button", "", ""; +}; + +&gpio1 { + gpio-line-names = + /* GPIO1 A0-A7 */ + "Pin 27 [UART6_RX_M1]", "Pin 28 [UART6_TX_M1]", "", "", + "USB2 Type-A [USB2_PWREN]", "", "", "Pin 15", + /* GPIO1 B0-B7 */ + "Pin 26", "Pin 21 [SPI0_MISO_M2]", "Pin 19 [SPI0_MOSI_M2/UART4_RX_M2]", "Pin 23 [SPI0_CLK_M2/UART4_TX_M2]", + "Pin 24 [SPI0_CS0_M2/UART7_RX_M2]", "Pin 22 [SPI0_CS1_M0/UART7_TX_M2]", "", "CSI-Pin 14 [MIPI_CAM2_CLKOUT]", + /* GPIO1 C0-C7 */ + "", "", "", "", + "Headphone detect [HP_DET_L]", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "USB3 Type-C [TYPEC5V_PWREN_H]", "5V Fan [PWM1_M1]", + "", "HDMI-in detect [HDMIIRX_DET_L]", "Pin 05 [I2C8_SCL_M2]", "Pin 03 [I2C8_SDA_M2]"; +}; + +&gpio2 { + gpio-line-names = + /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "SPI NOR Flash [FSPI_D0_M1]", "SPI NOR Flash [FSPI_D1_M1]", + /* GPIO2 B0-B7 */ + "SPI NOR Flash [FSPI_D2_M1]", "SPI NOR Flash [FSPI_D3_M1]", "", "SPI NOR Flash [FSPI_CLK_M1]", + "SPI NOR Flash [FSPI_CSN0_M1]", "", "", "", + /* GPIO2 C0-C7 */ + "", "CSI-Pin 11 [MIPI_CAM2_RESET_L]", "CSI-Pin 12 [MIPI_CAM2_PDN_L]", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* GPIO3 A0-A7 */ + "Pin 35 [SPI4_MISO_M1/PWM10_M0]", "Pin 38 [SPI4_MOSI_M1]", "Pin 40 [SPI4_CLK_M1/UART8_TX_M1]", "Pin 36 [SPI4_CS0_M1/UART8_RX_M1]", + "Pin 37 [SPI4_CS1_M1]", "USB3-A #2 [USB3_2_PWREN]", "DSI-Pin 12 [LCD_RST]", "Buzzer [PWM8_M0]", + /* GPIO3 B0-B7 */ + "Pin 33 [PWM9_M0]", "DSI-Pin 10 [PWM2_M1/LCD_BL]", "Pin 07", "Pin 16", + "Pin 18", "Pin 29 [UART3_TX_M1/PWM12_M0]", "Pin 31 [UART3_RX_M1/PWM13_M0]", "Pin 12", + /* GPIO3 C0-C7 */ + "DSI-Pin 08 [TP_INT_L]", "DSI-Pin 14 [TP_RST_L]", "Pin 11 [PWM14_M0]", "Pin 13 [PWM15_IR_M0]", + "", "", "", "DSI-Pin 06 [I2C5_SCL_M0_TP]", + /* GPIO3 D0-D7 */ + "DSI-Pin 05 [I2C5_SDA_M0_TP]", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* GPIO4 A0-A7 */ + "", "", "M.2 M-Key Slot4 [M2_D_PERST_L]", "", + "", "", "", "", + /* GPIO4 B0-B7 */ + "USB3-A #1 [USB3_TYPEC1_PWREN]", "", "", "M.2 M-Key Slot3 [M2_C_PERST_L]", + "M.2 M-Key Slot2 [M2_B_PERST_L]", "M.2 M-Key Slot1 [M2_A_CLKREQ_L]", "M.2 M-Key Slot1 [M2_A_PERST_L]", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +/* Connected to MIPI-DSI0 */ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + status = "disabled"; +}; + +&i2c6 { + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_5v0_typec>; + + usb_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "source"; + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; + try-power-role = "source"; + vbus-supply = <&vbus_5v0_typec>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +/* Connected to MIPI-CSI1 */ +/* &i2c7 */ + +/* GPIO Connector, connected to 40-pin GPIO header */ +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; +}; + +&pcie2x1l0 { + /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_b>; + status = "okay"; +}; + +&pcie2x1l1 { + /* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_d>; + status = "okay"; +}; + +&pcie30phy { + /* + * Data lane mapping <1 3 2 4> = x1x1 x1x1 (bifurcation of both ports) + * port 0 lane 0 - always mapped to controller 0 (4L) + * port 0 lane 1 - map to controller 2 (1L0) + * port 1 lane 0 - map to controller 1 (2L) + * port 1 lane 1 - map to controller 3 (1L1) + */ + data-lanes = <1 3 2 4>; + status = "okay"; +}; + +&pcie3x4 { + /* 1. M.2 socket, CON13: pcie30phy port0 lane0, @fe150000 */ + max-link-speed = <3>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_rst>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_a>; + status = "okay"; +}; + +&pcie3x2 { + /* 3. M.2 socket, CON15: pcie30phy port1 lane0, @fe160000 */ + max-link-speed = <3>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x2_rst>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_m2_c>; + status = "okay"; +}; + +&pinctrl { + audio { + headphone_detect: headphone-detect { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x2_rst: pcie3x2-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_rst: pcie3x4-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc_5v0_host20_en: vcc-5v0-host20-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_host30p1_en: vcc-5v0-host30p1-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_5v0_host30p2_en: vcc-5v0-host30p2-en { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec_5v_pwr_en: typec-5v-pwr-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* Connected to 5V Fan */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +/* Connected to MIPI-DSI0 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m1_pins>; +}; + +/* Connected to IR Receiver */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART0 */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4m1_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +/* Connected to Buzzer */ +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm8m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm9 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI4 */ +&pwm10 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm10m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART3 */ +&pwm12 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm12m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART3 */ +&pwm13 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm13m0_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Optimized for infrared applications */ +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m0_pins>; + status = "disabled"; +}; + +/* microSD card */ +&sdmmc { + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART4, UART7 and PWM10 */ +&spi0 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_cs0 &spi0m2_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with UART8 */ +&spi4 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m1_cs0 &spi4m1_pins>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with PWM4 */ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; +}; + +/* Debug UART */ +&uart2 { + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with PWM12 and PWM13 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; + status = "okay"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI0 */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +/* GPIO Connector, connected to 40-pin GPIO header */ +/* Shared with SPI4 */ +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; + status = "disabled"; +}; + +/* USB2 PHY for USB Type-C port */ +/* CM3588 USB Controller Config Table: USB20 OTG0 */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus_5v0_typec>; + status = "okay"; +}; + +/* USB2 PHY for USB 3.0 Type-A port 1 */ +/* CM3588 USB Controller Config Table: USB20 OTG1 */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc_5v0_host_30_p1>; + status = "okay"; +}; + +/* USB2 PHY for USB 2.0 Type-A */ +/* CM3588 USB Controller Config Table: USB20 HOST0 */ +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc_5v0_host_20>; + status = "okay"; +}; + +/* USB2 PHY for USB 3.0 Type-A port 2 */ +/* CM3588 USB Controller Config Table: USB20 HOST1 */ +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc_5v0_host_30_p2>; + status = "okay"; +}; + +/* USB 2.0 Type-A */ +/* PHY: <&u2phy2_host> */ +&usb_host0_ehci { + status = "okay"; +}; + +/* USB 2.0 Type-A */ +/* PHY: <&u2phy2_host> */ +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Type-C */ +/* PHYs: <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3> */ +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + dwc3_0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHY: <&u2phy3_host> */ +&usb_host1_ehci { + status = "okay"; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHY: <&u2phy3_host> */ +&usb_host1_ohci { + status = "okay"; +}; + +/* Upper USB 3.0 Type-A (port 1) */ +/* PHYs: <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3> */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* Lower USB 3.0 Type-A (port 2) */ +/* PHYs: <&combphy2_psu PHY_TYPE_USB3> */ +&usb_host2_xhci { + status = "okay"; +}; + +/* USB3 PHY for USB Type-C port */ +/* CM3588 USB Controller Config Table: USB30 OTG0 */ +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +/* USB3 PHY for USB 3.0 Type-A port 1 */ +/* CM3588 USB Controller Config Table: USB30 OTG1 */ +&usbdp_phy1 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-toybrick-x0.dts b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi index 9090c5c99f2..e3a9598b99f 100644 --- a/arch/arm/dts/rk3588-toybrick-x0.dts +++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -1,176 +1,115 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * Copyright (c) 2024 Sebastian Kropatsch * */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3588.dtsi" / { - model = "Rockchip Toybrick TB-RK3588X Board"; - compatible = "rockchip,rk3588-toybrick-x0", "rockchip,rk3588"; + model = "FriendlyElec CM3588"; + compatible = "friendlyarm,cm3588", "rockchip,rk3588"; aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; }; chosen { stdout-path = "serial2:1500000n8"; }; - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 1>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - poll-interval = <100>; - - button-vol-up { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - press-threshold-microvolt = <17000>; - }; - - button-vol-down { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - press-threshold-microvolt = <417000>; - }; + leds { + compatible = "gpio-leds"; - button-menu { - label = "Menu"; - linux,code = <KEY_MENU>; - press-threshold-microvolt = <890000>; + led_sys: led-0 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_sys_pin>; }; - button-escape { - label = "Escape"; - linux,code = <KEY_ESC>; - press-threshold-microvolt = <1235000>; + led_usr: led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_usr_pin>; }; }; - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc12v_dcin>; - pwms = <&pwm2 0 25000 0>; - }; - - pcie20_avdd0v85: pcie20-avdd0v85-regulator { + /* vcc_4v0_sys powers the RK806 and RK860's */ + vcc_4v0_sys: regulator-vcc-4v0-sys { compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd0v85"; + regulator-name = "vcc_4v0_sys"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - vin-supply = <&vdd_0v85_s0>; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; }; - pcie20_avdd1v8: pcie20-avdd1v8-regulator { + vcc_3v3_pcie20: regulator-vcc-3v3-pcie20 { compatible = "regulator-fixed"; - regulator-name = "pcie20_avdd1v8"; + regulator-name = "vcc_3v3_pcie20"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; }; - pcie30_avdd0v75: pcie30-avdd0v75-regulator { + vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 { compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v75"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <750000>; - vin-supply = <&avdd_0v75_s0>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&avcc_1v8_s0>; - }; - - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - vcc5v0_host: vcc5v0-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_host_en>; - regulator-name = "vcc5v0_host"; + pinctrl-0 = <&sd_s0_pwr>; regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; }; - vcc5v0_sys: vcc5v0-sys-regulator { + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usbdcin"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_dcin>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usbdcin>; - }; - - vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_1v1_nldo_s3"; + regulator-name = "vcc-1v1-nldo-s3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_4v0_sys>; }; }; +/* Combo PHY 0 is configured to act as as PCIe 2.0 PHY */ +/* Used by PCIe controller 4 (pcie2x1l2) */ &combphy0_ps { status = "okay"; }; -&combphy2_psu { - status = "okay"; +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; }; &cpu_b0 { @@ -189,34 +128,9 @@ cpu-supply = <&vdd_cpu_big1_s0>; }; -&cpu_l0 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l1 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l2 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&cpu_l3 { - cpu-supply = <&vdd_cpu_lit_s0>; -}; - -&gmac0 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - pinctrl-names = "default"; - rx_delay = <0x00>; - tx_delay = <0x43>; +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; status = "okay"; }; @@ -235,7 +149,7 @@ regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_4v0_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -252,7 +166,7 @@ regulator-min-microvolt = <550000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; + vin-supply = <&vcc_4v0_sys>; regulator-state-mem { regulator-off-in-suspend; @@ -263,72 +177,146 @@ &i2c2 { status = "okay"; + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; clock-output-names = "hym8563"; interrupt-parent = <&gpio0>; - interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&hym8563_int>; wakeup-source; }; }; -&mdio0 { - rgmii_phy: ethernet-phy@1 { - /* RTL8211F */ - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - pinctrl-names = "default"; - pinctrl-0 = <&rtl8211f_rst>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: audio-codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + #sound-dai-cells = <0>; }; }; +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&pcie2x1l2 { + /* r8125 ethernet, @fe190000 */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; +}; + &pinctrl { - rtl8211f { - rtl8211f_rst: rtl8211f-rst { - rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + gpio-leds { + led_sys_pin: led-sys-pin { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; + led_usr_pin: led-usr-pin { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + hym8563_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; - usb { - vcc5v0_host_en: vcc5v0-host-en { - rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie { + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; -}; -&pwm2 { - status = "okay"; + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; }; &saradc { - vref-supply = <&vcc_1v8_s0>; + vref-supply = <&avcc_1v8_s0>; status = "okay"; }; +/* eMMC */ &sdhci { bus-width = <8>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; - no-sdio; no-sd; + no-sdio; non-removable; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; status = "okay"; }; +/* microSD card */ +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; +}; + &spi2 { assigned-clocks = <&cru CLK_SPI2>; assigned-clock-rates = <200000000>; @@ -337,34 +325,38 @@ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; status = "okay"; - pmic@0 { + rk806_single: pmic@0 { compatible = "rockchip,rk806"; reg = <0x0>; - gpio-controller; - #gpio-cells = <2>; + interrupt-parent = <&gpio0>; interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; system-power-controller; - vcc1-supply = <&vcc5v0_sys>; - vcc2-supply = <&vcc5v0_sys>; - vcc3-supply = <&vcc5v0_sys>; - vcc4-supply = <&vcc5v0_sys>; - vcc5-supply = <&vcc5v0_sys>; - vcc6-supply = <&vcc5v0_sys>; - vcc7-supply = <&vcc5v0_sys>; - vcc8-supply = <&vcc5v0_sys>; - vcc9-supply = <&vcc5v0_sys>; - vcc10-supply = <&vcc5v0_sys>; + vcc1-supply = <&vcc_4v0_sys>; + vcc2-supply = <&vcc_4v0_sys>; + vcc3-supply = <&vcc_4v0_sys>; + vcc4-supply = <&vcc_4v0_sys>; + vcc5-supply = <&vcc_4v0_sys>; + vcc6-supply = <&vcc_4v0_sys>; + vcc7-supply = <&vcc_4v0_sys>; + vcc8-supply = <&vcc_4v0_sys>; + vcc9-supply = <&vcc_4v0_sys>; + vcc10-supply = <&vcc_4v0_sys>; vcc11-supply = <&vcc_2v0_pldo_s3>; - vcc12-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc_4v0_sys>; vcc13-supply = <&vcc_1v1_nldo_s3>; vcc14-supply = <&vcc_1v1_nldo_s3>; - vcca-supply = <&vcc5v0_sys>; + vcca-supply = <&vcc_4v0_sys>; + + gpio-controller; + #gpio-cells = <2>; rk806_dvs1_null: dvs1-null-pins { pins = "gpio_pwrctrl1"; @@ -383,12 +375,12 @@ regulators { vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { - regulator-name = "vdd_gpu_s0"; regulator-boot-on; - regulator-enable-ramp-delay = <400>; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; regulator-state-mem { regulator-off-in-suspend; @@ -396,12 +388,12 @@ }; vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { - regulator-name = "vdd_cpu_lit_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -409,12 +401,12 @@ }; vdd_log_s0: dcdc-reg3 { - regulator-name = "vdd_log_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <675000>; regulator-max-microvolt = <750000>; regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -423,13 +415,12 @@ }; vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { - regulator-name = "vdd_vdenc_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; - regulator-init-microvolt = <750000>; regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -437,12 +428,12 @@ }; vdd_ddr_s0: dcdc-reg5 { - regulator-name = "vdd_ddr_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <675000>; regulator-max-microvolt = <900000>; regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -451,9 +442,9 @@ }; vdd2_ddr_s3: dcdc-reg6 { - regulator-name = "vdd2_ddr_s3"; regulator-always-on; regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; regulator-state-mem { regulator-on-in-suspend; @@ -461,11 +452,12 @@ }; vcc_2v0_pldo_s3: dcdc-reg7 { - regulator-name = "vdd_2v0_pldo_s3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <2000000>; regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; regulator-state-mem { regulator-on-in-suspend; @@ -474,11 +466,11 @@ }; vcc_3v3_s3: dcdc-reg8 { - regulator-name = "vcc_3v3_s3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; regulator-state-mem { regulator-on-in-suspend; @@ -487,9 +479,9 @@ }; vddq_ddr_s0: dcdc-reg9 { - regulator-name = "vddq_ddr_s0"; regulator-always-on; regulator-boot-on; + regulator-name = "vddq_ddr_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -497,11 +489,11 @@ }; vcc_1v8_s3: dcdc-reg10 { - regulator-name = "vcc_1v8_s3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; regulator-state-mem { regulator-on-in-suspend; @@ -510,11 +502,11 @@ }; avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -522,11 +514,11 @@ }; vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -535,11 +527,11 @@ }; avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -547,11 +539,12 @@ }; vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -559,11 +552,12 @@ }; vccio_sd_s0: pldo-reg5 { - regulator-name = "vccio_sd_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -571,11 +565,11 @@ }; pldo6_s3: pldo-reg6 { - regulator-name = "pldo6_s3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; regulator-state-mem { regulator-on-in-suspend; @@ -584,11 +578,11 @@ }; vdd_0v75_s3: nldo-reg1 { - regulator-name = "vdd_0v75_s3"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <750000>; regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; regulator-state-mem { regulator-on-in-suspend; @@ -597,11 +591,11 @@ }; vdd_ddr_pll_s0: nldo-reg2 { - regulator-name = "vdd_ddr_pll_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <850000>; regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -610,11 +604,11 @@ }; avdd_0v75_s0: nldo-reg3 { - regulator-name = "avdd_0v75_s0"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <837500>; - regulator-max-microvolt = <837500>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -622,11 +616,11 @@ }; vdd_0v85_s0: nldo-reg4 { - regulator-name = "vdd_0v85_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <850000>; regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -634,11 +628,11 @@ }; vdd_0v75_s0: nldo-reg5 { - regulator-name = "vdd_0v75_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <750000>; regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; regulator-state-mem { regulator-off-in-suspend; @@ -648,41 +642,12 @@ }; }; -&u2phy2 { - status = "okay"; -}; - -&u2phy2_host { - phy-supply = <&vcc5v0_host>; - status = "okay"; -}; - -&u2phy3 { - status = "okay"; -}; - -&u2phy3_host { - phy-supply = <&vcc5v0_host>; +&tsadc { status = "okay"; }; +/* Debug UART */ &uart2 { + pinctrl-names = "default"; pinctrl-0 = <&uart2m0_xfer>; - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; }; diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts new file mode 100644 index 00000000000..d0b922b8d67 --- /dev/null +++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts @@ -0,0 +1,1177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Limited + * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/pwm/pwm.h> +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" + +/ { + model = "Radxa ROCK 5 ITX"; + compatible = "radxa,rock-5-itx", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Mask Rom"; + linux,code = <KEY_SETUP>; + press-threshold-microvolt = <1750>; + }; + }; + + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + dais = <&i2s0_8ch_p0>; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + power-led1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + hdd-led2 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 64 128 192 255>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm14 0 10000 0>; + }; + + /* M.2 E-KEY */ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + typec_vin: regulator-typec-vin { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + regulator-name = "typec_vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc33_io64: regulator-vcc33-io64 { + compatible = "regulator-fixed"; + regulator-name = "vcc33_io64"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_ekey: regulator-vcc3v3-ekey { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ekey_en>; + regulator-name = "vcc3v3_ekey"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lan: vcc3v3_lan_phy2: regulator-vcc3v3-lan { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_mkey: regulator-vcc3v3-mkey { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_pwren_h>; + regulator-name = "vcc3v3_mkey"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb20: vcc5v0_usb12: vcc5v0_usb34: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +/* CAM0 connector */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +/* M.2 E-key */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; +}; + +/* RTC and LCD0 connector */ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "wifi_32kout"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; +}; + +/* Audio codec and CAM1 connector */ +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +/* FUSB302 and LCD1 connector */ +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m4_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&typec_vin>; + + usb_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "source"; + source-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2c8m4_xfer { + rockchip,pins = + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_up_drv_level_6>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_up_drv_level_6>; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + hysteresis = <2000>; + temperature = <50000>; + type = "active"; + }; + + package_fan1: package-fan1 { + hysteresis = <2000>; + temperature = <65000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + cooling-device = <&fan0 THERMAL_NO_LIMIT 1>; + trip = <&package_fan0>; + }; + map1 { + cooling-device = <&fan0 2 THERMAL_NO_LIMIT>; + trip = <&package_fan1>; + }; + }; +}; + +/* M.2 E-key */ +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_0_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_ekey>; + status = "okay"; +}; + +/* RTL8125B_1 */ +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1_1_perstn>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_lan>; + status = "okay"; +}; + +/* RTL8125B_2 */ +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_2_perstn>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_lan_phy2>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 1 2 2>; + /* separate clock lines from the clock generator to phy and devices */ + rockchip,rx-common-refclk-mode = <0 0 0 0>; + status = "okay"; +}; + +/* ASMedia ASM1164 Sata controller */ +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc33_io64>; + status = "okay"; +}; + +/* M.2 M.key */ +&pcie3x4 { + num-lanes = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_perstn_m1_l>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_mkey>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_pins: led-pins { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20x1_2_perstn: pcie20x1-2-perstn { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_0_perstn_m1_l: pcie30x1-0-perstn-m1-l { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x1_1_perstn: pcie30x1-1-perstn { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ekey_en: ekey-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pcie30x4_pwren_h: pcie30x4-pwren-h { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + gl3523_reset: rl3523-reset { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmirx { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm14 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm14m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +/* M.2 E-KEY */ +&sdio { + broken-cd; + bus-width = <4>; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_ekey>; + status = "okay"; +}; + +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + status = "okay"; + + spi_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <837500>; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* Connected to M.2 E-key */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + /* connected to USB3 hub, which is powered by vcc5v0_usb12 */ + phy-supply = <&vcc5v0_usb12>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB2 hub, which is powered by vcc5v0_usb20 */ + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb20>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_xhci { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + peer-hub = <&hub_3_0>; + vdd-supply = <&vcc_3v3_s3>; + }; + + /* 3.0 hub on port 4 */ + hub_3_0: hub@2 { + compatible = "usb5e3,620"; + reg = <2>; + peer-hub = <&hub_2_0>; + pinctrl-names = "default"; + pinctrl-0 = <&gl3523_reset>; + reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc_3v3_s3>; + }; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi index 5984016b5f9..0bbeee399a6 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi @@ -1,413 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * */ -#include "rk3588s.dtsi" -#include "rk3588-pinctrl.dtsi" - -/ { - usb_host1_xhci: usb@fc400000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc400000 0x0 0x400000>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, - <&cru ACLK_USB3OTG1>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG1>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - pcie30_phy_grf: syscon@fd5b8000 { - compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; - reg = <0x0 0xfd5b8000 0x0 0x10000>; - }; - - pipe_phy1_grf: syscon@fd5c0000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c0000 0x0 0x100>; - }; - - usbdpphy1_grf: syscon@fd5cc000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5cc000 0x0 0x4000>; - }; - - usb2phy1_grf: syscon@fd5d4000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d4000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy1: usb2phy@4000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x4000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - i2s8_8ch: i2s@fddc8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc8000 0x0 0x1000>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 22>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S8_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s6_8ch: i2s@fddf4000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf4000 0x0 0x1000>; - interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 4>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S6_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s7_8ch: i2s@fddf8000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf8000 0x0 0x1000>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 21>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S7_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s10_8ch: i2s@fde00000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfde00000 0x0 0x1000>; - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 24>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S10_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - pcie3x4: pcie@fe150000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0x0f>; - clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, - <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, - <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, - <0 0 0 2 &pcie3x4_intc 1>, - <0 0 0 3 &pcie3x4_intc 2>, - <0 0 0 4 &pcie3x4_intc 3>; - linux,pci-domain = <0>; - max-link-speed = <3>; - msi-map = <0x0000 &its1 0x0000 0x1000>; - num-lanes = <4>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, - <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; - reg = <0xa 0x40000000 0x0 0x00400000>, - <0x0 0xfe150000 0x0 0x00010000>, - <0x0 0xf0000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x4_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - pcie3x2: pcie@fe160000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x10 0x1f>; - clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, - <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, - <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, - <0 0 0 2 &pcie3x2_intc 1>, - <0 0 0 3 &pcie3x2_intc 2>, - <0 0 0 4 &pcie3x2_intc 3>; - linux,pci-domain = <1>; - max-link-speed = <3>; - msi-map = <0x1000 &its1 0x1000 0x1000>; - num-lanes = <2>; - phys = <&pcie30phy>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, - <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; - reg = <0xa 0x40400000 0x0 0x00400000>, - <0x0 0xfe160000 0x0 0x00010000>, - <0x0 0xf1000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; - reset-names = "pwr", "pipe"; - status = "disabled"; - - pcie3x2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - pcie2x1l0: pcie@fe170000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x20 0x2f>; - clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, - <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, - <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, - <0 0 0 2 &pcie2x1l0_intc 1>, - <0 0 0 3 &pcie2x1l0_intc 2>, - <0 0 0 4 &pcie2x1l0_intc 3>; - linux,pci-domain = <2>; - max-link-speed = <2>; - msi-map = <0x2000 &its0 0x2000 0x1000>; - num-lanes = <1>; - phys = <&combphy1_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, - <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; - reg = <0xa 0x40800000 0x0 0x00400000>, - <0x0 0xfe170000 0x0 0x00010000>, - <0x0 0xf2000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l0_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - gmac0: ethernet@fe1b0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1b0000 0x0 0x10000>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, - <&cru CLK_GMAC0_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC0>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac0_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac0_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac0_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac0_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata1: sata@fe220000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe220000 0 0x1000>; - interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, - <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, - <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = <HBA_PORT_FBSCP>; - phys = <&combphy1_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - usbdp_phy1: phy@fed90000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed90000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY1_IMMORTAL>, - <&cru PCLK_USBDPPHY1>, - <&u2phy1>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, - <&cru SRST_USBDP_COMBO_PHY1_CMN>, - <&cru SRST_USBDP_COMBO_PHY1_LANE>, - <&cru SRST_USBDP_COMBO_PHY1_PCS>, - <&cru SRST_P_USBDPPHY1>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy1_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy1_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy1_ps: phy@fee10000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee10000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy1_grf>; - status = "disabled"; - }; - - pcie30phy: phy@fee80000 { - compatible = "rockchip,rk3588-pcie3-phy"; - reg = <0x0 0xfee80000 0x0 0x20000>; - #phy-cells = <0>; - clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; - clock-names = "pclk"; - resets = <&cru SRST_PCIE30_PHY>; - reset-names = "phy"; - rockchip,pipe-grf = <&php_grf>; - rockchip,phy-grf = <&pcie30_phy_grf>; - status = "disabled"; - }; -}; +#include "rk3588-extra.dtsi" diff --git a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi index 38b9dbf38a2..0bbeee399a6 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi @@ -4,4 +4,4 @@ * */ -#include "rk3588.dtsi" +#include "rk3588-extra.dtsi" diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi index 6ac5ac8b48a..a379269147c 100644 --- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi +++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi @@ -1,2670 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * */ -#include <dt-bindings/clock/rockchip,rk3588-cru.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/power/rk3588-power.h> -#include <dt-bindings/reset/rockchip,rk3588-cru.h> -#include <dt-bindings/phy/phy.h> -#include <dt-bindings/ata/ahci.h> - -/ { - compatible = "rockchip,rk3588"; - - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - serial6 = &uart6; - serial7 = &uart7; - serial8 = &uart8; - serial9 = &uart9; - spi0 = &spi0; - spi1 = &spi1; - spi2 = &spi2; - spi3 = &spi3; - spi4 = &spi4; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_l0>; - }; - core1 { - cpu = <&cpu_l1>; - }; - core2 { - cpu = <&cpu_l2>; - }; - core3 { - cpu = <&cpu_l3>; - }; - }; - cluster1 { - core0 { - cpu = <&cpu_b0>; - }; - core1 { - cpu = <&cpu_b1>; - }; - }; - cluster2 { - core0 { - cpu = <&cpu_b2>; - }; - core1 { - cpu = <&cpu_b3>; - }; - }; - }; - - cpu_l0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l2: cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x200>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l2>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_l3: cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x300>; - enable-method = "psci"; - capacity-dmips-mhz = <530>; - clocks = <&scmi_clk SCMI_CLK_CPUL>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l3>; - dynamic-power-coefficient = <228>; - #cooling-cells = <2>; - }; - - cpu_b0: cpu@400 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x400>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b0>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b1: cpu@500 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x500>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB01>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b1>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b2: cpu@600 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x600>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <816000000>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b2>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - cpu_b3: cpu@700 { - device_type = "cpu"; - compatible = "arm,cortex-a76"; - reg = <0x700>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_CLK_CPUB23>; - cpu-idle-states = <&CPU_SLEEP>; - i-cache-size = <65536>; - i-cache-line-size = <64>; - i-cache-sets = <256>; - d-cache-size = <65536>; - d-cache-line-size = <64>; - d-cache-sets = <256>; - next-level-cache = <&l2_cache_b3>; - dynamic-power-coefficient = <416>; - #cooling-cells = <2>; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP: cpu-sleep { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <100>; - exit-latency-us = <120>; - min-residency-us = <1000>; - }; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l2: l2-cache-l2 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l3: l2-cache-l3 { - compatible = "cache"; - cache-size = <131072>; - cache-line-size = <64>; - cache-sets = <512>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b0: l2-cache-b0 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b1: l2-cache-b1 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b2: l2-cache-b2 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_b3: l2-cache-b3 { - compatible = "cache"; - cache-size = <524288>; - cache-line-size = <64>; - cache-sets = <1024>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <3145728>; - cache-line-size = <64>; - cache-sets = <4096>; - cache-level = <3>; - cache-unified; - }; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - - scmi: scmi { - compatible = "arm,scmi-smc"; - arm,smc-id = <0x82000010>; - shmem = <&scmi_shmem>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; - }; - - pmu-a76 { - compatible = "arm,cortex-a76-pmu"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - spll: clock-0 { - compatible = "fixed-clock"; - clock-frequency = <702000000>; - clock-output-names = "spll"; - #clock-cells = <0>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; - - xin24m: clock-1 { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - xin32k: clock-2 { - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "xin32k"; - #clock-cells = <0>; - }; - - pmu_sram: sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - ranges = <0 0x0 0x0010f000 0x100>; - #address-cells = <1>; - #size-cells = <1>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - - gpu: gpu@fb000000 { - compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf"; - reg = <0x0 0xfb000000 0x0 0x200000>; - #cooling-cells = <2>; - assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; - assigned-clock-rates = <200000000>; - clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - clock-names = "core", "coregroup", "stacks"; - dynamic-power-coefficient = <2982>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "job", "mmu", "gpu"; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power RK3588_PD_GPU>; - status = "disabled"; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <675000 675000 850000>; - }; - opp-700000000 { - opp-hz = /bits/ 64 <700000000>; - opp-microvolt = <700000 700000 850000>; - }; - opp-800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <750000 750000 850000>; - }; - opp-900000000 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <800000 800000 850000>; - }; - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <850000 850000 850000>; - }; - }; - }; - - usb_host0_xhci: usb@fc000000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfc000000 0x0 0x400000>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, - <&cru ACLK_USB3OTG0>; - clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "otg"; - phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - phy_type = "utmi_wide"; - power-domains = <&power RK3588_PD_USB>; - resets = <&cru SRST_A_USB3OTG0>; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - status = "disabled"; - }; - - usb_host0_ehci: usb@fc800000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc800000 0x0 0x40000>; - interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host0_ohci: usb@fc840000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc840000 0x0 0x40000>; - interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; - phys = <&u2phy2_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ehci: usb@fc880000 { - compatible = "rockchip,rk3588-ehci", "generic-ehci"; - reg = <0x0 0xfc880000 0x0 0x40000>; - interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host1_ohci: usb@fc8c0000 { - compatible = "rockchip,rk3588-ohci", "generic-ohci"; - reg = <0x0 0xfc8c0000 0x0 0x40000>; - interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; - phys = <&u2phy3_host>; - phy-names = "usb"; - power-domains = <&power RK3588_PD_USB>; - status = "disabled"; - }; - - usb_host2_xhci: usb@fcd00000 { - compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; - reg = <0x0 0xfcd00000 0x0 0x400000>; - interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, - <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, - <&cru CLK_PIPEPHY2_PIPE_U3_G>; - clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; - dr_mode = "host"; - phys = <&combphy2_psu PHY_TYPE_USB3>; - phy-names = "usb3-phy"; - phy_type = "utmi_wide"; - resets = <&cru SRST_A_USB3OTG2>; - snps,dis_enblslpm_quirk; - snps,dis-u2-freeclk-exists-quirk; - snps,dis-del-phy-power-chg-quirk; - snps,dis-tx-ipgap-linecheck-quirk; - snps,dis_rxdet_inp3_quirk; - status = "disabled"; - }; - - mmu600_pcie: iommu@fc900000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfc900000 0x0 0x200000>; - interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - mmu600_php: iommu@fcb00000 { - compatible = "arm,smmu-v3"; - reg = <0x0 0xfcb00000 0x0 0x200000>; - interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; - #iommu-cells = <1>; - status = "disabled"; - }; - - pmu1grf: syscon@fd58a000 { - compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd"; - reg = <0x0 0xfd58a000 0x0 0x10000>; - }; - - sys_grf: syscon@fd58c000 { - compatible = "rockchip,rk3588-sys-grf", "syscon"; - reg = <0x0 0xfd58c000 0x0 0x1000>; - }; - - vop_grf: syscon@fd5a4000 { - compatible = "rockchip,rk3588-vop-grf", "syscon"; - reg = <0x0 0xfd5a4000 0x0 0x2000>; - }; - - vo0_grf: syscon@fd5a6000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a6000 0x0 0x2000>; - clocks = <&cru PCLK_VO0GRF>; - }; - - vo1_grf: syscon@fd5a8000 { - compatible = "rockchip,rk3588-vo-grf", "syscon"; - reg = <0x0 0xfd5a8000 0x0 0x100>; - clocks = <&cru PCLK_VO1GRF>; - }; - - usb_grf: syscon@fd5ac000 { - compatible = "rockchip,rk3588-usb-grf", "syscon"; - reg = <0x0 0xfd5ac000 0x0 0x4000>; - }; - - php_grf: syscon@fd5b0000 { - compatible = "rockchip,rk3588-php-grf", "syscon"; - reg = <0x0 0xfd5b0000 0x0 0x1000>; - }; - - pipe_phy0_grf: syscon@fd5bc000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5bc000 0x0 0x100>; - }; - - pipe_phy2_grf: syscon@fd5c4000 { - compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; - reg = <0x0 0xfd5c4000 0x0 0x100>; - }; - - usbdpphy0_grf: syscon@fd5c8000 { - compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; - reg = <0x0 0xfd5c8000 0x0 0x4000>; - }; - - usb2phy0_grf: syscon@fd5d0000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d0000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy0: usb2phy@0 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x0 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy2_grf: syscon@fd5d8000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5d8000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy2: usb2phy@8000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0x8000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy2"; - interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy2_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - usb2phy3_grf: syscon@fd5dc000 { - compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; - reg = <0x0 0xfd5dc000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - u2phy3: usb2phy@c000 { - compatible = "rockchip,rk3588-usb2phy"; - reg = <0xc000 0x10>; - #clock-cells = <0>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy3"; - interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; - resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; - reset-names = "phy", "apb"; - status = "disabled"; - - u2phy3_host: host-port { - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - hdptxphy0_grf: syscon@fd5e0000 { - compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; - reg = <0x0 0xfd5e0000 0x0 0x100>; - }; - - ioc: syscon@fd5f0000 { - compatible = "rockchip,rk3588-ioc", "syscon"; - reg = <0x0 0xfd5f0000 0x0 0x10000>; - }; - - system_sram1: sram@fd600000 { - compatible = "mmio-sram"; - reg = <0x0 0xfd600000 0x0 0x100000>; - ranges = <0x0 0x0 0xfd600000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - cru: clock-controller@fd7c0000 { - compatible = "rockchip,rk3588-cru"; - reg = <0x0 0xfd7c0000 0x0 0x5c000>; - assigned-clocks = - <&cru PLL_PPLL>, <&cru PLL_AUPLL>, - <&cru PLL_NPLL>, <&cru PLL_GPLL>, - <&cru ACLK_CENTER_ROOT>, - <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, - <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, - <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, - <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, - <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, - <&cru CLK_GPU>; - assigned-clock-rates = - <1100000000>, <786432000>, - <850000000>, <1188000000>, - <702000000>, - <400000000>, <500000000>, - <800000000>, <100000000>, - <400000000>, <100000000>, - <200000000>, <500000000>, - <375000000>, <150000000>, - <200000000>; - rockchip,grf = <&php_grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - i2c0: i2c@fd880000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfd880000 0x0 0x1000>; - interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; - clock-names = "i2c", "pclk"; - pinctrl-0 = <&i2c0m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart0: serial@fd890000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfd890000 0x0 0x100>; - interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 6>, <&dmac0 7>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart0m1_xfer>; - pinctrl-names = "default"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - pwm0: pwm@fd8b0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0000 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm0m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm1: pwm@fd8b0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0010 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm1m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm2: pwm@fd8b0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0020 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm2m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm3: pwm@fd8b0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfd8b0030 0x0 0x10>; - clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm3m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pmu: power-management@fd8d8000 { - compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; - reg = <0x0 0xfd8d8000 0x0 0x400>; - - power: power-controller { - compatible = "rockchip,rk3588-power-controller"; - #address-cells = <1>; - #power-domain-cells = <1>; - #size-cells = <0>; - status = "okay"; - - /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { - reg = <RK3588_PD_NPU>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPUTOP { - reg = <RK3588_PD_NPUTOP>; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>, - <&cru HCLK_NPU_CM0_ROOT>; - pm_qos = <&qos_npu0_mwr>, - <&qos_npu0_mro>, - <&qos_mcu_npu>; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3588_PD_NPU1 { - reg = <RK3588_PD_NPU1>; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_NPU2 { - reg = <RK3588_PD_NPU2>; - clocks = <&cru HCLK_NPU_ROOT>, - <&cru PCLK_NPU_ROOT>, - <&cru CLK_NPU_DSU0>; - pm_qos = <&qos_npu2>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { - reg = <RK3588_PD_GPU>; - clocks = <&cru CLK_GPU>, - <&cru CLK_GPU_COREGROUP>, - <&cru CLK_GPU_STACKS>; - pm_qos = <&qos_gpu_m0>, - <&qos_gpu_m1>, - <&qos_gpu_m2>, - <&qos_gpu_m3>; - #power-domain-cells = <0>; - }; - /* These power domains are grouped by VD_VCODEC */ - power-domain@RK3588_PD_VCODEC { - reg = <RK3588_PD_VCODEC>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_RKVDEC0 { - reg = <RK3588_PD_RKVDEC0>; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>, - <&cru ACLK_RKVDEC_CCU>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = <RK3588_PD_RKVDEC1>; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC1>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VENC0 { - reg = <RK3588_PD_VENC0>; - clocks = <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>; - pm_qos = <&qos_rkvenc0_m0ro>, - <&qos_rkvenc0_m1ro>, - <&qos_rkvenc0_m2wo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VENC1 { - reg = <RK3588_PD_VENC1>; - clocks = <&cru HCLK_RKVENC1>, - <&cru HCLK_RKVENC0>, - <&cru ACLK_RKVENC0>, - <&cru ACLK_RKVENC1>; - pm_qos = <&qos_rkvenc1_m0ro>, - <&qos_rkvenc1_m1ro>, - <&qos_rkvenc1_m2wo>; - #power-domain-cells = <0>; - }; - }; - }; - /* These power domains are grouped by VD_LOGIC */ - power-domain@RK3588_PD_VDPU { - reg = <RK3588_PD_VDPU>; - clocks = <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_LOW_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_JPEG_DECODER_ROOT>, - <&cru ACLK_IEP2P0>, - <&cru HCLK_IEP2P0>, - <&cru ACLK_JPEG_ENCODER0>, - <&cru HCLK_JPEG_ENCODER0>, - <&cru ACLK_JPEG_ENCODER1>, - <&cru HCLK_JPEG_ENCODER1>, - <&cru ACLK_JPEG_ENCODER2>, - <&cru HCLK_JPEG_ENCODER2>, - <&cru ACLK_JPEG_ENCODER3>, - <&cru HCLK_JPEG_ENCODER3>, - <&cru ACLK_JPEG_DECODER>, - <&cru HCLK_JPEG_DECODER>, - <&cru ACLK_RGA2>, - <&cru HCLK_RGA2>; - pm_qos = <&qos_iep>, - <&qos_jpeg_dec>, - <&qos_jpeg_enc0>, - <&qos_jpeg_enc1>, - <&qos_jpeg_enc2>, - <&qos_jpeg_enc3>, - <&qos_rga2_mro>, - <&qos_rga2_mwo>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - - power-domain@RK3588_PD_AV1 { - reg = <RK3588_PD_AV1>; - clocks = <&cru PCLK_AV1>, - <&cru ACLK_AV1>, - <&cru HCLK_VDPU_ROOT>; - pm_qos = <&qos_av1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC0 { - reg = <RK3588_PD_RKVDEC0>; - clocks = <&cru HCLK_RKVDEC0>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>, - <&cru ACLK_RKVDEC0>; - pm_qos = <&qos_rkvdec0>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RKVDEC1 { - reg = <RK3588_PD_RKVDEC1>; - clocks = <&cru HCLK_RKVDEC1>, - <&cru HCLK_VDPU_ROOT>, - <&cru ACLK_VDPU_ROOT>; - pm_qos = <&qos_rkvdec1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_RGA30 { - reg = <RK3588_PD_RGA30>; - clocks = <&cru ACLK_RGA3_0>, - <&cru HCLK_RGA3_0>; - pm_qos = <&qos_rga3_0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VOP { - reg = <RK3588_PD_VOP>; - clocks = <&cru PCLK_VOP_ROOT>, - <&cru HCLK_VOP_ROOT>, - <&cru ACLK_VOP>; - pm_qos = <&qos_vop_m0>, - <&qos_vop_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_VO0 { - reg = <RK3588_PD_VO0>; - clocks = <&cru PCLK_VO0_ROOT>, - <&cru PCLK_VO0_S_ROOT>, - <&cru HCLK_VO0_S_ROOT>, - <&cru ACLK_VO0_ROOT>, - <&cru HCLK_HDCP0>, - <&cru ACLK_HDCP0>, - <&cru HCLK_VOP_ROOT>; - pm_qos = <&qos_hdcp0>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_VO1 { - reg = <RK3588_PD_VO1>; - clocks = <&cru PCLK_VO1_ROOT>, - <&cru PCLK_VO1_S_ROOT>, - <&cru HCLK_VO1_S_ROOT>, - <&cru HCLK_HDCP1>, - <&cru ACLK_HDCP1>, - <&cru ACLK_HDMIRX_ROOT>, - <&cru HCLK_VO1USB_TOP_ROOT>; - pm_qos = <&qos_hdcp1>, - <&qos_hdmirx>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_VI { - reg = <RK3588_PD_VI>; - clocks = <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>, - <&cru HCLK_ISP0>, - <&cru ACLK_ISP0>, - <&cru HCLK_VICAP>, - <&cru ACLK_VICAP>; - pm_qos = <&qos_isp0_mro>, - <&qos_isp0_mwo>, - <&qos_vicap_m0>, - <&qos_vicap_m1>; - #address-cells = <1>; - #size-cells = <0>; - #power-domain-cells = <0>; - - power-domain@RK3588_PD_ISP1 { - reg = <RK3588_PD_ISP1>; - clocks = <&cru HCLK_ISP1>, - <&cru ACLK_ISP1>, - <&cru HCLK_VI_ROOT>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_isp1_mwo>, - <&qos_isp1_mro>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_FEC { - reg = <RK3588_PD_FEC>; - clocks = <&cru HCLK_FISHEYE0>, - <&cru ACLK_FISHEYE0>, - <&cru HCLK_FISHEYE1>, - <&cru ACLK_FISHEYE1>, - <&cru PCLK_VI_ROOT>; - pm_qos = <&qos_fisheye0>, - <&qos_fisheye1>; - #power-domain-cells = <0>; - }; - }; - power-domain@RK3588_PD_RGA31 { - reg = <RK3588_PD_RGA31>; - clocks = <&cru HCLK_RGA3_1>, - <&cru ACLK_RGA3_1>; - pm_qos = <&qos_rga3_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_USB { - reg = <RK3588_PD_USB>; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_USB_ROOT>, - <&cru ACLK_USB>, - <&cru HCLK_USB_ROOT>, - <&cru HCLK_HOST0>, - <&cru HCLK_HOST_ARB0>, - <&cru HCLK_HOST1>, - <&cru HCLK_HOST_ARB1>; - pm_qos = <&qos_usb3_0>, - <&qos_usb3_1>, - <&qos_usb2host_0>, - <&qos_usb2host_1>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_GMAC { - reg = <RK3588_PD_GMAC>; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_PCIE { - reg = <RK3588_PD_PCIE>; - clocks = <&cru PCLK_PHP_ROOT>, - <&cru ACLK_PCIE_ROOT>, - <&cru ACLK_PHP_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDIO { - reg = <RK3588_PD_SDIO>; - clocks = <&cru HCLK_SDIO>, - <&cru HCLK_NVM_ROOT>; - pm_qos = <&qos_sdio>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_AUDIO { - reg = <RK3588_PD_AUDIO>; - clocks = <&cru HCLK_AUDIO_ROOT>, - <&cru PCLK_AUDIO_ROOT>; - #power-domain-cells = <0>; - }; - power-domain@RK3588_PD_SDMMC { - reg = <RK3588_PD_SDMMC>; - pm_qos = <&qos_sdmmc>; - #power-domain-cells = <0>; - }; - }; - }; - - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; - interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "vdpu"; - assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - assigned-clock-rates = <400000000>, <400000000>; - clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3588_PD_AV1>; - resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; - }; - - vop: vop@fdd90000 { - compatible = "rockchip,rk3588-vop"; - reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; - reg-names = "vop", "gamma-lut"; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_VOP>, - <&cru HCLK_VOP>, - <&cru DCLK_VOP0>, - <&cru DCLK_VOP1>, - <&cru DCLK_VOP2>, - <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; - clock-names = "aclk", - "hclk", - "dclk_vp0", - "dclk_vp1", - "dclk_vp2", - "dclk_vp3", - "pclk_vop"; - iommus = <&vop_mmu>; - power-domains = <&power RK3588_PD_VOP>; - rockchip,grf = <&sys_grf>; - rockchip,vop-grf = <&vop_grf>; - rockchip,vo1-grf = <&vo1_grf>; - rockchip,pmu = <&pmu>; - status = "disabled"; - - vop_out: ports { - #address-cells = <1>; - #size-cells = <0>; - - vp0: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - vp1: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - vp2: port@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - vp3: port@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - }; - - vop_mmu: iommu@fdd97e00 { - compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; - reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; - interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - power-domains = <&power RK3588_PD_VOP>; - status = "disabled"; - }; - - i2s4_8ch: i2s@fddc0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddc0000 0x0 0x1000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 0>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO0>; - resets = <&cru SRST_M_I2S4_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s5_8ch: i2s@fddf0000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddf0000 0x0 0x1000>; - interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 2>; - dma-names = "tx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S5_8CH_TX>; - reset-names = "tx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s9_8ch: i2s@fddfc000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfddfc000 0x0 0x1000>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac2 23>; - dma-names = "rx"; - power-domains = <&power RK3588_PD_VO1>; - resets = <&cru SRST_M_I2S9_8CH_RX>; - reset-names = "rx-m"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - qos_gpu_m0: qos@fdf35000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35000 0x0 0x20>; - }; - - qos_gpu_m1: qos@fdf35200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35200 0x0 0x20>; - }; - - qos_gpu_m2: qos@fdf35400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35400 0x0 0x20>; - }; - - qos_gpu_m3: qos@fdf35600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf35600 0x0 0x20>; - }; - - qos_rga3_1: qos@fdf36000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf36000 0x0 0x20>; - }; - - qos_sdio: qos@fdf39000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf39000 0x0 0x20>; - }; - - qos_sdmmc: qos@fdf3d800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3d800 0x0 0x20>; - }; - - qos_usb3_1: qos@fdf3e000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e000 0x0 0x20>; - }; - - qos_usb3_0: qos@fdf3e200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e200 0x0 0x20>; - }; - - qos_usb2host_0: qos@fdf3e400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e400 0x0 0x20>; - }; - - qos_usb2host_1: qos@fdf3e600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf3e600 0x0 0x20>; - }; - - qos_fisheye0: qos@fdf40000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40000 0x0 0x20>; - }; - - qos_fisheye1: qos@fdf40200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40200 0x0 0x20>; - }; - - qos_isp0_mro: qos@fdf40400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40400 0x0 0x20>; - }; - - qos_isp0_mwo: qos@fdf40500 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40500 0x0 0x20>; - }; - - qos_vicap_m0: qos@fdf40600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40600 0x0 0x20>; - }; - - qos_vicap_m1: qos@fdf40800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf40800 0x0 0x20>; - }; - - qos_isp1_mwo: qos@fdf41000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41000 0x0 0x20>; - }; - - qos_isp1_mro: qos@fdf41100 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf41100 0x0 0x20>; - }; - - qos_rkvenc0_m0ro: qos@fdf60000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60000 0x0 0x20>; - }; - - qos_rkvenc0_m1ro: qos@fdf60200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60200 0x0 0x20>; - }; - - qos_rkvenc0_m2wo: qos@fdf60400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf60400 0x0 0x20>; - }; - - qos_rkvenc1_m0ro: qos@fdf61000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61000 0x0 0x20>; - }; - - qos_rkvenc1_m1ro: qos@fdf61200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61200 0x0 0x20>; - }; - - qos_rkvenc1_m2wo: qos@fdf61400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf61400 0x0 0x20>; - }; - - qos_rkvdec0: qos@fdf62000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf62000 0x0 0x20>; - }; - - qos_rkvdec1: qos@fdf63000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf63000 0x0 0x20>; - }; - - qos_av1: qos@fdf64000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf64000 0x0 0x20>; - }; - - qos_iep: qos@fdf66000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66000 0x0 0x20>; - }; - - qos_jpeg_dec: qos@fdf66200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66200 0x0 0x20>; - }; - - qos_jpeg_enc0: qos@fdf66400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66400 0x0 0x20>; - }; - - qos_jpeg_enc1: qos@fdf66600 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66600 0x0 0x20>; - }; - - qos_jpeg_enc2: qos@fdf66800 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66800 0x0 0x20>; - }; - - qos_jpeg_enc3: qos@fdf66a00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66a00 0x0 0x20>; - }; - - qos_rga2_mro: qos@fdf66c00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66c00 0x0 0x20>; - }; - - qos_rga2_mwo: qos@fdf66e00 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf66e00 0x0 0x20>; - }; - - qos_rga3_0: qos@fdf67000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67000 0x0 0x20>; - }; - - qos_vdpu: qos@fdf67200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf67200 0x0 0x20>; - }; - - qos_npu1: qos@fdf70000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf70000 0x0 0x20>; - }; - - qos_npu2: qos@fdf71000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf71000 0x0 0x20>; - }; - - qos_npu0_mwr: qos@fdf72000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72000 0x0 0x20>; - }; - - qos_npu0_mro: qos@fdf72200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72200 0x0 0x20>; - }; - - qos_mcu_npu: qos@fdf72400 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf72400 0x0 0x20>; - }; - - qos_hdcp0: qos@fdf80000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf80000 0x0 0x20>; - }; - - qos_hdcp1: qos@fdf81000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81000 0x0 0x20>; - }; - - qos_hdmirx: qos@fdf81200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf81200 0x0 0x20>; - }; - - qos_vop_m0: qos@fdf82000 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82000 0x0 0x20>; - }; - - qos_vop_m1: qos@fdf82200 { - compatible = "rockchip,rk3588-qos", "syscon"; - reg = <0x0 0xfdf82200 0x0 0x20>; - }; - - dfi: dfi@fe060000 { - reg = <0x00 0xfe060000 0x00 0x10000>; - compatible = "rockchip,rk3588-dfi"; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; - rockchip,pmu = <&pmu1grf>; - }; - - pcie2x1l1: pcie@fe180000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x30 0x3f>; - clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, - <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, - <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, - <0 0 0 2 &pcie2x1l1_intc 1>, - <0 0 0 3 &pcie2x1l1_intc 2>, - <0 0 0 4 &pcie2x1l1_intc 3>; - linux,pci-domain = <3>; - max-link-speed = <2>; - msi-map = <0x3000 &its0 0x3000 0x1000>; - num-lanes = <1>; - phys = <&combphy2_psu PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, - <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; - reg = <0xa 0x40c00000 0x0 0x00400000>, - <0x0 0xfe180000 0x0 0x00010000>, - <0x0 0xf3000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l1_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - pcie2x1l2: pcie@fe190000 { - compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; - bus-range = <0x40 0x4f>; - clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, - <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, - <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; - clock-names = "aclk_mst", "aclk_slv", - "aclk_dbi", "pclk", - "aux", "pipe"; - device_type = "pci"; - interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, - <0 0 0 2 &pcie2x1l2_intc 1>, - <0 0 0 3 &pcie2x1l2_intc 2>, - <0 0 0 4 &pcie2x1l2_intc 3>; - linux,pci-domain = <4>; - max-link-speed = <2>; - msi-map = <0x4000 &its0 0x4000 0x1000>; - num-lanes = <1>; - phys = <&combphy0_ps PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3588_PD_PCIE>; - ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, - <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; - reg = <0xa 0x41000000 0x0 0x00400000>, - <0x0 0xfe190000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; - resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; - reset-names = "pwr", "pipe"; - #address-cells = <3>; - #size-cells = <2>; - status = "disabled"; - - pcie2x1l2_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; - }; - }; - - gmac1: ethernet@fe1c0000 { - compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; - reg = <0x0 0xfe1c0000 0x0 0x10000>; - interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, - <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, - <&cru CLK_GMAC1_PTP_REF>; - clock-names = "stmmaceth", "clk_mac_ref", - "pclk_mac", "aclk_mac", - "ptp_ref"; - power-domains = <&power RK3588_PD_GMAC>; - resets = <&cru SRST_A_GMAC1>; - reset-names = "stmmaceth"; - rockchip,grf = <&sys_grf>; - rockchip,php-grf = <&php_grf>; - snps,axi-config = <&gmac1_stmmac_axi_setup>; - snps,mixed-burst; - snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; - snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; - snps,tso; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - }; - - gmac1_stmmac_axi_setup: stmmac-axi-config { - snps,blen = <0 0 0 0 16 8 4>; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <8>; - }; - - gmac1_mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - - gmac1_mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <2>; - queue0 {}; - queue1 {}; - }; - }; - - sata0: sata@fe210000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe210000 0 0x1000>; - interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, - <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, - <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = <HBA_PORT_FBSCP>; - phys = <&combphy0_ps PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sata2: sata@fe230000 { - compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; - reg = <0 0xfe230000 0 0x1000>; - interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, - <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, - <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; - clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; - ports-implemented = <0x1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - sata-port@0 { - reg = <0>; - hba-port-cap = <HBA_PORT_FBSCP>; - phys = <&combphy2_psu PHY_TYPE_SATA>; - phy-names = "sata-phy"; - snps,rx-ts-max = <32>; - snps,tx-ts-max = <32>; - }; - }; - - sfc: spi@fe2b0000 { - compatible = "rockchip,sfc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; - clock-names = "clk_sfc", "hclk_sfc"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdmmc: mmc@fe2c0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2c0000 0x0 0x4000>; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; - power-domains = <&power RK3588_PD_SDMMC>; - status = "disabled"; - }; - - sdio: mmc@fe2d0000 { - compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x00 0xfe2d0000 0x00 0x4000>; - interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - max-frequency = <200000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdiom1_pins>; - power-domains = <&power RK3588_PD_SDIO>; - status = "disabled"; - }; - - sdhci: mmc@fe2e0000 { - compatible = "rockchip,rk3588-dwcmshc"; - reg = <0x0 0xfe2e0000 0x0 0x10000>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; - assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; - assigned-clock-rates = <200000000>, <24000000>, <200000000>; - clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, - <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, - <&cru TMCLK_EMMC>; - clock-names = "core", "bus", "axi", "block", "timer"; - max-frequency = <200000000>; - pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, - <&emmc_cmd>, <&emmc_data_strobe>; - pinctrl-names = "default"; - resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, - <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, - <&cru SRST_T_EMMC>; - reset-names = "core", "bus", "axi", "block", "timer"; - status = "disabled"; - }; - - i2s0_8ch: i2s@fe470000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe470000 0x0 0x1000>; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; - dmas = <&dmac0 0>, <&dmac0 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_lrck - &i2s0_sclk - &i2s0_sdi0 - &i2s0_sdi1 - &i2s0_sdi2 - &i2s0_sdi3 - &i2s0_sdo0 - &i2s0_sdo1 - &i2s0_sdo2 - &i2s0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s1_8ch: i2s@fe480000 { - compatible = "rockchip,rk3588-i2s-tdm"; - reg = <0x0 0xfe480000 0x0 0x1000>; - interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; - clock-names = "mclk_tx", "mclk_rx", "hclk"; - dmas = <&dmac0 2>, <&dmac0 3>; - dma-names = "tx", "rx"; - resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; - reset-names = "tx-m", "rx-m"; - rockchip,trcm-sync-tx-only; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_lrck - &i2s1m0_sclk - &i2s1m0_sdi0 - &i2s1m0_sdi1 - &i2s1m0_sdi2 - &i2s1m0_sdi3 - &i2s1m0_sdo0 - &i2s1m0_sdo1 - &i2s1m0_sdo2 - &i2s1m0_sdo3>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s2_2ch: i2s@fe490000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe490000 0x0 0x1000>; - interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 0>, <&dmac1 1>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s2m1_lrck - &i2s2m1_sclk - &i2s2m1_sdi - &i2s2m1_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - i2s3_2ch: i2s@fe4a0000 { - compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; - reg = <0x0 0xfe4a0000 0x0 0x1000>; - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; - clock-names = "i2s_clk", "i2s_hclk"; - assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; - assigned-clock-parents = <&cru PLL_AUPLL>; - dmas = <&dmac1 2>, <&dmac1 3>; - dma-names = "tx", "rx"; - power-domains = <&power RK3588_PD_AUDIO>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s3_lrck - &i2s3_sclk - &i2s3_sdi - &i2s3_sdo>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@fe600000 { - compatible = "arm,gic-v3"; - reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ - <0x0 0xfe680000 0 0x100000>; /* GICR */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-controller; - mbi-alias = <0x0 0xfe610000>; - mbi-ranges = <424 56>; - msi-controller; - ranges; - #address-cells = <2>; - #interrupt-cells = <4>; - #size-cells = <2>; - - its0: msi-controller@fe640000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe640000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - its1: msi-controller@fe660000 { - compatible = "arm,gic-v3-its"; - reg = <0x0 0xfe660000 0x0 0x20000>; - msi-controller; - #msi-cells = <1>; - }; - - ppi-partitions { - ppi_partition0: interrupt-partition-0 { - affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; - }; - - ppi_partition1: interrupt-partition-1 { - affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; - }; - }; - }; - - dmac0: dma-controller@fea10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea10000 0x0 0x4000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - dmac1: dma-controller@fea30000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfea30000 0x0 0x4000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - i2c1: i2c@fea90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfea90000 0x0 0x1000>; - clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c1m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@feaa0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeaa0000 0x0 0x1000>; - clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c2m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@feab0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeab0000 0x0 0x1000>; - clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c3m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@feac0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeac0000 0x0 0x1000>; - clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c4m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@fead0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfead0000 0x0 0x1000>; - clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c5m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - timer0: timer@feae0000 { - compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; - reg = <0x0 0xfeae0000 0x0 0x20>; - interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; - clock-names = "pclk", "timer"; - }; - - wdt: watchdog@feaf0000 { - compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; - reg = <0x0 0xfeaf0000 0x0 0x100>; - clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; - clock-names = "tclk", "pclk"; - interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; - }; - - spi0: spi@feb00000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb00000 0x0 0x1000>; - interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 14>, <&dmac0 15>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi1: spi@feb10000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb10000 0x0 0x1000>; - interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac0 16>, <&dmac0 17>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi2: spi@feb20000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb20000 0x0 0x1000>; - interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 15>, <&dmac1 16>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi3: spi@feb30000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfeb30000 0x0 0x1000>; - interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac1 17>, <&dmac1 18>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart1: serial@feb40000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb40000 0x0 0x100>; - interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 8>, <&dmac0 9>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart1m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@feb50000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb50000 0x0 0x100>; - interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 10>, <&dmac0 11>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart2m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart3: serial@feb60000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb60000 0x0 0x100>; - interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac0 12>, <&dmac0 13>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart3m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@feb70000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb70000 0x0 0x100>; - interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 9>, <&dmac1 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart4m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@feb80000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb80000 0x0 0x100>; - interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 11>, <&dmac1 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart5m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart6: serial@feb90000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeb90000 0x0 0x100>; - interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac1 13>, <&dmac1 14>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart6m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart7: serial@feba0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfeba0000 0x0 0x100>; - interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 7>, <&dmac2 8>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart7m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart8: serial@febb0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebb0000 0x0 0x100>; - interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 9>, <&dmac2 10>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart8m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart9: serial@febc0000 { - compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; - reg = <0x0 0xfebc0000 0x0 0x100>; - interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; - clock-names = "baudclk", "apb_pclk"; - dmas = <&dmac2 11>, <&dmac2 12>; - dma-names = "tx", "rx"; - pinctrl-0 = <&uart9m1_xfer>; - pinctrl-names = "default"; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - pwm4: pwm@febd0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0000 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm4m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm5: pwm@febd0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0010 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm5m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm6: pwm@febd0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0020 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm6m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm7: pwm@febd0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebd0030 0x0 0x10>; - clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm7m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm8: pwm@febe0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0000 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm8m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm9: pwm@febe0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0010 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm9m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm10: pwm@febe0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0020 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm10m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm11: pwm@febe0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebe0030 0x0 0x10>; - clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm11m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm12: pwm@febf0000 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0000 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm12m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm13: pwm@febf0010 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0010 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm13m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm14: pwm@febf0020 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0020 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm14m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - pwm15: pwm@febf0030 { - compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; - reg = <0x0 0xfebf0030 0x0 0x10>; - clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; - clock-names = "pwm", "pclk"; - pinctrl-0 = <&pwm15m0_pins>; - pinctrl-names = "default"; - #pwm-cells = <3>; - status = "disabled"; - }; - - tsadc: tsadc@fec00000 { - compatible = "rockchip,rk3588-tsadc"; - reg = <0x0 0xfec00000 0x0 0x400>; - interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru CLK_TSADC>; - assigned-clock-rates = <2000000>; - resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; - reset-names = "tsadc-apb", "tsadc"; - rockchip,hw-tshut-temp = <120000>; - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ - pinctrl-0 = <&tsadc_gpio_func>; - pinctrl-1 = <&tsadc_shut>; - pinctrl-names = "gpio", "otpout"; - #thermal-sensor-cells = <1>; - status = "disabled"; - }; - - saradc: adc@fec10000 { - compatible = "rockchip,rk3588-saradc"; - reg = <0x0 0xfec10000 0x0 0x10000>; - interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; - #io-channel-cells = <1>; - clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_P_SARADC>; - reset-names = "saradc-apb"; - status = "disabled"; - }; - - i2c6: i2c@fec80000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec80000 0x0 0x1000>; - clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c6m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@fec90000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfec90000 0x0 0x1000>; - clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c7m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@feca0000 { - compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0xfeca0000 0x0 0x1000>; - clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; - clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-0 = <&i2c8m0_xfer>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi4: spi@fecb0000 { - compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; - reg = <0x0 0xfecb0000 0x0 0x1000>; - interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; - clock-names = "spiclk", "apb_pclk"; - dmas = <&dmac2 13>, <&dmac2 14>; - dma-names = "tx", "rx"; - num-cs = <2>; - pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - otp: efuse@fecc0000 { - compatible = "rockchip,rk3588-otp"; - reg = <0x0 0xfecc0000 0x0 0x400>; - clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, - <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; - clock-names = "otp", "apb_pclk", "phy", "arb"; - resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, - <&cru SRST_OTPC_ARB>; - reset-names = "otp", "apb", "arb"; - #address-cells = <1>; - #size-cells = <1>; - - cpu_code: cpu-code@2 { - reg = <0x02 0x2>; - }; - - otp_id: id@7 { - reg = <0x07 0x10>; - }; - - cpub0_leakage: cpu-leakage@17 { - reg = <0x17 0x1>; - }; - - cpub1_leakage: cpu-leakage@18 { - reg = <0x18 0x1>; - }; - - cpul_leakage: cpu-leakage@19 { - reg = <0x19 0x1>; - }; - - log_leakage: log-leakage@1a { - reg = <0x1a 0x1>; - }; - - gpu_leakage: gpu-leakage@1b { - reg = <0x1b 0x1>; - }; - - otp_cpu_version: cpu-version@1c { - reg = <0x1c 0x1>; - bits = <3 3>; - }; - - npu_leakage: npu-leakage@28 { - reg = <0x28 0x1>; - }; - - codec_leakage: codec-leakage@29 { - reg = <0x29 0x1>; - }; - }; - - dmac2: dma-controller@fed10000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfed10000 0x0 0x4000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, - <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - }; - - hdptxphy_hdmi0: phy@fed60000 { - compatible = "rockchip,rk3588-hdptx-phy"; - reg = <0x0 0xfed60000 0x0 0x2000>; - clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; - clock-names = "ref", "apb"; - #phy-cells = <0>; - resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, - <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, - <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, - <&cru SRST_HDPTX0_LCPLL>; - reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", - "lcpll"; - rockchip,grf = <&hdptxphy0_grf>; - status = "disabled"; - }; - - usbdp_phy0: phy@fed80000 { - compatible = "rockchip,rk3588-usbdp-phy"; - reg = <0x0 0xfed80000 0x0 0x10000>; - #phy-cells = <1>; - clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, - <&cru CLK_USBDP_PHY0_IMMORTAL>, - <&cru PCLK_USBDPPHY0>, - <&u2phy0>; - clock-names = "refclk", "immortal", "pclk", "utmi"; - resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, - <&cru SRST_USBDP_COMBO_PHY0_CMN>, - <&cru SRST_USBDP_COMBO_PHY0_LANE>, - <&cru SRST_USBDP_COMBO_PHY0_PCS>, - <&cru SRST_P_USBDPPHY0>; - reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; - rockchip,u2phy-grf = <&usb2phy0_grf>; - rockchip,usb-grf = <&usb_grf>; - rockchip,usbdpphy-grf = <&usbdpphy0_grf>; - rockchip,vo-grf = <&vo0_grf>; - status = "disabled"; - }; - - combphy0_ps: phy@fee00000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee00000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy0_grf>; - status = "disabled"; - }; - - combphy2_psu: phy@fee20000 { - compatible = "rockchip,rk3588-naneng-combphy"; - reg = <0x0 0xfee20000 0x0 0x100>; - clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, - <&cru PCLK_PHP_ROOT>; - clock-names = "ref", "apb", "pipe"; - assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; - assigned-clock-rates = <100000000>; - #phy-cells = <1>; - resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; - reset-names = "phy", "apb"; - rockchip,pipe-grf = <&php_grf>; - rockchip,pipe-phy-grf = <&pipe_phy2_grf>; - status = "disabled"; - }; - - system_sram2: sram@ff001000 { - compatible = "mmio-sram"; - reg = <0x0 0xff001000 0x0 0xef000>; - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3588-pinctrl"; - ranges; - rockchip,grf = <&ioc>; - #address-cells = <2>; - #size-cells = <2>; - - gpio0: gpio@fd8a0000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfd8a0000 0x0 0x100>; - interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; - gpio-controller; - gpio-ranges = <&pinctrl 0 0 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio1: gpio@fec20000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec20000 0x0 0x100>; - interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; - gpio-controller; - gpio-ranges = <&pinctrl 0 32 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio2: gpio@fec30000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec30000 0x0 0x100>; - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; - gpio-controller; - gpio-ranges = <&pinctrl 0 64 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio3: gpio@fec40000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec40000 0x0 0x100>; - interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; - gpio-controller; - gpio-ranges = <&pinctrl 0 96 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - - gpio4: gpio@fec50000 { - compatible = "rockchip,gpio-bank"; - reg = <0x0 0xfec50000 0x0 0x100>; - interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; - gpio-controller; - gpio-ranges = <&pinctrl 0 128 32>; - interrupt-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - }; - }; -}; - -#include "rk3588s-pinctrl.dtsi" +#include "rk3588-base.dtsi" diff --git a/env/common.c b/env/common.c index 8d47d726059..6cba7f1c187 100644 --- a/env/common.c +++ b/env/common.c @@ -401,7 +401,15 @@ int env_set_default_vars(int nvars, char * const vars[], int flags) * Special use-case: import from default environment * (and use \0 as a separator) */ - flags |= H_NOCLEAR | H_DEFAULT; + + /* + * When vars are passed remove variables that are not in + * the default environment. + */ + if (!nvars) + flags |= H_NOCLEAR; + + flags |= H_DEFAULT; return himport_r(&env_htab, default_environment, sizeof(default_environment), '\0', flags, 0, nvars, vars); @@ -38,14 +38,24 @@ static ulong env_new_offset = CONFIG_ENV_OFFSET_REDUND; DECLARE_GLOBAL_DATA_PTR; +__weak int spi_get_env_dev(void) +{ +#ifdef CONFIG_ENV_SPI_BUS + return CONFIG_ENV_SPI_BUS; +#else + return 0; +#endif +} + static int setup_flash_device(struct spi_flash **env_flash) { #if CONFIG_IS_ENABLED(DM_SPI_FLASH) struct udevice *new; int ret; + int dev = spi_get_env_dev(); /* speed and mode will be read from DT */ - ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, + ret = spi_flash_probe_bus_cs(dev, CONFIG_ENV_SPI_CS, &new); if (ret) { env_set_default("spi_flash_probe_bus_cs() failed", 0); diff --git a/env/ubi.c b/env/ubi.c index 0c3e93c2bf2..2f4ca571edb 100644 --- a/env/ubi.c +++ b/env/ubi.c @@ -53,7 +53,7 @@ static int env_ubi_save(void) if (gd->env_valid == ENV_VALID) { puts("Writing to redundant UBI... "); if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME_REDUND, - (void *)env_new, CONFIG_ENV_SIZE)) { + (void *)env_new, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to write env to %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME_REDUND); @@ -62,7 +62,7 @@ static int env_ubi_save(void) } else { puts("Writing to UBI... "); if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME, - (void *)env_new, CONFIG_ENV_SIZE)) { + (void *)env_new, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to write env to %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); @@ -92,7 +92,7 @@ static int env_ubi_save(void) return 1; } - if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME, (void *)env_new, + if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME, (void *)env_new, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to write env to %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); @@ -134,14 +134,14 @@ static int env_ubi_load(void) return -EIO; } - read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, + read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, 0, CONFIG_ENV_SIZE); if (read1_fail) printf("\n** Unable to read env from %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); read2_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME_REDUND, - (void *)tmp_env2, CONFIG_ENV_SIZE); + (void *)tmp_env2, 0, CONFIG_ENV_SIZE); if (read2_fail) printf("\n** Unable to read redundant env from %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME_REDUND); @@ -171,7 +171,7 @@ static int env_ubi_load(void) return -EIO; } - if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, CONFIG_ENV_SIZE)) { + if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to read env from %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); env_set_default(NULL, 0); @@ -196,7 +196,7 @@ static int env_ubi_erase(void) memset(env_buf, 0x0, CONFIG_ENV_SIZE); if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME, - (void *)env_buf, CONFIG_ENV_SIZE)) { + (void *)env_buf, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to erase env to %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); @@ -204,7 +204,7 @@ static int env_ubi_erase(void) } if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) { if (ubi_volume_write(ENV_UBI_VOLUME_REDUND, - (void *)env_buf, CONFIG_ENV_SIZE)) { + (void *)env_buf, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to erase env to %s:%s **\n", CONFIG_ENV_UBI_PART, ENV_UBI_VOLUME_REDUND); diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 52152a2295a..76f7102456e 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -2181,13 +2181,18 @@ static char *ext4fs_read_symlink(struct ext2fs_node *node) struct ext2fs_node *diro = node; int status; loff_t actread; + size_t alloc_size; if (!diro->inode_read) { status = ext4fs_read_inode(diro->data, diro->ino, &diro->inode); if (status == 0) return NULL; } - symlink = zalloc(le32_to_cpu(diro->inode.size) + 1); + + if (__builtin_add_overflow(le32_to_cpu(diro->inode.size), 1, &alloc_size)) + return NULL; + + symlink = zalloc(alloc_size); if (!symlink) return NULL; @@ -2383,6 +2388,20 @@ int ext4fs_mount(void) fs->inodesz = 128; fs->gdsize = 32; } else { + int missing = __le32_to_cpu(data->sblock.feature_incompat) & + ~(EXT4_FEATURE_INCOMPAT_SUPP | + EXT4_FEATURE_INCOMPAT_SUPP_LAZY_RO); + + if (missing) { + /* + * This code used to be relaxed about feature flags. + * We don't stop the mount to avoid breaking existing setups. + * But, incompatible features can cause serious read errors. + */ + log_err("fs uses incompatible features: %08x, ignoring\n", + missing); + } + debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n", __le32_to_cpu(data->sblock.feature_compatibility), __le32_to_cpu(data->sblock.feature_incompat), diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h index 84500e990aa..346752092b0 100644 --- a/fs/ext4/ext4_common.h +++ b/fs/ext4/ext4_common.h @@ -24,6 +24,7 @@ #include <ext4fs.h> #include <malloc.h> #include <asm/cache.h> +#include <linux/compat.h> #include <linux/errno.h> #if defined(CONFIG_EXT4_WRITE) #include "ext4_journal.h" @@ -43,9 +44,7 @@ static inline void *zalloc(size_t size) { - void *p = memalign(ARCH_DMA_MINALIGN, size); - memset(p, 0, size); - return p; + return kzalloc(size, 0); } int ext4fs_read_inode(struct ext2_data *data, int ino, diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index a2dfff81979..d109ed6e90d 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -866,6 +866,7 @@ int ext4fs_write(const char *fname, const char *buffer, ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256); bool store_link_in_inode = false; memset(filename, 0x00, 256); + int missing_feat; if (type != FILETYPE_REG && type != FILETYPE_SYMLINK) return -1; @@ -879,8 +880,15 @@ int ext4fs_write(const char *fname, const char *buffer, return -1; } - if (le32_to_cpu(fs->sb->feature_ro_compat) & EXT4_FEATURE_RO_COMPAT_METADATA_CSUM) { - printf("Unsupported feature metadata_csum found, not writing.\n"); + missing_feat = le32_to_cpu(fs->sb->feature_incompat) & ~EXT4_FEATURE_INCOMPAT_SUPP; + if (missing_feat) { + log_err("Unsupported features found %08x, not writing.\n", missing_feat); + return -1; + } + + missing_feat = le32_to_cpu(fs->sb->feature_ro_compat) & ~EXT4_FEATURE_RO_COMPAT_SUPP; + if (missing_feat) { + log_err("Unsupported RO compat features found %08x, not writing.\n", missing_feat); return -1; } diff --git a/fs/sandbox/sandboxfs.c b/fs/sandbox/sandboxfs.c index 773b583fa43..76f1a71f412 100644 --- a/fs/sandbox/sandboxfs.c +++ b/fs/sandbox/sandboxfs.c @@ -28,7 +28,7 @@ int sandbox_fs_read_at(const char *filename, loff_t pos, void *buffer, if (fd < 0) return fd; ret = os_lseek(fd, pos, OS_SEEK_SET); - if (ret == -1) { + if (ret < 0) { os_close(fd); return ret; } @@ -65,14 +65,14 @@ int sandbox_fs_write_at(const char *filename, loff_t pos, void *buffer, if (fd < 0) return fd; ret = os_lseek(fd, pos, OS_SEEK_SET); - if (ret == -1) { + if (ret < 0) { os_close(fd); return ret; } size = os_write(fd, buffer, towrite); os_close(fd); - if (size == -1) { + if (size < 0) { ret = -1; } else { ret = 0; diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 1430e671a5a..b9314019b1b 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -24,7 +24,12 @@ #include "sqfs_filesystem.h" #include "sqfs_utils.h" +#define MAX_SYMLINK_NEST 8 + static struct squashfs_ctxt ctxt; +static int symlinknest; + +static int sqfs_readdir_nest(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp); static int sqfs_disk_read(__u32 block, __u32 nr_blocks, void *buf) { @@ -422,8 +427,10 @@ static char *sqfs_resolve_symlink(struct squashfs_symlink_inode *sym, char *resolved, *target; u32 sz; - sz = get_unaligned_le32(&sym->symlink_size); - target = malloc(sz + 1); + if (__builtin_add_overflow(get_unaligned_le32(&sym->symlink_size), 1, &sz)) + return NULL; + + target = malloc(sz); if (!target) return NULL; @@ -431,9 +438,9 @@ static char *sqfs_resolve_symlink(struct squashfs_symlink_inode *sym, * There is no trailling null byte in the symlink's target path, so a * copy is made and a '\0' is added at its end. */ - target[sz] = '\0'; + target[sz - 1] = '\0'; /* Get target name (relative path) */ - strncpy(target, sym->symlink, sz); + strncpy(target, sym->symlink, sz - 1); /* Relative -> absolute path conversion */ resolved = sqfs_get_abs_path(base_path, target); @@ -472,6 +479,8 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, /* Start by root inode */ table = sqfs_find_inode(dirs->inode_table, le32_to_cpu(sblk->inodes), sblk->inodes, sblk->block_size); + if (!table) + return -EINVAL; dir = (struct squashfs_dir_inode *)table; ldir = (struct squashfs_ldir_inode *)table; @@ -506,7 +515,7 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, goto out; } - while (!sqfs_readdir(dirsp, &dent)) { + while (!sqfs_readdir_nest(dirsp, &dent)) { ret = strcmp(dent->name, token_list[j]); if (!ret) break; @@ -527,10 +536,17 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, /* Get reference to inode in the inode table */ table = sqfs_find_inode(dirs->inode_table, new_inode_number, sblk->inodes, sblk->block_size); + if (!table) + return -EINVAL; dir = (struct squashfs_dir_inode *)table; /* Check for symbolic link and inode type sanity */ if (get_unaligned_le16(&dir->inode_type) == SQFS_SYMLINK_TYPE) { + if (++symlinknest == MAX_SYMLINK_NEST) { + ret = -ELOOP; + goto out; + } + sym = (struct squashfs_symlink_inode *)table; /* Get first j + 1 tokens */ path = sqfs_concat_tokens(token_list, j + 1); @@ -551,8 +567,11 @@ static int sqfs_search_dir(struct squashfs_dir_stream *dirs, char **token_list, ret = -ENOMEM; goto out; } - /* Concatenate remaining tokens and symlink's target */ - res = malloc(strlen(rem) + strlen(target) + 1); + /* + * Concatenate remaining tokens and symlink's target. + * Allocate enough space for rem, target, '/' and '\0'. + */ + res = malloc(strlen(rem) + strlen(target) + 2); if (!res) { ret = -ENOMEM; goto out; @@ -878,7 +897,7 @@ out: return metablks_count; } -int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp) +static int sqfs_opendir_nest(const char *filename, struct fs_dir_stream **dirsp) { unsigned char *inode_table = NULL, *dir_table = NULL; int j, token_count = 0, ret = 0, metablks_count; @@ -973,8 +992,20 @@ out: return ret; } +int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp) +{ + symlinknest = 0; + return sqfs_opendir_nest(filename, dirsp); +} + int sqfs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) { + symlinknest = 0; + return sqfs_readdir_nest(fs_dirs, dentp); +} + +static int sqfs_readdir_nest(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) +{ struct squashfs_super_block *sblk = ctxt.sblk; struct squashfs_dir_stream *dirs; struct squashfs_lreg_inode *lreg; @@ -1023,6 +1054,8 @@ int sqfs_readdir(struct fs_dir_stream *fs_dirs, struct fs_dirent **dentp) i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset; ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes, sblk->block_size); + if (!ipos) + return -SQFS_STOP_READDIR; base = (struct squashfs_base_inode *)ipos; @@ -1317,8 +1350,8 @@ static int sqfs_get_lregfile_info(struct squashfs_lreg_inode *lreg, return datablk_count; } -int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, - loff_t *actread) +static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, + loff_t len, loff_t *actread) { char *dir = NULL, *fragment_block, *datablock = NULL; char *fragment = NULL, *file = NULL, *resolved, *data; @@ -1348,11 +1381,11 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, } /* - * sqfs_opendir will uncompress inode and directory tables, and will + * sqfs_opendir_nest will uncompress inode and directory tables, and will * return a pointer to the directory that contains the requested file. */ sqfs_split_path(&file, &dir, filename); - ret = sqfs_opendir(dir, &dirsp); + ret = sqfs_opendir_nest(dir, &dirsp); if (ret) { goto out; } @@ -1360,7 +1393,7 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, dirs = (struct squashfs_dir_stream *)dirsp; /* For now, only regular files are able to be loaded */ - while (!sqfs_readdir(dirsp, &dent)) { + while (!sqfs_readdir_nest(dirsp, &dent)) { ret = strcmp(dent->name, file); if (!ret) break; @@ -1379,6 +1412,10 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset; ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes, sblk->block_size); + if (!ipos) { + ret = -EINVAL; + goto out; + } base = (struct squashfs_base_inode *)ipos; switch (get_unaligned_le16(&base->inode_type)) { @@ -1409,9 +1446,14 @@ int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, break; case SQFS_SYMLINK_TYPE: case SQFS_LSYMLINK_TYPE: + if (++symlinknest == MAX_SYMLINK_NEST) { + ret = -ELOOP; + goto out; + } + symlink = (struct squashfs_symlink_inode *)ipos; resolved = sqfs_resolve_symlink(symlink, filename); - ret = sqfs_read(resolved, buf, offset, len, actread); + ret = sqfs_read_nest(resolved, buf, offset, len, actread); free(resolved); goto out; case SQFS_BLKDEV_TYPE: @@ -1582,7 +1624,14 @@ out: return ret; } -int sqfs_size(const char *filename, loff_t *size) +int sqfs_read(const char *filename, void *buf, loff_t offset, loff_t len, + loff_t *actread) +{ + symlinknest = 0; + return sqfs_read_nest(filename, buf, offset, len, actread); +} + +static int sqfs_size_nest(const char *filename, loff_t *size) { struct squashfs_super_block *sblk = ctxt.sblk; struct squashfs_symlink_inode *symlink; @@ -1598,10 +1647,10 @@ int sqfs_size(const char *filename, loff_t *size) sqfs_split_path(&file, &dir, filename); /* - * sqfs_opendir will uncompress inode and directory tables, and will + * sqfs_opendir_nest will uncompress inode and directory tables, and will * return a pointer to the directory that contains the requested file. */ - ret = sqfs_opendir(dir, &dirsp); + ret = sqfs_opendir_nest(dir, &dirsp); if (ret) { ret = -EINVAL; goto free_strings; @@ -1609,7 +1658,7 @@ int sqfs_size(const char *filename, loff_t *size) dirs = (struct squashfs_dir_stream *)dirsp; - while (!sqfs_readdir(dirsp, &dent)) { + while (!sqfs_readdir_nest(dirsp, &dent)) { ret = strcmp(dent->name, file); if (!ret) break; @@ -1627,6 +1676,13 @@ int sqfs_size(const char *filename, loff_t *size) i_number = dirs->dir_header->inode_number + dirs->entry->inode_offset; ipos = sqfs_find_inode(dirs->inode_table, i_number, sblk->inodes, sblk->block_size); + + if (!ipos) { + *size = 0; + ret = -EINVAL; + goto free_strings; + } + free(dirs->entry); dirs->entry = NULL; @@ -1642,6 +1698,11 @@ int sqfs_size(const char *filename, loff_t *size) break; case SQFS_SYMLINK_TYPE: case SQFS_LSYMLINK_TYPE: + if (++symlinknest == MAX_SYMLINK_NEST) { + *size = 0; + return -ELOOP; + } + symlink = (struct squashfs_symlink_inode *)ipos; resolved = sqfs_resolve_symlink(symlink, filename); ret = sqfs_size(resolved, size); @@ -1681,10 +1742,11 @@ int sqfs_exists(const char *filename) sqfs_split_path(&file, &dir, filename); /* - * sqfs_opendir will uncompress inode and directory tables, and will + * sqfs_opendir_nest will uncompress inode and directory tables, and will * return a pointer to the directory that contains the requested file. */ - ret = sqfs_opendir(dir, &dirsp); + symlinknest = 0; + ret = sqfs_opendir_nest(dir, &dirsp); if (ret) { ret = -EINVAL; goto free_strings; @@ -1692,7 +1754,7 @@ int sqfs_exists(const char *filename) dirs = (struct squashfs_dir_stream *)dirsp; - while (!sqfs_readdir(dirsp, &dent)) { + while (!sqfs_readdir_nest(dirsp, &dent)) { ret = strcmp(dent->name, file); if (!ret) break; @@ -1709,6 +1771,12 @@ free_strings: return ret == 0; } +int sqfs_size(const char *filename, loff_t *size) +{ + symlinknest = 0; + return sqfs_size_nest(filename, size); +} + void sqfs_close(void) { sqfs_decompressor_cleanup(&ctxt); diff --git a/fs/squashfs/sqfs_inode.c b/fs/squashfs/sqfs_inode.c index d25cfb53e75..bb3ccd37e33 100644 --- a/fs/squashfs/sqfs_inode.c +++ b/fs/squashfs/sqfs_inode.c @@ -78,11 +78,16 @@ int sqfs_inode_size(struct squashfs_base_inode *inode, u32 blk_size) case SQFS_SYMLINK_TYPE: case SQFS_LSYMLINK_TYPE: { + int size; + struct squashfs_symlink_inode *symlink = (struct squashfs_symlink_inode *)inode; - return sizeof(*symlink) + - get_unaligned_le32(&symlink->symlink_size); + if (__builtin_add_overflow(sizeof(*symlink), + get_unaligned_le32(&symlink->symlink_size), &size)) + return -EINVAL; + + return size; } case SQFS_BLKDEV_TYPE: diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index aa7f281ef6b..b6e03b76d41 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c @@ -451,7 +451,7 @@ int ubifs_validate_entry(struct ubifs_info *c, if (le32_to_cpu(dent->ch.len) != nlen + UBIFS_DENT_NODE_SZ + 1 || dent->type >= UBIFS_ITYPES_CNT || nlen > UBIFS_MAX_NLEN || dent->name[nlen] != 0 || - strnlen(dent->name, nlen) != nlen || + (key_type == UBIFS_XENT_KEY && strnlen(dent->name, nlen) != nlen) || le64_to_cpu(dent->inum) > MAX_INUM) { ubifs_err(c, "bad %s node", key_type == UBIFS_DENT_KEY ? "directory entry" : "extended attribute entry"); diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index d8d78a2d3d6..7718081f093 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -1758,11 +1758,13 @@ void ubifs_umount(struct ubifs_info *c) ubifs_debugging_exit(c); #ifdef __UBOOT__ ubi_close_volume(c->ubi); + c->ubi = NULL; mutex_unlock(&c->umount_mutex); /* Finally free U-Boot's global copy of superblock */ if (ubifs_sb != NULL) { - free(ubifs_sb->s_fs_info); - free(ubifs_sb); + kfree(ubifs_sb->s_fs_info); + kfree(ubifs_sb); + ubifs_sb = NULL; } #endif } @@ -2061,6 +2063,7 @@ static void ubifs_put_super(struct super_block *sb) #ifndef __UBOOT__ bdi_destroy(&c->bdi); ubi_close_volume(c->ubi); + c->ubi = NULL; mutex_unlock(&c->umount_mutex); #endif } @@ -2321,6 +2324,7 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent) goto out_umount; } #else + ubifs_iput(root); sb->s_root = NULL; #endif @@ -2340,6 +2344,7 @@ out_bdi: out_close: #endif ubi_close_volume(c->ubi); + c->ubi = NULL; out: return err; } diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 048730db7ff..398b076d783 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -319,9 +319,7 @@ static int filldir(struct ubifs_info *c, const char *name, int namlen, } ctime_r((time_t *)&inode->i_mtime, filetime); printf("%9lld %24.24s ", inode->i_size, filetime); -#ifndef __UBOOT__ ubifs_iput(inode); -#endif printf("%s\n", name); @@ -557,6 +555,7 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) /* We have some sort of symlink recursion, bail out */ if (symlink_count++ > 8) { + ubifs_iput(inode); printf("Symlink recursion, aborting\n"); return 0; } @@ -568,6 +567,7 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) * the leading slash */ next = name = link_name + 1; root_inum = 1; + ubifs_iput(inode); continue; } /* Relative to cur dir */ @@ -575,6 +575,7 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) link_name, next == NULL ? "" : next); memcpy(symlinkpath, buf, sizeof(buf)); next = name = symlinkpath; + ubifs_iput(inode); continue; } @@ -583,8 +584,10 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) */ /* Found the node! */ - if (!next || *next == '\0') + if (!next || *next == '\0') { + ubifs_iput(inode); return inum; + } root_inum = inum; name = next; @@ -614,7 +617,6 @@ int ubifs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info) int ubifs_ls(const char *filename) { - struct ubifs_info *c = ubifs_sb->s_fs_info; struct file *file; struct dentry *dentry; struct inode *dir; @@ -622,7 +624,11 @@ int ubifs_ls(const char *filename) unsigned long inum; int ret = 0; - c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY); + if (!ubifs_is_mounted()) { + debug("UBIFS not mounted, use ubifsmount to mount volume first!\n"); + return -1; + } + inum = ubifs_findfile(ubifs_sb, (char *)filename); if (!inum) { ret = -1; @@ -656,30 +662,33 @@ out_mem: free(dir); out: - ubi_close_volume(c->ubi); return ret; } int ubifs_exists(const char *filename) { - struct ubifs_info *c = ubifs_sb->s_fs_info; unsigned long inum; - c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY); + if (!ubifs_is_mounted()) { + debug("UBIFS not mounted, use ubifsmount to mount volume first!\n"); + return -1; + } + inum = ubifs_findfile(ubifs_sb, (char *)filename); - ubi_close_volume(c->ubi); return inum != 0; } int ubifs_size(const char *filename, loff_t *size) { - struct ubifs_info *c = ubifs_sb->s_fs_info; unsigned long inum; struct inode *inode; int err = 0; - c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY); + if (!ubifs_is_mounted()) { + debug("UBIFS not mounted, use ubifsmount to mount volume first!\n"); + return -1; + } inum = ubifs_findfile(ubifs_sb, (char *)filename); if (!inum) { @@ -698,7 +707,6 @@ int ubifs_size(const char *filename, loff_t *size) ubifs_iput(inode); out: - ubi_close_volume(c->ubi); return err; } @@ -885,6 +893,11 @@ int ubifs_read(const char *filename, void *buf, loff_t offset, int count; int last_block_size = 0; + if (!ubifs_is_mounted()) { + debug("UBIFS not mounted, use ubifsmount to mount volume first!\n"); + return -1; + } + *actread = 0; if (offset & (PAGE_SIZE - 1)) { @@ -893,7 +906,6 @@ int ubifs_read(const char *filename, void *buf, loff_t offset, return -1; } - c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY); /* ubifs_findfile will resolve symlinks, so we know that we get * the real file here */ inum = ubifs_findfile(ubifs_sb, (char *)filename); @@ -957,7 +969,6 @@ put_inode: ubifs_iput(inode); out: - ubi_close_volume(c->ubi); return err; } @@ -988,6 +999,5 @@ void uboot_ubifs_umount(void) printf("Unmounting UBIFS volume %s!\n", ((struct ubifs_info *)(ubifs_sb->s_fs_info))->vi.name); ubifs_umount(ubifs_sb->s_fs_info); - ubifs_sb = NULL; } } diff --git a/include/alist.h b/include/alist.h new file mode 100644 index 00000000000..586a1efa5c8 --- /dev/null +++ b/include/alist.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Handles a contiguous list of pointers which be allocated and freed + * + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __ALIST_H +#define __ALIST_H + +#include <stdbool.h> +#include <linux/bitops.h> +#include <linux/types.h> + +/** + * struct alist - object list that can be allocated and freed + * + * Holds a list of objects, each of the same size. The object is typically a + * C struct. The array is alloced in memory can change in size. + * + * The list rememebers the size of the list, but has a separate count of how + * much space is allocated, This allows it increase in size in steps as more + * elements are added, which is more efficient that reallocating the list every + * time a single item is added + * + * Two types of access are provided: + * + * alist_get...(index) + * gets an existing element, if its index is less that size + * + * alist_ensure(index) + * address an existing element, or creates a new one if not present + * + * @data: object data of size `@obj_size * @alloc`. The list can grow as + * needed but never shrinks + * @obj_size: Size of each object in bytes + * @count: number of objects in array + * @alloc: allocated length of array, to which @count can grow + * @flags: flags for the alist (ALISTF_...) + */ +struct alist { + void *data; + u16 obj_size; + u16 count; + u16 alloc; + u16 flags; +}; + +/** + * enum alist_flags - Flags for the alist + * + * @ALIST_FAIL: true if any allocation has failed. Once this has happened, the + * alist is dead and cannot grow further + */ +enum alist_flags { + ALISTF_FAIL = BIT(0), +}; + +/** + * alist_has() - Check if an index is within the list range + * + * Checks if index is within the current alist count + * + * @lst: alist to check + * @index: Index to check + * Returns: true if value, else false + */ +static inline bool alist_has(struct alist *lst, uint index) +{ + return index < lst->count; +} + +/** + * alist_err() - Check if the alist is still valid + * + * @lst: List to check + * Return: false if OK, true if any previous allocation failed + */ +static inline bool alist_err(struct alist *lst) +{ + return lst->flags & ALISTF_FAIL; +} + +/** + * alist_get_ptr() - Get the value of a pointer + * + * @lst: alist to check + * @index: Index to read from + * Returns: pointer, if present, else NULL + */ +const void *alist_get_ptr(const struct alist *lst, uint index); + +/** + * alist_getd() - Get the value of a pointer directly, with no checking + * + * This must only be called on indexes for which alist_has() returns true + * + * @lst: alist to check + * @index: Index to read from + * Returns: pointer value (may be NULL) + */ +static inline const void *alist_getd(struct alist *lst, uint index) +{ + return lst->data + index * lst->obj_size; +} + +/** get an entry as a constant */ +#define alist_get(_lst, _index, _struct) \ + ((const _struct *)alist_get_ptr(_lst, _index)) + +/** get an entry which can be written to */ +#define alist_getw(_lst, _index, _struct) \ + ((_struct *)alist_get_ptr(_lst, _index)) + +/** + * alist_ensure_ptr() - Ensure an object exists at a given index + * + * This provides read/write access to an array element. If it does not exist, + * it is allocated, reading for the caller to store the object into + * + * Allocates a object at the given index if needed + * + * @lst: alist to check + * @index: Index to address + * Returns: pointer where struct can be read/written, or NULL if out of memory + */ +void *alist_ensure_ptr(struct alist *lst, uint index); + +/** + * alist_ensure() - Address a struct, the correct object type + * + * Use as: + * struct my_struct *ptr = alist_ensure(&lst, 4, struct my_struct); + */ +#define alist_ensure(_lst, _index, _struct) \ + ((_struct *)alist_ensure_ptr(_lst, _index)) + +/** + * alist_add_placeholder() - Add a new item to the end of the list + * + * @lst: alist to add to + * Return: Pointer to the newly added position. Note that this is not inited so + * the caller must copy the requested struct to the returned pointer + */ +void *alist_add_placeholder(struct alist *lst); + +/** + * alist_add_ptr() - Ad a new object to the list + * + * @lst: alist to add to + * @obj: Pointer to object to copy in + * Returns: pointer to where the object was copied, or NULL if out of memory + */ +void *alist_add_ptr(struct alist *lst, void *obj); + +/** + * alist_expand_by() - Expand a list by the given amount + * + * @lst: alist to expand + * @inc_by: Amount to expand by + * Return: true if OK, false if out of memory + */ +bool alist_expand_by(struct alist *lst, uint inc_by); + +/** + * alist_add() - Used to add an object type with the correct type + * + * Use as: + * struct my_struct obj; + * struct my_struct *ptr = alist_add(&lst, &obj); + */ +#define alist_add(_lst, _obj) \ + ((typeof(_obj) *)alist_add_ptr(_lst, &(_obj))) + +/** + * alist_init() - Set up a new object list + * + * Sets up a list of objects, initially empty + * + * @lst: alist to set up + * @obj_size: Size of each element in bytes + * @alloc_size: Number of items to allowed to start, before reallocation is + * needed (0 to start with no space) + * Return: true if OK, false if out of memory + */ +bool alist_init(struct alist *lst, uint obj_size, uint alloc_size); + +#define alist_init_struct(_lst, _struct) \ + alist_init(_lst, sizeof(_struct), 0) + +/** + * alist_uninit_move_ptr() - Return the allocated contents and uninit the alist + * + * This returns the alist data to the caller, so that the caller receives data + * that it can be sure will hang around. The caller is responsible for freeing + * the data. + * + * If the alist size is 0, this returns NULL + * + * The alist is uninited as part of this. + * + * The alist must be inited before this can be called. + * + * @alist: alist to uninit + * @countp: if non-NULL, returns the number of objects in the returned data + * (which is @alist->size) + * Return: data contents, allocated with malloc(), or NULL if the data could not + * be allocated, or the data size is 0 + */ +void *alist_uninit_move_ptr(struct alist *alist, size_t *countp); + +/** + * alist_uninit_move() - Typed version of alist_uninit_move_ptr() + */ +#define alist_uninit_move(_lst, _countp, _struct) \ + (_struct *)alist_uninit_move_ptr(_lst, _countp) + +/** + * alist_uninit() - Free any memory used by an alist + * + * The alist must be inited before this can be called. + * + * @alist: alist to uninit + */ +void alist_uninit(struct alist *alist); + +#endif /* __ALIST_H */ diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 27aa75e7036..19c66e1fe5d 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -30,6 +30,7 @@ struct acpi_ctx; struct driver_rt; +struct upl; typedef struct global_data gd_t; @@ -491,6 +492,12 @@ struct global_data { * @dmtag_list: List of DM tags */ struct list_head dmtag_list; +#if CONFIG_IS_ENABLED(UPL) + /** + * @upl: Universal Payload-handoff information + */ + struct upl *upl; +#endif }; #ifndef DO_DEPS_ONLY static_assert(sizeof(struct global_data) == GD_SIZE); @@ -590,6 +597,14 @@ static_assert(sizeof(struct global_data) == GD_SIZE); #define gd_malloc_ptr() 0L #endif +#if CONFIG_IS_ENABLED(UPL) +#define gd_upl() gd->upl +#define gd_set_upl(_val) gd->upl = (_val) +#else +#define gd_upl() NULL +#define gd_set_upl(val) +#endif + /** * enum gd_flags - global data flags * @@ -701,6 +716,10 @@ enum gd_flags { * @GD_FLG_HUSH_MODERN_PARSER: Use hush 2021 parser. */ GD_FLG_HUSH_MODERN_PARSER = 0x2000000, + /** + * @GD_FLG_UPL: Read/write a Universal Payload (UPL) handoff + */ + GD_FLG_UPL = 0x4000000, }; #endif /* __ASSEMBLY__ */ diff --git a/include/bootstage.h b/include/bootstage.h index f4e77b09d74..57792648c49 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -258,7 +258,7 @@ void show_boot_progress(int val); * relocation, since memory can be overwritten later. * Return: Always returns 0, to indicate success */ -int bootstage_relocate(void); +int bootstage_relocate(void *to); /** * Add a new bootstage record @@ -395,7 +395,7 @@ static inline ulong bootstage_add_record(enum bootstage_id id, * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined */ -static inline int bootstage_relocate(void) +static inline int bootstage_relocate(void *to) { return 0; } diff --git a/include/configs/amd_versal2_mini.h b/include/configs/amd_versal2_mini.h new file mode 100644 index 00000000000..97e8f673a83 --- /dev/null +++ b/include/configs/amd_versal2_mini.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for AMD Versal Gen2 MINI configuration + * + * Copyright (C) 2023 - 2024, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#ifndef __CONFIG_VERSAL2_MINI_H +#define __CONFIG_VERSAL2_MINI_H + +#define CFG_EXTRA_ENV_SETTINGS + +#include <configs/amd_versal2.h> + +/* Undef unneeded configs */ +#undef CFG_EXTRA_ENV_SETTINGS + +#endif /* __CONFIG_VERSAL2_MINI_H */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 807c6963192..c327bbbe07d 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -59,9 +59,6 @@ #define CFG_SYS_I2C_RTC_ADDR 0x51 #endif -/* I2C */ -#define CFG_SYS_MAX_I2C_BUS 1 - #define I2C_SOFT_DECLARATIONS #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 769ece901c1..ed93b51d808 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -47,7 +47,6 @@ #endif /* RTC */ -#define CFG_SYS_RTC_BUS_NUM 1 #define I2C_MUX_CH_RTC 0xB /* Store environment at top of flash */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 0f591e3c4ab..d44ce45fd6b 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -10,8 +10,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CFG_SYS_RTC_BUS_NUM 0 - /* Store environment at top of flash */ /* diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 5e03a962d10..21804fc6654 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -66,7 +66,6 @@ /* RTC */ #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ -#define CFG_SYS_RTC_BUS_NUM 0 /* * Environment diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 3a316e73308..5b397e23d89 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -8,9 +8,6 @@ #include "lx2160a_common.h" -/* RTC */ -#define CFG_SYS_RTC_BUS_NUM 0 - /* MAC/PHY configuration */ /* Initial environment variables */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 6404b359111..e700a7b1135 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -8,9 +8,6 @@ #include "lx2160a_common.h" -/* RTC */ -#define CFG_SYS_RTC_BUS_NUM 4 - #if defined(CONFIG_FSL_MC_ENET) #define AQR113C_PHY_ADDR1 0x0 #define AQR113C_PHY_ADDR2 0x08 diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 54d7cea4c59..2d0db47b334 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -10,9 +10,6 @@ /* USB */ -/* RTC */ -#define CFG_SYS_RTC_BUS_NUM 0 - /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 9cf46b2c362..c245cbe427b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -57,8 +57,6 @@ #define CFG_FEC_MXC_PHYADDR 0x0 #endif -#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */ - /* * RTC */ diff --git a/include/configs/rock-5-itx-rk3588.h b/include/configs/rock-5-itx-rk3588.h new file mode 100644 index 00000000000..bc0f9e72bc5 --- /dev/null +++ b/include/configs/rock-5-itx-rk3588.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> + */ + +#ifndef __ROCK_5_ITX_RK3588_H +#define __ROCK_5_ITX_RK3588_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3588_common.h> + +#endif /* __ROCK_5_ITX_RK3588_H */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 45a3102aeee..d0ae5e18605 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -35,20 +35,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 /* - * I2C - */ - -#define CFG_I2C_MULTI_BUS - -/* - * Input - */ - -/* - * SPL - */ - -/* * Serial */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2da76f15431..ceeed174ec5 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -26,9 +26,6 @@ #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K -/* I2C Configs */ -#define CFG_I2C_MULTI_BUS - #if !defined(CONFIG_DM_PMIC) #define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index e06fc7fe155..5e21463305a 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -16,7 +16,6 @@ /* Watchdog */ /* Config on-board RTC */ -#define CFG_SYS_RTC_BUS_NUM 2 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 76fcaff0e42..cdbcaef76eb 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -117,46 +117,51 @@ #define CLK_TOP_I2S1_MCK_DIV_PD 104 #define CLK_TOP_I2S2_MCK_DIV_PD 105 #define CLK_TOP_I2S3_MCK_DIV_PD 106 +#define CLK_TOP_A1SYS_HP_DIV_PD 107 +#define CLK_TOP_A2SYS_HP_DIV_PD 108 /* INFRACFG */ -#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_TRNG 1 +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 #define CLK_INFRA_AUDIO_PD 2 #define CLK_INFRA_IRRX_PD 3 #define CLK_INFRA_APXGPT_PD 4 #define CLK_INFRA_PMIC_PD 5 +#define CLK_INFRA_TRNG 6 /* PERICFG */ -#define CLK_PERI_THERM_PD 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_0_PD 10 -#define CLK_PERI_MSDC30_1_PD 11 -#define CLK_PERI_UART0_PD 12 -#define CLK_PERI_UART1_PD 13 -#define CLK_PERI_UART2_PD 14 -#define CLK_PERI_UART3_PD 15 -#define CLK_PERI_BTIF_PD 16 -#define CLK_PERI_I2C0_PD 17 -#define CLK_PERI_I2C1_PD 18 -#define CLK_PERI_I2C2_PD 19 -#define CLK_PERI_SPI1_PD 20 -#define CLK_PERI_AUXADC_PD 21 -#define CLK_PERI_SPI0_PD 22 -#define CLK_PERI_SNFI_PD 23 -#define CLK_PERI_NFI_PD 24 -#define CLK_PERI_NFIECC_PD 25 -#define CLK_PERI_FLASH_PD 26 -#define CLK_PERI_IRTX_PD 27 +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_THERM_PD 1 +#define CLK_PERI_PWM1_PD 2 +#define CLK_PERI_PWM2_PD 3 +#define CLK_PERI_PWM3_PD 4 +#define CLK_PERI_PWM4_PD 5 +#define CLK_PERI_PWM5_PD 6 +#define CLK_PERI_PWM6_PD 7 +#define CLK_PERI_PWM7_PD 8 +#define CLK_PERI_PWM_PD 9 +#define CLK_PERI_AP_DMA_PD 10 +#define CLK_PERI_MSDC30_0_PD 11 +#define CLK_PERI_MSDC30_1_PD 12 +#define CLK_PERI_UART0_PD 13 +#define CLK_PERI_UART1_PD 14 +#define CLK_PERI_UART2_PD 15 +#define CLK_PERI_UART3_PD 16 +#define CLK_PERI_UART4_PD 17 +#define CLK_PERI_BTIF_PD 18 +#define CLK_PERI_I2C0_PD 19 +#define CLK_PERI_I2C1_PD 20 +#define CLK_PERI_I2C2_PD 21 +#define CLK_PERI_SPI1_PD 22 +#define CLK_PERI_AUXADC_PD 23 +#define CLK_PERI_SPI0_PD 24 +#define CLK_PERI_SNFI_PD 25 +#define CLK_PERI_NFI_PD 26 +#define CLK_PERI_NFIECC_PD 27 +#define CLK_PERI_FLASH_PD 28 +#define CLK_PERI_IRTX_PD 29 /* APMIXEDSYS */ @@ -169,6 +174,7 @@ #define CLK_APMIXED_AUD2PLL 6 #define CLK_APMIXED_TRGPLL 7 #define CLK_APMIXED_SGMIPLL 8 +#define CLK_APMIXED_MAIN_CORE_EN 9 /* AUDIOSYS */ @@ -206,7 +212,7 @@ #define CLK_AUDIO_DLMCH 31 #define CLK_AUDIO_ARB1 32 #define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB3 34 +#define CLK_AUDIO_AWB2 34 #define CLK_AUDIO_DAI 35 #define CLK_AUDIO_MOD 36 #define CLK_AUDIO_ASRCI3 37 diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h index 71ced1593af..0caeb65c3d2 100644 --- a/include/dt-bindings/clock/mt7623-clk.h +++ b/include/dt-bindings/clock/mt7623-clk.h @@ -7,407 +7,477 @@ #define _DT_BINDINGS_CLK_MT2701_H /* TOPCKGEN */ -#define CLK_TOP_FCLKS_OFF 0 - -#define CLK_TOP_DPI 0 -#define CLK_TOP_DMPLL 1 -#define CLK_TOP_VENCPLL 2 -#define CLK_TOP_HDMI_0_PIX340M 3 -#define CLK_TOP_HDMI_0_DEEP340M 4 -#define CLK_TOP_HDMI_0_PLL340M 5 -#define CLK_TOP_HADDS2_FB 6 -#define CLK_TOP_WBG_DIG_416M 7 -#define CLK_TOP_DSI0_LNTC_DSI 8 -#define CLK_TOP_HDMI_SCL_RX 9 -#define CLK_TOP_32K_EXTERNAL 10 -#define CLK_TOP_HDMITX_CLKDIG_CTS 11 -#define CLK_TOP_AUD_EXT1 12 -#define CLK_TOP_AUD_EXT2 13 -#define CLK_TOP_NFI1X_PAD 14 - -#define CLK_TOP_SYSPLL 15 -#define CLK_TOP_SYSPLL_D2 16 -#define CLK_TOP_SYSPLL_D3 17 -#define CLK_TOP_SYSPLL_D5 18 -#define CLK_TOP_SYSPLL_D7 19 -#define CLK_TOP_SYSPLL1_D2 20 -#define CLK_TOP_SYSPLL1_D4 21 -#define CLK_TOP_SYSPLL1_D8 22 -#define CLK_TOP_SYSPLL1_D16 23 -#define CLK_TOP_SYSPLL2_D2 24 -#define CLK_TOP_SYSPLL2_D4 25 -#define CLK_TOP_SYSPLL2_D8 26 -#define CLK_TOP_SYSPLL3_D2 27 -#define CLK_TOP_SYSPLL3_D4 28 -#define CLK_TOP_SYSPLL4_D2 29 -#define CLK_TOP_SYSPLL4_D4 30 -#define CLK_TOP_UNIVPLL 31 -#define CLK_TOP_UNIVPLL_D2 32 -#define CLK_TOP_UNIVPLL_D3 33 -#define CLK_TOP_UNIVPLL_D5 34 -#define CLK_TOP_UNIVPLL_D7 35 -#define CLK_TOP_UNIVPLL_D26 36 -#define CLK_TOP_UNIVPLL_D52 37 -#define CLK_TOP_UNIVPLL_D108 38 -#define CLK_TOP_USB_PHY48M 39 -#define CLK_TOP_UNIVPLL1_D2 40 -#define CLK_TOP_UNIVPLL1_D4 41 -#define CLK_TOP_UNIVPLL1_D8 42 -#define CLK_TOP_UNIVPLL2_D2 43 -#define CLK_TOP_UNIVPLL2_D4 44 -#define CLK_TOP_UNIVPLL2_D8 45 -#define CLK_TOP_UNIVPLL2_D16 46 -#define CLK_TOP_UNIVPLL2_D32 47 -#define CLK_TOP_UNIVPLL3_D2 48 -#define CLK_TOP_UNIVPLL3_D4 49 -#define CLK_TOP_UNIVPLL3_D8 50 -#define CLK_TOP_MSDCPLL 51 -#define CLK_TOP_MSDCPLL_D2 52 -#define CLK_TOP_MSDCPLL_D4 53 -#define CLK_TOP_MSDCPLL_D8 54 -#define CLK_TOP_MMPLL 55 -#define CLK_TOP_MMPLL_D2 56 -#define CLK_TOP_DMPLL_D2 57 -#define CLK_TOP_DMPLL_D4 58 -#define CLK_TOP_DMPLL_X2 59 -#define CLK_TOP_TVDPLL 60 -#define CLK_TOP_TVDPLL_D2 61 -#define CLK_TOP_TVDPLL_D4 62 -#define CLK_TOP_VDECPLL 63 -#define CLK_TOP_TVD2PLL 64 -#define CLK_TOP_TVD2PLL_D2 65 -#define CLK_TOP_MIPIPLL 66 -#define CLK_TOP_MIPIPLL_D2 67 -#define CLK_TOP_MIPIPLL_D4 68 -#define CLK_TOP_HDMIPLL 69 -#define CLK_TOP_HDMIPLL_D2 70 -#define CLK_TOP_HDMIPLL_D3 71 -#define CLK_TOP_ARMPLL_1P3G 72 -#define CLK_TOP_AUDPLL 73 -#define CLK_TOP_AUDPLL_D4 74 -#define CLK_TOP_AUDPLL_D8 75 -#define CLK_TOP_AUDPLL_D16 76 -#define CLK_TOP_AUDPLL_D24 77 -#define CLK_TOP_AUD1PLL_98M 78 -#define CLK_TOP_AUD2PLL_90M 79 -#define CLK_TOP_HADDS2PLL_98M 80 -#define CLK_TOP_HADDS2PLL_294M 81 -#define CLK_TOP_ETHPLL_500M 82 -#define CLK_TOP_CLK26M_D8 83 -#define CLK_TOP_32K_INTERNAL 84 -#define CLK_TOP_AXISEL_D4 85 -#define CLK_TOP_8BDAC 86 - -#define CLK_TOP_AXI_SEL 87 -#define CLK_TOP_MEM_SEL 88 -#define CLK_TOP_DDRPHYCFG_SEL 89 -#define CLK_TOP_MM_SEL 90 -#define CLK_TOP_PWM_SEL 91 -#define CLK_TOP_VDEC_SEL 92 -#define CLK_TOP_MFG_SEL 93 -#define CLK_TOP_CAMTG_SEL 94 -#define CLK_TOP_UART_SEL 95 -#define CLK_TOP_SPI0_SEL 96 -#define CLK_TOP_USB20_SEL 97 -#define CLK_TOP_MSDC30_0_SEL 98 -#define CLK_TOP_MSDC30_1_SEL 99 -#define CLK_TOP_MSDC30_2_SEL 100 -#define CLK_TOP_AUDIO_SEL 101 -#define CLK_TOP_AUDINTBUS_SEL 102 -#define CLK_TOP_PMICSPI_SEL 103 -#define CLK_TOP_SCP_SEL 104 -#define CLK_TOP_DPI0_SEL 105 -#define CLK_TOP_DPI1_SEL 106 -#define CLK_TOP_TVE_SEL 107 -#define CLK_TOP_HDMI_SEL 108 -#define CLK_TOP_APLL_SEL 109 -#define CLK_TOP_RTC_SEL 110 -#define CLK_TOP_NFI2X_SEL 111 -#define CLK_TOP_EMMC_HCLK_SEL 112 -#define CLK_TOP_FLASH_SEL 113 -#define CLK_TOP_DI_SEL 114 -#define CLK_TOP_NR_SEL 115 -#define CLK_TOP_OSD_SEL 116 -#define CLK_TOP_HDMIRX_BIST_SEL 117 -#define CLK_TOP_INTDIR_SEL 118 -#define CLK_TOP_ASM_I_SEL 119 -#define CLK_TOP_ASM_M_SEL 120 -#define CLK_TOP_ASM_H_SEL 121 -#define CLK_TOP_MS_CARD_SEL 122 -#define CLK_TOP_ETHIF_SEL 123 -#define CLK_TOP_HDMIRX26_24_SEL 124 -#define CLK_TOP_MSDC30_3_SEL 125 -#define CLK_TOP_CMSYS_SEL 126 -#define CLK_TOP_SPI1_SEL 127 -#define CLK_TOP_SPI2_SEL 128 -#define CLK_TOP_8BDAC_SEL 129 -#define CLK_TOP_AUD2DVD_SEL 130 -#define CLK_TOP_PADMCLK_SEL 131 -#define CLK_TOP_AUD_MUX1_SEL 132 -#define CLK_TOP_AUD_MUX2_SEL 133 -#define CLK_TOP_AUDPLL_MUX_SEL 134 -#define CLK_TOP_AUD_K1_SRC_SEL 135 -#define CLK_TOP_AUD_K2_SRC_SEL 136 -#define CLK_TOP_AUD_K3_SRC_SEL 137 -#define CLK_TOP_AUD_K4_SRC_SEL 138 -#define CLK_TOP_AUD_K5_SRC_SEL 139 -#define CLK_TOP_AUD_K6_SRC_SEL 140 - -#define CLK_TOP_AUD_EXTCK1_DIV 141 -#define CLK_TOP_AUD_EXTCK2_DIV 142 -#define CLK_TOP_AUD_MUX1_DIV 143 -#define CLK_TOP_AUD_MUX2_DIV 144 -#define CLK_TOP_AUD_K1_SRC_DIV 145 -#define CLK_TOP_AUD_K2_SRC_DIV 146 -#define CLK_TOP_AUD_K3_SRC_DIV 147 -#define CLK_TOP_AUD_K4_SRC_DIV 148 -#define CLK_TOP_AUD_K5_SRC_DIV 149 -#define CLK_TOP_AUD_K6_SRC_DIV 150 -#define CLK_TOP_AUD_48K_TIMING 151 -#define CLK_TOP_AUD_44K_TIMING 152 -#define CLK_TOP_AUD_I2S1_MCLK 153 -#define CLK_TOP_AUD_I2S2_MCLK 154 -#define CLK_TOP_AUD_I2S3_MCLK 155 -#define CLK_TOP_AUD_I2S4_MCLK 156 -#define CLK_TOP_AUD_I2S5_MCLK 157 -#define CLK_TOP_AUD_I2S6_MCLK 158 +#define CLK_TOP_SYSPLL 1 +#define CLK_TOP_SYSPLL_D2 2 +#define CLK_TOP_SYSPLL_D3 3 +#define CLK_TOP_SYSPLL_D5 4 +#define CLK_TOP_SYSPLL_D7 5 +#define CLK_TOP_SYSPLL1_D2 6 +#define CLK_TOP_SYSPLL1_D4 7 +#define CLK_TOP_SYSPLL1_D8 8 +#define CLK_TOP_SYSPLL1_D16 9 +#define CLK_TOP_SYSPLL2_D2 10 +#define CLK_TOP_SYSPLL2_D4 11 +#define CLK_TOP_SYSPLL2_D8 12 +#define CLK_TOP_SYSPLL3_D2 13 +#define CLK_TOP_SYSPLL3_D4 14 +#define CLK_TOP_SYSPLL4_D2 15 +#define CLK_TOP_SYSPLL4_D4 16 +#define CLK_TOP_UNIVPLL 17 +#define CLK_TOP_UNIVPLL_D2 18 +#define CLK_TOP_UNIVPLL_D3 19 +#define CLK_TOP_UNIVPLL_D5 20 +#define CLK_TOP_UNIVPLL_D7 21 +#define CLK_TOP_UNIVPLL_D26 22 +#define CLK_TOP_UNIVPLL_D52 23 +#define CLK_TOP_UNIVPLL_D108 24 +#define CLK_TOP_USB_PHY48M 25 +#define CLK_TOP_UNIVPLL1_D2 26 +#define CLK_TOP_UNIVPLL1_D4 27 +#define CLK_TOP_UNIVPLL1_D8 28 +#define CLK_TOP_UNIVPLL2_D2 29 +#define CLK_TOP_UNIVPLL2_D4 30 +#define CLK_TOP_UNIVPLL2_D8 31 +#define CLK_TOP_UNIVPLL2_D16 32 +#define CLK_TOP_UNIVPLL2_D32 33 +#define CLK_TOP_UNIVPLL3_D2 34 +#define CLK_TOP_UNIVPLL3_D4 35 +#define CLK_TOP_UNIVPLL3_D8 36 +#define CLK_TOP_MSDCPLL 37 +#define CLK_TOP_MSDCPLL_D2 38 +#define CLK_TOP_MSDCPLL_D4 39 +#define CLK_TOP_MSDCPLL_D8 40 +#define CLK_TOP_MMPLL 41 +#define CLK_TOP_MMPLL_D2 42 +#define CLK_TOP_DMPLL 43 +#define CLK_TOP_DMPLL_D2 44 +#define CLK_TOP_DMPLL_D4 45 +#define CLK_TOP_DMPLL_X2 46 +#define CLK_TOP_TVDPLL 47 +#define CLK_TOP_TVDPLL_D2 48 +#define CLK_TOP_TVDPLL_D4 49 +#define CLK_TOP_TVD2PLL 50 +#define CLK_TOP_TVD2PLL_D2 51 +#define CLK_TOP_HADDS2PLL_98M 52 +#define CLK_TOP_HADDS2PLL_294M 53 +#define CLK_TOP_HADDS2_FB 54 +#define CLK_TOP_MIPIPLL_D2 55 +#define CLK_TOP_MIPIPLL_D4 56 +#define CLK_TOP_HDMIPLL 57 +#define CLK_TOP_HDMIPLL_D2 58 +#define CLK_TOP_HDMIPLL_D3 59 +#define CLK_TOP_HDMI_SCL_RX 60 +#define CLK_TOP_HDMI_0_PIX340M 61 +#define CLK_TOP_HDMI_0_DEEP340M 62 +#define CLK_TOP_HDMI_0_PLL340M 63 +#define CLK_TOP_AUD1PLL_98M 64 +#define CLK_TOP_AUD2PLL_90M 65 +#define CLK_TOP_AUDPLL 66 +#define CLK_TOP_AUDPLL_D4 67 +#define CLK_TOP_AUDPLL_D8 68 +#define CLK_TOP_AUDPLL_D16 69 +#define CLK_TOP_AUDPLL_D24 70 +#define CLK_TOP_ETHPLL_500M 71 +#define CLK_TOP_VDECPLL 72 +#define CLK_TOP_VENCPLL 73 +#define CLK_TOP_MIPIPLL 74 +#define CLK_TOP_ARMPLL_1P3G 75 + +#define CLK_TOP_MM_SEL 76 +#define CLK_TOP_DDRPHYCFG_SEL 77 +#define CLK_TOP_MEM_SEL 78 +#define CLK_TOP_AXI_SEL 79 +#define CLK_TOP_CAMTG_SEL 80 +#define CLK_TOP_MFG_SEL 81 +#define CLK_TOP_VDEC_SEL 82 +#define CLK_TOP_PWM_SEL 83 +#define CLK_TOP_MSDC30_0_SEL 84 +#define CLK_TOP_USB20_SEL 85 +#define CLK_TOP_SPI0_SEL 86 +#define CLK_TOP_UART_SEL 87 +#define CLK_TOP_AUDINTBUS_SEL 88 +#define CLK_TOP_AUDIO_SEL 89 +#define CLK_TOP_MSDC30_2_SEL 90 +#define CLK_TOP_MSDC30_1_SEL 91 +#define CLK_TOP_DPI1_SEL 92 +#define CLK_TOP_DPI0_SEL 93 +#define CLK_TOP_SCP_SEL 94 +#define CLK_TOP_PMICSPI_SEL 95 +#define CLK_TOP_APLL_SEL 96 +#define CLK_TOP_HDMI_SEL 97 +#define CLK_TOP_TVE_SEL 98 +#define CLK_TOP_EMMC_HCLK_SEL 99 +#define CLK_TOP_NFI2X_SEL 100 +#define CLK_TOP_RTC_SEL 101 +#define CLK_TOP_OSD_SEL 102 +#define CLK_TOP_NR_SEL 103 +#define CLK_TOP_DI_SEL 104 +#define CLK_TOP_FLASH_SEL 105 +#define CLK_TOP_ASM_M_SEL 106 +#define CLK_TOP_ASM_I_SEL 107 +#define CLK_TOP_INTDIR_SEL 108 +#define CLK_TOP_HDMIRX_BIST_SEL 109 +#define CLK_TOP_ETHIF_SEL 110 +#define CLK_TOP_MS_CARD_SEL 111 +#define CLK_TOP_ASM_H_SEL 112 +#define CLK_TOP_SPI1_SEL 113 +#define CLK_TOP_CMSYS_SEL 114 +#define CLK_TOP_MSDC30_3_SEL 115 +#define CLK_TOP_HDMIRX26_24_SEL 116 +#define CLK_TOP_AUD2DVD_SEL 117 +#define CLK_TOP_8BDAC_SEL 118 +#define CLK_TOP_SPI2_SEL 119 +#define CLK_TOP_AUD_MUX1_SEL 120 +#define CLK_TOP_AUD_MUX2_SEL 121 +#define CLK_TOP_AUDPLL_MUX_SEL 122 +#define CLK_TOP_AUD_K1_SRC_SEL 123 +#define CLK_TOP_AUD_K2_SRC_SEL 124 +#define CLK_TOP_AUD_K3_SRC_SEL 125 +#define CLK_TOP_AUD_K4_SRC_SEL 126 +#define CLK_TOP_AUD_K5_SRC_SEL 127 +#define CLK_TOP_AUD_K6_SRC_SEL 128 +#define CLK_TOP_PADMCLK_SEL 129 +#define CLK_TOP_AUD_EXTCK1_DIV 130 +#define CLK_TOP_AUD_EXTCK2_DIV 131 +#define CLK_TOP_AUD_MUX1_DIV 132 +#define CLK_TOP_AUD_MUX2_DIV 133 +#define CLK_TOP_AUD_K1_SRC_DIV 134 +#define CLK_TOP_AUD_K2_SRC_DIV 135 +#define CLK_TOP_AUD_K3_SRC_DIV 136 +#define CLK_TOP_AUD_K4_SRC_DIV 137 +#define CLK_TOP_AUD_K5_SRC_DIV 138 +#define CLK_TOP_AUD_K6_SRC_DIV 139 +#define CLK_TOP_AUD_I2S1_MCLK 140 +#define CLK_TOP_AUD_I2S2_MCLK 141 +#define CLK_TOP_AUD_I2S3_MCLK 142 +#define CLK_TOP_AUD_I2S4_MCLK 143 +#define CLK_TOP_AUD_I2S5_MCLK 144 +#define CLK_TOP_AUD_I2S6_MCLK 145 +#define CLK_TOP_AUD_48K_TIMING 146 +#define CLK_TOP_AUD_44K_TIMING 147 + +#define CLK_TOP_32K_INTERNAL 148 +#define CLK_TOP_32K_EXTERNAL 149 +#define CLK_TOP_CLK26M_D8 150 +#define CLK_TOP_8BDAC 151 +#define CLK_TOP_WBG_DIG_416M 152 +#define CLK_TOP_DPI 153 +#define CLK_TOP_DSI0_LNTC_DSI 154 +#define CLK_TOP_AUD_EXT1 155 +#define CLK_TOP_AUD_EXT2 156 +#define CLK_TOP_NFI1X_PAD 157 +#define CLK_TOP_AXISEL_D4 158 #define CLK_TOP_NR 159 /* APMIXEDSYS */ -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIVPLL 2 -#define CLK_APMIXED_MMPLL 3 -#define CLK_APMIXED_MSDCPLL 4 -#define CLK_APMIXED_TVDPLL 5 -#define CLK_APMIXED_AUD1PLL 6 -#define CLK_APMIXED_TRGPLL 7 -#define CLK_APMIXED_ETHPLL 8 -#define CLK_APMIXED_VDECPLL 9 -#define CLK_APMIXED_HADDS2PLL 10 -#define CLK_APMIXED_AUD2PLL 11 -#define CLK_APMIXED_TVD2PLL 12 -#define CLK_APMIXED_NR 13 + +#define CLK_APMIXED_ARMPLL 1 +#define CLK_APMIXED_MAINPLL 2 +#define CLK_APMIXED_UNIVPLL 3 +#define CLK_APMIXED_MMPLL 4 +#define CLK_APMIXED_MSDCPLL 5 +#define CLK_APMIXED_TVDPLL 6 +#define CLK_APMIXED_AUD1PLL 7 +#define CLK_APMIXED_TRGPLL 8 +#define CLK_APMIXED_ETHPLL 9 +#define CLK_APMIXED_VDECPLL 10 +#define CLK_APMIXED_HADDS2PLL 11 +#define CLK_APMIXED_AUD2PLL 12 +#define CLK_APMIXED_TVD2PLL 13 +#define CLK_APMIXED_HDMI_REF 14 +#define CLK_APMIXED_NR 15 + +/* DDRPHY */ + +#define CLK_DDRPHY_VENCPLL 1 +#define CLK_DDRPHY_NR 2 /* INFRACFG */ -#define CLK_INFRA_DBG 0 -#define CLK_INFRA_SMI 1 -#define CLK_INFRA_QAXI_CM4 2 -#define CLK_INFRA_AUD_SPLIN_B 3 -#define CLK_INFRA_AUDIO 4 -#define CLK_INFRA_EFUSE 5 -#define CLK_INFRA_L2C_SRAM 6 -#define CLK_INFRA_M4U 7 -#define CLK_INFRA_CONNMCU 8 -#define CLK_INFRA_TRNG 9 -#define CLK_INFRA_RAMBUFIF 10 -#define CLK_INFRA_CPUM 11 -#define CLK_INFRA_KP 12 -#define CLK_INFRA_CEC 13 -#define CLK_INFRA_IRRX 14 -#define CLK_INFRA_PMICSPI 15 -#define CLK_INFRA_PMICWRAP 16 -#define CLK_INFRA_DDCCI 17 -#define CLK_INFRA_CPUSEL 18 -#define CLK_INFRA_NR 19 + +#define CLK_INFRA_DBG 1 +#define CLK_INFRA_SMI 2 +#define CLK_INFRA_QAXI_CM4 3 +#define CLK_INFRA_AUD_SPLIN_B 4 +#define CLK_INFRA_AUDIO 5 +#define CLK_INFRA_EFUSE 6 +#define CLK_INFRA_L2C_SRAM 7 +#define CLK_INFRA_M4U 8 +#define CLK_INFRA_CONNMCU 9 +#define CLK_INFRA_TRNG 10 +#define CLK_INFRA_RAMBUFIF 11 +#define CLK_INFRA_CPUM 12 +#define CLK_INFRA_KP 13 +#define CLK_INFRA_CEC 14 +#define CLK_INFRA_IRRX 15 +#define CLK_INFRA_PMICSPI 16 +#define CLK_INFRA_PMICWRAP 17 +#define CLK_INFRA_DDCCI 18 +#define CLK_INFRA_CLK_13M 19 +#define CLK_INFRA_CPUSEL 20 +#define CLK_INFRA_NR 21 /* PERICFG */ -#define CLK_PERI_NFI 0 -#define CLK_PERI_THERM 1 -#define CLK_PERI_PWM1 2 -#define CLK_PERI_PWM2 3 -#define CLK_PERI_PWM3 4 -#define CLK_PERI_PWM4 5 -#define CLK_PERI_PWM5 6 -#define CLK_PERI_PWM6 7 -#define CLK_PERI_PWM7 8 -#define CLK_PERI_PWM 9 -#define CLK_PERI_USB0 10 -#define CLK_PERI_USB1 11 -#define CLK_PERI_AP_DMA 12 -#define CLK_PERI_MSDC30_0 13 -#define CLK_PERI_MSDC30_1 14 -#define CLK_PERI_MSDC30_2 15 -#define CLK_PERI_MSDC30_3 16 -#define CLK_PERI_MSDC50_3 17 -#define CLK_PERI_NLI 18 -#define CLK_PERI_UART0 19 -#define CLK_PERI_UART1 20 -#define CLK_PERI_UART2 21 -#define CLK_PERI_UART3 22 -#define CLK_PERI_BTIF 23 -#define CLK_PERI_I2C0 24 -#define CLK_PERI_I2C1 25 -#define CLK_PERI_I2C2 26 -#define CLK_PERI_I2C3 27 -#define CLK_PERI_AUXADC 28 -#define CLK_PERI_SPI0 39 -#define CLK_PERI_ETH 30 -#define CLK_PERI_USB0_MCU 31 - -#define CLK_PERI_USB1_MCU 32 -#define CLK_PERI_USB_SLV 33 -#define CLK_PERI_GCPU 34 -#define CLK_PERI_NFI_ECC 35 -#define CLK_PERI_NFI_PAD 36 -#define CLK_PERI_FLASH 37 -#define CLK_PERI_HOST89_INT 38 -#define CLK_PERI_HOST89_SPI 39 -#define CLK_PERI_HOST89_DVD 40 -#define CLK_PERI_SPI1 41 -#define CLK_PERI_SPI2 42 -#define CLK_PERI_FCI 43 -#define CLK_PERI_NR 44 + +#define CLK_PERI_NFI 1 +#define CLK_PERI_THERM 2 +#define CLK_PERI_PWM1 3 +#define CLK_PERI_PWM2 4 +#define CLK_PERI_PWM3 5 +#define CLK_PERI_PWM4 6 +#define CLK_PERI_PWM5 7 +#define CLK_PERI_PWM6 8 +#define CLK_PERI_PWM7 9 +#define CLK_PERI_PWM 10 +#define CLK_PERI_USB0 11 +#define CLK_PERI_USB1 12 +#define CLK_PERI_AP_DMA 13 +#define CLK_PERI_MSDC30_0 14 +#define CLK_PERI_MSDC30_1 15 +#define CLK_PERI_MSDC30_2 16 +#define CLK_PERI_MSDC30_3 17 +#define CLK_PERI_MSDC50_3 18 +#define CLK_PERI_NLI 19 +#define CLK_PERI_UART0 20 +#define CLK_PERI_UART1 21 +#define CLK_PERI_UART2 22 +#define CLK_PERI_UART3 23 +#define CLK_PERI_BTIF 24 +#define CLK_PERI_I2C0 25 +#define CLK_PERI_I2C1 26 +#define CLK_PERI_I2C2 27 +#define CLK_PERI_I2C3 28 +#define CLK_PERI_AUXADC 29 +#define CLK_PERI_SPI0 30 +#define CLK_PERI_ETH 31 +#define CLK_PERI_USB0_MCU 32 + +#define CLK_PERI_USB1_MCU 33 +#define CLK_PERI_USB_SLV 34 +#define CLK_PERI_GCPU 35 +#define CLK_PERI_NFI_ECC 36 +#define CLK_PERI_NFI_PAD 37 +#define CLK_PERI_FLASH 38 +#define CLK_PERI_HOST89_INT 39 +#define CLK_PERI_HOST89_SPI 40 +#define CLK_PERI_HOST89_DVD 41 +#define CLK_PERI_SPI1 42 +#define CLK_PERI_SPI2 43 +#define CLK_PERI_FCI 44 + +#define CLK_PERI_UART0_SEL 45 +#define CLK_PERI_UART1_SEL 46 +#define CLK_PERI_UART2_SEL 47 +#define CLK_PERI_UART3_SEL 48 +#define CLK_PERI_NR 49 /* AUDIO */ -#define CLK_AUD_AFE 0 -#define CLK_AUD_LRCK_DETECT 1 -#define CLK_AUD_I2S 2 -#define CLK_AUD_APLL_TUNER 3 -#define CLK_AUD_HDMI 4 -#define CLK_AUD_SPDF 5 -#define CLK_AUD_SPDF2 6 -#define CLK_AUD_APLL 7 -#define CLK_AUD_TML 8 -#define CLK_AUD_AHB_IDLE_EXT 9 -#define CLK_AUD_AHB_IDLE_INT 10 - -#define CLK_AUD_I2SIN1 11 -#define CLK_AUD_I2SIN2 12 -#define CLK_AUD_I2SIN3 13 -#define CLK_AUD_I2SIN4 14 -#define CLK_AUD_I2SIN5 15 -#define CLK_AUD_I2SIN6 16 -#define CLK_AUD_I2SO1 17 -#define CLK_AUD_I2SO2 18 -#define CLK_AUD_I2SO3 19 -#define CLK_AUD_I2SO4 20 -#define CLK_AUD_I2SO5 21 -#define CLK_AUD_I2SO6 22 -#define CLK_AUD_ASRCI1 23 -#define CLK_AUD_ASRCI2 24 -#define CLK_AUD_ASRCO1 25 -#define CLK_AUD_ASRCO2 26 -#define CLK_AUD_ASRC11 27 -#define CLK_AUD_ASRC12 28 -#define CLK_AUD_HDMIRX 29 -#define CLK_AUD_INTDIR 30 -#define CLK_AUD_A1SYS 31 -#define CLK_AUD_A2SYS 32 -#define CLK_AUD_AFE_CONN 33 -#define CLK_AUD_AFE_PCMIF 34 -#define CLK_AUD_AFE_MRGIF 35 - -#define CLK_AUD_MMIF_UL1 36 -#define CLK_AUD_MMIF_UL2 37 -#define CLK_AUD_MMIF_UL3 38 -#define CLK_AUD_MMIF_UL4 39 -#define CLK_AUD_MMIF_UL5 40 -#define CLK_AUD_MMIF_UL6 41 -#define CLK_AUD_MMIF_DL1 42 -#define CLK_AUD_MMIF_DL2 43 -#define CLK_AUD_MMIF_DL3 44 -#define CLK_AUD_MMIF_DL4 45 -#define CLK_AUD_MMIF_DL5 46 -#define CLK_AUD_MMIF_DL6 47 -#define CLK_AUD_MMIF_DLMCH 48 -#define CLK_AUD_MMIF_ARB1 49 -#define CLK_AUD_MMIF_AWB1 50 -#define CLK_AUD_MMIF_AWB2 51 -#define CLK_AUD_MMIF_DAI 52 - -#define CLK_AUD_DMIC1 53 -#define CLK_AUD_DMIC2 54 -#define CLK_AUD_ASRCI3 55 -#define CLK_AUD_ASRCI4 56 -#define CLK_AUD_ASRCI5 57 -#define CLK_AUD_ASRCI6 58 -#define CLK_AUD_ASRCO3 59 -#define CLK_AUD_ASRCO4 60 -#define CLK_AUD_ASRCO5 61 -#define CLK_AUD_ASRCO6 62 -#define CLK_AUD_MEM_ASRC1 63 -#define CLK_AUD_MEM_ASRC2 64 -#define CLK_AUD_MEM_ASRC3 65 -#define CLK_AUD_MEM_ASRC4 66 -#define CLK_AUD_MEM_ASRC5 67 -#define CLK_AUD_DSD_ENC 68 -#define CLK_AUD_ASRC_BRG 60 -#define CLK_AUD_NR 70 + +#define CLK_AUD_AFE 1 +#define CLK_AUD_LRCK_DETECT 2 +#define CLK_AUD_I2S 3 +#define CLK_AUD_APLL_TUNER 4 +#define CLK_AUD_HDMI 5 +#define CLK_AUD_SPDF 6 +#define CLK_AUD_SPDF2 7 +#define CLK_AUD_APLL 8 +#define CLK_AUD_TML 9 +#define CLK_AUD_AHB_IDLE_EXT 10 +#define CLK_AUD_AHB_IDLE_INT 11 + +#define CLK_AUD_I2SIN1 12 +#define CLK_AUD_I2SIN2 13 +#define CLK_AUD_I2SIN3 14 +#define CLK_AUD_I2SIN4 15 +#define CLK_AUD_I2SIN5 16 +#define CLK_AUD_I2SIN6 17 +#define CLK_AUD_I2SO1 18 +#define CLK_AUD_I2SO2 19 +#define CLK_AUD_I2SO3 20 +#define CLK_AUD_I2SO4 21 +#define CLK_AUD_I2SO5 22 +#define CLK_AUD_I2SO6 23 +#define CLK_AUD_ASRCI1 24 +#define CLK_AUD_ASRCI2 25 +#define CLK_AUD_ASRCO1 26 +#define CLK_AUD_ASRCO2 27 +#define CLK_AUD_ASRC11 28 +#define CLK_AUD_ASRC12 29 +#define CLK_AUD_HDMIRX 30 +#define CLK_AUD_INTDIR 31 +#define CLK_AUD_A1SYS 32 +#define CLK_AUD_A2SYS 33 +#define CLK_AUD_AFE_CONN 34 +#define CLK_AUD_AFE_PCMIF 35 +#define CLK_AUD_AFE_MRGIF 36 + +#define CLK_AUD_MMIF_UL1 37 +#define CLK_AUD_MMIF_UL2 38 +#define CLK_AUD_MMIF_UL3 39 +#define CLK_AUD_MMIF_UL4 40 +#define CLK_AUD_MMIF_UL5 41 +#define CLK_AUD_MMIF_UL6 42 +#define CLK_AUD_MMIF_DL1 43 +#define CLK_AUD_MMIF_DL2 44 +#define CLK_AUD_MMIF_DL3 45 +#define CLK_AUD_MMIF_DL4 46 +#define CLK_AUD_MMIF_DL5 47 +#define CLK_AUD_MMIF_DL6 48 +#define CLK_AUD_MMIF_DLMCH 49 +#define CLK_AUD_MMIF_ARB1 50 +#define CLK_AUD_MMIF_AWB1 51 +#define CLK_AUD_MMIF_AWB2 52 +#define CLK_AUD_MMIF_DAI 53 + +#define CLK_AUD_DMIC1 54 +#define CLK_AUD_DMIC2 55 +#define CLK_AUD_ASRCI3 56 +#define CLK_AUD_ASRCI4 57 +#define CLK_AUD_ASRCI5 58 +#define CLK_AUD_ASRCI6 59 +#define CLK_AUD_ASRCO3 60 +#define CLK_AUD_ASRCO4 61 +#define CLK_AUD_ASRCO5 62 +#define CLK_AUD_ASRCO6 63 +#define CLK_AUD_MEM_ASRC1 64 +#define CLK_AUD_MEM_ASRC2 65 +#define CLK_AUD_MEM_ASRC3 66 +#define CLK_AUD_MEM_ASRC4 67 +#define CLK_AUD_MEM_ASRC5 68 +#define CLK_AUD_DSD_ENC 69 +#define CLK_AUD_ASRC_BRG 70 +#define CLK_AUD_NR 71 /* MMSYS */ -#define CLK_MM_SMI_COMMON 0 -#define CLK_MM_SMI_LARB0 1 -#define CLK_MM_CMDQ 2 -#define CLK_MM_MUTEX 3 -#define CLK_MM_DISP_COLOR 4 -#define CLK_MM_DISP_BLS 5 -#define CLK_MM_DISP_WDMA 6 -#define CLK_MM_DISP_RDMA 7 -#define CLK_MM_DISP_OVL 8 -#define CLK_MM_MDP_TDSHP 9 -#define CLK_MM_MDP_WROT 10 -#define CLK_MM_MDP_WDMA 11 -#define CLK_MM_MDP_RSZ1 12 -#define CLK_MM_MDP_RSZ0 13 -#define CLK_MM_MDP_RDMA 14 -#define CLK_MM_MDP_BLS_26M 15 -#define CLK_MM_CAM_MDP 16 -#define CLK_MM_FAKE_ENG 17 -#define CLK_MM_MUTEX_32K 18 -#define CLK_MM_DISP_RDMA1 19 -#define CLK_MM_DISP_UFOE 20 - -#define CLK_MM_DSI_ENGINE 21 -#define CLK_MM_DSI_DIG 22 -#define CLK_MM_DPI_DIGL 23 -#define CLK_MM_DPI_ENGINE 24 -#define CLK_MM_DPI1_DIGL 25 -#define CLK_MM_DPI1_ENGINE 26 -#define CLK_MM_TVE_OUTPUT 27 -#define CLK_MM_TVE_INPUT 28 -#define CLK_MM_HDMI_PIXEL 29 -#define CLK_MM_HDMI_PLL 30 -#define CLK_MM_HDMI_AUDIO 31 -#define CLK_MM_HDMI_SPDIF 32 -#define CLK_MM_TVE_FMM 33 -#define CLK_MM_NR 34 + +#define CLK_MM_SMI_COMMON 1 +#define CLK_MM_SMI_LARB0 2 +#define CLK_MM_CMDQ 3 +#define CLK_MM_MUTEX 4 +#define CLK_MM_DISP_COLOR 5 +#define CLK_MM_DISP_BLS 6 +#define CLK_MM_DISP_WDMA 7 +#define CLK_MM_DISP_RDMA 8 +#define CLK_MM_DISP_OVL 9 +#define CLK_MM_MDP_TDSHP 10 +#define CLK_MM_MDP_WROT 11 +#define CLK_MM_MDP_WDMA 12 +#define CLK_MM_MDP_RSZ1 13 +#define CLK_MM_MDP_RSZ0 14 +#define CLK_MM_MDP_RDMA 15 +#define CLK_MM_MDP_BLS_26M 16 +#define CLK_MM_CAM_MDP 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_MUTEX_32K 19 +#define CLK_MM_DISP_RDMA1 20 +#define CLK_MM_DISP_UFOE 21 + +#define CLK_MM_DSI_ENGINE 22 +#define CLK_MM_DSI_DIG 23 +#define CLK_MM_DPI_DIGL 24 +#define CLK_MM_DPI_ENGINE 25 +#define CLK_MM_DPI1_DIGL 26 +#define CLK_MM_DPI1_ENGINE 27 +#define CLK_MM_TVE_OUTPUT 28 +#define CLK_MM_TVE_INPUT 29 +#define CLK_MM_HDMI_PIXEL 30 +#define CLK_MM_HDMI_PLL 31 +#define CLK_MM_HDMI_AUDIO 32 +#define CLK_MM_HDMI_SPDIF 33 +#define CLK_MM_TVE_FMM 34 +#define CLK_MM_NR 35 /* IMGSYS */ -#define CLK_IMG_SMI_COMM 0 -#define CLK_IMG_RESZ 1 -#define CLK_IMG_JPGDEC_SMI 2 -#define CLK_IMG_JPGDEC 3 -#define CLK_IMG_VENC_LT 4 -#define CLK_IMG_VENC 5 -#define CLK_IMG_NR 6 + +#define CLK_IMG_SMI_COMM 1 +#define CLK_IMG_RESZ 2 +#define CLK_IMG_JPGDEC_SMI 3 +#define CLK_IMG_JPGDEC 4 +#define CLK_IMG_VENC_LT 5 +#define CLK_IMG_VENC 6 +#define CLK_IMG_NR 7 /* VDEC */ -#define CLK_VDEC_CKGEN 0 -#define CLK_VDEC_LARB 1 -#define CLK_VDEC_NR 2 + +#define CLK_VDEC_CKGEN 1 +#define CLK_VDEC_LARB 2 +#define CLK_VDEC_NR 3 /* HIFSYS */ -#define CLK_HIFSYS_USB0PHY 0 -#define CLK_HIFSYS_USB1PHY 1 -#define CLK_HIFSYS_PCIE0 2 -#define CLK_HIFSYS_PCIE1 3 -#define CLK_HIFSYS_PCIE2 4 -#define CLK_HIFSYS_NR 5 + +#define CLK_HIFSYS_USB0PHY 1 +#define CLK_HIFSYS_USB1PHY 2 +#define CLK_HIFSYS_PCIE0 3 +#define CLK_HIFSYS_PCIE1 4 +#define CLK_HIFSYS_PCIE2 5 +#define CLK_HIFSYS_NR 6 /* ETHSYS */ -#define CLK_ETHSYS_HSDMA 0 -#define CLK_ETHSYS_ESW 1 -#define CLK_ETHSYS_GP2 2 -#define CLK_ETHSYS_GP1 3 -#define CLK_ETHSYS_PCM 4 -#define CLK_ETHSYS_GDMA 5 -#define CLK_ETHSYS_I2S 6 -#define CLK_ETHSYS_CRYPTO 7 -#define CLK_ETHSYS_NR 8 +#define CLK_ETHSYS_HSDMA 1 +#define CLK_ETHSYS_ESW 2 +#define CLK_ETHSYS_GP2 3 +#define CLK_ETHSYS_GP1 4 +#define CLK_ETHSYS_PCM 5 +#define CLK_ETHSYS_GDMA 6 +#define CLK_ETHSYS_I2S 7 +#define CLK_ETHSYS_CRYPTO 8 +#define CLK_ETHSYS_NR 9 /* G3DSYS */ -#define CLK_G3DSYS_CORE 0 -#define CLK_G3DSYS_NR 1 +#define CLK_G3DSYS_CORE 1 +#define CLK_G3DSYS_NR 2 + +/* BDP */ + +#define CLK_BDP_BRG_BA 1 +#define CLK_BDP_BRG_DRAM 2 +#define CLK_BDP_LARB_DRAM 3 +#define CLK_BDP_WR_VDI_PXL 4 +#define CLK_BDP_WR_VDI_DRAM 5 +#define CLK_BDP_WR_B 6 +#define CLK_BDP_DGI_IN 7 +#define CLK_BDP_DGI_OUT 8 +#define CLK_BDP_FMT_MAST_27 9 +#define CLK_BDP_FMT_B 10 +#define CLK_BDP_OSD_B 11 +#define CLK_BDP_OSD_DRAM 12 +#define CLK_BDP_OSD_AGENT 13 +#define CLK_BDP_OSD_PXL 14 +#define CLK_BDP_RLE_B 15 +#define CLK_BDP_RLE_AGENT 16 +#define CLK_BDP_RLE_DRAM 17 +#define CLK_BDP_F27M 18 +#define CLK_BDP_F27M_VDOUT 19 +#define CLK_BDP_F27_74_74 20 +#define CLK_BDP_F2FS 21 +#define CLK_BDP_F2FS74_148 22 +#define CLK_BDP_FB 23 +#define CLK_BDP_VDO_DRAM 24 +#define CLK_BDP_VDO_2FS 25 +#define CLK_BDP_VDO_B 26 +#define CLK_BDP_WR_DI_PXL 27 +#define CLK_BDP_WR_DI_DRAM 28 +#define CLK_BDP_WR_DI_B 29 +#define CLK_BDP_NR_PXL 30 +#define CLK_BDP_NR_DRAM 31 +#define CLK_BDP_NR_B 32 + +#define CLK_BDP_RX_F 33 +#define CLK_BDP_RX_X 34 +#define CLK_BDP_RXPDT 35 +#define CLK_BDP_RX_CSCL_N 36 +#define CLK_BDP_RX_CSCL 37 +#define CLK_BDP_RX_DDCSCL_N 38 +#define CLK_BDP_RX_DDCSCL 39 +#define CLK_BDP_RX_VCO 40 +#define CLK_BDP_RX_DP 41 +#define CLK_BDP_RX_P 42 +#define CLK_BDP_RX_M 43 +#define CLK_BDP_RX_PLL 44 +#define CLK_BDP_BRG_RT_B 45 +#define CLK_BDP_BRG_RT_DRAM 46 +#define CLK_BDP_LARBRT_DRAM 47 +#define CLK_BDP_TMDS_SYN 48 +#define CLK_BDP_HDMI_MON 49 +#define CLK_BDP_NR 50 #endif /* _DT_BINDINGS_CLK_MT2701_H */ diff --git a/include/dt-bindings/clock/mt7981-clk.h b/include/dt-bindings/clock/mt7981-clk.h index e24c759e499..52325916015 100644 --- a/include/dt-bindings/clock/mt7981-clk.h +++ b/include/dt-bindings/clock/mt7981-clk.h @@ -8,260 +8,219 @@ #ifndef _DT_BINDINGS_CLK_MT7981_H #define _DT_BINDINGS_CLK_MT7981_H -/* INFRACFG */ - -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_UART 1 -#define CK_INFRA_ISPI0 2 -#define CK_INFRA_I2C 3 -#define CK_INFRA_ISPI1 4 -#define CK_INFRA_PWM 5 -#define CK_INFRA_66M_MCK 6 -#define CK_INFRA_CK_F32K 7 -#define CK_INFRA_PCIE_CK 8 -#define CK_INFRA_PWM_BCK 9 -#define CK_INFRA_PWM_CK1 10 -#define CK_INFRA_PWM_CK2 11 -#define CK_INFRA_133M_HCK 12 -#define CK_INFRA_66M_PHCK 13 -#define CK_INFRA_FAUD_L_CK 14 -#define CK_INFRA_FAUD_AUD_CK 15 -#define CK_INFRA_FAUD_EG2_CK 16 -#define CK_INFRA_I2CS_CK 17 -#define CK_INFRA_MUX_UART0 18 -#define CK_INFRA_MUX_UART1 19 -#define CK_INFRA_MUX_UART2 20 -#define CK_INFRA_NFI_CK 21 -#define CK_INFRA_SPINFI_CK 22 -#define CK_INFRA_MUX_SPI0 23 -#define CK_INFRA_MUX_SPI1 24 -#define CK_INFRA_MUX_SPI2 25 -#define CK_INFRA_RTC_32K 26 -#define CK_INFRA_FMSDC_CK 27 -#define CK_INFRA_FMSDC_HCK_CK 28 -#define CK_INFRA_PERI_133M 29 -#define CK_INFRA_133M_PHCK 30 -#define CK_INFRA_USB_SYS_CK 31 -#define CK_INFRA_USB_CK 32 -#define CK_INFRA_USB_XHCI_CK 33 -#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -#define CK_INFRA_F26M_CK0 35 -#define CK_INFRA_133M_MCK 36 -#define CLK_INFRA_NR_CLK 37 - /* TOPCKGEN */ -#define CK_TOP_CB_CKSQ_40M 0 -#define CK_TOP_CB_M_416M 1 -#define CK_TOP_CB_M_D2 2 -#define CK_TOP_CB_M_D3 3 -#define CK_TOP_M_D3_D2 4 -#define CK_TOP_CB_M_D4 5 -#define CK_TOP_CB_M_D8 6 -#define CK_TOP_M_D8_D2 7 -#define CK_TOP_CB_MM_720M 8 -#define CK_TOP_CB_MM_D2 9 -#define CK_TOP_CB_MM_D3 10 -#define CK_TOP_CB_MM_D3_D5 11 -#define CK_TOP_CB_MM_D4 12 -#define CK_TOP_CB_MM_D6 13 -#define CK_TOP_MM_D6_D2 14 -#define CK_TOP_CB_MM_D8 15 -#define CK_TOP_CB_APLL2_196M 16 -#define CK_TOP_APLL2_D2 17 -#define CK_TOP_APLL2_D4 18 -#define CK_TOP_NET1_2500M 19 -#define CK_TOP_CB_NET1_D4 20 -#define CK_TOP_CB_NET1_D5 21 -#define CK_TOP_NET1_D5_D2 22 -#define CK_TOP_NET1_D5_D4 23 -#define CK_TOP_CB_NET1_D8 24 -#define CK_TOP_NET1_D8_D2 25 -#define CK_TOP_NET1_D8_D4 26 -#define CK_TOP_CB_NET2_800M 27 -#define CK_TOP_CB_NET2_D2 28 -#define CK_TOP_CB_NET2_D4 29 -#define CK_TOP_NET2_D4_D2 30 -#define CK_TOP_NET2_D4_D4 31 -#define CK_TOP_CB_NET2_D6 32 -#define CK_TOP_CB_WEDMCU_208M 33 -#define CK_TOP_CB_SGM_325M 34 -#define CK_TOP_CKSQ_40M_D2 35 -#define CK_TOP_CB_RTC_32K 36 -#define CK_TOP_CB_RTC_32P7K 37 -#define CK_TOP_USB_TX250M 38 -#define CK_TOP_FAUD 39 -#define CK_TOP_NFI1X 40 -#define CK_TOP_USB_EQ_RX250M 41 -#define CK_TOP_USB_CDR_CK 42 -#define CK_TOP_USB_LN0_CK 43 -#define CK_TOP_SPINFI_BCK 44 -#define CK_TOP_SPI 45 -#define CK_TOP_SPIM_MST 46 -#define CK_TOP_UART_BCK 47 -#define CK_TOP_PWM_BCK 48 -#define CK_TOP_I2C_BCK 49 -#define CK_TOP_PEXTP_TL 50 -#define CK_TOP_EMMC_208M 51 -#define CK_TOP_EMMC_400M 52 -#define CK_TOP_DRAMC_REF 53 -#define CK_TOP_DRAMC_MD32 54 -#define CK_TOP_SYSAXI 55 -#define CK_TOP_SYSAPB 56 -#define CK_TOP_ARM_DB_MAIN 57 -#define CK_TOP_AP2CNN_HOST 58 -#define CK_TOP_NETSYS 59 -#define CK_TOP_NETSYS_500M 60 -#define CK_TOP_NETSYS_WED_MCU 61 -#define CK_TOP_NETSYS_2X 62 -#define CK_TOP_SGM_325M 63 -#define CK_TOP_SGM_REG 64 -#define CK_TOP_F26M 65 -#define CK_TOP_EIP97B 66 -#define CK_TOP_USB3_PHY 67 -#define CK_TOP_AUD 68 -#define CK_TOP_A1SYS 69 -#define CK_TOP_AUD_L 70 -#define CK_TOP_A_TUNER 71 -#define CK_TOP_U2U3_REF 72 -#define CK_TOP_U2U3_SYS 73 -#define CK_TOP_U2U3_XHCI 74 -#define CK_TOP_USB_FRMCNT 75 -#define CK_TOP_NFI1X_SEL 76 -#define CK_TOP_SPINFI_SEL 77 -#define CK_TOP_SPI_SEL 78 -#define CK_TOP_SPIM_MST_SEL 79 -#define CK_TOP_UART_SEL 80 -#define CK_TOP_PWM_SEL 81 -#define CK_TOP_I2C_SEL 82 -#define CK_TOP_PEXTP_TL_SEL 83 -#define CK_TOP_EMMC_208M_SEL 84 -#define CK_TOP_EMMC_400M_SEL 85 -#define CK_TOP_F26M_SEL 86 -#define CK_TOP_DRAMC_SEL 87 -#define CK_TOP_DRAMC_MD32_SEL 88 -#define CK_TOP_SYSAXI_SEL 89 -#define CK_TOP_SYSAPB_SEL 90 -#define CK_TOP_ARM_DB_MAIN_SEL 91 -#define CK_TOP_AP2CNN_HOST_SEL 92 -#define CK_TOP_NETSYS_SEL 93 -#define CK_TOP_NETSYS_500M_SEL 94 -#define CK_TOP_NETSYS_MCU_SEL 95 -#define CK_TOP_NETSYS_2X_SEL 96 -#define CK_TOP_SGM_325M_SEL 97 -#define CK_TOP_SGM_REG_SEL 98 -#define CK_TOP_EIP97B_SEL 99 -#define CK_TOP_USB3_PHY_SEL 100 -#define CK_TOP_AUD_SEL 101 -#define CK_TOP_A1SYS_SEL 102 -#define CK_TOP_AUD_L_SEL 103 -#define CK_TOP_A_TUNER_SEL 104 -#define CK_TOP_U2U3_SEL 105 -#define CK_TOP_U2U3_SYS_SEL 106 -#define CK_TOP_U2U3_XHCI_SEL 107 -#define CK_TOP_USB_FRMCNT_SEL 108 -#define CLK_TOP_NR_CLK 109 +#define CLK_TOP_CB_CKSQ_40M 0 +#define CLK_TOP_CB_M_416M 1 +#define CLK_TOP_CB_M_D2 2 +#define CLK_TOP_CB_M_D3 3 +#define CLK_TOP_M_D3_D2 4 +#define CLK_TOP_CB_M_D4 5 +#define CLK_TOP_CB_M_D8 6 +#define CLK_TOP_M_D8_D2 7 +#define CLK_TOP_CB_MM_720M 8 +#define CLK_TOP_CB_MM_D2 9 +#define CLK_TOP_CB_MM_D3 10 +#define CLK_TOP_CB_MM_D3_D5 11 +#define CLK_TOP_CB_MM_D4 12 +#define CLK_TOP_CB_MM_D6 13 +#define CLK_TOP_MM_D6_D2 14 +#define CLK_TOP_CB_MM_D8 15 +#define CLK_TOP_CB_APLL2_196M 16 +#define CLK_TOP_APLL2_D2 17 +#define CLK_TOP_APLL2_D4 18 +#define CLK_TOP_NET1_2500M 19 +#define CLK_TOP_CB_NET1_D4 20 +#define CLK_TOP_CB_NET1_D5 21 +#define CLK_TOP_NET1_D5_D2 22 +#define CLK_TOP_NET1_D5_D4 23 +#define CLK_TOP_CB_NET1_D8 24 +#define CLK_TOP_NET1_D8_D2 25 +#define CLK_TOP_NET1_D8_D4 26 +#define CLK_TOP_CB_NET2_800M 27 +#define CLK_TOP_CB_NET2_D2 28 +#define CLK_TOP_CB_NET2_D4 29 +#define CLK_TOP_NET2_D4_D2 30 +#define CLK_TOP_NET2_D4_D4 31 +#define CLK_TOP_CB_NET2_D6 32 +#define CLK_TOP_CB_WEDMCU_208M 33 +#define CLK_TOP_CB_SGM_325M 34 +#define CLK_TOP_CKSQ_40M_D2 35 +#define CLK_TOP_CB_RTC_32K 36 +#define CLK_TOP_CB_RTC_32P7K 37 +#define CLK_TOP_USB_TX250M 38 +#define CLK_TOP_FAUD 39 +#define CLK_TOP_NFI1X 40 +#define CLK_TOP_USB_EQ_RX250M 41 +#define CLK_TOP_USB_CDR_CK 42 +#define CLK_TOP_USB_LN0_CK 43 +#define CLK_TOP_SPINFI_BCK 44 +#define CLK_TOP_SPI 45 +#define CLK_TOP_SPIM_MST 46 +#define CLK_TOP_UART_BCK 47 +#define CLK_TOP_PWM_BCK 48 +#define CLK_TOP_I2C_BCK 49 +#define CLK_TOP_PEXTP_TL 50 +#define CLK_TOP_EMMC_208M 51 +#define CLK_TOP_EMMC_400M 52 +#define CLK_TOP_DRAMC_REF 53 +#define CLK_TOP_DRAMC_MD32 54 +#define CLK_TOP_SYSAXI 55 +#define CLK_TOP_SYSAPB 56 +#define CLK_TOP_ARM_DB_MAIN 57 +#define CLK_TOP_AP2CNN_HOST 58 +#define CLK_TOP_NETSYS 59 +#define CLK_TOP_NETSYS_500M 60 +#define CLK_TOP_NETSYS_WED_MCU 61 +#define CLK_TOP_NETSYS_2X 62 +#define CLK_TOP_SGM_325M 63 +#define CLK_TOP_SGM_REG 64 +#define CLK_TOP_F26M 65 +#define CLK_TOP_EIP97B 66 +#define CLK_TOP_USB3_PHY 67 +#define CLK_TOP_AUD 68 +#define CLK_TOP_A1SYS 69 +#define CLK_TOP_AUD_L 70 +#define CLK_TOP_A_TUNER 71 +#define CLK_TOP_U2U3_REF 72 +#define CLK_TOP_U2U3_SYS 73 +#define CLK_TOP_U2U3_XHCI 74 +#define CLK_TOP_USB_FRMCNT 75 +#define CLK_TOP_NFI1X_SEL 76 +#define CLK_TOP_SPINFI_SEL 77 +#define CLK_TOP_SPI_SEL 78 +#define CLK_TOP_SPIM_MST_SEL 79 +#define CLK_TOP_UART_SEL 80 +#define CLK_TOP_PWM_SEL 81 +#define CLK_TOP_I2C_SEL 82 +#define CLK_TOP_PEXTP_TL_SEL 83 +#define CLK_TOP_EMMC_208M_SEL 84 +#define CLK_TOP_EMMC_400M_SEL 85 +#define CLK_TOP_F26M_SEL 86 +#define CLK_TOP_DRAMC_SEL 87 +#define CLK_TOP_DRAMC_MD32_SEL 88 +#define CLK_TOP_SYSAXI_SEL 89 +#define CLK_TOP_SYSAPB_SEL 90 +#define CLK_TOP_ARM_DB_MAIN_SEL 91 +#define CLK_TOP_AP2CNN_HOST_SEL 92 +#define CLK_TOP_NETSYS_SEL 93 +#define CLK_TOP_NETSYS_500M_SEL 94 +#define CLK_TOP_NETSYS_MCU_SEL 95 +#define CLK_TOP_NETSYS_2X_SEL 96 +#define CLK_TOP_SGM_325M_SEL 97 +#define CLK_TOP_SGM_REG_SEL 98 +#define CLK_TOP_EIP97B_SEL 99 +#define CLK_TOP_USB3_PHY_SEL 100 +#define CLK_TOP_AUD_SEL 101 +#define CLK_TOP_A1SYS_SEL 102 +#define CLK_TOP_AUD_L_SEL 103 +#define CLK_TOP_A_TUNER_SEL 104 +#define CLK_TOP_U2U3_SEL 105 +#define CLK_TOP_U2U3_SYS_SEL 106 +#define CLK_TOP_U2U3_XHCI_SEL 107 +#define CLK_TOP_USB_FRMCNT_SEL 108 +#define CLK_TOP_AUD_I2S_M 109 +#define CLK_TOP_NR_CLK 110 -/* - * INFRACFG_AO - * clock muxes need to be append to infracfg domain, and clock gates - * need to be keep in infracgh_ao domain - */ -#define INFRACFG_AO_OFFSET 10 +/* INFRACFG */ -#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK) -#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET) -#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET) -#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET) -#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET) -#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET) -#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET) -#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET) -#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET) -#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET) -#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET) -#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET) -#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET) -#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET) -#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET) -#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET) -#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET) -#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET) -#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET) -#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET) +#define CLK_INFRA_66M_MCK 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_SPI2_SEL 6 +#define CLK_INFRA_PWM1_SEL 7 +#define CLK_INFRA_PWM2_SEL 8 +#define CLK_INFRA_PWM3_SEL 9 +#define CLK_INFRA_PWM_BSEL 10 +#define CLK_INFRA_PCIE_SEL 11 +#define CLK_INFRA_GPT_STA 12 +#define CLK_INFRA_PWM_HCK 13 +#define CLK_INFRA_PWM_STA 14 +#define CLK_INFRA_PWM1_CK 15 +#define CLK_INFRA_PWM2_CK 16 +#define CLK_INFRA_PWM3_CK 17 +#define CLK_INFRA_CQ_DMA_CK 18 +#define CLK_INFRA_AUD_BUS_CK 19 +#define CLK_INFRA_AUD_26M_CK 20 +#define CLK_INFRA_AUD_L_CK 21 +#define CLK_INFRA_AUD_AUD_CK 22 +#define CLK_INFRA_AUD_EG2_CK 23 +#define CLK_INFRA_DRAMC_26M_CK 24 +#define CLK_INFRA_DBG_CK 25 +#define CLK_INFRA_AP_DMA_CK 26 +#define CLK_INFRA_SEJ_CK 27 +#define CLK_INFRA_SEJ_13M_CK 28 +#define CLK_INFRA_THERM_CK 29 +#define CLK_INFRA_I2C0_CK 30 +#define CLK_INFRA_UART0_CK 31 +#define CLK_INFRA_UART1_CK 32 +#define CLK_INFRA_UART2_CK 33 +#define CLK_INFRA_SPI2_CK 34 +#define CLK_INFRA_SPI2_HCK_CK 35 +#define CLK_INFRA_NFI1_CK 36 +#define CLK_INFRA_SPINFI1_CK 37 +#define CLK_INFRA_NFI_HCK_CK 38 +#define CLK_INFRA_SPI0_CK 39 +#define CLK_INFRA_SPI1_CK 40 +#define CLK_INFRA_SPI0_HCK_CK 41 +#define CLK_INFRA_SPI1_HCK_CK 42 +#define CLK_INFRA_FRTC_CK 43 +#define CLK_INFRA_MSDC_CK 44 +#define CLK_INFRA_MSDC_HCK_CK 45 +#define CLK_INFRA_MSDC_133M_CK 46 +#define CLK_INFRA_MSDC_66M_CK 47 +#define CLK_INFRA_ADC_26M_CK 48 +#define CLK_INFRA_ADC_FRC_CK 49 +#define CLK_INFRA_FBIST2FPC_CK 50 +#define CLK_INFRA_I2C_MCK_CK 51 +#define CLK_INFRA_I2C_PCK_CK 52 +#define CLK_INFRA_IUSB_133_CK 53 +#define CLK_INFRA_IUSB_66M_CK 54 +#define CLK_INFRA_IUSB_SYS_CK 55 +#define CLK_INFRA_IUSB_CK 56 +#define CLK_INFRA_IPCIE_CK 57 +#define CLK_INFRA_IPCIE_PIPE_CK 58 +#define CLK_INFRA_IPCIER_CK 59 +#define CLK_INFRA_IPCIEB_CK 60 +#define CLK_INFRA_NR_CLK 61 /* APMIXEDSYS */ -#define CK_APMIXED_ARMPLL 0 -#define CK_APMIXED_NET2PLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_SGMPLL 3 -#define CK_APMIXED_WEDMCUPLL 4 -#define CK_APMIXED_NET1PLL 5 -#define CK_APMIXED_MPLL 6 -#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 -#define CK_SGM0_CK0_EN 2 -#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 #define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 -#define CK_SGM1_CK1_EN 2 -#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 #define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ -#define CK_ETH_FE_EN 0 -#define CK_ETH_GP2_EN 1 -#define CK_ETH_GP1_EN 2 -#define CK_ETH_WOCPU0_EN 3 +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU0_EN 3 #define CLK_ETH_NR_CLK 4 #endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/include/dt-bindings/clock/mt7986-clk.h b/include/dt-bindings/clock/mt7986-clk.h index 820f8631831..5da260386fd 100644 --- a/include/dt-bindings/clock/mt7986-clk.h +++ b/include/dt-bindings/clock/mt7986-clk.h @@ -8,240 +8,169 @@ #ifndef _DT_BINDINGS_CLK_MT7986_H #define _DT_BINDINGS_CLK_MT7986_H -/* INFRACFG */ - -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_UART 1 -#define CK_INFRA_ISPI0 2 -#define CK_INFRA_I2C 3 -#define CK_INFRA_ISPI1 4 -#define CK_INFRA_PWM 5 -#define CK_INFRA_66M_MCK 6 -#define CK_INFRA_CK_F32K 7 -#define CK_INFRA_PCIE_CK 8 -#define CK_INFRA_PWM_BCK 9 -#define CK_INFRA_PWM_CK1 10 -#define CK_INFRA_PWM_CK2 11 -#define CK_INFRA_133M_HCK 12 -#define CK_INFRA_EIP_CK 13 -#define CK_INFRA_66M_PHCK 14 -#define CK_INFRA_FAUD_L_CK 15 -#define CK_INFRA_FAUD_AUD_CK 17 -#define CK_INFRA_FAUD_EG2_CK 17 -#define CK_INFRA_I2CS_CK 18 -#define CK_INFRA_MUX_UART0 19 -#define CK_INFRA_MUX_UART1 20 -#define CK_INFRA_MUX_UART2 21 -#define CK_INFRA_NFI_CK 22 -#define CK_INFRA_SPINFI_CK 23 -#define CK_INFRA_MUX_SPI0 24 -#define CK_INFRA_MUX_SPI1 25 -#define CK_INFRA_RTC_32K 26 -#define CK_INFRA_FMSDC_CK 27 -#define CK_INFRA_FMSDC_HCK_CK 28 -#define CK_INFRA_PERI_133M 29 -#define CK_INFRA_133M_PHCK 30 -#define CK_INFRA_USB_SYS_CK 31 -#define CK_INFRA_USB_CK 32 -#define CK_INFRA_USB_XHCI_CK 33 -#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34 -#define CK_INFRA_F26M_CK0 35 -#define CK_INFRA_HD_133M 36 -#define CLK_INFRA_NR_CLK 37 - /* TOPCKGEN */ -#define CK_TOP_CB_CKSQ_40M 0 -#define CK_TOP_CB_M_416M 1 -#define CK_TOP_CB_M_D2 2 -#define CK_TOP_CB_M_D4 3 -#define CK_TOP_CB_M_D8 4 -#define CK_TOP_M_D8_D2 5 -#define CK_TOP_M_D3_D2 6 -#define CK_TOP_CB_MM_D2 7 -#define CK_TOP_CB_MM_D4 8 -#define CK_TOP_CB_MM_D8 9 -#define CK_TOP_MM_D8_D2 10 -#define CK_TOP_MM_D3_D8 11 -#define CK_TOP_CB_U2_PHYD_CK 12 -#define CK_TOP_CB_APLL2_196M 13 -#define CK_TOP_APLL2_D4 14 -#define CK_TOP_CB_NET1_D4 15 -#define CK_TOP_CB_NET1_D5 16 -#define CK_TOP_NET1_D5_D2 17 -#define CK_TOP_NET1_D5_D4 18 -#define CK_TOP_NET1_D8_D2 19 -#define CK_TOP_NET1_D8_D4 20 -#define CK_TOP_CB_NET2_800M 21 -#define CK_TOP_CB_NET2_D4 22 -#define CK_TOP_NET2_D4_D2 23 -#define CK_TOP_NET2_D3_D2 24 -#define CK_TOP_CB_WEDMCU_760M 25 -#define CK_TOP_WEDMCU_D5_D2 26 -#define CK_TOP_CB_SGM_325M 27 -#define CK_TOP_CB_CKSQ_40M_D2 28 -#define CK_TOP_CB_RTC_32K 29 -#define CK_TOP_CB_RTC_32P7K 30 -#define CK_TOP_NFI1X 31 -#define CK_TOP_USB_EQ_RX250M 32 -#define CK_TOP_USB_TX250M 33 -#define CK_TOP_USB_LN0_CK 34 -#define CK_TOP_USB_CDR_CK 35 -#define CK_TOP_SPINFI_BCK 36 -#define CK_TOP_I2C_BCK 37 -#define CK_TOP_PEXTP_TL 38 -#define CK_TOP_EMMC_250M 39 -#define CK_TOP_EMMC_416M 40 -#define CK_TOP_F_26M_ADC_CK 41 -#define CK_TOP_SYSAXI 42 -#define CK_TOP_NETSYS_WED_MCU 43 -#define CK_TOP_NETSYS_2X 44 -#define CK_TOP_SGM_325M 45 -#define CK_TOP_A1SYS 46 -#define CK_TOP_EIP_B 47 -#define CK_TOP_F26M 48 -#define CK_TOP_AUD_L 49 -#define CK_TOP_A_TUNER 50 -#define CK_TOP_U2U3_REF 51 -#define CK_TOP_U2U3_SYS 52 -#define CK_TOP_U2U3_XHCI 53 -#define CK_TOP_AP2CNN_HOST 54 -#define CK_TOP_NFI1X_SEL 55 -#define CK_TOP_SPINFI_SEL 56 -#define CK_TOP_SPI_SEL 57 -#define CK_TOP_SPIM_MST_SEL 58 -#define CK_TOP_UART_SEL 59 -#define CK_TOP_PWM_SEL 60 -#define CK_TOP_I2C_SEL 61 -#define CK_TOP_PEXTP_TL_SEL 62 -#define CK_TOP_EMMC_250M_SEL 63 -#define CK_TOP_EMMC_416M_SEL 64 -#define CK_TOP_F_26M_ADC_SEL 65 -#define CK_TOP_DRAMC_SEL 66 -#define CK_TOP_DRAMC_MD32_SEL 67 -#define CK_TOP_SYSAXI_SEL 68 -#define CK_TOP_SYSAPB_SEL 69 -#define CK_TOP_ARM_DB_MAIN_SEL 70 -#define CK_TOP_ARM_DB_JTSEL 71 -#define CK_TOP_NETSYS_SEL 72 -#define CK_TOP_NETSYS_500M_SEL 73 -#define CK_TOP_NETSYS_MCU_SEL 74 -#define CK_TOP_NETSYS_2X_SEL 75 -#define CK_TOP_SGM_325M_SEL 76 -#define CK_TOP_SGM_REG_SEL 77 -#define CK_TOP_A1SYS_SEL 78 -#define CK_TOP_CONN_MCUSYS_SEL 79 -#define CK_TOP_EIP_B_SEL 80 -#define CK_TOP_PCIE_PHY_SEL 81 -#define CK_TOP_USB3_PHY_SEL 82 -#define CK_TOP_F26M_SEL 83 -#define CK_TOP_AUD_L_SEL 84 -#define CK_TOP_A_TUNER_SEL 85 -#define CK_TOP_U2U3_SEL 86 -#define CK_TOP_U2U3_SYS_SEL 87 -#define CK_TOP_U2U3_XHCI_SEL 88 -#define CK_TOP_DA_U2_REFSEL 89 -#define CK_TOP_DA_U2_CK_1P_SEL 90 -#define CK_TOP_AP2CNN_HOST_SEL 91 -#define CLK_TOP_NR_CLK 92 +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +/* #define CLK_TOP_A_TUNER 4 */ +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D4 5 +#define CLK_TOP_MPLL_D8 6 +#define CLK_TOP_MPLL_D8_D2 7 +#define CLK_TOP_MPLL_D3_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D4 10 +#define CLK_TOP_MMPLL_D8 11 +#define CLK_TOP_MMPLL_D8_D2 12 +#define CLK_TOP_MMPLL_D3_D8 13 +#define CLK_TOP_MMPLL_U2PHYD 14 +#define CLK_TOP_APLL2_D4 15 +#define CLK_TOP_NET1PLL_D4 16 +#define CLK_TOP_NET1PLL_D5 17 +#define CLK_TOP_NET1PLL_D5_D2 18 +#define CLK_TOP_NET1PLL_D5_D4 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET2PLL_D4 22 +#define CLK_TOP_NET2PLL_D4_D2 23 +#define CLK_TOP_NET2PLL_D3_D2 24 +#define CLK_TOP_WEDMCUPLL_D5_D2 25 +#define CLK_TOP_NFI1X_SEL 26 +#define CLK_TOP_SPINFI_SEL 27 +#define CLK_TOP_SPI_SEL 28 +#define CLK_TOP_SPIM_MST_SEL 29 +#define CLK_TOP_UART_SEL 30 +#define CLK_TOP_PWM_SEL 31 +#define CLK_TOP_I2C_SEL 32 +#define CLK_TOP_PEXTP_TL_SEL 33 +#define CLK_TOP_EMMC_250M_SEL 34 +#define CLK_TOP_EMMC_416M_SEL 35 +#define CLK_TOP_F_26M_ADC_SEL 36 +#define CLK_TOP_DRAMC_SEL 37 +#define CLK_TOP_DRAMC_MD32_SEL 38 +#define CLK_TOP_SYSAXI_SEL 39 +#define CLK_TOP_SYSAPB_SEL 40 +#define CLK_TOP_ARM_DB_MAIN_SEL 41 +#define CLK_TOP_ARM_DB_JTSEL 42 +#define CLK_TOP_NETSYS_SEL 43 +#define CLK_TOP_NETSYS_500M_SEL 44 +#define CLK_TOP_NETSYS_MCU_SEL 45 +#define CLK_TOP_NETSYS_2X_SEL 46 +#define CLK_TOP_SGM_325M_SEL 47 +#define CLK_TOP_SGM_REG_SEL 48 +#define CLK_TOP_A1SYS_SEL 49 +#define CLK_TOP_CONN_MCUSYS_SEL 50 +#define CLK_TOP_EIP_B_SEL 51 +#define CLK_TOP_PCIE_PHY_SEL 52 +#define CLK_TOP_USB3_PHY_SEL 53 +#define CLK_TOP_F26M_SEL 54 +#define CLK_TOP_AUD_L_SEL 55 +#define CLK_TOP_A_TUNER_SEL 56 +#define CLK_TOP_U2U3_SEL 57 +#define CLK_TOP_U2U3_SYS_SEL 58 +#define CLK_TOP_U2U3_XHCI_SEL 59 +#define CLK_TOP_DA_U2_REFSEL 60 +#define CLK_TOP_DA_U2_CK_1P_SEL 61 +#define CLK_TOP_AP2CNN_HOST_SEL 62 +#define CLK_TOP_NR_CLK 63 -/* - * INFRACFG_AO - * clock muxes need to be append to infracfg domain, and clock gates - * need to be keep in infracgh_ao domain - */ +/* INFRACFG */ -#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK) -#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK) -#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK) -#define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK) -#define CK_INFRA_GPT_STA 0 -#define CK_INFRA_PWM_HCK 1 -#define CK_INFRA_PWM_STA 2 -#define CK_INFRA_PWM1_CK 3 -#define CK_INFRA_PWM2_CK 4 -#define CK_INFRA_CQ_DMA_CK 5 -#define CK_INFRA_EIP97_CK 6 -#define CK_INFRA_AUD_BUS_CK 7 -#define CK_INFRA_AUD_26M_CK 8 -#define CK_INFRA_AUD_L_CK 9 -#define CK_INFRA_AUD_AUD_CK 10 -#define CK_INFRA_AUD_EG2_CK 11 -#define CK_INFRA_DRAMC_26M_CK 12 -#define CK_INFRA_DBG_CK 13 -#define CK_INFRA_AP_DMA_CK 14 -#define CK_INFRA_SEJ_CK 15 -#define CK_INFRA_SEJ_13M_CK 16 -#define CK_INFRA_THERM_CK 17 -#define CK_INFRA_I2CO_CK 18 -#define CK_INFRA_TRNG_CK 19 -#define CK_INFRA_UART0_CK 20 -#define CK_INFRA_UART1_CK 21 -#define CK_INFRA_UART2_CK 22 -#define CK_INFRA_NFI1_CK 23 -#define CK_INFRA_SPINFI1_CK 24 -#define CK_INFRA_NFI_HCK_CK 25 -#define CK_INFRA_SPI0_CK 26 -#define CK_INFRA_SPI1_CK 27 -#define CK_INFRA_SPI0_HCK_CK 28 -#define CK_INFRA_SPI1_HCK_CK 29 -#define CK_INFRA_FRTC_CK 30 -#define CK_INFRA_MSDC_CK 31 -#define CK_INFRA_MSDC_HCK_CK 32 -#define CK_INFRA_MSDC_133M_CK 33 -#define CK_INFRA_MSDC_66M_CK 34 -#define CK_INFRA_ADC_26M_CK 35 -#define CK_INFRA_ADC_FRC_CK 36 -#define CK_INFRA_FBIST2FPC_CK 37 -#define CK_INFRA_IUSB_133_CK 38 -#define CK_INFRA_IUSB_66M_CK 39 -#define CK_INFRA_IUSB_SYS_CK 40 -#define CK_INFRA_IUSB_CK 41 -#define CK_INFRA_IPCIE_CK 42 -#define CK_INFRA_IPCIER_CK 43 -#define CK_INFRA_IPCIEB_CK 44 -#define CLK_INFRA_AO_NR_CLK 45 +#define CLK_INFRA_SYSAXI_D2 0 +#define CLK_INFRA_UART0_SEL 1 +#define CLK_INFRA_UART1_SEL 2 +#define CLK_INFRA_UART2_SEL 3 +#define CLK_INFRA_SPI0_SEL 4 +#define CLK_INFRA_SPI1_SEL 5 +#define CLK_INFRA_PWM1_SEL 6 +#define CLK_INFRA_PWM2_SEL 7 +#define CLK_INFRA_PWM_BSEL 8 +#define CLK_INFRA_PCIE_SEL 9 +#define CLK_INFRA_GPT_STA 10 +#define CLK_INFRA_PWM_HCK 11 +#define CLK_INFRA_PWM_STA 12 +#define CLK_INFRA_PWM1_CK 13 +#define CLK_INFRA_PWM2_CK 14 +#define CLK_INFRA_CQ_DMA_CK 15 +#define CLK_INFRA_EIP97_CK 16 +#define CLK_INFRA_AUD_BUS_CK 17 +#define CLK_INFRA_AUD_26M_CK 18 +#define CLK_INFRA_AUD_L_CK 19 +#define CLK_INFRA_AUD_AUD_CK 20 +#define CLK_INFRA_AUD_EG2_CK 21 +#define CLK_INFRA_DRAMC_26M_CK 22 +#define CLK_INFRA_DBG_CK 23 +#define CLK_INFRA_AP_DMA_CK 24 +#define CLK_INFRA_SEJ_CK 25 +#define CLK_INFRA_SEJ_13M_CK 26 +#define CLK_INFRA_THERM_CK 27 +#define CLK_INFRA_I2C0_CK 28 +#define CLK_INFRA_UART0_CK 29 +#define CLK_INFRA_UART1_CK 30 +#define CLK_INFRA_UART2_CK 31 +#define CLK_INFRA_NFI1_CK 32 +#define CLK_INFRA_SPINFI1_CK 33 +#define CLK_INFRA_NFI_HCK_CK 34 +#define CLK_INFRA_SPI0_CK 35 +#define CLK_INFRA_SPI1_CK 36 +#define CLK_INFRA_SPI0_HCK_CK 37 +#define CLK_INFRA_SPI1_HCK_CK 38 +#define CLK_INFRA_FRTC_CK 39 +#define CLK_INFRA_MSDC_CK 40 +#define CLK_INFRA_MSDC_HCK_CK 41 +#define CLK_INFRA_MSDC_133M_CK 42 +#define CLK_INFRA_MSDC_66M_CK 43 +#define CLK_INFRA_ADC_26M_CK 44 +#define CLK_INFRA_ADC_FRC_CK 45 +#define CLK_INFRA_FBIST2FPC_CK 46 +#define CLK_INFRA_IUSB_133_CK 47 +#define CLK_INFRA_IUSB_66M_CK 48 +#define CLK_INFRA_IUSB_SYS_CK 49 +#define CLK_INFRA_IUSB_CK 50 +#define CLK_INFRA_IPCIE_CK 51 +#define CLK_INFRA_IPCIE_PIPE_CK 52 +#define CLK_INFRA_IPCIER_CK 53 +#define CLK_INFRA_IPCIEB_CK 54 +#define CLK_INFRA_TRNG_CK 55 +#define CLK_INFRA_AO_NR_CLK 46 /* APMIXEDSYS */ -#define CK_APMIXED_ARMPLL 0 -#define CK_APMIXED_NET2PLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_SGMPLL 3 -#define CK_APMIXED_WEDMCUPLL 4 -#define CK_APMIXED_NET1PLL 5 -#define CK_APMIXED_MPLL 6 -#define CK_APMIXED_APLL2 7 +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_NET2PLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_SGMPLL 3 +#define CLK_APMIXED_WEDMCUPLL 4 +#define CLK_APMIXED_NET1PLL 5 +#define CLK_APMIXED_MPLL 6 +#define CLK_APMIXED_APLL2 7 #define CLK_APMIXED_NR_CLK 8 /* SGMIISYS_0 */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 -#define CK_SGM0_CK0_EN 2 -#define CK_SGM0_CDR_CK0_EN 3 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGM0_CK0_EN 2 +#define CLK_SGM0_CDR_CK0_EN 3 #define CLK_SGMII0_NR_CLK 4 /* SGMIISYS_1 */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 -#define CK_SGM1_CK1_EN 2 -#define CK_SGM1_CDR_CK1_EN 3 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGM1_CK1_EN 2 +#define CLK_SGM1_CDR_CK1_EN 3 #define CLK_SGMII1_NR_CLK 4 /* ETHSYS */ -#define CK_ETH_FE_EN 0 -#define CK_ETH_GP2_EN 1 -#define CK_ETH_GP1_EN 2 -#define CK_ETH_WOCPU1_EN 3 -#define CK_ETH_WOCPU0_EN 4 +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_WOCPU1_EN 3 +#define CLK_ETH_WOCPU0_EN 4 #define CLK_ETH_NR_CLK 5 #endif diff --git a/include/dt-bindings/clock/mt7988-clk.h b/include/dt-bindings/clock/mt7988-clk.h index 5c21bf63119..e6e6978809d 100644 --- a/include/dt-bindings/clock/mt7988-clk.h +++ b/include/dt-bindings/clock/mt7988-clk.h @@ -8,342 +8,257 @@ #ifndef _DT_BINDINGS_CLK_MT7988_H #define _DT_BINDINGS_CLK_MT7988_H -/* INFRACFG */ -/* mtk_fixed_factor */ -#define CK_INFRA_CK_F26M 0 -#define CK_INFRA_PWM_O 1 -#define CK_INFRA_PCIE_OCC_P0 2 -#define CK_INFRA_PCIE_OCC_P1 3 -#define CK_INFRA_PCIE_OCC_P2 4 -#define CK_INFRA_PCIE_OCC_P3 5 -#define CK_INFRA_133M_HCK 6 -#define CK_INFRA_133M_PHCK 7 -#define CK_INFRA_66M_PHCK 8 -#define CK_INFRA_FAUD_L_O 9 -#define CK_INFRA_FAUD_AUD_O 10 -#define CK_INFRA_FAUD_EG2_O 11 -#define CK_INFRA_I2C_O 12 -#define CK_INFRA_UART_O0 13 -#define CK_INFRA_UART_O1 14 -#define CK_INFRA_UART_O2 15 -#define CK_INFRA_NFI_O 16 -#define CK_INFRA_SPINFI_O 17 -#define CK_INFRA_SPI0_O 18 -#define CK_INFRA_SPI1_O 19 -#define CK_INFRA_LB_MUX_FRTC 20 -#define CK_INFRA_FRTC 21 -#define CK_INFRA_FMSDC400_O 22 -#define CK_INFRA_FMSDC2_HCK_OCC 23 -#define CK_INFRA_PERI_133M 24 -#define CK_INFRA_USB_O 25 -#define CK_INFRA_USB_O_P1 26 -#define CK_INFRA_USB_FRMCNT_O 27 -#define CK_INFRA_USB_FRMCNT_O_P1 28 -#define CK_INFRA_USB_XHCI_O 29 -#define CK_INFRA_USB_XHCI_O_P1 30 -#define CK_INFRA_USB_PIPE_O 31 -#define CK_INFRA_USB_PIPE_O_P1 32 -#define CK_INFRA_USB_UTMI_O 33 -#define CK_INFRA_USB_UTMI_O_P1 34 -#define CK_INFRA_PCIE_PIPE_OCC_P0 35 -#define CK_INFRA_PCIE_PIPE_OCC_P1 36 -#define CK_INFRA_PCIE_PIPE_OCC_P2 37 -#define CK_INFRA_PCIE_PIPE_OCC_P3 38 -#define CK_INFRA_F26M_O0 39 -#define CK_INFRA_F26M_O1 40 -#define CK_INFRA_133M_MCK 41 -#define CK_INFRA_66M_MCK 42 -#define CK_INFRA_PERI_66M_O 43 -#define CK_INFRA_USB_SYS_O 44 -#define CK_INFRA_USB_SYS_O_P1 45 - /* INFRACFG_AO */ -#define GATE_OFFSET 65 /* mtk_mux */ -#define CK_INFRA_MUX_UART0_SEL 46 /* Linux CLK ID (0) */ -#define CK_INFRA_MUX_UART1_SEL 47 /* Linux CLK ID (1) */ -#define CK_INFRA_MUX_UART2_SEL 48 /* Linux CLK ID (2) */ -#define CK_INFRA_MUX_SPI0_SEL 49 /* Linux CLK ID (3) */ -#define CK_INFRA_MUX_SPI1_SEL 50 /* Linux CLK ID (4) */ -#define CK_INFRA_MUX_SPI2_SEL 51 /* Linux CLK ID (5) */ -#define CK_INFRA_PWM_SEL 52 /* Linux CLK ID (6) */ -#define CK_INFRA_PWM_CK1_SEL 53 /* Linux CLK ID (7) */ -#define CK_INFRA_PWM_CK2_SEL 54 /* Linux CLK ID (8) */ -#define CK_INFRA_PWM_CK3_SEL 55 /* Linux CLK ID (9) */ -#define CK_INFRA_PWM_CK4_SEL 56 /* Linux CLK ID (10) */ -#define CK_INFRA_PWM_CK5_SEL 57 /* Linux CLK ID (11) */ -#define CK_INFRA_PWM_CK6_SEL 58 /* Linux CLK ID (12) */ -#define CK_INFRA_PWM_CK7_SEL 59 /* Linux CLK ID (13) */ -#define CK_INFRA_PWM_CK8_SEL 60 /* Linux CLK ID (14) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 61 /* Linux CLK ID (15) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 62 /* Linux CLK ID (16) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 63 /* Linux CLK ID (17) */ -#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 64 /* Linux CLK ID (18) */ +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_SEL 5 +#define CLK_INFRA_PWM_SEL 6 +#define CLK_INFRA_PWM_CK1_SEL 7 +#define CLK_INFRA_PWM_CK2_SEL 8 +#define CLK_INFRA_PWM_CK3_SEL 9 +#define CLK_INFRA_PWM_CK4_SEL 10 +#define CLK_INFRA_PWM_CK5_SEL 11 +#define CLK_INFRA_PWM_CK6_SEL 12 +#define CLK_INFRA_PWM_CK7_SEL 13 +#define CLK_INFRA_PWM_CK8_SEL 14 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 + +/* INFRACFG */ /* mtk_gate */ -#define CK_INFRA_66M_GPT_BCK (65 - GATE_OFFSET) /* Linux CLK ID (19) */ -#define CK_INFRA_66M_PWM_HCK (66 - GATE_OFFSET) /* Linux CLK ID (20) */ -#define CK_INFRA_66M_PWM_BCK (67 - GATE_OFFSET) /* Linux CLK ID (21) */ -#define CK_INFRA_66M_PWM_CK1 (68 - GATE_OFFSET) /* Linux CLK ID (22) */ -#define CK_INFRA_66M_PWM_CK2 (69 - GATE_OFFSET) /* Linux CLK ID (23) */ -#define CK_INFRA_66M_PWM_CK3 (70 - GATE_OFFSET) /* Linux CLK ID (24) */ -#define CK_INFRA_66M_PWM_CK4 (71 - GATE_OFFSET) /* Linux CLK ID (25) */ -#define CK_INFRA_66M_PWM_CK5 (72 - GATE_OFFSET) /* Linux CLK ID (26) */ -#define CK_INFRA_66M_PWM_CK6 (73 - GATE_OFFSET) /* Linux CLK ID (27) */ -#define CK_INFRA_66M_PWM_CK7 (74 - GATE_OFFSET) /* Linux CLK ID (28) */ -#define CK_INFRA_66M_PWM_CK8 (75 - GATE_OFFSET) /* Linux CLK ID (29) */ -#define CK_INFRA_133M_CQDMA_BCK (76 - GATE_OFFSET) /* Linux CLK ID (30) */ -#define CK_INFRA_66M_AUD_SLV_BCK (77 - GATE_OFFSET) /* Linux CLK ID (31) */ -#define CK_INFRA_AUD_26M (78 - GATE_OFFSET) /* Linux CLK ID (32) */ -#define CK_INFRA_AUD_L (79 - GATE_OFFSET) /* Linux CLK ID (33) */ -#define CK_INFRA_AUD_AUD (80 - GATE_OFFSET) /* Linux CLK ID (34) */ -#define CK_INFRA_AUD_EG2 (81 - GATE_OFFSET) /* Linux CLK ID (35) */ -#define CK_INFRA_DRAMC_F26M (82 - GATE_OFFSET) /* Linux CLK ID (36) */ -#define CK_INFRA_133M_DBG_ACKM (83 - GATE_OFFSET) /* Linux CLK ID (37) */ -#define CK_INFRA_66M_AP_DMA_BCK (84 - GATE_OFFSET) /* Linux CLK ID (38) */ -#define CK_INFRA_66M_SEJ_BCK (85 - GATE_OFFSET) /* Linux CLK ID (39) */ -#define CK_INFRA_PRE_CK_SEJ_F13M (86 - GATE_OFFSET) /* Linux CLK ID (40) */ -#define CK_INFRA_66M_TRNG (87 - GATE_OFFSET) /* Linux CLK ID (41) */ -#define CK_INFRA_26M_THERM_SYSTEM (88 - GATE_OFFSET) /* Linux CLK ID (42) */ -#define CK_INFRA_I2C_BCK (89 - GATE_OFFSET) /* Linux CLK ID (43) */ -#define CK_INFRA_66M_UART0_PCK (90 - GATE_OFFSET) /* Linux CLK ID (44) */ -#define CK_INFRA_66M_UART1_PCK (91 - GATE_OFFSET) /* Linux CLK ID (45) */ -#define CK_INFRA_66M_UART2_PCK (92 - GATE_OFFSET) /* Linux CLK ID (46) */ -#define CK_INFRA_52M_UART0_CK (93 - GATE_OFFSET) /* Linux CLK ID (47) */ -#define CK_INFRA_52M_UART1_CK (94 - GATE_OFFSET) /* Linux CLK ID (48) */ -#define CK_INFRA_52M_UART2_CK (95 - GATE_OFFSET) /* Linux CLK ID (49) */ -#define CK_INFRA_NFI (96 - GATE_OFFSET) /* Linux CLK ID (50) */ -#define CK_INFRA_SPINFI (97 - GATE_OFFSET) /* Linux CLK ID (51) */ -#define CK_INFRA_66M_NFI_HCK (98 - GATE_OFFSET) /* Linux CLK ID (52) */ -#define CK_INFRA_104M_SPI0 (99 - GATE_OFFSET) /* Linux CLK ID (53) */ -#define CK_INFRA_104M_SPI1 (100 - GATE_OFFSET) /* Linux CLK ID (54) */ -#define CK_INFRA_104M_SPI2_BCK (101 - GATE_OFFSET) /* Linux CLK ID (55) */ -#define CK_INFRA_66M_SPI0_HCK (102 - GATE_OFFSET) /* Linux CLK ID (56) */ -#define CK_INFRA_66M_SPI1_HCK (103 - GATE_OFFSET) /* Linux CLK ID (57) */ -#define CK_INFRA_66M_SPI2_HCK (104 - GATE_OFFSET) /* Linux CLK ID (58) */ -#define CK_INFRA_66M_FLASHIF_AXI (105 - GATE_OFFSET) /* Linux CLK ID (59) */ -#define CK_INFRA_RTC (106 - GATE_OFFSET) /* Linux CLK ID (60) */ -#define CK_INFRA_26M_ADC_BCK (107 - GATE_OFFSET) /* Linux CLK ID (61) */ -#define CK_INFRA_RC_ADC (108 - GATE_OFFSET) /* Linux CLK ID (62) */ -#define CK_INFRA_MSDC400 (109 - GATE_OFFSET) /* Linux CLK ID (63) */ -#define CK_INFRA_MSDC2_HCK (110 - GATE_OFFSET) /* Linux CLK ID (64) */ -#define CK_INFRA_133M_MSDC_0_HCK (111 - GATE_OFFSET) /* Linux CLK ID (65) */ -#define CK_INFRA_66M_MSDC_0_HCK (112 - GATE_OFFSET) /* Linux CLK ID (66) */ -#define CK_INFRA_133M_CPUM_BCK (113 - GATE_OFFSET) /* Linux CLK ID (67) */ -#define CK_INFRA_BIST2FPC (114 - GATE_OFFSET) /* Linux CLK ID (68) */ -#define CK_INFRA_I2C_X16W_MCK_CK_P1 (115 - GATE_OFFSET) /* Linux CLK ID (69) */ -#define CK_INFRA_I2C_X16W_PCK_CK_P1 (116 - GATE_OFFSET) /* Linux CLK ID (70) */ -#define CK_INFRA_133M_USB_HCK (117 - GATE_OFFSET) /* Linux CLK ID (71) */ -#define CK_INFRA_133M_USB_HCK_CK_P1 (118 - GATE_OFFSET) /* Linux CLK ID (72) */ -#define CK_INFRA_66M_USB_HCK (119 - GATE_OFFSET) /* Linux CLK ID (73) */ -#define CK_INFRA_66M_USB_HCK_CK_P1 (120 - GATE_OFFSET) /* Linux CLK ID (74) */ -#define CK_INFRA_USB_SYS (121 - GATE_OFFSET) /* Linux CLK ID (75) */ -#define CK_INFRA_USB_SYS_CK_P1 (122 - GATE_OFFSET) /* Linux CLK ID (76) */ -#define CK_INFRA_USB_REF (123 - GATE_OFFSET) /* Linux CLK ID (77) */ -#define CK_INFRA_USB_CK_P1 (124 - GATE_OFFSET) /* Linux CLK ID (78) */ -#define CK_INFRA_USB_FRMCNT (125 - GATE_OFFSET) /* Linux CLK ID (79) */ -#define CK_INFRA_USB_FRMCNT_CK_P1 (126 - GATE_OFFSET) /* Linux CLK ID (80) */ -#define CK_INFRA_USB_PIPE (127 - GATE_OFFSET) /* Linux CLK ID (81) */ -#define CK_INFRA_USB_PIPE_CK_P1 (128 - GATE_OFFSET) /* Linux CLK ID (82) */ -#define CK_INFRA_USB_UTMI (129 - GATE_OFFSET) /* Linux CLK ID (83) */ -#define CK_INFRA_USB_UTMI_CK_P1 (130 - GATE_OFFSET) /* Linux CLK ID (84) */ -#define CK_INFRA_USB_XHCI (131 - GATE_OFFSET) /* Linux CLK ID (85) */ -#define CK_INFRA_USB_XHCI_CK_P1 (132 - GATE_OFFSET) /* Linux CLK ID (86) */ -#define CK_INFRA_PCIE_GFMUX_TL_P0 (133 - GATE_OFFSET) /* Linux CLK ID (87) */ -#define CK_INFRA_PCIE_GFMUX_TL_P1 (134 - GATE_OFFSET) /* Linux CLK ID (88) */ -#define CK_INFRA_PCIE_GFMUX_TL_P2 (135 - GATE_OFFSET) /* Linux CLK ID (89) */ -#define CK_INFRA_PCIE_GFMUX_TL_P3 (136 - GATE_OFFSET) /* Linux CLK ID (90) */ -#define CK_INFRA_PCIE_PIPE_P0 (137 - GATE_OFFSET) /* Linux CLK ID (91) */ -#define CK_INFRA_PCIE_PIPE_P1 (138 - GATE_OFFSET) /* Linux CLK ID (92) */ -#define CK_INFRA_PCIE_PIPE_P2 (139 - GATE_OFFSET) /* Linux CLK ID (93) */ -#define CK_INFRA_PCIE_PIPE_P3 (140 - GATE_OFFSET) /* Linux CLK ID (94) */ -#define CK_INFRA_133M_PCIE_CK_P0 (141 - GATE_OFFSET) /* Linux CLK ID (95) */ -#define CK_INFRA_133M_PCIE_CK_P1 (142 - GATE_OFFSET) /* Linux CLK ID (96) */ -#define CK_INFRA_133M_PCIE_CK_P2 (143 - GATE_OFFSET) /* Linux CLK ID (97) */ -#define CK_INFRA_133M_PCIE_CK_P3 (144 - GATE_OFFSET) /* Linux CLK ID (98) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P0 (145 - GATE_OFFSET) /* Linux CLK ID (99) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P1 \ - (146 - GATE_OFFSET) /* Linux CLK ID (100) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P2 \ - (147 - GATE_OFFSET) /* Linux CLK ID (101) */ -#define CK_INFRA_PCIE_PERI_26M_CK_P3 \ - (148 - GATE_OFFSET) /* Linux CLK ID (102) */ +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 +#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 +#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 +#define CLK_INFRA_66M_GPT_BCK 23 +#define CLK_INFRA_66M_PWM_HCK 24 +#define CLK_INFRA_66M_PWM_BCK 25 +#define CLK_INFRA_66M_PWM_CK1 26 +#define CLK_INFRA_66M_PWM_CK2 27 +#define CLK_INFRA_66M_PWM_CK3 28 +#define CLK_INFRA_66M_PWM_CK4 29 +#define CLK_INFRA_66M_PWM_CK5 30 +#define CLK_INFRA_66M_PWM_CK6 31 +#define CLK_INFRA_66M_PWM_CK7 32 +#define CLK_INFRA_66M_PWM_CK8 33 +#define CLK_INFRA_133M_CQDMA_BCK 34 +#define CLK_INFRA_66M_AUD_SLV_BCK 35 +#define CLK_INFRA_AUD_26M 36 +#define CLK_INFRA_AUD_L 37 +#define CLK_INFRA_AUD_AUD 38 +#define CLK_INFRA_AUD_EG2 39 +#define CLK_INFRA_DRAMC_F26M 40 +#define CLK_INFRA_133M_DBG_ACKM 41 +#define CLK_INFRA_66M_AP_DMA_BCK 42 +#define CLK_INFRA_66M_SEJ_BCK 43 +#define CLK_INFRA_PRE_CK_SEJ_F13M 44 +/* #define CLK_INFRA_66M_TRNG 44 */ +#define CLK_INFRA_26M_THERM_SYSTEM 45 +#define CLK_INFRA_I2C_BCK 46 +/* #define CLK_INFRA_66M_UART0_PCK 46 */ +/* #define CLK_INFRA_66M_UART1_PCK 47 */ +/* #define CLK_INFRA_66M_UART2_PCK 48 */ +#define CLK_INFRA_52M_UART0_CK 47 +#define CLK_INFRA_52M_UART1_CK 48 +#define CLK_INFRA_52M_UART2_CK 49 +#define CLK_INFRA_NFI 50 +#define CLK_INFRA_SPINFI 51 +#define CLK_INFRA_66M_NFI_HCK 52 +#define CLK_INFRA_104M_SPI0 53 +#define CLK_INFRA_104M_SPI1 54 +#define CLK_INFRA_104M_SPI2_BCK 55 +#define CLK_INFRA_66M_SPI0_HCK 56 +#define CLK_INFRA_66M_SPI1_HCK 57 +#define CLK_INFRA_66M_SPI2_HCK 58 +#define CLK_INFRA_66M_FLASHIF_AXI 59 +#define CLK_INFRA_RTC 60 +#define CLK_INFRA_26M_ADC_BCK 61 +#define CLK_INFRA_RC_ADC 62 +#define CLK_INFRA_MSDC400 63 +#define CLK_INFRA_MSDC2_HCK 64 +#define CLK_INFRA_133M_MSDC_0_HCK 65 +#define CLK_INFRA_66M_MSDC_0_HCK 66 +#define CLK_INFRA_133M_CPUM_BCK 67 +#define CLK_INFRA_BIST2FPC 68 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 +#define CLK_INFRA_133M_USB_HCK 71 +#define CLK_INFRA_133M_USB_HCK_CK_P1 72 +#define CLK_INFRA_66M_USB_HCK 73 +#define CLK_INFRA_66M_USB_HCK_CK_P1 74 +#define CLK_INFRA_USB_SYS 75 +#define CLK_INFRA_USB_SYS_CK_P1 76 +#define CLK_INFRA_USB_REF 77 +#define CLK_INFRA_USB_CK_P1 78 +#define CLK_INFRA_USB_FRMCNT 79 +#define CLK_INFRA_USB_FRMCNT_CK_P1 80 +#define CLK_INFRA_USB_PIPE 81 +#define CLK_INFRA_USB_PIPE_CK_P1 82 +#define CLK_INFRA_USB_UTMI 83 +#define CLK_INFRA_USB_UTMI_CK_P1 84 +#define CLK_INFRA_USB_XHCI 85 +#define CLK_INFRA_USB_XHCI_CK_P1 86 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 +#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 +#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 +#define CLK_INFRA_PCIE_PIPE_P0 91 +#define CLK_INFRA_PCIE_PIPE_P1 92 +#define CLK_INFRA_PCIE_PIPE_P2 93 +#define CLK_INFRA_PCIE_PIPE_P3 94 +#define CLK_INFRA_133M_PCIE_CK_P0 95 +#define CLK_INFRA_133M_PCIE_CK_P1 96 +#define CLK_INFRA_133M_PCIE_CK_P2 97 +#define CLK_INFRA_133M_PCIE_CK_P3 98 /* TOPCKGEN */ +/* mtk_fixed_clk */ +#define CLK_TOP_XTAL 0 /* mtk_fixed_factor */ -#define CK_TOP_CB_CKSQ_40M 0 /* Linux CLK ID (74) */ -#define CK_TOP_CB_M_416M 1 /* Linux CLK ID (75) */ -#define CK_TOP_CB_M_D2 2 /* Linux CLK ID (76) */ -#define CK_TOP_M_D3_D2 3 /* Linux CLK ID (77) */ -#define CK_TOP_CB_M_D4 4 /* Linux CLK ID (78) */ -#define CK_TOP_CB_M_D8 5 /* Linux CLK ID (79) */ -#define CK_TOP_M_D8_D2 6 /* Linux CLK ID (80) */ -#define CK_TOP_CB_MM_720M 7 /* Linux CLK ID (81) */ -#define CK_TOP_CB_MM_D2 8 /* Linux CLK ID (82) */ -#define CK_TOP_CB_MM_D3_D5 9 /* Linux CLK ID (83) */ -#define CK_TOP_CB_MM_D4 10 /* Linux CLK ID (84) */ -#define CK_TOP_MM_D6_D2 11 /* Linux CLK ID (85) */ -#define CK_TOP_CB_MM_D8 12 /* Linux CLK ID (86) */ -#define CK_TOP_CB_APLL2_196M 13 /* Linux CLK ID (87) */ -#define CK_TOP_CB_APLL2_D4 14 /* Linux CLK ID (88) */ -#define CK_TOP_CB_NET1_D4 15 /* Linux CLK ID (89) */ -#define CK_TOP_CB_NET1_D5 16 /* Linux CLK ID (90) */ -#define CK_TOP_NET1_D5_D2 17 /* Linux CLK ID (91) */ -#define CK_TOP_NET1_D5_D4 18 /* Linux CLK ID (92) */ -#define CK_TOP_CB_NET1_D8 19 /* Linux CLK ID (93) */ -#define CK_TOP_NET1_D8_D2 20 /* Linux CLK ID (94) */ -#define CK_TOP_NET1_D8_D4 21 /* Linux CLK ID (95) */ -#define CK_TOP_NET1_D8_D8 22 /* Linux CLK ID (96) */ -#define CK_TOP_NET1_D8_D16 23 /* Linux CLK ID (97) */ -#define CK_TOP_CB_NET2_800M 24 /* Linux CLK ID (98) */ -#define CK_TOP_CB_NET2_D2 25 /* Linux CLK ID (99) */ -#define CK_TOP_CB_NET2_D4 26 /* Linux CLK ID (100) */ -#define CK_TOP_NET2_D4_D4 27 /* Linux CLK ID (101) */ -#define CK_TOP_NET2_D4_D8 28 /* Linux CLK ID (102) */ -#define CK_TOP_CB_NET2_D6 29 /* Linux CLK ID (103) */ -#define CK_TOP_CB_NET2_D8 30 /* Linux CLK ID (104) */ -#define CK_TOP_CB_WEDMCU_208M 31 /* Linux CLK ID (105) */ -#define CK_TOP_CB_SGM_325M 32 /* Linux CLK ID (106) */ -#define CK_TOP_CB_NETSYS_850M 33 /* Linux CLK ID (107) */ -#define CK_TOP_CB_MSDC_400M 34 /* Linux CLK ID (108) */ -#define CK_TOP_CKSQ_40M_D2 35 /* Linux CLK ID (109) */ -#define CK_TOP_CB_RTC_32K 36 /* Linux CLK ID (110) */ -#define CK_TOP_CB_RTC_32P7K 37 /* Linux CLK ID (111) */ -#define CK_TOP_INFRA_F32K 38 /* Linux CLK ID (112) */ -#define CK_TOP_CKSQ_SRC 39 /* Linux CLK ID (113) */ -#define CK_TOP_NETSYS_2X 40 /* Linux CLK ID (114) */ -#define CK_TOP_NETSYS_GSW 41 /* Linux CLK ID (115) */ -#define CK_TOP_NETSYS_WED_MCU 42 /* Linux CLK ID (116) */ -#define CK_TOP_EIP197 43 /* Linux CLK ID (117) */ -#define CK_TOP_EMMC_250M 44 /* Linux CLK ID (118) */ -#define CK_TOP_EMMC_400M 45 /* Linux CLK ID (119) */ -#define CK_TOP_SPI 46 /* Linux CLK ID (120) */ -#define CK_TOP_SPIM_MST 47 /* Linux CLK ID (121) */ -#define CK_TOP_NFI1X 48 /* Linux CLK ID (122) */ -#define CK_TOP_SPINFI_BCK 49 /* Linux CLK ID (123) */ -#define CK_TOP_I2C_BCK 50 /* Linux CLK ID (124) */ -#define CK_TOP_USB_SYS 51 /* Linux CLK ID (125) */ -#define CK_TOP_USB_SYS_P1 52 /* Linux CLK ID (126) */ -#define CK_TOP_USB_XHCI 53 /* Linux CLK ID (127) */ -#define CK_TOP_USB_XHCI_P1 54 /* Linux CLK ID (128) */ -#define CK_TOP_USB_FRMCNT 55 /* Linux CLK ID (129) */ -#define CK_TOP_USB_FRMCNT_P1 56 /* Linux CLK ID (130) */ -#define CK_TOP_AUD 57 /* Linux CLK ID (131) */ -#define CK_TOP_A1SYS 58 /* Linux CLK ID (132) */ -#define CK_TOP_AUD_L 59 /* Linux CLK ID (133) */ -#define CK_TOP_A_TUNER 60 /* Linux CLK ID (134) */ -#define CK_TOP_SYSAXI 61 /* Linux CLK ID (135) */ -#define CK_TOP_INFRA_F26M 62 /* Linux CLK ID (136) */ -#define CK_TOP_USB_REF 63 /* Linux CLK ID (137) */ -#define CK_TOP_USB_CK_P1 64 /* Linux CLK ID (138) */ +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D3_D2 5 +#define CLK_TOP_MPLL_D4 6 +#define CLK_TOP_MPLL_D8 7 +#define CLK_TOP_MPLL_D8_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D3_D5 10 +#define CLK_TOP_MMPLL_D4 11 +#define CLK_TOP_MMPLL_D6_D2 12 +#define CLK_TOP_MMPLL_D8 13 +#define CLK_TOP_APLL2_D4 14 +#define CLK_TOP_NET1PLL_D4 15 +#define CLK_TOP_NET1PLL_D5 16 +#define CLK_TOP_NET1PLL_D5_D2 17 +#define CLK_TOP_NET1PLL_D5_D4 18 +#define CLK_TOP_NET1PLL_D8 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET1PLL_D8_D8 22 +#define CLK_TOP_NET1PLL_D8_D16 23 +#define CLK_TOP_NET2PLL_D2 24 +#define CLK_TOP_NET2PLL_D4 25 +#define CLK_TOP_NET2PLL_D4_D4 26 +#define CLK_TOP_NET2PLL_D4_D8 27 +#define CLK_TOP_NET2PLL_D6 28 +#define CLK_TOP_NET2PLL_D8 29 /* mtk_mux */ -#define CK_TOP_NETSYS_SEL 65 /* Linux CLK ID (0) */ -#define CK_TOP_NETSYS_500M_SEL 66 /* Linux CLK ID (1) */ -#define CK_TOP_NETSYS_2X_SEL 67 /* Linux CLK ID (2) */ -#define CK_TOP_NETSYS_GSW_SEL 68 /* Linux CLK ID (3) */ -#define CK_TOP_ETH_GMII_SEL 69 /* Linux CLK ID (4) */ -#define CK_TOP_NETSYS_MCU_SEL 70 /* Linux CLK ID (5) */ -#define CK_TOP_NETSYS_PAO_2X_SEL 71 /* Linux CLK ID (6) */ -#define CK_TOP_EIP197_SEL 72 /* Linux CLK ID (7) */ -#define CK_TOP_AXI_INFRA_SEL 73 /* Linux CLK ID (8) */ -#define CK_TOP_UART_SEL 74 /* Linux CLK ID (9) */ -#define CK_TOP_EMMC_250M_SEL 75 /* Linux CLK ID (10) */ -#define CK_TOP_EMMC_400M_SEL 76 /* Linux CLK ID (11) */ -#define CK_TOP_SPI_SEL 77 /* Linux CLK ID (12) */ -#define CK_TOP_SPIM_MST_SEL 78 /* Linux CLK ID (13) */ -#define CK_TOP_NFI1X_SEL 79 /* Linux CLK ID (14) */ -#define CK_TOP_SPINFI_SEL 80 /* Linux CLK ID (15) */ -#define CK_TOP_PWM_SEL 81 /* Linux CLK ID (16) */ -#define CK_TOP_I2C_SEL 82 /* Linux CLK ID (17) */ -#define CK_TOP_PCIE_MBIST_250M_SEL 83 /* Linux CLK ID (18) */ -#define CK_TOP_PEXTP_TL_SEL 84 /* Linux CLK ID (19) */ -#define CK_TOP_PEXTP_TL_P1_SEL 85 /* Linux CLK ID (20) */ -#define CK_TOP_PEXTP_TL_P2_SEL 86 /* Linux CLK ID (21) */ -#define CK_TOP_PEXTP_TL_P3_SEL 87 /* Linux CLK ID (22) */ -#define CK_TOP_USB_SYS_SEL 88 /* Linux CLK ID (23) */ -#define CK_TOP_USB_SYS_P1_SEL 89 /* Linux CLK ID (24) */ -#define CK_TOP_USB_XHCI_SEL 90 /* Linux CLK ID (25) */ -#define CK_TOP_USB_XHCI_P1_SEL 91 /* Linux CLK ID (26) */ -#define CK_TOP_USB_FRMCNT_SEL 92 /* Linux CLK ID (27) */ -#define CK_TOP_USB_FRMCNT_P1_SEL 93 /* Linux CLK ID (28) */ -#define CK_TOP_AUD_SEL 94 /* Linux CLK ID (29) */ -#define CK_TOP_A1SYS_SEL 95 /* Linux CLK ID (30) */ -#define CK_TOP_AUD_L_SEL 96 /* Linux CLK ID (31) */ -#define CK_TOP_A_TUNER_SEL 97 /* Linux CLK ID (32) */ -#define CK_TOP_SSPXTP_SEL 98 /* Linux CLK ID (33) */ -#define CK_TOP_USB_PHY_SEL 99 /* Linux CLK ID (34) */ -#define CK_TOP_USXGMII_SBUS_0_SEL 100 /* Linux CLK ID (35) */ -#define CK_TOP_USXGMII_SBUS_1_SEL 101 /* Linux CLK ID (36) */ -#define CK_TOP_SGM_0_SEL 102 /* Linux CLK ID (37) */ -#define CK_TOP_SGM_SBUS_0_SEL 103 /* Linux CLK ID (38) */ -#define CK_TOP_SGM_1_SEL 104 /* Linux CLK ID (39) */ -#define CK_TOP_SGM_SBUS_1_SEL 105 /* Linux CLK ID (40) */ -#define CK_TOP_XFI_PHY_0_XTAL_SEL 106 /* Linux CLK ID (41) */ -#define CK_TOP_XFI_PHY_1_XTAL_SEL 107 /* Linux CLK ID (42) */ -#define CK_TOP_SYSAXI_SEL 108 /* Linux CLK ID (43) */ -#define CK_TOP_SYSAPB_SEL 109 /* Linux CLK ID (44) */ -#define CK_TOP_ETH_REFCK_50M_SEL 110 /* Linux CLK ID (45) */ -#define CK_TOP_ETH_SYS_200M_SEL 111 /* Linux CLK ID (46) */ -#define CK_TOP_ETH_SYS_SEL 112 /* Linux CLK ID (47) */ -#define CK_TOP_ETH_XGMII_SEL 113 /* Linux CLK ID (48) */ -#define CK_TOP_BUS_TOPS_SEL 114 /* Linux CLK ID (49) */ -#define CK_TOP_NPU_TOPS_SEL 115 /* Linux CLK ID (50) */ -#define CK_TOP_DRAMC_SEL 116 /* Linux CLK ID (51) */ -#define CK_TOP_DRAMC_MD32_SEL 117 /* Linux CLK ID (52) */ -#define CK_TOP_INFRA_F26M_SEL 118 /* Linux CLK ID (53) */ -#define CK_TOP_PEXTP_P0_SEL 119 /* Linux CLK ID (54) */ -#define CK_TOP_PEXTP_P1_SEL 120 /* Linux CLK ID (55) */ -#define CK_TOP_PEXTP_P2_SEL 121 /* Linux CLK ID (56) */ -#define CK_TOP_PEXTP_P3_SEL 122 /* Linux CLK ID (57) */ -#define CK_TOP_DA_XTP_GLB_P0_SEL 123 /* Linux CLK ID (58) */ -#define CK_TOP_DA_XTP_GLB_P1_SEL 124 /* Linux CLK ID (59) */ -#define CK_TOP_DA_XTP_GLB_P2_SEL 125 /* Linux CLK ID (60) */ -#define CK_TOP_DA_XTP_GLB_P3_SEL 126 /* Linux CLK ID (61) */ -#define CK_TOP_CKM_SEL 127 /* Linux CLK ID (62) */ -#define CK_TOP_DA_SELM_XTAL_SEL 128 /* Linux CLK ID (63) */ -#define CK_TOP_PEXTP_SEL 129 /* Linux CLK ID (64) */ -#define CK_TOP_TOPS_P2_26M_SEL 130 /* Linux CLK ID (65) */ -#define CK_TOP_MCUSYS_BACKUP_625M_SEL 131 /* Linux CLK ID (66) */ -#define CK_TOP_NETSYS_SYNC_250M_SEL 132 /* Linux CLK ID (67) */ -#define CK_TOP_MACSEC_SEL 133 /* Linux CLK ID (68) */ -#define CK_TOP_NETSYS_TOPS_400M_SEL 134 /* Linux CLK ID (69) */ -#define CK_TOP_NETSYS_PPEFB_250M_SEL 135 /* Linux CLK ID (70) */ -#define CK_TOP_NETSYS_WARP_SEL 136 /* Linux CLK ID (71) */ -#define CK_TOP_ETH_MII_SEL 137 /* Linux CLK ID (72) */ -#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 138 /* Linux CLK ID (73) */ +#define CLK_TOP_NETSYS_SEL 30 +#define CLK_TOP_NETSYS_500M_SEL 31 +#define CLK_TOP_NETSYS_2X_SEL 32 +#define CLK_TOP_NETSYS_GSW_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_NETSYS_MCU_SEL 35 +#define CLK_TOP_NETSYS_PAO_2X_SEL 36 +#define CLK_TOP_EIP197_SEL 37 +#define CLK_TOP_AXI_INFRA_SEL 38 +#define CLK_TOP_UART_SEL 39 +#define CLK_TOP_EMMC_250M_SEL 40 +#define CLK_TOP_EMMC_400M_SEL 41 +#define CLK_TOP_SPI_SEL 42 +#define CLK_TOP_SPIM_MST_SEL 43 +#define CLK_TOP_NFI1X_SEL 44 +#define CLK_TOP_SPINFI_SEL 45 +#define CLK_TOP_PWM_SEL 46 +#define CLK_TOP_I2C_SEL 47 +#define CLK_TOP_PCIE_MBIST_250M_SEL 48 +#define CLK_TOP_PEXTP_TL_SEL 49 +#define CLK_TOP_PEXTP_TL_P1_SEL 50 +#define CLK_TOP_PEXTP_TL_P2_SEL 51 +#define CLK_TOP_PEXTP_TL_P3_SEL 52 +#define CLK_TOP_USB_SYS_SEL 53 +#define CLK_TOP_USB_SYS_P1_SEL 54 +#define CLK_TOP_USB_XHCI_SEL 55 +#define CLK_TOP_USB_XHCI_P1_SEL 56 +#define CLK_TOP_USB_FRMCNT_SEL 57 +#define CLK_TOP_USB_FRMCNT_P1_SEL 58 +#define CLK_TOP_AUD_SEL 59 +#define CLK_TOP_A1SYS_SEL 60 +#define CLK_TOP_AUD_L_SEL 61 +#define CLK_TOP_A_TUNER_SEL 62 +#define CLK_TOP_SSPXTP_SEL 63 +#define CLK_TOP_USB_PHY_SEL 64 +#define CLK_TOP_USXGMII_SBUS_0_SEL 65 +#define CLK_TOP_USXGMII_SBUS_1_SEL 66 +#define CLK_TOP_SGM_0_SEL 67 +#define CLK_TOP_SGM_SBUS_0_SEL 68 +#define CLK_TOP_SGM_1_SEL 69 +#define CLK_TOP_SGM_SBUS_1_SEL 70 +#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 +#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 +#define CLK_TOP_SYSAXI_SEL 73 +#define CLK_TOP_SYSAPB_SEL 74 +#define CLK_TOP_ETH_REFCK_50M_SEL 75 +#define CLK_TOP_ETH_SYS_200M_SEL 76 +#define CLK_TOP_ETH_SYS_SEL 77 +#define CLK_TOP_ETH_XGMII_SEL 78 +#define CLK_TOP_BUS_TOPS_SEL 79 +#define CLK_TOP_NPU_TOPS_SEL 80 +#define CLK_TOP_DRAMC_SEL 81 +#define CLK_TOP_DRAMC_MD32_SEL 82 +#define CLK_TOP_INFRA_F26M_SEL 83 +#define CLK_TOP_PEXTP_P0_SEL 84 +#define CLK_TOP_PEXTP_P1_SEL 85 +#define CLK_TOP_PEXTP_P2_SEL 86 +#define CLK_TOP_PEXTP_P3_SEL 87 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 +#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 +#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 +#define CLK_TOP_CKM_SEL 92 +#define CLK_TOP_DA_SEL 93 +#define CLK_TOP_PEXTP_SEL 94 +#define CLK_TOP_TOPS_P2_26M_SEL 95 +#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 +#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 +#define CLK_TOP_MACSEC_SEL 98 +#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 +#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 +#define CLK_TOP_NETSYS_WARP_SEL 101 +#define CLK_TOP_ETH_MII_SEL 102 +#define CLK_TOP_NPU_SEL 103 /* APMIXEDSYS */ /* mtk_pll_data */ -#define CK_APMIXED_NETSYSPLL 0 -#define CK_APMIXED_MPLL 1 -#define CK_APMIXED_MMPLL 2 -#define CK_APMIXED_APLL2 3 -#define CK_APMIXED_NET1PLL 4 -#define CK_APMIXED_NET2PLL 5 -#define CK_APMIXED_WEDMCUPLL 6 -#define CK_APMIXED_SGMPLL 7 -#define CK_APMIXED_ARM_B 8 -#define CK_APMIXED_CCIPLL2_B 9 -#define CK_APMIXED_USXGMIIPLL 10 -#define CK_APMIXED_MSDCPLL 11 +#define CLK_APMIXED_NETSYSPLL 0 +#define CLK_APMIXED_MPLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_APLL2 3 +#define CLK_APMIXED_NET1PLL 4 +#define CLK_APMIXED_NET2PLL 5 +#define CLK_APMIXED_WEDMCUPLL 6 +#define CLK_APMIXED_SGMPLL 7 +#define CLK_APMIXED_ARM_B 8 +#define CLK_APMIXED_CCIPLL2_B 9 +#define CLK_APMIXED_USXGMIIPLL 10 +#define CLK_APMIXED_MSDCPLL 11 /* ETHSYS ETH DMA */ /* mtk_gate */ -#define CK_ETHDMA_FE_EN 0 +#define CLK_ETHDMA_FE_EN 0 /* SGMIISYS_0 */ /* mtk_gate */ -#define CK_SGM0_TX_EN 0 -#define CK_SGM0_RX_EN 1 +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 /* SGMIISYS_1 */ /* mtk_gate */ -#define CK_SGM1_TX_EN 0 -#define CK_SGM1_RX_EN 1 +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 /* ETHWARP */ /* mtk_gate */ -#define CK_ETHWARP_WOCPU2_EN 0 -#define CK_ETHWARP_WOCPU1_EN 1 -#define CK_ETHWARP_WOCPU0_EN 2 +#define CLK_ETHWARP_WOCPU2_EN 0 +#define CLK_ETHWARP_WOCPU1_EN 1 +#define CLK_ETHWARP_WOCPU0_EN 2 #endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h deleted file mode 100644 index e5e59690b5f..00000000000 --- a/include/dt-bindings/clock/px30-cru.h +++ /dev/null @@ -1,389 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine <zhangqing@rock-chips.com> - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H -#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_NPLL 4 -#define APLL_BOOST_H 5 -#define APLL_BOOST_L 6 -#define ARMCLK 7 - -/* sclk gates (special clocks) */ -#define USB480M 14 -#define SCLK_PDM 15 -#define SCLK_I2S0_TX 16 -#define SCLK_I2S0_TX_OUT 17 -#define SCLK_I2S0_RX 18 -#define SCLK_I2S0_RX_OUT 19 -#define SCLK_I2S1 20 -#define SCLK_I2S1_OUT 21 -#define SCLK_I2S2 22 -#define SCLK_I2S2_OUT 23 -#define SCLK_UART1 24 -#define SCLK_UART2 25 -#define SCLK_UART3 26 -#define SCLK_UART4 27 -#define SCLK_UART5 28 -#define SCLK_I2C0 29 -#define SCLK_I2C1 30 -#define SCLK_I2C2 31 -#define SCLK_I2C3 32 -#define SCLK_I2C4 33 -#define SCLK_PWM0 34 -#define SCLK_PWM1 35 -#define SCLK_SPI0 36 -#define SCLK_SPI1 37 -#define SCLK_TIMER0 38 -#define SCLK_TIMER1 39 -#define SCLK_TIMER2 40 -#define SCLK_TIMER3 41 -#define SCLK_TIMER4 42 -#define SCLK_TIMER5 43 -#define SCLK_TSADC 44 -#define SCLK_SARADC 45 -#define SCLK_OTP 46 -#define SCLK_OTP_USR 47 -#define SCLK_CRYPTO 48 -#define SCLK_CRYPTO_APK 49 -#define SCLK_DDRC 50 -#define SCLK_ISP 51 -#define SCLK_CIF_OUT 52 -#define SCLK_RGA_CORE 53 -#define SCLK_VOPB_PWM 54 -#define SCLK_NANDC 55 -#define SCLK_SDIO 56 -#define SCLK_EMMC 57 -#define SCLK_SFC 58 -#define SCLK_SDMMC 59 -#define SCLK_OTG_ADP 60 -#define SCLK_GMAC_SRC 61 -#define SCLK_GMAC 62 -#define SCLK_GMAC_RX_TX 63 -#define SCLK_MAC_REF 64 -#define SCLK_MAC_REFOUT 65 -#define SCLK_MAC_OUT 66 -#define SCLK_SDMMC_DRV 67 -#define SCLK_SDMMC_SAMPLE 68 -#define SCLK_SDIO_DRV 69 -#define SCLK_SDIO_SAMPLE 70 -#define SCLK_EMMC_DRV 71 -#define SCLK_EMMC_SAMPLE 72 -#define SCLK_GPU 73 -#define SCLK_PVTM 74 -#define SCLK_CORE_VPU 75 -#define SCLK_GMAC_RMII 76 -#define SCLK_UART2_SRC 77 -#define SCLK_NANDC_DIV 78 -#define SCLK_NANDC_DIV50 79 -#define SCLK_SDIO_DIV 80 -#define SCLK_SDIO_DIV50 81 -#define SCLK_EMMC_DIV 82 -#define SCLK_EMMC_DIV50 83 - -/* dclk gates */ -#define DCLK_VOPB 150 -#define DCLK_VOPL 151 - -/* aclk gates */ -#define ACLK_GPU 170 -#define ACLK_BUS_PRE 171 -#define ACLK_CRYPTO 172 -#define ACLK_VI_PRE 173 -#define ACLK_VO_PRE 174 -#define ACLK_VPU 175 -#define ACLK_PERI_PRE 176 -#define ACLK_GMAC 178 -#define ACLK_CIF 179 -#define ACLK_ISP 180 -#define ACLK_VOPB 181 -#define ACLK_VOPL 182 -#define ACLK_RGA 183 -#define ACLK_GIC 184 -#define ACLK_DCF 186 -#define ACLK_DMAC 187 - -/* hclk gates */ -#define HCLK_BUS_PRE 240 -#define HCLK_CRYPTO 241 -#define HCLK_VI_PRE 242 -#define HCLK_VO_PRE 243 -#define HCLK_VPU 244 -#define HCLK_PERI_PRE 245 -#define HCLK_MMC_NAND 246 -#define HCLK_SDMMC 247 -#define HCLK_USB 248 -#define HCLK_CIF 249 -#define HCLK_ISP 250 -#define HCLK_VOPB 251 -#define HCLK_VOPL 252 -#define HCLK_RGA 253 -#define HCLK_NANDC 254 -#define HCLK_SDIO 255 -#define HCLK_EMMC 256 -#define HCLK_SFC 257 -#define HCLK_OTG 258 -#define HCLK_HOST 259 -#define HCLK_HOST_ARB 260 -#define HCLK_PDM 261 -#define HCLK_I2S0 262 -#define HCLK_I2S1 263 -#define HCLK_I2S2 264 - -/* pclk gates */ -#define PCLK_BUS_PRE 320 -#define PCLK_DDR 321 -#define PCLK_VO_PRE 322 -#define PCLK_GMAC 323 -#define PCLK_MIPI_DSI 324 -#define PCLK_MIPIDSIPHY 325 -#define PCLK_MIPICSIPHY 326 -#define PCLK_USB_GRF 327 -#define PCLK_DCF 328 -#define PCLK_UART1 329 -#define PCLK_UART2 330 -#define PCLK_UART3 331 -#define PCLK_UART4 332 -#define PCLK_UART5 333 -#define PCLK_I2C0 334 -#define PCLK_I2C1 335 -#define PCLK_I2C2 336 -#define PCLK_I2C3 337 -#define PCLK_I2C4 338 -#define PCLK_PWM0 339 -#define PCLK_PWM1 340 -#define PCLK_SPI0 341 -#define PCLK_SPI1 342 -#define PCLK_SARADC 343 -#define PCLK_TSADC 344 -#define PCLK_TIMER 345 -#define PCLK_OTP_NS 346 -#define PCLK_WDT_NS 347 -#define PCLK_GPIO1 348 -#define PCLK_GPIO2 349 -#define PCLK_GPIO3 350 -#define PCLK_ISP 351 -#define PCLK_CIF 352 -#define PCLK_OTP_PHY 353 - -#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) - -/* pmu-clocks indices */ - -#define PLL_GPLL 1 - -#define SCLK_RTC32K_PMU 4 -#define SCLK_WIFI_PMU 5 -#define SCLK_UART0_PMU 6 -#define SCLK_PVTM_PMU 7 -#define PCLK_PMU_PRE 8 -#define SCLK_REF24M_PMU 9 -#define SCLK_USBPHY_REF 10 -#define SCLK_MIPIDSIPHY_REF 11 - -#define XIN24M_DIV 12 - -#define PCLK_GPIO0_PMU 20 -#define PCLK_UART0_PMU 21 - -#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_CORE_NOC 13 -#define SRST_STRC_A 14 -#define SRST_L2C 15 - -#define SRST_DAP 16 -#define SRST_CORE_PVTM 17 -#define SRST_GPU 18 -#define SRST_GPU_NIU 19 -#define SRST_UPCTL2 20 -#define SRST_UPCTL2_A 21 -#define SRST_UPCTL2_P 22 -#define SRST_MSCH 23 -#define SRST_MSCH_P 24 -#define SRST_DDRMON_P 25 -#define SRST_DDRSTDBY_P 26 -#define SRST_DDRSTDBY 27 -#define SRST_DDRGRF_p 28 -#define SRST_AXI_SPLIT_A 29 -#define SRST_AXI_CMD_A 30 -#define SRST_AXI_CMD_P 31 - -#define SRST_DDRPHY 32 -#define SRST_DDRPHYDIV 33 -#define SRST_DDRPHY_P 34 -#define SRST_VPU_A 36 -#define SRST_VPU_NIU_A 37 -#define SRST_VPU_H 38 -#define SRST_VPU_NIU_H 39 -#define SRST_VI_NIU_A 40 -#define SRST_VI_NIU_H 41 -#define SRST_ISP_H 42 -#define SRST_ISP 43 -#define SRST_CIF_A 44 -#define SRST_CIF_H 45 -#define SRST_CIF_PCLKIN 46 -#define SRST_MIPICSIPHY_P 47 - -#define SRST_VO_NIU_A 48 -#define SRST_VO_NIU_H 49 -#define SRST_VO_NIU_P 50 -#define SRST_VOPB_A 51 -#define SRST_VOPB_H 52 -#define SRST_VOPB 53 -#define SRST_PWM_VOPB 54 -#define SRST_VOPL_A 55 -#define SRST_VOPL_H 56 -#define SRST_VOPL 57 -#define SRST_RGA_A 58 -#define SRST_RGA_H 59 -#define SRST_RGA 60 -#define SRST_MIPIDSI_HOST_P 61 -#define SRST_MIPIDSIPHY_P 62 -#define SRST_VPU_CORE 63 - -#define SRST_PERI_NIU_A 64 -#define SRST_USB_NIU_H 65 -#define SRST_USB2OTG_H 66 -#define SRST_USB2OTG 67 -#define SRST_USB2OTG_ADP 68 -#define SRST_USB2HOST_H 69 -#define SRST_USB2HOST_ARB_H 70 -#define SRST_USB2HOST_AUX_H 71 -#define SRST_USB2HOST_EHCI 72 -#define SRST_USB2HOST 73 -#define SRST_USBPHYPOR 74 -#define SRST_USBPHY_OTG_PORT 75 -#define SRST_USBPHY_HOST_PORT 76 -#define SRST_USBPHY_GRF 77 -#define SRST_CPU_BOOST_P 78 -#define SRST_CPU_BOOST 79 - -#define SRST_MMC_NAND_NIU_H 80 -#define SRST_SDIO_H 81 -#define SRST_EMMC_H 82 -#define SRST_SFC_H 83 -#define SRST_SFC 84 -#define SRST_SDCARD_NIU_H 85 -#define SRST_SDMMC_H 86 -#define SRST_NANDC_H 89 -#define SRST_NANDC 90 -#define SRST_GMAC_NIU_A 92 -#define SRST_GMAC_NIU_P 93 -#define SRST_GMAC_A 94 - -#define SRST_PMU_NIU_P 96 -#define SRST_PMU_SGRF_P 97 -#define SRST_PMU_GRF_P 98 -#define SRST_PMU 99 -#define SRST_PMU_MEM_P 100 -#define SRST_PMU_GPIO0_P 101 -#define SRST_PMU_UART0_P 102 -#define SRST_PMU_CRU_P 103 -#define SRST_PMU_PVTM 104 -#define SRST_PMU_UART 105 -#define SRST_PMU_NIU_H 106 -#define SRST_PMU_DDR_FAIL_SAVE 107 -#define SRST_PMU_CORE_PERF_A 108 -#define SRST_PMU_CORE_GRF_P 109 -#define SRST_PMU_GPU_PERF_A 110 -#define SRST_PMU_GPU_GRF_P 111 - -#define SRST_CRYPTO_NIU_A 112 -#define SRST_CRYPTO_NIU_H 113 -#define SRST_CRYPTO_A 114 -#define SRST_CRYPTO_H 115 -#define SRST_CRYPTO 116 -#define SRST_CRYPTO_APK 117 -#define SRST_BUS_NIU_H 120 -#define SRST_USB_NIU_P 121 -#define SRST_BUS_TOP_NIU_P 122 -#define SRST_INTMEM_A 123 -#define SRST_GIC_A 124 -#define SRST_ROM_H 126 -#define SRST_DCF_A 127 - -#define SRST_DCF_P 128 -#define SRST_PDM_H 129 -#define SRST_PDM 130 -#define SRST_I2S0_H 131 -#define SRST_I2S0_TX 132 -#define SRST_I2S1_H 133 -#define SRST_I2S1 134 -#define SRST_I2S2_H 135 -#define SRST_I2S2 136 -#define SRST_UART1_P 137 -#define SRST_UART1 138 -#define SRST_UART2_P 139 -#define SRST_UART2 140 -#define SRST_UART3_P 141 -#define SRST_UART3 142 -#define SRST_UART4_P 143 - -#define SRST_UART4 144 -#define SRST_UART5_P 145 -#define SRST_UART5 146 -#define SRST_I2C0_P 147 -#define SRST_I2C0 148 -#define SRST_I2C1_P 149 -#define SRST_I2C1 150 -#define SRST_I2C2_P 151 -#define SRST_I2C2 152 -#define SRST_I2C3_P 153 -#define SRST_I2C3 154 -#define SRST_PWM0_P 157 -#define SRST_PWM0 158 -#define SRST_PWM1_P 159 - -#define SRST_PWM1 160 -#define SRST_SPI0_P 161 -#define SRST_SPI0 162 -#define SRST_SPI1_P 163 -#define SRST_SPI1 164 -#define SRST_SARADC_P 165 -#define SRST_SARADC 166 -#define SRST_TSADC_P 167 -#define SRST_TSADC 168 -#define SRST_TIMER_P 169 -#define SRST_TIMER0 170 -#define SRST_TIMER1 171 -#define SRST_TIMER2 172 -#define SRST_TIMER3 173 -#define SRST_TIMER4 174 -#define SRST_TIMER5 175 - -#define SRST_OTP_NS_P 176 -#define SRST_OTP_NS_SBPI 177 -#define SRST_OTP_NS_USR 178 -#define SRST_OTP_PHY_P 179 -#define SRST_OTP_PHY 180 -#define SRST_WDT_NS_P 181 -#define SRST_GPIO1_P 182 -#define SRST_GPIO2_P 183 -#define SRST_GPIO3_P 184 -#define SRST_SGRF_P 185 -#define SRST_GRF_P 186 -#define SRST_I2S0_RX 191 - -#endif diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h deleted file mode 100644 index 1a873432f96..00000000000 --- a/include/dt-bindings/clock/rockchip,rk808.h +++ /dev/null @@ -1,11 +0,0 @@ -/* - * This header provides constants clk index RK808 pmic clkout - */ -#ifndef _CLK_ROCKCHIP_RK808 -#define _CLK_ROCKCHIP_RK808 - -/* CLOCKOUT index */ -#define RK808_CLKOUT0 0 -#define RK808_CLKOUT1 1 - -#endif diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h deleted file mode 100644 index 30917a99ad2..00000000000 --- a/include/dt-bindings/power/px30-power.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ -#define __DT_BINDINGS_POWER_PX30_POWER_H__ - -/* VD_CORE */ -#define PX30_PD_A35_0 0 -#define PX30_PD_A35_1 1 -#define PX30_PD_A35_2 2 -#define PX30_PD_A35_3 3 -#define PX30_PD_SCU 4 - -/* VD_LOGIC */ -#define PX30_PD_USB 5 -#define PX30_PD_DDR 6 -#define PX30_PD_SDCARD 7 -#define PX30_PD_CRYPTO 8 -#define PX30_PD_GMAC 9 -#define PX30_PD_MMC_NAND 10 -#define PX30_PD_VPU 11 -#define PX30_PD_VO 12 -#define PX30_PD_VI 13 -#define PX30_PD_GPU 14 - -/* VD_PMU */ -#define PX30_PD_PMU 15 - -#endif diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h deleted file mode 100644 index 4b0914c0989..00000000000 --- a/include/dt-bindings/soc/rockchip,boot-mode.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ROCKCHIP_BOOT_MODE_H -#define __ROCKCHIP_BOOT_MODE_H - -/*high 24 bits is tag, low 8 bits is type*/ -#define REBOOT_FLAG 0x5242C300 -/* normal boot */ -#define BOOT_NORMAL (REBOOT_FLAG + 0) -/* enter bootloader rockusb mode */ -#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) -/* enter recovery */ -#define BOOT_RECOVERY (REBOOT_FLAG + 3) - /* enter fastboot mode */ -#define BOOT_FASTBOOT (REBOOT_FLAG + 9) - -#endif diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h deleted file mode 100644 index 668f199df9f..00000000000 --- a/include/dt-bindings/soc/rockchip,vop2.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ - -#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -#define __DT_BINDINGS_ROCKCHIP_VOP2_H - -#define ROCKCHIP_VOP2_EP_RGB0 1 -#define ROCKCHIP_VOP2_EP_HDMI0 2 -#define ROCKCHIP_VOP2_EP_EDP0 3 -#define ROCKCHIP_VOP2_EP_MIPI0 4 -#define ROCKCHIP_VOP2_EP_LVDS0 5 -#define ROCKCHIP_VOP2_EP_MIPI1 6 -#define ROCKCHIP_VOP2_EP_LVDS1 7 -#define ROCKCHIP_VOP2_EP_HDMI1 8 -#define ROCKCHIP_VOP2_EP_EDP1 9 -#define ROCKCHIP_VOP2_EP_DP0 10 -#define ROCKCHIP_VOP2_EP_DP1 11 - -#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ diff --git a/include/ext4fs.h b/include/ext4fs.h index d96edfd0576..41f9eb8bd33 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -34,12 +34,63 @@ struct disk_partition; #define EXT4_TOPDIR_FL 0x00020000 /* Top of directory hierarchies*/ #define EXT4_EXTENTS_FL 0x00080000 /* Inode uses extents */ #define EXT4_EXT_MAGIC 0xf30a -#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 + +#define EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001 +#define EXT4_FEATURE_RO_COMPAT_LARGE_FILE 0x0002 +#define EXT4_FEATURE_RO_COMPAT_BTREE_DIR 0x0004 +#define EXT4_FEATURE_RO_COMPAT_HUGE_FILE 0x0008 +#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM 0x0010 +#define EXT4_FEATURE_RO_COMPAT_DIR_NLINK 0x0020 +#define EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE 0x0040 +#define EXT4_FEATURE_RO_COMPAT_QUOTA 0x0100 +#define EXT4_FEATURE_RO_COMPAT_BIGALLOC 0x0200 #define EXT4_FEATURE_RO_COMPAT_METADATA_CSUM 0x0400 + +#define EXT4_FEATURE_INCOMPAT_FILETYPE 0x0002 +#define EXT4_FEATURE_INCOMPAT_RECOVER 0x0004 #define EXT4_FEATURE_INCOMPAT_EXTENTS 0x0040 #define EXT4_FEATURE_INCOMPAT_64BIT 0x0080 +#define EXT4_FEATURE_INCOMPAT_MMP 0x0100 +#define EXT4_FEATURE_INCOMPAT_FLEX_BG 0x0200 +#define EXT4_FEATURE_INCOMPAT_CSUM_SEED 0x2000 +#define EXT4_FEATURE_INCOMPAT_ENCRYPT 0x10000 + #define EXT4_INDIRECT_BLOCKS 12 +/* + * Incompat features supported by this implementation. + */ +#define EXT4_FEATURE_INCOMPAT_SUPP (EXT4_FEATURE_INCOMPAT_FILETYPE | \ + EXT4_FEATURE_INCOMPAT_RECOVER | \ + EXT4_FEATURE_INCOMPAT_EXTENTS | \ + EXT4_FEATURE_INCOMPAT_64BIT | \ + EXT4_FEATURE_INCOMPAT_FLEX_BG) + +/* + * Incompat features supported by this implementation only in a lazy + * way, good enough for reading files. + * + * - Multi mount protection (mmp) is not supported, but for read-only + * we get away with it. + * - Same for metadata_csum_seed and metadata_csum. + * - The implementation has also no clue about fscrypt, but it can read + * unencrypted files. Reading encrypted files will read garbage. + */ +#define EXT4_FEATURE_INCOMPAT_SUPP_LAZY_RO (EXT4_FEATURE_INCOMPAT_MMP | \ + EXT4_FEATURE_INCOMPAT_CSUM_SEED | \ + EXT4_FEATURE_INCOMPAT_ENCRYPT) + +/* + * Read-only compat features we support. + * If unknown ro compat features are detected, writing to the fs is denied. + */ +#define EXT4_FEATURE_RO_COMPAT_SUPP (EXT4_FEATURE_RO_COMPAT_SPARSE_SUPER | \ + EXT4_FEATURE_RO_COMPAT_LARGE_FILE | \ + EXT4_FEATURE_RO_COMPAT_HUGE_FILE | \ + EXT4_FEATURE_RO_COMPAT_GDT_CSUM | \ + EXT4_FEATURE_RO_COMPAT_DIR_NLINK | \ + EXT4_FEATURE_RO_COMPAT_EXTRA_ISIZE) + #define EXT4_BG_INODE_UNINIT 0x0001 #define EXT4_BG_BLOCK_UNINIT 0x0002 #define EXT4_BG_INODE_ZEROED 0x0004 diff --git a/include/i2c.h b/include/i2c.h index 4e59009cd93..91917f54be9 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -645,20 +645,8 @@ void i2c_early_init_f(void); */ #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ -#if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ -#define CFG_SYS_I2C_DIRECT_BUS 1 -#define CFG_SYS_I2C_MAX_HOPS 0 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) -#else -/* we use i2c muxes */ -#undef CFG_SYS_I2C_DIRECT_BUS -#endif - -/* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CFG_SYS_RTC_BUS_NUM) -#define CFG_SYS_RTC_BUS_NUM 0 -#endif struct i2c_adapter { void (*init)(struct i2c_adapter *adap, int speed, @@ -703,48 +691,13 @@ struct i2c_adapter { struct i2c_adapter *i2c_get_adapter(int index); -#ifndef CFG_SYS_I2C_DIRECT_BUS -struct i2c_mux { - int id; - char name[16]; -}; - -struct i2c_next_hop { - struct i2c_mux mux; - uint8_t chip; - uint8_t channel; -}; - -struct i2c_bus_hose { - int adapter; - struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS]; -}; -#define I2C_NULL_HOP {{-1, ""}, 0, 0} -extern struct i2c_bus_hose i2c_bus[]; - -#define I2C_ADAPTER(bus) i2c_bus[bus].adapter -#else #define I2C_ADAPTER(bus) bus -#endif #define I2C_BUS gd->cur_i2c_bus #define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus)) #define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus) #define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) -#ifndef CFG_SYS_I2C_DIRECT_BUS -#define I2C_MUX_PCA9540_ID 1 -#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"} -#define I2C_MUX_PCA9542_ID 2 -#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"} -#define I2C_MUX_PCA9544_ID 3 -#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"} -#define I2C_MUX_PCA9547_ID 4 -#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"} -#define I2C_MUX_PCA9548_ID 5 -#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"} -#endif - #ifndef I2C_SOFT_DECLARATIONS # if (defined(CONFIG_AT91RM9200) || \ defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ @@ -938,66 +891,6 @@ int i2c_set_bus_speed(unsigned int); unsigned int i2c_get_bus_speed(void); #endif /* CONFIG_SYS_I2C_LEGACY */ -/* - * only for backwardcompatibility, should go away if we switched - * completely to new multibus support. - */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS) -# if !defined(CFG_SYS_MAX_I2C_BUS) -# define CFG_SYS_MAX_I2C_BUS 2 -# endif -# define I2C_MULTI_BUS 1 -#else -# define CFG_SYS_MAX_I2C_BUS 1 -# define I2C_MULTI_BUS 0 -#endif - -/* NOTE: These two functions MUST be always_inline to avoid code growth! */ -static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline)); -static inline unsigned int I2C_GET_BUS(void) -{ - return I2C_MULTI_BUS ? i2c_get_bus_num() : 0; -} - -static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline)); -static inline void I2C_SET_BUS(unsigned int bus) -{ - if (I2C_MULTI_BUS) - i2c_set_bus_num(bus); -} - -/* Multi I2C definitions */ -enum { - I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7, - I2C_8, I2C_9, I2C_10, -}; - -/** - * Get FDT values for i2c bus. - * - * @param blob Device tree blbo - * Return: the number of I2C bus - */ -void board_i2c_init(const void *blob); - -/** - * Find the I2C bus number by given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * Return: the number of I2C bus (zero based), or -1 on error - */ -int i2c_get_bus_num_fdt(int node); - -/** - * Reset the I2C bus represented by the given a FDT I2C node. - * - * @param blob Device tree blbo - * @param node FDT I2C node to find - * Return: 0 if port was reset, -1 if not found - */ -int i2c_reset_port_fdt(const void *blob, int node); - #endif /* !CONFIG_DM_I2C */ #endif /* _I2C_H_ */ diff --git a/include/imx8image.h b/include/imx8image.h index 32064bfeeb8..85fb642ae39 100644 --- a/include/imx8image.h +++ b/include/imx8image.h @@ -162,6 +162,7 @@ enum imx8image_cmd { enum imx8image_core_type { CFG_CORE_INVALID, CFG_SCU, + CFG_PWR, CFG_M40, CFG_M41, CFG_A35, diff --git a/include/linux/compiler_types.h b/include/linux/compiler_types.h index 1a3060117f1..8b6ce9c11cd 100644 --- a/include/linux/compiler_types.h +++ b/include/linux/compiler_types.h @@ -71,6 +71,13 @@ extern void __chk_io_ptr(const volatile void __iomem *); #endif /* + * At least gcc 5.1 or clang 8 are needed. + */ +#ifndef COMPILER_HAS_GENERIC_BUILTIN_OVERFLOW +#error Unsupported compiler +#endif + +/* * Some architectures need to provide custom definitions of macros provided * by linux/compiler-*.h, and can do so using asm/compiler.h. We include that * conditionally rather than using an asm-generic wrapper in order to avoid diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 983a55ce70e..6751fb52c5a 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -26,6 +26,7 @@ #include <dm/device.h> #endif #include <dm/ofnode.h> +#include <blk.h> #define MAX_MTD_DEVICES 32 #endif @@ -412,6 +413,30 @@ int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf); +#if CONFIG_IS_ENABLED(MTD_BLOCK) +static inline struct mtd_info *blk_desc_to_mtd(struct blk_desc *bdesc) +{ + void *priv = dev_get_priv(bdesc->bdev); + + if (!priv) + return NULL; + + return *((struct mtd_info **)priv); +} + +int mtd_bind(struct udevice *dev, struct mtd_info **mtd); +#else +static inline struct mtd_info *blk_desc_to_mtd(struct blk_desc *bdesc) +{ + return NULL; +} + +static inline int mtd_bind(struct udevice *dev, struct mtd_info **mtd) +{ + return -EOPNOTSUPP; +} +#endif + int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); int mtd_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops); diff --git a/include/os.h b/include/os.h index 877404a6c13..4371270a1ee 100644 --- a/include/os.h +++ b/include/os.h @@ -29,7 +29,7 @@ int os_printf(const char *format, ...); * @fd: File descriptor as returned by os_open() * @buf: Buffer to place data * @count: Number of bytes to read - * Return: number of bytes read, or -1 on error + * Return: number of bytes read, or -errno on error */ ssize_t os_read(int fd, void *buf, size_t count); @@ -39,7 +39,7 @@ ssize_t os_read(int fd, void *buf, size_t count); * @fd: File descriptor as returned by os_open() * @buf: Buffer containing data to write * @count: Number of bytes to write - * Return: number of bytes written, or -1 on error + * Return: number of bytes written, or -errno on error */ ssize_t os_write(int fd, const void *buf, size_t count); @@ -49,7 +49,7 @@ ssize_t os_write(int fd, const void *buf, size_t count); * @fd: File descriptor as returned by os_open() * @offset: File offset (based on whence) * @whence: Position offset is relative to (see below) - * Return: new file offset + * Return: new file offset, or -errno on error */ off_t os_lseek(int fd, off_t offset, int whence); diff --git a/include/part.h b/include/part.h index b187ec4b4bd..54b986cee63 100644 --- a/include/part.h +++ b/include/part.h @@ -30,12 +30,17 @@ struct block_drvr { #define PART_TYPE_ISO 0x03 #define PART_TYPE_AMIGA 0x04 #define PART_TYPE_EFI 0x05 +#define PART_TYPE_MTD 0x06 +#define PART_TYPE_UBI 0x07 /* maximum number of partition entries supported by search */ #define DOS_ENTRY_NUMBERS 8 #define ISO_ENTRY_NUMBERS 64 #define MAC_ENTRY_NUMBERS 64 #define AMIGA_ENTRY_NUMBERS 8 +#define MTD_ENTRY_NUMBERS 64 +#define UBI_ENTRY_NUMBERS UBI_MAX_VOLUMES + /* * Type string for U-Boot bootable partitions */ diff --git a/include/spi.h b/include/spi.h index 7e38cc2a2ad..9e9851284c8 100644 --- a/include/spi.h +++ b/include/spi.h @@ -743,4 +743,6 @@ int dm_spi_get_mmap(struct udevice *dev, ulong *map_basep, uint *map_sizep, #define spi_get_ops(dev) ((struct dm_spi_ops *)(dev)->driver->ops) #define spi_emul_get_ops(dev) ((struct dm_spi_emul_ops *)(dev)->driver->ops) +int spi_get_env_dev(void); + #endif /* _SPI_H_ */ diff --git a/include/spl.h b/include/spl.h index 1eebea3f981..f92089b69ea 100644 --- a/include/spl.h +++ b/include/spl.h @@ -1073,4 +1073,20 @@ static inline bool spl_decompression_enabled(void) { return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA); } + +/** + * spl_write_upl_handoff() - Write a Universal Payload hand-off structure + * + * @spl_image: Information about the image being booted + * Return: 0 if OK, -ve on error + */ +int spl_write_upl_handoff(struct spl_image_info *spl_image); + +/** + * spl_upl_init() - Get UPL ready for information to be added + * + * This must be called before upl_add_image(), etc. + */ +void spl_upl_init(void); + #endif diff --git a/include/test/suites.h b/include/test/suites.h index 365d5f20dfe..2ceef577f7f 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -63,5 +63,6 @@ int do_ut_str(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_time(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_unicode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_upl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); #endif /* __TEST_SUITES_H__ */ diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index d7a8851094b..ea0db69c72a 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -48,11 +48,20 @@ extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp); extern int ubi_init(void); extern void ubi_exit(void); extern int ubi_part(char *part_name, const char *vid_header_offset); -extern int ubi_volume_write(char *volume, void *buf, size_t size); -extern int ubi_volume_read(char *volume, char *buf, size_t size); +extern int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size); +extern int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size); extern struct ubi_device *ubi_devices[]; int cmd_ubifs_mount(char *vol_name); int cmd_ubifs_umount(void); +#if IS_ENABLED(CONFIG_UBI_BLOCK) +int ubi_bind(struct udevice *dev); +#else +static inline int ubi_bind(struct udevice *dev) +{ + return -EOPNOTSUPP; +} +#endif + #endif diff --git a/include/upl.h b/include/upl.h new file mode 100644 index 00000000000..2ec5ef1b5cf --- /dev/null +++ b/include/upl.h @@ -0,0 +1,382 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * UPL handoff generation + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#ifndef __UPL_WRITE_H +#define __UPL_WRITE_H + +#ifndef USE_HOSTCC + +#include <alist.h> +#include <image.h> +#include <dm/ofnode_decl.h> + +struct unit_test_state; + +#define UPLP_ADDRESS_CELLS "#address-cells" +#define UPLP_SIZE_CELLS "#size-cells" + +#define UPLN_OPTIONS "options" +#define UPLN_UPL_PARAMS "upl-params" +#define UPLP_SMBIOS "smbios" +#define UPLP_ACPI "acpi" +#define UPLP_BOOTMODE "bootmode" +#define UPLP_ADDR_WIDTH "addr-width" +#define UPLP_ACPI_NVS_SIZE "acpi-nvs-size" + +#define UPLPATH_UPL_IMAGE "/options/upl-image" +#define UPLN_UPL_IMAGE "upl-image" +#define UPLN_IMAGE "image" +#define UPLP_FIT "fit" +#define UPLP_CONF_OFFSET "conf-offset" +#define UPLP_LOAD "load" +#define UPLP_SIZE "size" +#define UPLP_OFFSET "offset" +#define UPLP_DESCRIPTION "description" + +#define UPLN_MEMORY "memory" +#define UPLP_HOTPLUGGABLE "hotpluggable" + +#define UPLPATH_MEMORY_MAP "/memory-map" +#define UPLN_MEMORY_MAP "memory-map" +#define UPLP_USAGE "usage" + +#define UPLN_MEMORY_RESERVED "reserved-memory" +#define UPLPATH_MEMORY_RESERVED "/reserved-memory" +#define UPLP_NO_MAP "no-map" + +#define UPLN_SERIAL "serial" +#define UPLP_REG "reg" +#define UPLP_COMPATIBLE "compatible" +#define UPLP_CLOCK_FREQUENCY "clock-frequency" +#define UPLP_CURRENT_SPEED "current-speed" +#define UPLP_REG_IO_SHIFT "reg-io-shift" +#define UPLP_REG_OFFSET "reg-offset" +#define UPLP_REG_IO_WIDTH "reg-io-width" +#define UPLP_VIRTUAL_REG "virtual-reg" +#define UPLP_ACCESS_TYPE "access-type" + +#define UPLN_GRAPHICS "framebuffer" +#define UPLC_GRAPHICS "simple-framebuffer" +#define UPLP_WIDTH "width" +#define UPLP_HEIGHT "height" +#define UPLP_STRIDE "stride" +#define UPLP_GRAPHICS_FORMAT "format" + +/** + * enum upl_boot_mode - Encodes the boot mode + * + * Each is a bit number from the boot_mode mask + */ +enum upl_boot_mode { + UPLBM_FULL, + UPLBM_MINIMAL, + UPLBM_FAST, + UPLBM_DIAG, + UPLBM_DEFAULT, + UPLBM_S2, + UPLBM_S3, + UPLBM_S4, + UPLBM_S5, + UPLBM_FACTORY, + UPLBM_FLASH, + UPLBM_RECOVERY, + + UPLBM_COUNT, +}; + +/** + * struct upl_image - UPL image informaiton + * + * @load: Address image was loaded to + * @size: Size of image in bytes + * @offset: Offset of the image in the FIT (0=none) + * @desc: Description of the iamge (taken from the FIT) + */ +struct upl_image { + ulong load; + ulong size; + uint offset; + const char *description; +}; + +/** + * struct memregion - Information about a region of memory + * + * @base: Base address + * @size: Size in bytes + */ +struct memregion { + ulong base; + ulong size; +}; + +/** + * struct upl_mem - Information about physical-memory layout + * + * TODO: Figure out initial-mapped-area + * + * @region: Memory region list (struct memregion) + * @hotpluggable: true if hotpluggable + */ +struct upl_mem { + struct alist region; + bool hotpluggable; +}; + +/** + * enum upl_usage - Encodes the usage + * + * Each is a bit number from the usage mask + */ +enum upl_usage { + UPLUS_ACPI_RECLAIM, + UPLUS_ACPI_NVS, + UPLUS_BOOT_CODE, + UPLUS_BOOT_DATA, + UPLUS_RUNTIME_CODE, + UPLUS_RUNTIME_DATA, + UPLUS_COUNT +}; + +/** + * struct upl_memmap - Information about logical-memory layout + * + * @name: Node name to use + * @region: Memory region list (struct memregion) + * @usage: Memory-usage mask (enum upl_usage) + */ +struct upl_memmap { + const char *name; + struct alist region; + uint usage; +}; + +/** + * struct upl_memres - Reserved memory + * + * @name: Node name to use + * @region: Reserved memory region list (struct memregion) + * @no_map: true to indicate that a virtual mapping must not be created + */ +struct upl_memres { + const char *name; + struct alist region; + bool no_map; +}; + +enum upl_serial_access_type { + UPLSAT_MMIO, + UPLSAT_IO, +}; + +/* serial defaults */ +enum { + UPLD_REG_IO_SHIFT = 0, + UPLD_REG_OFFSET = 0, + UPLD_REG_IO_WIDTH = 1, +}; + +/** + * enum upl_access_type - Access types + * + * @UPLAT_MMIO: Memory-mapped I/O + * @UPLAT_IO: Separate I/O + */ +enum upl_access_type { + UPLAT_MMIO, + UPLAT_IO, +}; + +/** + * struct upl_serial - Serial console + * + * @compatible: Compatible string (NULL if there is no serial console) + * @clock_frequency: Input clock frequency of UART + * @current_speed: Current baud rate of UART + * @reg: List of base address and size of registers (struct memregion) + * @reg_shift_log2: log2 of distance between each register + * @reg_offset: Offset of registers from the base address + * @reg_width: Register width in bytes + * @virtual_reg: Virtual register access (0 for none) + * @access_type: Register access type to use + */ +struct upl_serial { + const char *compatible; + uint clock_frequency; + uint current_speed; + struct alist reg; + uint reg_io_shift; + uint reg_offset; + uint reg_io_width; + ulong virtual_reg; + enum upl_serial_access_type access_type; +}; + +/** + * enum upl_graphics_format - Graphics formats + * + * @UPLGF_ARGB32: 32bpp format using 0xaarrggbb + * @UPLGF_ABGR32: 32bpp format using 0xaabbggrr + * @UPLGF_ARGB64: 64bpp format using 0xaaaabbbbggggrrrr + */ +enum upl_graphics_format { + UPLGF_ARGB32, + UPLGF_ABGR32, + UPLGF_ABGR64, +}; + +/** + * @reg: List of base address and size of registers (struct memregion) + * @width: Width of display in pixels + * @height: Height of display in pixels + * @stride: Number of bytes from one line to the next + * @format: Pixel format + */ +struct upl_graphics { + struct alist reg; + uint width; + uint height; + uint stride; + enum upl_graphics_format format; +}; + +/* + * Information about the UPL state + * + * @addr_cells: Number of address cells used in the handoff + * @size_cells: Number of size cells used in the handoff + * @bootmode: Boot-mode mask (enum upl_boot_mode) + * @fit: Address of FIT image that was loaded + * @conf_offset: Offset in FIT of the configuration that was selected + * @addr_width: Adress-bus width of machine, e.g. 46 for 46 bits + * @acpi_nvs_size: Size of the ACPI non-volatile-storage area in bytes + * @image: Information about each image (struct upl_image) + * @mem: Information about physical-memory regions (struct upl_mem) + * @nennap: Information about logical-memory regions (struct upl_memmap) + * @nennap: Information about reserved-memory regions (struct upl_memres) + */ +struct upl { + int addr_cells; + int size_cells; + + ulong smbios; + ulong acpi; + uint bootmode; + ulong fit; + uint conf_offset; + uint addr_width; + uint acpi_nvs_size; + + struct alist image; + struct alist mem; + struct alist memmap; + struct alist memres; + struct upl_serial serial; + struct upl_graphics graphics; +}; + +/** + * upl_write_handoff() - Write a Unversal Payload handoff structure + * + * upl: UPL state to write + * @root: root node to write it to + * @skip_existing: Avoid recreating any nodes which already exist in the + * devicetree. For example, if there is a serial node, just leave it alone, + * since don't need to create a new one + * Return: 0 on success, -ve on error + */ +int upl_write_handoff(const struct upl *upl, ofnode root, bool skip_existing); + +/** + * upl_create_handoff_tree() - Write a Unversal Payload handoff structure + * + * upl: UPL state to write + * @treep: Returns a new tree containing the handoff + * Return: 0 on success, -ve on error + */ +int upl_create_handoff_tree(const struct upl *upl, oftree *treep); + +/** + * upl_read_handoff() - Read a Unversal Payload handoff structure + * + * upl: UPL state to read into + * @tree: Devicetree containing the data to read + * Return: 0 on success, -ve on error + */ +int upl_read_handoff(struct upl *upl, oftree tree); + +/** + * upl_get_test_data() - Fill a UPL with some test data + * + * @uts: Test state (can be uninited) + * @upl: Returns test data + * Return: 0 on success, 1 on error + */ +int upl_get_test_data(struct unit_test_state *uts, struct upl *upl); +#endif /* USE_HOSTCC */ + +#if CONFIG_IS_ENABLED(UPL) && defined(CONFIG_SPL_BUILD) + +/** + * upl_set_fit_info() - Set up basic info about the FIT + * + * @fit: Address of FIT + * @conf_offset: Configuration node being used + * @entry_addr: Entry address for next phase + */ +void upl_set_fit_info(ulong fit, int conf_offset, ulong entry_addr); + +/** + * upl_set_fit_addr() - Set up the address of the FIT + * + * @fit: Address of FIT + */ +void upl_set_fit_addr(ulong fit); + +#else +static inline void upl_set_fit_addr(ulong fit) {} +static inline void upl_set_fit_info(ulong fit, int conf_offset, + ulong entry_addr) {} +#endif /* UPL && SPL */ + +/** + * _upl_add_image() - Internal function to add a new image to the UPL + * + * @node: Image node offset in FIT + * @load_addr: Address to which images was loaded + * @size: Image size in bytes + * @desc: Description of image + * Return: 0 if OK, -ENOMEM if out of memory + */ +int _upl_add_image(int node, ulong load_addr, ulong size, const char *desc); + +/** + * upl_add_image() - Add a new image to the UPL + * + * @fit: Pointer to FIT + * @node: Image node offset in FIT + * @load_addr: Address to which images was loaded + * @size: Image size in bytes + * Return: 0 if OK, -ENOMEM if out of memory + */ +static inline int upl_add_image(const void *fit, int node, ulong load_addr, + ulong size) +{ + if (CONFIG_IS_ENABLED(UPL) && IS_ENABLED(CONFIG_SPL_BUILD)) { + const char *desc = fdt_getprop(fit, node, FIT_DESC_PROP, NULL); + + return _upl_add_image(node, load_addr, size, desc); + } + + return 0; +} + +/** upl_init() - Set up a UPL struct */ +void upl_init(struct upl *upl); + +#endif /* __UPL_WRITE_H */ diff --git a/include/zynqpl.h b/include/zynqpl.h index d7dc064585e..08d067d8757 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -20,9 +20,11 @@ extern struct xilinx_fpga_op zynq_op; #define XILINX_ZYNQ_XC7Z007S 0x3 #define XILINX_ZYNQ_XC7Z010 0x2 +#define XILINX_ZYNQ_XC7Z010_LR 0x4 #define XILINX_ZYNQ_XC7Z012S 0x1c #define XILINX_ZYNQ_XC7Z014S 0x8 #define XILINX_ZYNQ_XC7Z015 0x1b +#define XILINX_ZYNQ_XC7Z020_LR 0x9 #define XILINX_ZYNQ_XC7Z020 0x7 #define XILINX_ZYNQ_XC7Z030 0xc #define XILINX_ZYNQ_XC7Z035 0x12 @@ -32,9 +34,11 @@ extern struct xilinx_fpga_op zynq_op; /* Device Image Sizes */ #define XILINX_XC7Z007S_SIZE 16669920/8 #define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z010_LR_SIZE 16669920/8 #define XILINX_XC7Z012S_SIZE 28085344/8 #define XILINX_XC7Z014S_SIZE 32364512/8 #define XILINX_XC7Z015_SIZE 28085344/8 +#define XILINX_XC7Z020_LR_SIZE 32364512/8 #define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z030_SIZE 47839328/8 #define XILINX_XC7Z035_SIZE 106571232/8 @@ -44,9 +48,11 @@ extern struct xilinx_fpga_op zynq_op; /* Device Names */ #define XILINX_XC7Z007S_NAME "7z007s" #define XILINX_XC7Z010_NAME "7z010" +#define XILINX_XC7Z010_LR_NAME "xc7z010_lr" #define XILINX_XC7Z012S_NAME "7z012s" #define XILINX_XC7Z014S_NAME "7z014s" #define XILINX_XC7Z015_NAME "7z015" +#define XILINX_XC7Z020_LR_NAME "xa7z020_lr" #define XILINX_XC7Z020_NAME "7z020" #define XILINX_XC7Z030_NAME "7z030" #define XILINX_XC7Z035_NAME "7z035" diff --git a/lib/Makefile b/lib/Makefile index e389ad014f8..81b503ab526 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -147,6 +147,7 @@ endif obj-$(CONFIG_$(SPL_)OID_REGISTRY) += oid_registry.o obj-y += abuf.o +obj-y += alist.o obj-y += date.o obj-y += rtc-lib.o obj-$(CONFIG_LIB_ELF) += elf.o diff --git a/lib/alist.c b/lib/alist.c new file mode 100644 index 00000000000..b7928cad520 --- /dev/null +++ b/lib/alist.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Handles a contiguous list of pointers which be allocated and freed + * + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <alist.h> +#include <display_options.h> +#include <malloc.h> +#include <stdio.h> +#include <string.h> + +enum { + ALIST_INITIAL_SIZE = 4, /* default size of unsized list */ +}; + +bool alist_init(struct alist *lst, uint obj_size, uint start_size) +{ + /* Avoid realloc for the initial size to help malloc_simple */ + memset(lst, '\0', sizeof(struct alist)); + if (start_size) { + lst->data = calloc(obj_size, start_size); + if (!lst->data) { + lst->flags = ALISTF_FAIL; + return false; + } + lst->alloc = start_size; + } + lst->obj_size = obj_size; + + return true; +} + +void alist_uninit(struct alist *lst) +{ + free(lst->data); + + /* Clear fields to avoid any confusion */ + memset(lst, '\0', sizeof(struct alist)); +} + +/** + * alist_expand_to() - Expand a list to the given size + * + * @lst: List to modify + * @inc_by: Amount to expand to + * Return: true if OK, false if out of memory + */ +static bool alist_expand_to(struct alist *lst, uint new_alloc) +{ + void *new_data; + + if (lst->flags & ALISTF_FAIL) + return false; + + /* avoid using realloc() since it increases code size */ + new_data = malloc(lst->obj_size * new_alloc); + if (!new_data) { + lst->flags |= ALISTF_FAIL; + return false; + } + + memcpy(new_data, lst->data, lst->obj_size * lst->alloc); + free(lst->data); + + memset(new_data + lst->obj_size * lst->alloc, '\0', + lst->obj_size * (new_alloc - lst->alloc)); + lst->alloc = new_alloc; + lst->data = new_data; + + return true; +} + +bool alist_expand_by(struct alist *lst, uint inc_by) +{ + return alist_expand_to(lst, lst->alloc + inc_by); +} + +/** + * alist_expand_min() - Expand to at least the provided size + * + * Expands to the lowest power of two which can incorporate the new size + * + * @lst: alist to expand + * @min_alloc: Minimum new allocated size; if 0 then ALIST_INITIAL_SIZE is used + * Return: true if OK, false if out of memory + */ +static bool alist_expand_min(struct alist *lst, uint min_alloc) +{ + uint new_alloc; + + for (new_alloc = lst->alloc ?: ALIST_INITIAL_SIZE; + new_alloc < min_alloc;) + new_alloc *= 2; + + return alist_expand_to(lst, new_alloc); +} + +const void *alist_get_ptr(const struct alist *lst, uint index) +{ + if (index >= lst->count) + return NULL; + + return lst->data + index * lst->obj_size; +} + +void *alist_ensure_ptr(struct alist *lst, uint index) +{ + uint minsize = index + 1; + void *ptr; + + if (index >= lst->alloc && !alist_expand_min(lst, minsize)) + return NULL; + + ptr = lst->data + index * lst->obj_size; + if (minsize >= lst->count) + lst->count = minsize; + + return ptr; +} + +void *alist_add_placeholder(struct alist *lst) +{ + return alist_ensure_ptr(lst, lst->count); +} + +void *alist_add_ptr(struct alist *lst, void *obj) +{ + void *ptr; + + ptr = alist_add_placeholder(lst); + if (!ptr) + return NULL; + memcpy(ptr, obj, lst->obj_size); + + return ptr; +} + +void *alist_uninit_move_ptr(struct alist *alist, size_t *countp) +{ + void *ptr; + + if (countp) + *countp = alist->count; + if (!alist->count) { + alist_uninit(alist); + return NULL; + } + + ptr = alist->data; + + /* Clear everything out so there is no record of the data */ + alist_init(alist, alist->obj_size, 0); + + return ptr; +} diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index eedc5f39549..4f52284b4c6 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -2509,16 +2509,12 @@ static efi_status_t EFIAPI efi_protocols_per_handle( return EFI_EXIT(EFI_INVALID_PARAMETER); *protocol_buffer = NULL; - *protocol_buffer_count = 0; efiobj = efi_search_obj(handle); if (!efiobj) return EFI_EXIT(EFI_INVALID_PARAMETER); - /* Count protocols */ - list_for_each(protocol_handle, &efiobj->protocols) { - ++*protocol_buffer_count; - } + *protocol_buffer_count = list_count_nodes(&efiobj->protocols); /* Copy GUIDs */ if (*protocol_buffer_count) { diff --git a/lib/efi_loader/efi_fdt.c b/lib/efi_loader/efi_fdt.c index c5ecade3aeb..f882622fdad 100644 --- a/lib/efi_loader/efi_fdt.c +++ b/lib/efi_loader/efi_fdt.c @@ -14,7 +14,7 @@ #include <vsprintf.h> /** - * distro_efi_get_fdt_name() - get the filename for reading the .dtb file + * efi_get_distro_fdt_name() - get the filename for reading the .dtb file * * @fname: buffer for filename * @size: buffer size diff --git a/lib/elf.c b/lib/elf.c index dc13935e103..28ec87b8e48 100644 --- a/lib/elf.c +++ b/lib/elf.c @@ -90,6 +90,10 @@ unsigned long load_elf64_image_phdr(unsigned long addr) void *dst = (void *)(ulong)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; + /* Only load PT_LOAD program header */ + if (phdr->p_type != PT_LOAD) + continue; + debug("Loading phdr %i to 0x%p (%lu bytes)\n", i, dst, (ulong)phdr->p_filesz); if (phdr->p_filesz) @@ -205,6 +209,10 @@ unsigned long load_elf_image_phdr(unsigned long addr) void *dst = (void *)(uintptr_t)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; + /* Only load PT_LOAD program header */ + if (phdr->p_type != PT_LOAD) + continue; + debug("Loading phdr %i to 0x%p (%i bytes)\n", i, dst, phdr->p_filesz); if (phdr->p_filesz) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 6865f78c70d..5edc8dd2f9f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1685,6 +1685,7 @@ int fdtdec_setup(void) gd->fdt_src = FDTSRC_BLOBLIST; log_debug("Devicetree is in bloblist at %p\n", gd->fdt_blob); + ret = 0; } else { log_debug("No FDT found in bloblist\n"); ret = -ENOENT; diff --git a/lib/strto.c b/lib/strto.c index 5157332d6c1..f83ac67c666 100644 --- a/lib/strto.c +++ b/lib/strto.c @@ -236,12 +236,14 @@ const char **str_to_list(const char *instr) return NULL; /* count the number of space-separated strings */ - for (count = *str != '\0', p = str; *p; p++) { + for (count = 0, p = str; *p; p++) { if (*p == ' ') { count++; *p = '\0'; } } + if (p != str && p[-1]) + count++; /* allocate the pointer array, allowing for a NULL terminator */ ptr = calloc(count + 1, sizeof(char *)); diff --git a/net/wget.c b/net/wget.c index f1dd7abeff6..945bfd26693 100644 --- a/net/wget.c +++ b/net/wget.c @@ -244,7 +244,7 @@ static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, pkt_in_q = (void *)image_load_addr + PKT_QUEUE_OFFSET + (pkt_q_idx * PKT_QUEUE_PACKET_SIZE); - ptr1 = map_sysmem((phys_addr_t)pkt_in_q, len); + ptr1 = map_sysmem((ulong)pkt_in_q, len); memcpy(ptr1, pkt, len); unmap_sysmem(ptr1); @@ -314,9 +314,8 @@ static void wget_connected(uchar *pkt, unsigned int tcp_seq_num, for (i = 0; i < pkt_q_idx; i++) { int err; - ptr1 = map_sysmem( - (phys_addr_t)(pkt_q[i].pkt), - pkt_q[i].len); + ptr1 = map_sysmem((ulong)pkt_q[i].pkt, + pkt_q[i].len); err = store_block(ptr1, pkt_q[i].tcp_seq_num - initial_data_seq_num, diff --git a/scripts/decodecode b/scripts/decodecode index 9cef558528a..6364218b217 100755 --- a/scripts/decodecode +++ b/scripts/decodecode @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # SPDX-License-Identifier: GPL-2.0 # Disassemble the Code: line in Linux oopses # usage: decodecode < oops.file @@ -6,6 +6,9 @@ # options: set env. variable AFLAGS=options to pass options to "as"; # e.g., to decode an i386 oops on an x86_64 system, use: # AFLAGS=--32 decodecode < 386.oops +# PC=hex - the PC (program counter) the oops points to + +faultlinenum=1 cleanup() { rm -f $T $T.s $T.o $T.oo $T.aa $T.dis @@ -60,15 +63,27 @@ case $width in 4) type=4byte ;; esac +if [ -z "$ARCH" ]; then + case `uname -m` in + aarch64*) ARCH=arm64 ;; + arm*) ARCH=arm ;; + loongarch*) ARCH=loongarch ;; + esac +fi + +# Params: (tmp_file, pc_sub) disas() { - ${CROSS_COMPILE}as $AFLAGS -o $1.o $1.s > /dev/null 2>&1 + t=$1 + pc_sub=$2 + + ${CROSS_COMPILE}as $AFLAGS -o $t.o $t.s > /dev/null 2>&1 if [ "$ARCH" = "arm" ]; then if [ $width -eq 2 ]; then OBJDUMPFLAGS="-M force-thumb" fi - ${CROSS_COMPILE}strip $1.o + ${CROSS_COMPILE}strip $t.o fi if [ "$ARCH" = "arm64" ]; then @@ -76,11 +91,120 @@ disas() { type=inst fi - ${CROSS_COMPILE}strip $1.o + ${CROSS_COMPILE}strip $t.o + fi + + if [ "$ARCH" = "riscv" ]; then + OBJDUMPFLAGS="-M no-aliases --section=.text -D" + ${CROSS_COMPILE}strip $t.o + fi + + if [ "$ARCH" = "loongarch" ]; then + ${CROSS_COMPILE}strip $t.o + fi + + if [ $pc_sub -ne 0 ]; then + if [ $PC ]; then + adj_vma=$(( $PC - $pc_sub )) + OBJDUMPFLAGS="$OBJDUMPFLAGS --adjust-vma=$adj_vma" + fi fi - ${CROSS_COMPILE}objdump $OBJDUMPFLAGS -S $1.o | \ - grep -v "/tmp\|Disassembly\|\.text\|^$" > $1.dis 2>&1 + ${CROSS_COMPILE}objdump $OBJDUMPFLAGS -S $t.o | \ + grep -v "/tmp\|Disassembly\|\.text\|^$" > $t.dis 2>&1 +} + +# Match the maximum number of opcode bytes from @op_bytes contained within +# @opline +# +# Params: +# @op_bytes: The string of bytes from the Code: line +# @opline: The disassembled line coming from objdump +# +# Returns: +# The max number of opcode bytes from the beginning of @op_bytes which match +# the opcode bytes in the objdump line. +get_substr_opcode_bytes_num() +{ + local op_bytes=$1 + local opline=$2 + + local retval=0 + substr="" + + for opc in $op_bytes; + do + substr+="$opc" + + opcode="$substr" + if [ "$ARCH" = "riscv" ]; then + opcode=$(echo $opcode | tr ' ' '\n' | tac | tr -d '\n') + fi + + # return if opcode bytes do not match @opline anymore + if ! echo $opline | grep -q "$opcode"; + then + break + fi + + # add trailing space + substr+=" " + retval=$((retval+1)) + done + + return $retval +} + +# Return the line number in objdump output to where the IP marker in the Code: +# line points to +# +# Params: +# @all_code: code in bytes without the marker +# @dis_file: disassembled file +# @ip_byte: The byte to which the IP points to +get_faultlinenum() +{ + local all_code="$1" + local dis_file="$2" + + # num bytes including IP byte + local num_bytes_ip=$(( $3 + 1 * $width )) + + # Add the two header lines (we're counting from 1). + local retval=3 + + # remove marker + all_code=$(echo $all_code | sed -e 's/[<>()]//g') + + while read line + do + get_substr_opcode_bytes_num "$all_code" "$line" + ate_opcodes=$? + + if ! (( $ate_opcodes )); then + continue + fi + + num_bytes_ip=$((num_bytes_ip - ($ate_opcodes * $width) )) + if (( $num_bytes_ip <= 0 )); then + break + fi + + # Delete matched opcode bytes from all_code. For that, compute + # how many chars those opcodes are represented by and include + # trailing space. + # + # a byte is 2 chars, ate_opcodes is also the number of trailing + # spaces + del_chars=$(( ($ate_opcodes * $width * 2) + $ate_opcodes )) + + all_code=$(echo $all_code | sed -e "s!^.\{$del_chars\}!!") + + let "retval+=1" + + done < $dis_file + + return $retval } marker=`expr index "$code" "\<"` @@ -90,36 +214,39 @@ fi touch $T.oo if [ $marker -ne 0 ]; then + # How many bytes to subtract from the program counter + # in order to get to the beginning virtual address of the + # Code: + pc_sub=$(( (($marker - 1) / (2 * $width + 1)) * $width )) echo All code >> $T.oo echo ======== >> $T.oo beforemark=`echo "$code"` echo -n " .$type 0x" > $T.s + echo $beforemark | sed -e 's/ /,0x/g; s/[<>()]//g' >> $T.s - disas $T + + disas $T $pc_sub + cat $T.dis >> $T.oo - rm -f $T.o $T.s $T.dis -# and fix code at-and-after marker + get_faultlinenum "$code" "$T.dis" $pc_sub + faultlinenum=$? + + # and fix code at-and-after marker code=`echo "$code" | cut -c$((${marker} + 1))-` + + rm -f $T.o $T.s $T.dis fi + echo Code starting with the faulting instruction > $T.aa echo =========================================== >> $T.aa -code=`echo $code | sed -e 's/ [<(]/ /;s/[>)] / /;s/ /,0x/g; s/[>)]$//'` +code=`echo $code | sed -e 's/\r//;s/ [<(]/ /;s/[>)] / /;s/ /,0x/g; s/[>)]$//'` echo -n " .$type 0x" > $T.s echo $code >> $T.s -disas $T +disas $T 0 cat $T.dis >> $T.aa -# (lines of whole $T.oo) - (lines of $T.aa, i.e. "Code starting") + 3, -# i.e. the title + the "===..=" line (sed is counting from 1, 0 address is -# special) -faultlinenum=$(( $(wc -l $T.oo | cut -d" " -f1) - \ - $(wc -l $T.aa | cut -d" " -f1) + 3)) - -faultline=`cat $T.dis | head -1 | cut -d":" -f2-` -faultline=`echo "$faultline" | sed -e 's/\[/\\\[/g; s/\]/\\\]/g'` - -cat $T.oo | sed -e "${faultlinenum}s/^\(.*:\)\(.*\)/\1\*\2\t\t<-- trapping instruction/" +cat $T.oo | sed -e "${faultlinenum}s/^\([^:]*:\)\(.*\)/\1\*\2\t\t<-- trapping instruction/" echo cat $T.aa cleanup diff --git a/test/boot/Makefile b/test/boot/Makefile index 068522cb9e0..8ec5daa7bfe 100644 --- a/test/boot/Makefile +++ b/test/boot/Makefile @@ -13,3 +13,5 @@ ifdef CONFIG_OF_LIVE obj-$(CONFIG_BOOTMETH_VBE_SIMPLE) += vbe_simple.o endif obj-$(CONFIG_BOOTMETH_VBE) += vbe_fixup.o + +obj-$(CONFIG_UPL) += upl.o diff --git a/test/boot/upl.c b/test/boot/upl.c new file mode 100644 index 00000000000..364fb0526e4 --- /dev/null +++ b/test/boot/upl.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * UPL handoff testing + * + * Copyright 2024 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <abuf.h> +#include <mapmem.h> +#include <upl.h> +#include <dm/ofnode.h> +#include <test/suites.h> +#include <test/test.h> +#include <test/ut.h> +#include "bootstd_common.h" + +/* Declare a new upl test */ +#define UPL_TEST(_name, _flags) UNIT_TEST(_name, _flags, upl_test) + +static int add_region(struct unit_test_state *uts, struct alist *lst, + ulong base, ulong size) +{ + struct memregion region; + + region.base = base; + region.size = size; + ut_assertnonnull(alist_add(lst, region)); + + return 0; +} + +int upl_get_test_data(struct unit_test_state *uts, struct upl *upl) +{ + struct upl_memmap memmap; + struct upl_memres memres; + struct upl_image img; + struct upl_mem mem; + + upl_init(upl); + + upl->addr_cells = 1; + upl->size_cells = 1; + upl->smbios = 0x123; + upl->acpi = 0x456; + upl->bootmode = BIT(UPLBM_DEFAULT) | BIT(UPLBM_S3); + upl->fit = 0x789; + upl->conf_offset = 0x234; + upl->addr_width = 46; + upl->acpi_nvs_size = 0x100; + + /* image[0] */ + img.load = 0x1; + img.size = 0x2; + img.offset = 0x3; + img.description = "U-Boot"; + ut_assertnonnull(alist_add(&upl->image, img)); + + /* image[1] */ + img.load = 0x4; + img.size = 0x5; + img.offset = 0x6; + img.description = "ATF"; + ut_assertnonnull(alist_add(&upl->image, img)); + + /* mem[0] : 3 regions */ + memset(&mem, '\0', sizeof(mem)); + alist_init_struct(&mem.region, struct memregion); + ut_assertok(add_region(uts, &mem.region, 0x10, 0x20)); + ut_assertok(add_region(uts, &mem.region, 0x30, 0x40)); + ut_assertok(add_region(uts, &mem.region, 0x40, 0x50)); + ut_assertnonnull(alist_add(&upl->mem, mem)); + + /* mem[0] : 1 region */ + alist_init_struct(&mem.region, struct memregion); + ut_assertok(add_region(uts, &mem.region, 0x70, 0x80)); + mem.hotpluggable = true; + ut_assertnonnull(alist_add(&upl->mem, mem)); + mem.hotpluggable = false; + + /* memmap[0] : 5 regions */ + alist_init_struct(&memmap.region, struct memregion); + memmap.name = "acpi"; + memmap.usage = BIT(UPLUS_ACPI_RECLAIM); + ut_assertok(add_region(uts, &memmap.region, 0x11, 0x12)); + ut_assertok(add_region(uts, &memmap.region, 0x13, 0x14)); + ut_assertok(add_region(uts, &memmap.region, 0x15, 0x16)); + ut_assertok(add_region(uts, &memmap.region, 0x17, 0x18)); + ut_assertok(add_region(uts, &memmap.region, 0x19, 0x1a)); + ut_assertnonnull(alist_add(&upl->memmap, memmap)); + + /* memmap[1] : 1 region */ + memmap.name = "u-boot"; + memmap.usage = BIT(UPLUS_BOOT_DATA); + alist_init_struct(&memmap.region, struct memregion); + ut_assertok(add_region(uts, &memmap.region, 0x21, 0x22)); + ut_assertnonnull(alist_add(&upl->memmap, memmap)); + + /* memmap[2] : 1 region */ + alist_init_struct(&memmap.region, struct memregion); + memmap.name = "efi"; + memmap.usage = BIT(UPLUS_RUNTIME_CODE); + ut_assertok(add_region(uts, &memmap.region, 0x23, 0x24)); + ut_assertnonnull(alist_add(&upl->memmap, memmap)); + + /* memmap[3]: 2 regions */ + alist_init_struct(&memmap.region, struct memregion); + memmap.name = "empty"; + memmap.usage = 0; + ut_assertok(add_region(uts, &memmap.region, 0x25, 0x26)); + ut_assertok(add_region(uts, &memmap.region, 0x27, 0x28)); + ut_assertnonnull(alist_add(&upl->memmap, memmap)); + + /* memmap[4]: 1 region */ + alist_init_struct(&memmap.region, struct memregion); + memmap.name = "acpi-things"; + memmap.usage = BIT(UPLUS_RUNTIME_CODE) | BIT(UPLUS_ACPI_NVS); + ut_assertok(add_region(uts, &memmap.region, 0x29, 0x2a)); + ut_assertnonnull(alist_add(&upl->memmap, memmap)); + + /* memres[0]: 1 region */ + alist_init_struct(&memres.region, struct memregion); + memset(&memres, '\0', sizeof(memres)); + memres.name = "mmio"; + ut_assertok(add_region(uts, &memres.region, 0x2b, 0x2c)); + ut_assertnonnull(alist_add(&upl->memres, memres)); + + /* memres[1]: 2 regions */ + alist_init_struct(&memres.region, struct memregion); + memres.name = "memory"; + ut_assertok(add_region(uts, &memres.region, 0x2d, 0x2e)); + ut_assertok(add_region(uts, &memres.region, 0x2f, 0x30)); + memres.no_map = true; + ut_assertnonnull(alist_add(&upl->memres, memres)); + + upl->serial.compatible = "ns16550a"; + upl->serial.clock_frequency = 1843200; + upl->serial.current_speed = 115200; + alist_init_struct(&upl->serial.reg, struct memregion); + ut_assertok(add_region(uts, &upl->serial.reg, 0xf1de0000, 0x100)); + upl->serial.reg_io_shift = 2; + upl->serial.reg_offset = 0x40; + upl->serial.reg_io_width = 1; + upl->serial.virtual_reg = 0x20000000; + upl->serial.access_type = UPLSAT_MMIO; + + alist_init_struct(&upl->graphics.reg, struct memregion); + ut_assertok(add_region(uts, &upl->graphics.reg, 0xd0000000, 0x10000000)); + upl->graphics.width = 1280; + upl->graphics.height = 1280; + upl->graphics.stride = upl->graphics.width * 4; + upl->graphics.format = UPLGF_ARGB32; + + return 0; +} + +static int compare_upl_image(struct unit_test_state *uts, + const struct upl_image *base, + const struct upl_image *cmp) +{ + ut_asserteq(base->load, cmp->load); + ut_asserteq(base->size, cmp->size); + ut_asserteq(base->offset, cmp->offset); + ut_asserteq_str(base->description, cmp->description); + + return 0; +} + +static int compare_upl_memregion(struct unit_test_state *uts, + const struct memregion *base, + const struct memregion *cmp) +{ + ut_asserteq(base->base, cmp->base); + ut_asserteq(base->size, cmp->size); + + return 0; +} + +static int compare_upl_mem(struct unit_test_state *uts, + const struct upl_mem *base, + const struct upl_mem *cmp) +{ + int i; + + ut_asserteq(base->region.count, cmp->region.count); + ut_asserteq(base->hotpluggable, cmp->hotpluggable); + for (i = 0; i < base->region.count; i++) { + ut_assertok(compare_upl_memregion(uts, + alist_get(&base->region, i, struct memregion), + alist_get(&cmp->region, i, struct memregion))); + } + + return 0; +} + +static int check_device_name(struct unit_test_state *uts, const char *base, + const char *cmp) +{ + const char *p; + + p = strchr(cmp, '@'); + if (p) { + ut_assertnonnull(p); + ut_asserteq_strn(base, cmp); + ut_asserteq(p - cmp, strlen(base)); + } else { + ut_asserteq_str(base, cmp); + } + + return 0; +} + +static int compare_upl_memmap(struct unit_test_state *uts, + const struct upl_memmap *base, + const struct upl_memmap *cmp) +{ + int i; + + ut_assertok(check_device_name(uts, base->name, cmp->name)); + ut_asserteq(base->region.count, cmp->region.count); + ut_asserteq(base->usage, cmp->usage); + for (i = 0; i < base->region.count; i++) + ut_assertok(compare_upl_memregion(uts, + alist_get(&base->region, i, struct memregion), + alist_get(&cmp->region, i, struct memregion))); + + return 0; +} + +static int compare_upl_memres(struct unit_test_state *uts, + const struct upl_memres *base, + const struct upl_memres *cmp) +{ + int i; + + ut_assertok(check_device_name(uts, base->name, cmp->name)); + ut_asserteq(base->region.count, cmp->region.count); + ut_asserteq(base->no_map, cmp->no_map); + for (i = 0; i < base->region.count; i++) + ut_assertok(compare_upl_memregion(uts, + alist_get(&base->region, i, struct memregion), + alist_get(&cmp->region, i, struct memregion))); + + return 0; +} + +static int compare_upl_serial(struct unit_test_state *uts, + struct upl_serial *base, struct upl_serial *cmp) +{ + int i; + + ut_asserteq_str(base->compatible, cmp->compatible); + ut_asserteq(base->clock_frequency, cmp->clock_frequency); + ut_asserteq(base->current_speed, cmp->current_speed); + for (i = 0; i < base->reg.count; i++) + ut_assertok(compare_upl_memregion(uts, + alist_get(&base->reg, i, struct memregion), + alist_get(&cmp->reg, i, struct memregion))); + ut_asserteq(base->reg_io_shift, cmp->reg_io_shift); + ut_asserteq(base->reg_offset, cmp->reg_offset); + ut_asserteq(base->reg_io_width, cmp->reg_io_width); + ut_asserteq(base->virtual_reg, cmp->virtual_reg); + ut_asserteq(base->access_type, cmp->access_type); + + return 0; +} + +static int compare_upl_graphics(struct unit_test_state *uts, + struct upl_graphics *base, + struct upl_graphics *cmp) +{ + int i; + + for (i = 0; i < base->reg.count; i++) + ut_assertok(compare_upl_memregion(uts, + alist_get(&base->reg, i, struct memregion), + alist_get(&cmp->reg, i, struct memregion))); + ut_asserteq(base->width, cmp->width); + ut_asserteq(base->height, cmp->height); + ut_asserteq(base->stride, cmp->stride); + ut_asserteq(base->format, cmp->format); + + return 0; +} + +static int compare_upl(struct unit_test_state *uts, struct upl *base, + struct upl *cmp) +{ + int i; + + ut_asserteq(base->addr_cells, cmp->addr_cells); + ut_asserteq(base->size_cells, cmp->size_cells); + + ut_asserteq(base->smbios, cmp->smbios); + ut_asserteq(base->acpi, cmp->acpi); + ut_asserteq(base->bootmode, cmp->bootmode); + ut_asserteq(base->fit, cmp->fit); + ut_asserteq(base->conf_offset, cmp->conf_offset); + ut_asserteq(base->addr_width, cmp->addr_width); + ut_asserteq(base->acpi_nvs_size, cmp->acpi_nvs_size); + + ut_asserteq(base->image.count, cmp->image.count); + for (i = 0; i < base->image.count; i++) + ut_assertok(compare_upl_image(uts, + alist_get(&base->image, i, struct upl_image), + alist_get(&cmp->image, i, struct upl_image))); + + ut_asserteq(base->mem.count, cmp->mem.count); + for (i = 0; i < base->mem.count; i++) + ut_assertok(compare_upl_mem(uts, + alist_get(&base->mem, i, struct upl_mem), + alist_get(&cmp->mem, i, struct upl_mem))); + + ut_asserteq(base->memmap.count, cmp->memmap.count); + for (i = 0; i < base->memmap.count; i++) + ut_assertok(compare_upl_memmap(uts, + alist_get(&base->memmap, i, struct upl_memmap), + alist_get(&cmp->memmap, i, struct upl_memmap))); + + ut_asserteq(base->memres.count, cmp->memres.count); + for (i = 0; i < base->memres.count; i++) + ut_assertok(compare_upl_memres(uts, + alist_get(&base->memres, i, struct upl_memres), + alist_get(&cmp->memres, i, struct upl_memres))); + + ut_assertok(compare_upl_serial(uts, &base->serial, &cmp->serial)); + ut_assertok(compare_upl_graphics(uts, &base->graphics, &cmp->graphics)); + + return 0; +} + +/* Basic test of writing and reading UPL handoff */ +static int upl_test_base(struct unit_test_state *uts) +{ + oftree tree, check_tree; + struct upl upl, check; + struct abuf buf; + + if (!CONFIG_IS_ENABLED(OFNODE_MULTI_TREE)) + return -EAGAIN; /* skip test */ + ut_assertok(upl_get_test_data(uts, &upl)); + + ut_assertok(upl_create_handoff_tree(&upl, &tree)); + ut_assertok(oftree_to_fdt(tree, &buf)); + + /* + * strings in check_tree and therefore check are only valid so long as + * buf stays around. As soon as we call abuf_uninit they go away + */ + check_tree = oftree_from_fdt(abuf_data(&buf)); + ut_assert(ofnode_valid(oftree_path(check_tree, "/"))); + + ut_assertok(upl_read_handoff(&check, check_tree)); + ut_assertok(compare_upl(uts, &upl, &check)); + abuf_uninit(&buf); + + return 0; +} +UPL_TEST(upl_test_base, 0); + +/* Test 'upl info' command */ +static int upl_test_info(struct unit_test_state *uts) +{ + gd_set_upl(NULL); + ut_assertok(run_command("upl info", 0)); + ut_assert_nextline("UPL state: inactive"); + ut_assert_console_end(); + + gd_set_upl((struct upl *)uts); /* set it to any non-zero value */ + ut_assertok(run_command("upl info", 0)); + ut_assert_nextline("UPL state: active"); + ut_assert_console_end(); + gd_set_upl(NULL); + + return 0; +} +UPL_TEST(upl_test_info, UT_TESTF_CONSOLE_REC); + +/* Test 'upl read' and 'upl_write' commands */ +static int upl_test_read_write(struct unit_test_state *uts) +{ + ulong addr; + + if (!CONFIG_IS_ENABLED(OFNODE_MULTI_TREE)) + return -EAGAIN; /* skip test */ + ut_assertok(run_command("upl write", 0)); + + addr = env_get_hex("upladdr", 0); + ut_assert_nextline("UPL handoff written to %lx size %lx", addr, + env_get_hex("uplsize", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("upl read ${upladdr}", 0)); + ut_assert_nextline("Reading UPL at %lx", addr); + ut_assert_console_end(); + + return 0; +} +UPL_TEST(upl_test_read_write, UT_TESTF_CONSOLE_REC); + +/* Test UPL passthrough */ +static int upl_test_info_norun(struct unit_test_state *uts) +{ + const struct upl_image *img; + struct upl *upl = gd_upl(); + const void *fit; + + ut_assertok(run_command("upl info -v", 0)); + ut_assert_nextline("UPL state: active"); + ut_assert_nextline("fit %lx", upl->fit); + ut_assert_nextline("conf_offset %x", upl->conf_offset); + ut_assert_nextlinen("image 0"); + ut_assert_nextlinen("image 1"); + ut_assert_console_end(); + + /* check the offsets */ + fit = map_sysmem(upl->fit, 0); + ut_asserteq_str("conf-1", fdt_get_name(fit, upl->conf_offset, NULL)); + + ut_asserteq(2, upl->image.count); + + img = alist_get(&upl->image, 1, struct upl_image); + ut_asserteq_str("firmware-1", fdt_get_name(fit, img->offset, NULL)); + ut_asserteq(CONFIG_TEXT_BASE, img->load); + + return 0; +} +UPL_TEST(upl_test_info_norun, UT_TESTF_CONSOLE_REC | UT_TESTF_MANUAL); + +int do_ut_upl(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(upl_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(upl_test); + + return cmd_ut_category("cmd_upl", "cmd_upl_", tests, n_ents, argc, + argv); +} diff --git a/test/cmd/wget.c b/test/cmd/wget.c index 356a4dcd8fa..b0feb21dc41 100644 --- a/test/cmd/wget.c +++ b/test/cmd/wget.c @@ -26,6 +26,8 @@ #define SHIFT_TO_TCPHDRLEN_FIELD(x) ((x) << 4) #define LEN_B_TO_DW(x) ((x) >> 2) +int net_set_ack_options(union tcp_build_pkt *b); + static int sb_arp_handler(struct udevice *dev, void *packet, unsigned int len) { @@ -105,6 +107,10 @@ static int sb_ack_handler(struct udevice *dev, void *packet, const char *payload1 = "HTTP/1.1 200 OK\r\n" "Content-Length: 30\r\n\r\n\r\n" "<html><body>Hi</body></html>\r\n"; + union tcp_build_pkt *b = (union tcp_build_pkt *)tcp; + const int recv_payload_len = len - net_set_ack_options(b) - IP_HDR_SIZE - ETHER_HDR_SIZE; + static int next_seq; + const int bottom_payload_len = 10; /* Don't allow the buffer to overrun */ if (priv->recv_packets >= PKTBUFSRX) @@ -119,13 +125,31 @@ static int sb_ack_handler(struct udevice *dev, void *packet, tcp_send->tcp_dst = tcp->tcp_src; data = (void *)tcp_send + IP_TCP_HDR_SIZE; - if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1) { + if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1 && recv_payload_len == 0) { + // ignore ACK for three-way handshaking + return 0; + } else if (ntohl(tcp->tcp_seq) == 1 && ntohl(tcp->tcp_ack) == 1) { + // recv HTTP request message and reply top half data tcp_send->tcp_seq = htonl(ntohl(tcp->tcp_ack)); - tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + 1); - payload_len = strlen(payload1); + tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + recv_payload_len); + + payload_len = strlen(payload1) - bottom_payload_len; memcpy(data, payload1, payload_len); tcp_send->tcp_flags = TCP_ACK; - } else if (ntohl(tcp->tcp_seq) == 2) { + + next_seq = ntohl(tcp_send->tcp_seq) + payload_len; + } else if (ntohl(tcp->tcp_ack) == next_seq) { + // reply bottom half data + const int top_payload_len = strlen(payload1) - bottom_payload_len; + + tcp_send->tcp_seq = htonl(next_seq); + tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + recv_payload_len); + + payload_len = bottom_payload_len; + memcpy(data, payload1 + top_payload_len, payload_len); + tcp_send->tcp_flags = TCP_ACK; + } else { + // close connection tcp_send->tcp_seq = htonl(ntohl(tcp->tcp_ack)); tcp_send->tcp_ack = htonl(ntohl(tcp->tcp_seq) + 1); payload_len = 0; @@ -148,11 +172,9 @@ static int sb_ack_handler(struct udevice *dev, void *packet, pkt_len, IPPROTO_TCP); - if (ntohl(tcp->tcp_seq) == 1 || ntohl(tcp->tcp_seq) == 2) { - priv->recv_packet_length[priv->recv_packets] = - ETHER_HDR_SIZE + IP_TCP_HDR_SIZE + payload_len; - ++priv->recv_packets; - } + priv->recv_packet_length[priv->recv_packets] = + ETHER_HDR_SIZE + IP_TCP_HDR_SIZE + payload_len; + ++priv->recv_packets; return 0; } diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 4e4aa8f1cb2..38ba89ee33e 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -133,6 +133,9 @@ static struct cmd_tbl cmd_ut_sub[] = { #ifdef CONFIG_CMD_SEAMA U_BOOT_CMD_MKENT(seama, CONFIG_SYS_MAXARGS, 1, do_ut_seama, "", ""), #endif +#ifdef CONFIG_CMD_UPL + U_BOOT_CMD_MKENT(upl, CONFIG_SYS_MAXARGS, 1, do_ut_upl, "", ""), +#endif }; static int do_ut_all(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/test/env/cmd_ut_env.c b/test/env/cmd_ut_env.c index 13e0998341e..238cf310367 100644 --- a/test/env/cmd_ut_env.c +++ b/test/env/cmd_ut_env.c @@ -9,6 +9,33 @@ #include <test/suites.h> #include <test/ut.h> +static int env_test_env_cmd(struct unit_test_state *uts) +{ + ut_assertok(run_command("setenv non_default_var1 1", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("setenv non_default_var2 1", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("env print non_default_var1", 0)); + ut_assert_nextline("non_default_var1=1"); + ut_assert_console_end(); + + ut_assertok(run_command("env default non_default_var1 non_default_var2", 0)); + ut_assert_nextline("WARNING: 'non_default_var1' not in imported env, deleting it!"); + ut_assert_nextline("WARNING: 'non_default_var2' not in imported env, deleting it!"); + ut_assert_console_end(); + + ut_asserteq(1, run_command("env exists non_default_var1", 0)); + ut_assert_console_end(); + + ut_asserteq(1, run_command("env exists non_default_var2", 0)); + ut_assert_console_end(); + + return 0; +} +ENV_TEST(env_test_env_cmd, UT_TESTF_CONSOLE_REC); + int do_ut_env(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct unit_test *tests = UNIT_TEST_SUITE_START(env_test); diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index 7d5fb9b07e0..56105a59236 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -10,63 +10,12 @@ #include <test/spl.h> #include <test/ut.h> -/* Context used for this test */ -struct text_ctx { - int fd; -}; - -static ulong read_fit_image(struct spl_load_info *load, ulong offset, - ulong size, void *buf) -{ - struct text_ctx *text_ctx = load->priv; - off_t ret; - ssize_t res; - - ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET); - if (ret != offset) { - printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset, - ret, errno); - return 0; - } - - res = os_read(text_ctx->fd, buf, size); - if (res == -1) { - printf("Failed to read %lx bytes, got %ld (errno=%d)\n", - size, res, errno); - return 0; - } - - return size; -} - static int spl_test_load(struct unit_test_state *uts) { struct spl_image_info image; - struct legacy_img_hdr *header; - struct text_ctx text_ctx; - struct spl_load_info load; char fname[256]; - int ret; - int fd; - - memset(&load, '\0', sizeof(load)); - spl_set_bl_len(&load, 512); - load.read = read_fit_image; - - ret = sandbox_find_next_phase(fname, sizeof(fname), true); - if (ret) - ut_assertf(0, "%s not found, error %d\n", fname, ret); - - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); - - fd = os_open(fname, OS_O_RDONLY); - ut_assert(fd >= 0); - ut_asserteq(512, os_read(fd, header, 512)); - text_ctx.fd = fd; - - load.priv = &text_ctx; - ut_assertok(spl_load_simple_fit(&image, &load, 0, header)); + ut_assertok(sandbox_spl_load_fit(fname, sizeof(fname), &image)); return 0; } diff --git a/test/lib/Makefile b/test/lib/Makefile index e75a263e6a4..70f14c46b1e 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -5,6 +5,7 @@ ifeq ($(CONFIG_SPL_BUILD),) obj-y += cmd_ut_lib.o obj-y += abuf.o +obj-y += alist.o obj-$(CONFIG_EFI_LOADER) += efi_device_path.o obj-$(CONFIG_EFI_SECURE_BOOT) += efi_image_region.o obj-y += hexdump.o diff --git a/test/lib/alist.c b/test/lib/alist.c new file mode 100644 index 00000000000..d41845c7e6c --- /dev/null +++ b/test/lib/alist.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023 Google LLC + * Written by Simon Glass <sjg@chromium.org> + */ + +#include <alist.h> +#include <string.h> +#include <test/lib.h> +#include <test/test.h> +#include <test/ut.h> + +struct my_struct { + uint val; + uint other_val; +}; + +enum { + obj_size = sizeof(struct my_struct), +}; + +/* Test alist_init() */ +static int lib_test_alist_init(struct unit_test_state *uts) +{ + struct alist lst; + ulong start; + + start = ut_check_free(); + + /* with a size of 0, the fields should be inited, with no memory used */ + memset(&lst, '\xff', sizeof(lst)); + ut_assert(alist_init_struct(&lst, struct my_struct)); + ut_asserteq_ptr(NULL, lst.data); + ut_asserteq(0, lst.count); + ut_asserteq(0, lst.alloc); + ut_assertok(ut_check_delta(start)); + alist_uninit(&lst); + ut_asserteq_ptr(NULL, lst.data); + ut_asserteq(0, lst.count); + ut_asserteq(0, lst.alloc); + + /* use an impossible size */ + ut_asserteq(false, alist_init(&lst, obj_size, + CONFIG_SYS_MALLOC_LEN)); + ut_assertnull(lst.data); + ut_asserteq(0, lst.count); + ut_asserteq(0, lst.alloc); + + /* use a small size */ + ut_assert(alist_init(&lst, obj_size, 4)); + ut_assertnonnull(lst.data); + ut_asserteq(0, lst.count); + ut_asserteq(4, lst.alloc); + + /* free it */ + alist_uninit(&lst); + ut_asserteq_ptr(NULL, lst.data); + ut_asserteq(0, lst.count); + ut_asserteq(0, lst.alloc); + ut_assertok(ut_check_delta(start)); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_alist_init, 0); + +/* Test alist_get() and alist_getd() */ +static int lib_test_alist_get(struct unit_test_state *uts) +{ + struct alist lst; + ulong start; + void *ptr; + + start = ut_check_free(); + + ut_assert(alist_init(&lst, obj_size, 3)); + ut_asserteq(0, lst.count); + ut_asserteq(3, lst.alloc); + + ut_assertnull(alist_get_ptr(&lst, 2)); + ut_assertnull(alist_get_ptr(&lst, 3)); + + ptr = alist_ensure_ptr(&lst, 1); + ut_assertnonnull(ptr); + ut_asserteq(2, lst.count); + ptr = alist_ensure_ptr(&lst, 2); + ut_asserteq(3, lst.count); + ut_assertnonnull(ptr); + + ptr = alist_ensure_ptr(&lst, 3); + ut_assertnonnull(ptr); + ut_asserteq(4, lst.count); + ut_asserteq(6, lst.alloc); + + ut_assertnull(alist_get_ptr(&lst, 4)); + + alist_uninit(&lst); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_alist_get, 0); + +/* Test alist_has() */ +static int lib_test_alist_has(struct unit_test_state *uts) +{ + struct alist lst; + ulong start; + void *ptr; + + start = ut_check_free(); + + ut_assert(alist_init(&lst, obj_size, 3)); + + ut_assert(!alist_has(&lst, 0)); + ut_assert(!alist_has(&lst, 1)); + ut_assert(!alist_has(&lst, 2)); + ut_assert(!alist_has(&lst, 3)); + + /* create a new one to force expansion */ + ptr = alist_ensure_ptr(&lst, 4); + ut_assertnonnull(ptr); + + ut_assert(alist_has(&lst, 0)); + ut_assert(alist_has(&lst, 1)); + ut_assert(alist_has(&lst, 2)); + ut_assert(alist_has(&lst, 3)); + ut_assert(alist_has(&lst, 4)); + ut_assert(!alist_has(&lst, 5)); + + alist_uninit(&lst); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_alist_has, 0); + +/* Test alist_ensure() */ +static int lib_test_alist_ensure(struct unit_test_state *uts) +{ + struct my_struct *ptr3, *ptr4; + struct alist lst; + ulong start; + + start = ut_check_free(); + + ut_assert(alist_init_struct(&lst, struct my_struct)); + ut_asserteq(obj_size, lst.obj_size); + ut_asserteq(0, lst.count); + ut_asserteq(0, lst.alloc); + ptr3 = alist_ensure_ptr(&lst, 3); + ut_asserteq(4, lst.count); + ut_asserteq(4, lst.alloc); + ut_assertnonnull(ptr3); + ptr3->val = 3; + + ptr4 = alist_ensure_ptr(&lst, 4); + ut_asserteq(8, lst.alloc); + ut_asserteq(5, lst.count); + ut_assertnonnull(ptr4); + ptr4->val = 4; + ut_asserteq(4, alist_get(&lst, 4, struct my_struct)->val); + + ut_asserteq_ptr(ptr4, alist_ensure(&lst, 4, struct my_struct)); + + alist_ensure(&lst, 4, struct my_struct)->val = 44; + ut_asserteq(44, alist_get(&lst, 4, struct my_struct)->val); + ut_asserteq(3, alist_get(&lst, 3, struct my_struct)->val); + ut_assertnull(alist_get(&lst, 7, struct my_struct)); + ut_asserteq(8, lst.alloc); + ut_asserteq(5, lst.count); + + /* add some more, checking handling of malloc() failure */ + malloc_enable_testing(0); + ut_assertnonnull(alist_ensure(&lst, 7, struct my_struct)); + ut_assertnull(alist_ensure(&lst, 8, struct my_struct)); + malloc_disable_testing(); + + lst.flags &= ~ALISTF_FAIL; + ut_assertnonnull(alist_ensure(&lst, 8, struct my_struct)); + ut_asserteq(16, lst.alloc); + ut_asserteq(9, lst.count); + + alist_uninit(&lst); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_alist_ensure, 0); + +/* Test alist_add() bits not tested by lib_test_alist_ensure() */ +static int lib_test_alist_add(struct unit_test_state *uts) +{ + struct my_struct data, *ptr, *ptr2; + const struct my_struct *chk; + struct alist lst; + ulong start; + + start = ut_check_free(); + + ut_assert(alist_init_struct(&lst, struct my_struct)); + + data.val = 123; + data.other_val = 456; + ptr = alist_add(&lst, data); + ut_assertnonnull(ptr); + ut_asserteq(4, lst.alloc); + ut_asserteq(1, lst.count); + + ut_asserteq(123, ptr->val); + ut_asserteq(456, ptr->other_val); + + ptr2 = alist_add_placeholder(&lst); + ut_assertnonnull(ptr2); + + ptr2->val = 321; + ptr2->other_val = 654; + + chk = alist_get(&lst, 1, struct my_struct); + ut_asserteq(321, chk->val); + ut_asserteq(654, chk->other_val); + + ptr2 = alist_getw(&lst, 1, struct my_struct); + ut_asserteq(321, ptr2->val); + ut_asserteq(654, ptr2->other_val); + + alist_uninit(&lst); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_alist_add, 0); diff --git a/test/py/tests/test_upl.py b/test/py/tests/test_upl.py new file mode 100644 index 00000000000..3164bda6b71 --- /dev/null +++ b/test/py/tests/test_upl.py @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2024 Google LLC +# +# Test addition of Universal Payload + +import os + +import pytest +import u_boot_utils + +@pytest.mark.boardspec('sandbox_vpl') +def test_upl_handoff(u_boot_console): + """Test of UPL handoff + + This works by starting up U-Boot VPL, which gets to SPL and then sets up a + UPL handoff using the FIT containing U-Boot proper. It then jumps to U-Boot + proper and runs a test to check that the parameters are correct. + + The entire FIT is loaded into memory in SPL (in upl_load_from_image()) so + that it can be inpected in upl_test_info_norun + """ + cons = u_boot_console + ram = os.path.join(cons.config.build_dir, 'ram.bin') + fdt = os.path.join(cons.config.build_dir, 'u-boot.dtb') + + # Remove any existing RAM file, so we don't have old data present + if os.path.exists(ram): + os.remove(ram) + flags = ['-m', ram, '-d', fdt, '--upl'] + cons.restart_uboot_with_flags(flags, use_dtb=False) + + # Make sure that Universal Payload is detected in U-Boot proper + output = cons.run_command('upl info') + assert 'UPL state: active' == output + + # Check the FIT offsets look correct + output = cons.run_command('ut upl -f upl_test_info_norun') + assert 'Failures: 0' in output diff --git a/test/str_ut.c b/test/str_ut.c index 389779859a3..96e048975d8 100644 --- a/test/str_ut.c +++ b/test/str_ut.c @@ -342,9 +342,7 @@ static int test_str_to_list(struct unit_test_state *uts) ut_asserteq_str("space", ptr[3]); ut_assertnonnull(ptr[4]); ut_asserteq_str("", ptr[4]); - ut_assertnonnull(ptr[5]); - ut_asserteq_str("", ptr[5]); - ut_assertnull(ptr[6]); + ut_assertnull(ptr[5]); str_free_list(ptr); ut_assertok(ut_check_delta(start)); diff --git a/tools/imx8image.c b/tools/imx8image.c index 76d0cd62dcc..5eb4b9612c8 100644 --- a/tools/imx8image.c +++ b/tools/imx8image.c @@ -57,6 +57,7 @@ static table_entry_t imx8image_cmds[] = { static table_entry_t imx8image_core_entries[] = { {CFG_SCU, "SCU", "scu core", }, + {CFG_PWR, "PWR", "uPower core", }, {CFG_M40, "M40", "M4 core 0", }, {CFG_M41, "M41", "M4 core 1", }, {CFG_A35, "A35", "A35 core", }, @@ -119,7 +120,7 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t cmd, char *token, } else if (!strncmp(token, "IMX8QM", 6)) { soc = QM; } else if (!strncmp(token, "ULP", 3)) { - soc = IMX9; + soc = ULP; } else if (!strncmp(token, "IMX9", 4)) { soc = IMX9; } else { @@ -181,6 +182,10 @@ static void parse_cfg_fld(image_t *param_stack, int32_t *cmd, char *token, param_stack[p_idx].option = SCFW; param_stack[p_idx++].filename = token; break; + case CFG_PWR: + param_stack[p_idx].option = UPOWER; + param_stack[p_idx++].filename = token; + break; case CFG_M40: param_stack[p_idx].option = M40; param_stack[p_idx].ext = 0; diff --git a/tools/sunxi_toc0.c b/tools/sunxi_toc0.c index 292649fe90f..76693647a09 100644 --- a/tools/sunxi_toc0.c +++ b/tools/sunxi_toc0.c @@ -444,7 +444,7 @@ static int toc0_verify_cert_item(const uint8_t *buf, uint32_t len, RSA *fw_key, /* If a digest was provided, compare it to the embedded digest. */ extension = &totalSequence->mainSequence.explicit3.extension; - if (digest && memcmp(&extension->digest, digest, SHA256_DIGEST_LENGTH)) { + if (memcmp(&extension->digest, digest, SHA256_DIGEST_LENGTH)) { pr_err("Wrong firmware digest in certificate\n"); goto err; } |
