diff options
124 files changed, 552 insertions, 984 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index df373d38a55..fedfdb21457 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1190,6 +1190,7 @@ config ARCH_SUNXI select DM_SPI_FLASH if SPI && MTD select DM_KEYBOARD select DM_SERIAL + select MMU_PGPROT if ARM64 select OF_BOARD_SETUP select OF_CONTROL select PINCTRL diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index f7707acdf1a..044a7c16cc5 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -74,10 +74,19 @@ back_in_32: .word 0xf57ff06f // isb .word 0xe590d000 // ldr sp, [r0] .word 0xe590e004 // ldr lr, [r0, #4] + .word 0xe5901014 // ldr r1, [r0, #20] + .word 0xe121f301 // msr SP_irq, r1 .word 0xe5901010 // ldr r1, [r0, #16] .word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR .word 0xe590100c // ldr r1, [r0, #12] .word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR .word 0xf57ff06f // isb +#ifdef CONFIG_MACH_SUN55I_A523 + .word 0xe5901018 // ldr r1, [r0, #24] + .word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR + .word 0xe590101c // ldr r1, [r0, #28] + .word 0xee0c1ffc // mcr 15, 0, r1, cr12, cr12, {7}; ICC_IGRPEN1 +#endif + .word 0xe12fff1e // bx lr ; return to FEL ENDPROC(return_to_fel) diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 24c81391d58..d79aea97a40 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -26,11 +26,21 @@ .word 0xe580e004 // str lr, [r0, #4] .word 0xe10fe000 // mrs lr, CPSR .word 0xe580e008 // str lr, [r0, #8] + .word 0xe101e300 // mrs lr, SP_irq + .word 0xe580e014 // str lr, [r0, #20] .word 0xee11ef10 // mrc 15, 0, lr, cr1, cr0, {0} .word 0xe580e00c // str lr, [r0, #12] .word 0xee1cef10 // mrc 15, 0, lr, cr12, cr0, {0} .word 0xe580e010 // str lr, [r0, #16] - +#ifdef CONFIG_MACH_SUN55I_A523 + .word 0xee1cefbc // mrc 15, 0, lr, cr12, cr12, {5} + .word 0xe31e0001 // tst lr, #1 + .word 0x0a000003 // beq cc <start32+0x48> + .word 0xee14ef16 // mrc 15, 0, lr, cr4, cr6, {0} + .word 0xe580e018 // str lr, [r0, #24] + .word 0xee1ceffc // mrc 15, 0, lr, cr12, cr12, {7} + .word 0xe580e01c // str lr, [r0, #28] +#endif .word 0xe59f1034 // ldr r1, [pc, #52] ; RVBAR_ADDRESS .word 0xe59f0034 // ldr r0, [pc, #52] ; SUNXI_SRAMC_BASE .word 0xe5900024 // ldr r0, [r0, #36] ; SRAM_VER_REG diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 2cec91cb20e..00bdd5f938d 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -10,6 +10,12 @@ #ifndef _SUNXI_CLOCK_SUN4I_H #define _SUNXI_CLOCK_SUN4I_H +#define CCU_AHB_GATE0 0x60 +#define CCU_MMC0_CLK_CFG 0x88 +#define CCU_MMC1_CLK_CFG 0x8c +#define CCU_MMC2_CLK_CFG 0x90 +#define CCU_MMC3_CLK_CFG 0x94 + struct sunxi_ccm_reg { u32 pll1_cfg; /* 0x00 pll1 control */ u32 pll1_tun; /* 0x04 pll1 tuning */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 76dd33c9477..ccacc99d018 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -13,218 +13,23 @@ #include <linux/bitops.h> #endif -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ - u8 reserved_0x004[12]; - u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ - u8 reserved_0x014[12]; - u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ - u8 reserved_0x020[4]; - u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ - u8 reserved_0x028[4]; - u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ - u8 reserved_0x034[12]; - u32 pll3_cfg; /* 0x040 pll3 (video0) control */ - u8 reserved_0x044[4]; - u32 pll_video1_cfg; /* 0x048 pll video1 control */ - u8 reserved_0x04c[12]; - u32 pll4_cfg; /* 0x058 pll4 (ve) control */ - u8 reserved_0x05c[4]; - u32 pll10_cfg; /* 0x060 pll10 (de) control */ - u8 reserved_0x064[12]; - u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ - u8 reserved_0x074[4]; - u32 pll2_cfg; /* 0x078 pll2 (audio) control */ - u8 reserved_0x07c[148]; - u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ - u8 reserved_0x114[20]; - u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ - u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ - u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ - u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ - u8 reserved_0x138[8]; - u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ - u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ - u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ - u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ - u8 reserved_0x150[8]; - u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ - u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ - u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ - u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ - u8 reserved_0x168[8]; - u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ - u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ - u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ - u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ - u8 reserved_0x180[384]; - u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ - u8 reserved_0x304[12]; - u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ - u8 reserved_0x314[12]; - u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ - u8 reserved_0x324[4]; - u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ - u8 reserved_0x32c[4]; - u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ - u8 reserved_0x334[12]; - u32 pll3_bias; /* 0x340 pll3 (video0) bias */ - u8 reserved_0x344[4]; - u32 pll_video1_bias; /* 0x348 pll video1 bias */ - u8 reserved_0x34c[12]; - u32 pll4_bias; /* 0x358 pll4 (ve) bias */ - u8 reserved_0x35c[4]; - u32 pll10_bias; /* 0x360 pll10 (de) bias */ - u8 reserved_0x364[12]; - u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ - u8 reserved_0x374[4]; - u32 pll2_bias; /* 0x378 pll2 (audio) bias */ - u8 reserved_0x37c[132]; - u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ - u8 reserved_0x404[252]; - u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ - u8 reserved_0x504[12]; - u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ - u8 reserved_0x514[8]; - u32 ahb3_cfg; /* 0x51c AHB3 clock control */ - u32 apb1_cfg; /* 0x520 APB1 clock control */ - u32 apb2_cfg; /* 0x524 APB2 clock control */ - u8 reserved_0x528[24]; - u32 mbus_cfg; /* 0x540 MBUS clock control */ - u8 reserved_0x544[188]; - u32 de_clk_cfg; /* 0x600 DE clock control */ - u8 reserved_0x604[8]; - u32 de_gate_reset; /* 0x60c DE gate/reset control */ - u8 reserved_0x610[16]; - u32 di_clk_cfg; /* 0x620 DI clock control */ - u8 reserved_0x024[8]; - u32 di_gate_reset; /* 0x62c DI gate/reset control */ - u8 reserved_0x630[64]; - u32 gpu_clk_cfg; /* 0x670 GPU clock control */ - u8 reserved_0x674[8]; - u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ - u32 ce_clk_cfg; /* 0x680 CE clock control */ - u8 reserved_0x684[8]; - u32 ce_gate_reset; /* 0x68c CE gate/reset control */ - u32 ve_clk_cfg; /* 0x690 VE clock control */ - u8 reserved_0x694[8]; - u32 ve_gate_reset; /* 0x69c VE gate/reset control */ - u8 reserved_0x6a0[16]; - u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ - u8 reserved_0x6b4[8]; - u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ - u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ - u8 reserved_0x6c4[8]; - u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ - u8 reserved_0x6d0[60]; - u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ - u8 reserved_0x710[12]; - u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ - u8 reserved_0x720[12]; - u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ - u8 reserved_0x730[12]; - u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ - u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ - u8 reserved_0x744[72]; - u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ - u8 reserved_0x790[12]; - u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ - u8 reserved_0x7a0[12]; - u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ - u8 reserved_0x7b0[12]; - u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ - u8 reserved_0x7c0[64]; - u32 dram_clk_cfg; /* 0x800 DRAM clock control */ - u32 mbus_gate; /* 0x804 MBUS gate control */ - u8 reserved_0x808[4]; - u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ - u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ - u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ - u8 reserved_0x818[20]; - u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ - u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ - u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ - u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ - u8 reserved_0x83c[16]; - u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ - u8 reserved_0x850[188]; - u32 uart_gate_reset; /* 0x90c UART gate/reset control */ - u8 reserved_0x910[12]; - u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ - u8 reserved_0x920[28]; - u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ - u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ - u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ - u8 reserved_0x948[36]; - u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ - u8 reserved_0x970[12]; - u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ - u8 reserved_0x980[48]; - u32 ts_clk_cfg; /* 0x9b0 TS clock control */ - u8 reserved_0x9b4[8]; - u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ - u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ - u8 reserved_0x9c4[8]; - u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ - u8 reserved_0x9d0[44]; - u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ - u8 reserved_0xa00[12]; - u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ - u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ - u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ - u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ - u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ - u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ - u8 reserved_0xa24[8]; - u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ - u8 reserved_0xa30[16]; - u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ - u8 reserved_0xa44[8]; - u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ - u8 reserved_0xa50[16]; - u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ - u8 reserved_0xa64[8]; - u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ - u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ - u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ - u8 reserved_0xa78[4]; - u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ - u8 reserved_0xa80[12]; - u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ - u8 reserved_0xa90[32]; - u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ - u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ - u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ - u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ - u8 reserved_0xac0[64]; - u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ - u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ - u8 reserved_0xb08[8]; - u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ - u8 reserved_0xb14[8]; - u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ - u8 reserved_0xb20[60]; - u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ - u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ - u8 reserved_0xb64[24]; - u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ - u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ - u8 reserved_0xb84[24]; - u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ - u8 reserved_0xba0[96]; - u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ - u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ - u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ - u8 reserved_0xc0c[32]; - u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ - u8 reserved_0xc30[16]; - u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ - u8 reserved_0xc44[8]; - u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ - u8 reserved_0xc50[688]; - u32 ccu_sec_switch; /* 0xf00 CCU security switch */ - u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ -}; +#define CCU_H6_PLL1_CFG 0x000 +#define CCU_H6_PLL5_CFG 0x010 +#define CCU_H6_PLL6_CFG 0x020 +#define CCU_H6_CPU_AXI_CFG 0x500 +#define CCU_H6_PSI_AHB1_AHB2_CFG 0x510 +#define CCU_H6_AHB3_CFG 0x51c +#define CCU_H6_APB1_CFG 0x520 +#define CCU_H6_APB2_CFG 0x524 +#define CCU_H6_MBUS_CFG 0x540 +#define CCU_H6_DRAM_CLK_CFG 0x800 +#define CCU_H6_DRAM_GATE_RESET 0x80c +#define CCU_MMC0_CLK_CFG 0x830 +#define CCU_MMC1_CLK_CFG 0x834 +#define CCU_MMC2_CLK_CFG 0x838 +#define CCU_H6_MMC_GATE_RESET 0x84c +#define CCU_H6_UART_GATE_RESET 0x90c +#define CCU_H6_I2C_GATE_RESET 0x91c /* pll1 bit field */ #define CCM_PLL1_CTRL_EN BIT(31) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index 7fcf340db69..28c3faccbbc 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -10,6 +10,13 @@ #ifndef _SUNXI_CLOCK_SUN6I_H #define _SUNXI_CLOCK_SUN6I_H +#define CCU_AHB_GATE0 0x060 +#define CCU_MMC0_CLK_CFG 0x088 +#define CCU_MMC1_CLK_CFG 0x08c +#define CCU_MMC2_CLK_CFG 0x090 +#define CCU_MMC3_CLK_CFG 0x094 +#define CCU_AHB_RESET0_CFG 0x2c0 + struct sunxi_ccm_reg { u32 pll1_cfg; /* 0x00 pll1 control */ u32 reserved0; diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h index 35ca0491ac9..5ad2163926a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h @@ -13,6 +13,13 @@ #ifndef _SUNXI_CLOCK_SUN8I_A83T_H #define _SUNXI_CLOCK_SUN8I_A83T_H +#define CCU_AHB_GATE0 0x060 +#define CCU_MMC0_CLK_CFG 0x088 +#define CCU_MMC1_CLK_CFG 0x08c +#define CCU_MMC2_CLK_CFG 0x090 +#define CCU_MMC3_CLK_CFG 0x094 +#define CCU_AHB_RESET0_CFG 0x2c0 + struct sunxi_ccm_reg { u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 006f7761fc6..8d696e533f8 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -12,6 +12,13 @@ #include <linux/bitops.h> #endif +#define CCU_MMC0_CLK_CFG 0x410 +#define CCU_MMC1_CLK_CFG 0x414 +#define CCU_MMC2_CLK_CFG 0x418 +#define CCU_MMC3_CLK_CFG 0x41c +#define CCU_AHB_GATE0 0x580 +#define CCU_AHB_RESET0_CFG 0x5a0 + struct sunxi_ccm_reg { u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h new file mode 100644 index 00000000000..bc9e0d868c5 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_dw_helpers.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Helpers that are commonly used with DW memory controller. + * + * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com> + * + */ + +#ifndef _DRAM_DW_HELPERS_H +#define _DRAM_DW_HELPERS_H + +#include <asm/arch/dram.h> + +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config); +void mctl_auto_detect_rank_width(const struct dram_para *para, + struct dram_config *config); +void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config); +unsigned long mctl_calc_size(const struct dram_config *config); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h index f0caecc807d..af6cd337d7e 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h @@ -315,12 +315,15 @@ check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); struct dram_para { u32 clk; enum sunxi_dram_type type; + const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; +}; + +struct dram_config { u8 cols; u8 rows; u8 ranks; u8 bus_full_width; - const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; }; static inline int ns_to_t(int nanoseconds) @@ -330,6 +333,6 @@ static inline int ns_to_t(int nanoseconds) return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); } -void mctl_set_timing_params(struct dram_para *para); +void mctl_set_timing_params(void); #endif /* _SUNXI_DRAM_SUN50I_H6_H */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h index fd63d3aad83..d6653c3bb06 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h +++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h @@ -9,46 +9,12 @@ #define _SUN50I_PRCM_H #ifndef __ASSEMBLY__ -#include <linux/compiler.h> -struct sunxi_prcm_reg { - u32 cpus_cfg; /* 0x000 */ - u8 res0[0x8]; /* 0x004 */ - u32 apbs1_cfg; /* 0x00c */ - u32 apbs2_cfg; /* 0x010 */ - u8 res1[0x108]; /* 0x014 */ - u32 tmr_gate_reset; /* 0x11c */ - u8 res2[0xc]; /* 0x120 */ - u32 twd_gate_reset; /* 0x12c */ - u8 res3[0xc]; /* 0x130 */ - u32 pwm_gate_reset; /* 0x13c */ - u8 res4[0x4c]; /* 0x140 */ - u32 uart_gate_reset; /* 0x18c */ - u8 res5[0xc]; /* 0x190 */ - u32 twi_gate_reset; /* 0x19c */ - u8 res6[0x1c]; /* 0x1a0 */ - u32 rsb_gate_reset; /* 0x1bc */ - u32 cir_cfg; /* 0x1c0 */ - u8 res7[0x8]; /* 0x1c4 */ - u32 cir_gate_reset; /* 0x1cc */ - u8 res8[0x10]; /* 0x1d0 */ - u32 w1_cfg; /* 0x1e0 */ - u8 res9[0x8]; /* 0x1e4 */ - u32 w1_gate_reset; /* 0x1ec */ - u8 res10[0x1c]; /* 0x1f0 */ - u32 rtc_gate_reset; /* 0x20c */ - u8 res11[0x34]; /* 0x210 */ - u32 pll_ldo_cfg; /* 0x244 */ - u8 res12[0x8]; /* 0x248 */ - u32 sys_pwroff_gating; /* 0x250 */ - u8 res13[0xbc]; /* 0x254 */ - u32 res_cal_ctrl; /* 0x310 */ - u32 ohms200; /* 0x314 */ - u32 ohms240; /* 0x318 */ - u32 res_cal_status; /* 0x31c */ -}; -check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c); -check_member(sunxi_prcm_reg, res_cal_status, 0x31c); +#define CCU_PRCM_I2C_GATE_RESET 0x19c +#define CCU_PRCM_PLL_LDO_CFG 0x244 +#define CCU_PRCM_SYS_PWROFF_GATING 0x250 +#define CCU_PRCM_RES_CAL_CTRL 0x310 +#define CCU_PRCM_OHMS240 0x318 #define PRCM_TWI_GATE (1 << 0) #define PRCM_TWI_RESET (1 << 16) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ab432390d3c..fce817c9d40 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -782,49 +782,6 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. -config USB0_VBUS_PIN - string "Vbus enable pin for usb0 (otg)" - default "" - ---help--- - Set the Vbus enable pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB0_VBUS_DET - string "Vbus detect pin for usb0 (otg)" - default "" - ---help--- - Set the Vbus detect pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB0_ID_DET - string "ID detect pin for usb0 (otg)" - default "" - ---help--- - Set the ID detect pin for usb0 (otg). This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. - -config USB1_VBUS_PIN - string "Vbus enable pin for usb1 (ehci0)" - default "PH6" if MACH_SUN4I || MACH_SUN7I - default "PH27" if MACH_SUN6I - ---help--- - Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes - a string in the format understood by sunxi_name_to_gpio, e.g. - PH1 for pin 1 of port H. - -config USB2_VBUS_PIN - string "Vbus enable pin for usb2 (ehci1)" - default "PH3" if MACH_SUN4I || MACH_SUN7I - default "PH24" if MACH_SUN6I - ---help--- - See USB1_VBUS_PIN help text. - -config USB3_VBUS_PIN - string "Vbus enable pin for usb3 (ehci2)" - default "" - ---help--- - See USB1_VBUS_PIN help text. - config I2C0_ENABLE bool "Enable I2C/TWI controller 0" default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index eb6a49119a1..a33cd5b0f07 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -41,8 +41,8 @@ obj-$(CONFIG_DRAM_SUN9I) += dram_sun9i.o obj-$(CONFIG_SPL_SPI_SUNXI) += spl_spi_sunxi.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ -obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o +obj-$(CONFIG_DRAM_SUN50I_H6) += dram_sun50i_h6.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H6) += dram_timings/ -obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o +obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/ endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 701899ee4b2..b1bf51f40c5 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -35,6 +35,9 @@ struct fel_stash { uint32_t cpsr; uint32_t sctlr; uint32_t vbar; + uint32_t sp_irq; + uint32_t icc_pmr; + uint32_t icc_igrpen1; }; struct fel_stash fel_stash __section(".data"); diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 359513d1669..4c522f60810 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -6,86 +6,83 @@ #ifdef CONFIG_XPL_BUILD void clock_init_safe(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) { /* this seems to enable PLLs on H616 */ - setbits_le32(&prcm->sys_pwroff_gating, 0x10); - setbits_le32(&prcm->res_cal_ctrl, 2); + setbits_le32(prcm + CCU_PRCM_SYS_PWROFF_GATING, 0x10); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 2); } if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { - clrbits_le32(&prcm->res_cal_ctrl, 1); - setbits_le32(&prcm->res_cal_ctrl, 1); + clrbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, 1); } if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { /* set key field for ldo enable */ - setbits_le32(&prcm->pll_ldo_cfg, 0xA7000000); + setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0xA7000000); /* set PLL VDD LDO output to 1.14 V */ - setbits_le32(&prcm->pll_ldo_cfg, 0x60000); + setbits_le32(prcm + CCU_PRCM_PLL_LDO_CFG, 0x60000); } clock_set_pll1(408000000); - writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); - while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) + writel(CCM_PLL6_DEFAULT, ccm + CCU_H6_PLL6_CFG); + while (!(readl(ccm + CCU_H6_PLL6_CFG) & CCM_PLL6_LOCK)) ; - clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, + clrsetbits_le32(ccm + CCU_H6_CPU_AXI_CFG, + CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, CCM_CPU_AXI_DEFAULT_FACTORS); - writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); + writel(CCM_PSI_AHB1_AHB2_DEFAULT, ccm + CCU_H6_PSI_AHB1_AHB2_CFG); #ifdef CCM_AHB3_DEFAULT - writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); + writel(CCM_AHB3_DEFAULT, ccm + CCU_H6_AHB3_CFG); #endif - writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg); + writel(CCM_APB1_DEFAULT, ccm + CCU_H6_APB1_CFG); /* * The mux and factor are set, but the clock will be enabled in * DRAM initialization code. */ - writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); + writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), ccm + CCU_H6_MBUS_CFG); } void clock_init_uart(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; /* uart clock source is apb2 */ writel(APB2_CLK_SRC_OSC24M| APB2_CLK_RATE_N_1| APB2_CLK_RATE_M(1), - &ccm->apb2_cfg); + ccm + CCU_H6_APB2_CFG); /* open the clock for uart */ - setbits_le32(&ccm->uart_gate_reset, + setbits_le32(ccm + CCU_H6_UART_GATE_RESET, 1 << (CONFIG_CONS_INDEX - 1)); /* deassert uart reset */ - setbits_le32(&ccm->uart_gate_reset, + setbits_le32(ccm + CCU_H6_UART_GATE_RESET, 1 << (RESET_SHIFT + CONFIG_CONS_INDEX - 1)); } void clock_set_pll1(unsigned int clk) { - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; u32 val; /* Do not support clocks < 288MHz as they need factor P */ if (clk < 288000000) clk = 288000000; /* Switch to 24MHz clock while changing PLL1 */ - val = readl(&ccm->cpu_axi_cfg); + val = readl(ccm + CCU_H6_CPU_AXI_CFG); val &= ~CCM_CPU_AXI_MUX_MASK; val |= CCM_CPU_AXI_MUX_OSC24M; - writel(val, &ccm->cpu_axi_cfg); + writel(val, ccm + CCU_H6_CPU_AXI_CFG); /* clk = 24*n/p, p is ignored if clock is >288MHz */ val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2; @@ -94,22 +91,20 @@ void clock_set_pll1(unsigned int clk) val |= CCM_PLL1_OUT_EN; if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN; - writel(val, &ccm->pll1_cfg); - while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} + writel(val, ccm + CCU_H6_PLL1_CFG); + while (!(readl(ccm + CCU_H6_PLL1_CFG) & CCM_PLL1_LOCK)) {} /* Switch CPU to PLL1 */ - val = readl(&ccm->cpu_axi_cfg); + val = readl(ccm + CCU_H6_CPU_AXI_CFG); val &= ~CCM_CPU_AXI_MUX_MASK; val |= CCM_CPU_AXI_MUX_PLL_CPUX; - writel(val, &ccm->cpu_axi_cfg); + writel(val, ccm + CCU_H6_CPU_AXI_CFG); } int clock_twi_onoff(int port, int state) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + void *const ccm = (void *)SUNXI_CCM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; u32 value, *ptr; int shift; @@ -117,10 +112,10 @@ int clock_twi_onoff(int port, int state) if (port == 5) { shift = 0; - ptr = &prcm->twi_gate_reset; + ptr = prcm + CCU_PRCM_I2C_GATE_RESET; } else { shift = port; - ptr = &ccm->twi_gate_reset; + ptr = ccm + CCU_H6_I2C_GATE_RESET; } /* set the apb clock gate and reset for twi */ @@ -136,9 +131,8 @@ int clock_twi_onoff(int port, int state) /* PLL_PERIPH0 clock, used by the MMC driver */ unsigned int clock_get_pll6(void) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - uint32_t rval = readl(&ccm->pll6_cfg); + void *const ccm = (void *)SUNXI_CCM_BASE; + uint32_t rval = readl(ccm + CCU_H6_PLL6_CFG); int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> CCM_PLL6_CTRL_DIV2_SHIFT) + 1; diff --git a/arch/arm/mach-sunxi/dram_dw_helpers.c b/arch/arm/mach-sunxi/dram_dw_helpers.c new file mode 100644 index 00000000000..24767354935 --- /dev/null +++ b/arch/arm/mach-sunxi/dram_dw_helpers.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Helpers that are commonly used with DW memory controller. + * + * (C) Copyright 2025 Jernej Skrabec <jernej.skrabec@gmail.com> + * + */ + +#include <init.h> +#include <asm/arch/dram_dw_helpers.h> + +void mctl_auto_detect_rank_width(const struct dram_para *para, + struct dram_config *config) +{ + /* this is minimum size that it's supported */ + config->cols = 8; + config->rows = 13; + + /* + * Strategy here is to test most demanding combination first and least + * demanding last, otherwise HW might not be fully utilized. For + * example, half bus width and rank = 1 combination would also work + * on HW with full bus width and rank = 2, but only 1/4 RAM would be + * visible. + */ + + debug("testing 32-bit width, rank = 2\n"); + config->bus_full_width = 1; + config->ranks = 2; + if (mctl_core_init(para, config)) + return; + + debug("testing 32-bit width, rank = 1\n"); + config->bus_full_width = 1; + config->ranks = 1; + if (mctl_core_init(para, config)) + return; + + debug("testing 16-bit width, rank = 2\n"); + config->bus_full_width = 0; + config->ranks = 2; + if (mctl_core_init(para, config)) + return; + + debug("testing 16-bit width, rank = 1\n"); + config->bus_full_width = 0; + config->ranks = 1; + if (mctl_core_init(para, config)) + return; + + panic("This DRAM setup is currently not supported.\n"); +} + +static void mctl_write_pattern(void) +{ + unsigned int i; + u32 *ptr, val; + + ptr = (u32 *)CFG_SYS_SDRAM_BASE; + for (i = 0; i < 16; ptr++, i++) { + if (i & 1) + val = ~(ulong)ptr; + else + val = (ulong)ptr; + writel(val, ptr); + } +} + +static bool mctl_check_pattern(ulong offset) +{ + unsigned int i; + u32 *ptr, val; + + ptr = (u32 *)CFG_SYS_SDRAM_BASE; + for (i = 0; i < 16; ptr++, i++) { + if (i & 1) + val = ~(ulong)ptr; + else + val = (ulong)ptr; + if (val != *(ptr + offset / 4)) + return false; + } + + return true; +} + +void mctl_auto_detect_dram_size(const struct dram_para *para, + struct dram_config *config) +{ + unsigned int shift, cols, rows; + u32 buffer[16]; + + /* max. config for columns, but not rows */ + config->cols = 11; + config->rows = 13; + mctl_core_init(para, config); + + /* + * Store content so it can be restored later. This is important + * if controller was already initialized and holds any data + * which is important for restoring system. + */ + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + + mctl_write_pattern(); + + shift = config->bus_full_width + 1; + + /* detect column address bits */ + for (cols = 8; cols < 11; cols++) { + if (mctl_check_pattern(1ULL << (cols + shift))) + break; + } + debug("detected %u columns\n", cols); + + /* restore data */ + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); + + /* reconfigure to make sure that all active rows are accessible */ + config->cols = 8; + config->rows = 17; + mctl_core_init(para, config); + + /* store data again as it might be moved */ + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); + + mctl_write_pattern(); + + /* detect row address bits */ + shift = config->bus_full_width + 4 + config->cols; + for (rows = 13; rows < 17; rows++) { + if (mctl_check_pattern(1ULL << (rows + shift))) + break; + } + debug("detected %u rows\n", rows); + + /* restore data again */ + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); + + config->cols = cols; + config->rows = rows; +} + +unsigned long mctl_calc_size(const struct dram_config *config) +{ + u8 width = config->bus_full_width ? 4 : 2; + + /* 8 banks */ + return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; +} diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c index e7862bd06ea..84fd64a2bfc 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h6.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> +#include <asm/arch/dram_dw_helpers.h> #include <asm/arch/cpu.h> #include <asm/arch/prcm.h> #include <linux/bitops.h> @@ -34,23 +35,26 @@ * similar PHY is ZynqMP. */ -static void mctl_sys_init(struct dram_para *para); -static void mctl_com_init(struct dram_para *para); -static bool mctl_channel_init(struct dram_para *para); +static void mctl_sys_init(u32 clk_rate); +static void mctl_com_init(const struct dram_para *para, + const struct dram_config *config); +static bool mctl_channel_init(const struct dram_para *para, + const struct dram_config *config); -static bool mctl_core_init(struct dram_para *para) +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config) { - mctl_sys_init(para); - mctl_com_init(para); + mctl_sys_init(para->clk); + mctl_com_init(para, config); switch (para->type) { case SUNXI_DRAM_TYPE_LPDDR3: case SUNXI_DRAM_TYPE_DDR3: - mctl_set_timing_params(para); + mctl_set_timing_params(); break; default: panic("Unsupported DRAM type!"); }; - return mctl_channel_init(para); + return mctl_channel_init(para, config); } /* PHY initialisation */ @@ -150,36 +154,36 @@ static void mctl_set_master_priority(void) MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32); } -static void mctl_sys_init(struct dram_para *para) +static void mctl_sys_init(u32 clk_rate) { - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; /* Put all DRAM-related blocks to reset state */ - clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET); - clrbits_le32(&ccm->dram_gate_reset, BIT(0)); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE | MBUS_RESET); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0)); udelay(5); - writel(0, &ccm->dram_gate_reset); - clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); - clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + writel(0, ccm + CCU_H6_DRAM_GATE_RESET); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Set PLL5 rate to doubled DRAM clock rate */ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | - CCM_PLL5_CTRL_N(para->clk * 2 / 24), &ccm->pll5_cfg); - mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK); + CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG); + mctl_await_completion(ccm + CCU_H6_PLL5_CFG, + CCM_PLL5_LOCK, CCM_PLL5_LOCK); /* Configure DRAM mod clock */ - writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); - setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE); - writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); + writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_CLK_UPDATE); + writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET); udelay(5); - setbits_le32(&ccm->dram_gate_reset, BIT(0)); + setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(0)); /* Disable all channels */ writel(0, &mctl_com->maer0); @@ -187,24 +191,24 @@ static void mctl_sys_init(struct dram_para *para) writel(0, &mctl_com->maer2); /* Configure MBUS and enable DRAM mod reset */ - setbits_le32(&ccm->mbus_cfg, MBUS_RESET); - setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); - setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Unknown hack from the BSP, which enables access of mctl_ctl regs */ writel(0x8000, &mctl_ctl->unk_0x00c); } -static void mctl_set_addrmap(struct dram_para *para) +static void mctl_set_addrmap(const struct dram_config *config) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - u8 cols = para->cols; - u8 rows = para->rows; - u8 ranks = para->ranks; + u8 cols = config->cols; + u8 rows = config->rows; + u8 ranks = config->ranks; - if (!para->bus_full_width) + if (!config->bus_full_width) cols -= 1; /* Ranks */ @@ -282,7 +286,8 @@ static void mctl_set_addrmap(struct dram_para *para) mctl_ctl->addrmap[8] = 0x3F3F; } -static void mctl_com_init(struct dram_para *para) +static void mctl_com_init(const struct dram_para *para, + const struct dram_config *config) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; @@ -292,7 +297,7 @@ static void mctl_com_init(struct dram_para *para) (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; u32 reg_val, tmp; - mctl_set_addrmap(para); + mctl_set_addrmap(config); setbits_le32(&mctl_com->cr, BIT(31)); @@ -311,12 +316,12 @@ static void mctl_com_init(struct dram_para *para) clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val); /* TODO: DDR4 */ - reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks); + reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(config->ranks); if (para->type == SUNXI_DRAM_TYPE_LPDDR3) reg_val |= MSTR_DEVICETYPE_LPDDR3; if (para->type == SUNXI_DRAM_TYPE_DDR3) reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE; - if (para->bus_full_width) + if (config->bus_full_width) reg_val |= MSTR_BUSWIDTH_FULL; else reg_val |= MSTR_BUSWIDTH_HALF; @@ -328,7 +333,7 @@ static void mctl_com_init(struct dram_para *para) reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T; writel(reg_val | 0x400, &mctl_phy->dcr); - if (para->ranks == 2) + if (config->ranks == 2) writel(0x0303, &mctl_ctl->odtmap); else writel(0x0201, &mctl_ctl->odtmap); @@ -346,13 +351,13 @@ static void mctl_com_init(struct dram_para *para) } writel(reg_val, &mctl_ctl->odtcfg); - if (!para->bus_full_width) { + if (!config->bus_full_width) { writel(0x0, &mctl_phy->dx[2].gcr[0]); writel(0x0, &mctl_phy->dx[3].gcr[0]); } } -static void mctl_bit_delay_set(struct dram_para *para) +static void mctl_bit_delay_set(const struct dram_para *para) { struct sunxi_mctl_phy_reg * const mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; @@ -411,7 +416,8 @@ static void mctl_bit_delay_set(struct dram_para *para) } } -static bool mctl_channel_init(struct dram_para *para) +static bool mctl_channel_init(const struct dram_para *para, + const struct dram_config *config) { struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; @@ -446,14 +452,14 @@ static bool mctl_channel_init(struct dram_para *para) udelay(100); - if (para->ranks == 2) + if (config->ranks == 2) setbits_le32(&mctl_phy->dtcr[1], 0x30000); else clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000); if (sunxi_dram_is_lpddr(para->type)) clrbits_le32(&mctl_phy->dtcr[1], BIT(1)); - if (para->ranks == 2) { + if (config->ranks == 2) { writel(0x00010001, &mctl_phy->rankidr); writel(0x20000, &mctl_phy->odtcr); } else { @@ -555,90 +561,6 @@ static bool mctl_channel_init(struct dram_para *para) return true; } -static void mctl_auto_detect_rank_width(struct dram_para *para) -{ - /* this is minimum size that it's supported */ - para->cols = 8; - para->rows = 13; - - /* - * Previous versions of this driver tried to auto detect the rank - * and width by looking at controller registers. However this proved - * to be not reliable, so this approach here is the more robust - * solution. Check the git history for details. - * - * Strategy here is to test most demanding combination first and least - * demanding last, otherwise HW might not be fully utilized. For - * example, half bus width and rank = 1 combination would also work - * on HW with full bus width and rank = 2, but only 1/4 RAM would be - * visible. - */ - - debug("testing 32-bit width, rank = 2\n"); - para->bus_full_width = 1; - para->ranks = 2; - if (mctl_core_init(para)) - return; - - debug("testing 32-bit width, rank = 1\n"); - para->bus_full_width = 1; - para->ranks = 1; - if (mctl_core_init(para)) - return; - - debug("testing 16-bit width, rank = 2\n"); - para->bus_full_width = 0; - para->ranks = 2; - if (mctl_core_init(para)) - return; - - debug("testing 16-bit width, rank = 1\n"); - para->bus_full_width = 0; - para->ranks = 1; - if (mctl_core_init(para)) - return; - - panic("This DRAM setup is currently not supported.\n"); -} - -static void mctl_auto_detect_dram_size(struct dram_para *para) -{ - /* TODO: non-(LP)DDR3 */ - - /* detect row address bits */ - para->cols = 8; - para->rows = 18; - mctl_core_init(para); - - for (para->rows = 13; para->rows < 18; para->rows++) { - /* 8 banks, 8 bit per byte and 16/32 bit width */ - if (mctl_mem_matches((1 << (para->rows + para->cols + - 4 + para->bus_full_width)))) - break; - } - - /* detect column address bits */ - para->cols = 11; - mctl_core_init(para); - - for (para->cols = 8; para->cols < 11; para->cols++) { - /* 8 bits per byte and 16/32 bit width */ - if (mctl_mem_matches(1 << (para->cols + 1 + - para->bus_full_width))) - break; - } -} - -unsigned long mctl_calc_size(struct dram_para *para) -{ - u8 width = para->bus_full_width ? 4 : 2; - - /* TODO: non-(LP)DDR3 */ - - /* 8 banks */ - return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks; -} - #define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \ {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ @@ -661,36 +583,36 @@ unsigned long mctl_calc_size(struct dram_para *para) { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }} -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - struct dram_para para = { - .clk = CONFIG_DRAM_CLK, +static const struct dram_para para = { + .clk = CONFIG_DRAM_CLK, #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3 - .type = SUNXI_DRAM_TYPE_LPDDR3, - .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, - .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS, + .type = SUNXI_DRAM_TYPE_LPDDR3, + .dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS, + .dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS, #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333) - .type = SUNXI_DRAM_TYPE_DDR3, - .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS, - .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS, + .type = SUNXI_DRAM_TYPE_DDR3, + .dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS, + .dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS, #endif - }; +}; +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; + struct dram_config config; unsigned long size; - setbits_le32(&prcm->res_cal_ctrl, BIT(8)); - clrbits_le32(&prcm->ohms240, 0x3f); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8)); + clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f); - mctl_auto_detect_rank_width(¶); - mctl_auto_detect_dram_size(¶); + mctl_auto_detect_rank_width(¶, &config); + mctl_auto_detect_dram_size(¶, &config); - mctl_core_init(¶); + mctl_core_init(¶, &config); - size = mctl_calc_size(¶); + size = mctl_calc_size(&config); clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0); diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index cd9d321a018..5a59f82d1ef 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -17,6 +17,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> +#include <asm/arch/dram_dw_helpers.h> #include <asm/arch/cpu.h> #include <asm/arch/prcm.h> #include <linux/bitops.h> @@ -93,34 +94,34 @@ static void mctl_set_master_priority(void) static void mctl_sys_init(u32 clk_rate) { - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void * const ccm = (void *)SUNXI_CCM_BASE; struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; /* Put all DRAM-related blocks to reset state */ - clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); - clrbits_le32(&ccm->mbus_cfg, MBUS_RESET); - clrbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT)); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); + clrbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); udelay(5); - clrbits_le32(&ccm->dram_gate_reset, BIT(RESET_SHIFT)); - clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); - clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + clrbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(RESET_SHIFT)); + clrbits_le32(ccm + CCU_H6_PLL5_CFG, CCM_PLL5_CTRL_EN); + clrbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Set PLL5 rate to doubled DRAM clock rate */ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN | CCM_PLL5_OUT_EN | - CCM_PLL5_CTRL_N(clk_rate * 2 / 24), &ccm->pll5_cfg); - mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK); + CCM_PLL5_CTRL_N(clk_rate * 2 / 24), ccm + CCU_H6_PLL5_CFG); + mctl_await_completion(ccm + CCU_H6_PLL5_CFG, + CCM_PLL5_LOCK, CCM_PLL5_LOCK); /* Configure DRAM mod clock */ - writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg); - writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset); + writel(DRAM_CLK_SRC_PLL5, ccm + CCU_H6_DRAM_CLK_CFG); + writel(BIT(RESET_SHIFT), ccm + CCU_H6_DRAM_GATE_RESET); udelay(5); - setbits_le32(&ccm->dram_gate_reset, BIT(GATE_SHIFT)); + setbits_le32(ccm + CCU_H6_DRAM_GATE_RESET, BIT(GATE_SHIFT)); /* Disable all channels */ writel(0, &mctl_com->maer0); @@ -128,12 +129,12 @@ static void mctl_sys_init(u32 clk_rate) writel(0, &mctl_com->maer2); /* Configure MBUS and enable DRAM mod reset */ - setbits_le32(&ccm->mbus_cfg, MBUS_RESET); - setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_RESET); + setbits_le32(ccm + CCU_H6_MBUS_CFG, MBUS_ENABLE); clrbits_le32(&mctl_com->unk_0x500, BIT(25)); - setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET); + setbits_le32(ccm + CCU_H6_DRAM_CLK_CFG, DRAM_MOD_RESET); udelay(5); /* Unknown hack, which enables access of mctl_ctl regs */ @@ -1310,154 +1311,14 @@ static bool mctl_ctrl_init(const struct dram_para *para, return true; } -static bool mctl_core_init(const struct dram_para *para, - const struct dram_config *config) +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config) { mctl_sys_init(para->clk); return mctl_ctrl_init(para, config); } -static void mctl_auto_detect_rank_width(const struct dram_para *para, - struct dram_config *config) -{ - /* this is minimum size that it's supported */ - config->cols = 8; - config->rows = 13; - - /* - * Strategy here is to test most demanding combination first and least - * demanding last, otherwise HW might not be fully utilized. For - * example, half bus width and rank = 1 combination would also work - * on HW with full bus width and rank = 2, but only 1/4 RAM would be - * visible. - */ - - debug("testing 32-bit width, rank = 2\n"); - config->bus_full_width = 1; - config->ranks = 2; - if (mctl_core_init(para, config)) - return; - - debug("testing 32-bit width, rank = 1\n"); - config->bus_full_width = 1; - config->ranks = 1; - if (mctl_core_init(para, config)) - return; - - debug("testing 16-bit width, rank = 2\n"); - config->bus_full_width = 0; - config->ranks = 2; - if (mctl_core_init(para, config)) - return; - - debug("testing 16-bit width, rank = 1\n"); - config->bus_full_width = 0; - config->ranks = 1; - if (mctl_core_init(para, config)) - return; - - panic("This DRAM setup is currently not supported.\n"); -} - -static void mctl_write_pattern(void) -{ - unsigned int i; - u32 *ptr, val; - - ptr = (u32 *)CFG_SYS_SDRAM_BASE; - for (i = 0; i < 16; ptr++, i++) { - if (i & 1) - val = ~(ulong)ptr; - else - val = (ulong)ptr; - writel(val, ptr); - } -} - -static bool mctl_check_pattern(ulong offset) -{ - unsigned int i; - u32 *ptr, val; - - ptr = (u32 *)CFG_SYS_SDRAM_BASE; - for (i = 0; i < 16; ptr++, i++) { - if (i & 1) - val = ~(ulong)ptr; - else - val = (ulong)ptr; - if (val != *(ptr + offset / 4)) - return false; - } - - return true; -} - -static void mctl_auto_detect_dram_size(const struct dram_para *para, - struct dram_config *config) -{ - unsigned int shift, cols, rows; - u32 buffer[16]; - - /* max. config for columns, but not rows */ - config->cols = 11; - config->rows = 13; - mctl_core_init(para, config); - - /* - * Store content so it can be restored later. This is important - * if controller was already initialized and holds any data - * which is important for restoring system. - */ - memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); - - mctl_write_pattern(); - - shift = config->bus_full_width + 1; - - /* detect column address bits */ - for (cols = 8; cols < 11; cols++) { - if (mctl_check_pattern(1ULL << (cols + shift))) - break; - } - debug("detected %u columns\n", cols); - - /* restore data */ - memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); - - /* reconfigure to make sure that all active rows are accessible */ - config->cols = 8; - config->rows = 17; - mctl_core_init(para, config); - - /* store data again as it might be moved */ - memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer)); - - mctl_write_pattern(); - - /* detect row address bits */ - shift = config->bus_full_width + 4 + config->cols; - for (rows = 13; rows < 17; rows++) { - if (mctl_check_pattern(1ULL << (rows + shift))) - break; - } - debug("detected %u rows\n", rows); - - /* restore data again */ - memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer)); - - config->cols = cols; - config->rows = rows; -} - -static unsigned long mctl_calc_size(const struct dram_config *config) -{ - u8 width = config->bus_full_width ? 4 : 2; - - /* 8 banks */ - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; -} - static const struct dram_para para = { .clk = CONFIG_DRAM_CLK, #ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333 @@ -1481,13 +1342,12 @@ static const struct dram_para para = { unsigned long sunxi_dram_init(void) { - struct sunxi_prcm_reg *const prcm = - (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + void *const prcm = (void *)SUNXI_PRCM_BASE; struct dram_config config; unsigned long size; - setbits_le32(&prcm->res_cal_ctrl, BIT(8)); - clrbits_le32(&prcm->ohms240, 0x3f); + setbits_le32(prcm + CCU_PRCM_RES_CAL_CTRL, BIT(8)); + clrbits_le32(prcm + CCU_PRCM_OHMS240, 0x3f); mctl_auto_detect_rank_width(¶, &config); mctl_auto_detect_dram_size(¶, &config); diff --git a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c index afe8e25c7f5..1ed46fed411 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_ddr3_1333.c @@ -37,7 +37,7 @@ static u32 mr_ddr3[7] = { }; /* TODO: flexible timing */ -void mctl_set_timing_params(struct dram_para *para) +void mctl_set_timing_params(void) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c index c243b574406..c02f542c989 100644 --- a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c +++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3.c @@ -16,7 +16,7 @@ static u32 mr_lpddr3[12] = { }; /* TODO: flexible timing */ -void mctl_set_timing_params(struct dram_para *para) +void mctl_set_timing_params(void) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S index 422007c985b..a6d75c32ed9 100644 --- a/arch/arm/mach-sunxi/rmr_switch.S +++ b/arch/arm/mach-sunxi/rmr_switch.S @@ -49,10 +49,22 @@ start32: str lr, [r0, #4] mrs lr, CPSR str lr, [r0, #8] + mrs lr, SP_irq + str lr, [r0, #20] mrc p15, 0, lr, cr1, cr0, 0 // SCTLR str lr, [r0, #12] mrc p15, 0, lr, cr12, cr0, 0 // VBAR str lr, [r0, #16] +//#ifdef CONFIG_MACH_SUN55I_A523 + mrc p15, 0, lr, cr12, cr12, 5 // ICC_SRE + tst lr, #1 + beq 1f + mrc p15, 0, lr, c4, c6, 0 // ICC_PMR + str lr, [r0, #24] + mrc p15, 0, lr, c12, c12, 7 // ICC_IGRPEN1 + str lr, [r0, #28] +1: +//#endif ldr r1, =CONFIG_SUNXI_RVBAR_ADDRESS ldr r0, =SUNXI_SRAMC_BASE diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 5a10fce7273..20fa977504f 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_MMC_SUNXI_SLOT_EXTRA=1 -CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index 5001ce9ce52..4bb34d02fba 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=0 -CONFIG_USB1_VBUS_PIN="PG11" # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index bc0fc0efe0a..5183ece0762 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=0 -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_USB1_VBUS_PIN="PG11" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_VGA_VIA_LCD=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 22d80ca2c9c..73b28455038 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="PC17" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_I2C1_ENABLE=y CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index e10660c933c..f885fc01e6e 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_USB0_VBUS_PIN="PC17" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_I2C1_ENABLE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index ac900477d1e..34c1f5fd5ab 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC_SUNXI_SLOT_EXTRA=3 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 00a98140b37..5f44d3de4ea 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="PC17" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_I2C1_ENABLE=y CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index f4ae3ae6d8b..271d911bb8c 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_USB0_VBUS_PIN="PC17" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_I2C1_ENABLE=y CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index df4acaf33e2..e90cdda639e 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -6,14 +6,13 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=15291 CONFIG_DRAM_ODT_EN=y -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PB3" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 51f26f48b29..eda0c95584c 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=123 -CONFIG_USB0_VBUS_PIN="PB9" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 0f8e571efed..32775a314ca 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 520939538f8..92e3016703e 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=0 -CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 8b3a9eac788..2290a440fe5 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-auxtek-t004" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 -CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 2cc7bbbd8b7..b1195afea20 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB1_VBUS_PIN="PH23" -CONFIG_USB2_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index d26aa0bb1b4..1e793f1cfc6 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -7,7 +7,6 @@ CONFIG_DRAM_CLK=600 CONFIG_DRAM_ZQ=15291 CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 02be8971df9..46025e95fb8 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_USB1_VBUS_PIN="PH0" -CONFIG_USB2_VBUS_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index c220d269ab6..70d2cfa563d 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-r8-chip" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y -CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y CONFIG_CHIP_DIP_SCAN=y CONFIG_SPL_I2C=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 05874125f4b..17737d86ded 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-gr8-chip-pro" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y -CONFIG_USB0_VBUS_PIN="PB10" CONFIG_SPL_I2C=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=sunxi-nand.0" diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 1cd39d498f2..61fcb61cede 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908" CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 -CONFIG_USB1_VBUS_PIN="" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 40f52d1a8d3..4713fbea341 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -5,9 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" -CONFIG_USB0_ID_DET="PH4" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 270bd7d351a..368919d6d15 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=240 CONFIG_DRAM_ZQ=251 -CONFIG_USB1_VBUS_PIN="" CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0" diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index d3678ad5c75..5b8428f2714 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -5,11 +5,8 @@ CONFIG_SPL=y CONFIG_MACH_SUN9I=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH16" -CONFIG_USB1_VBUS_PIN="PH14" -CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y CONFIG_SYS_I2C_SUN8I_RSB=y +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP809_POWER=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index 184143d7086..5f117f30986 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_USB0_VBUS_PIN="PH17" -CONFIG_USB0_VBUS_DET="PH22" -CONFIG_USB0_ID_DET="PH19" CONFIG_VIDEO_VGA=y CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 29f4df2b81c..e02e70f1473 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -7,10 +7,6 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH11" -CONFIG_USB1_VBUS_PIN="PD29" -CONFIG_USB2_VBUS_PIN="PL6" CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -21,6 +17,7 @@ CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_DLDO4_VOLT=3300 diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index 18b1cfaa811..5130f278816 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -5,9 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index abaf386563e..7d33a531ffb 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-empire-electronix-m712" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 24e8b5be1b5..2bc9a0917c5 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird" CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=251 -CONFIG_USB1_VBUS_PIN="PH24" -CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 541f98db9e1..6789e6b2b7e 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -4,10 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-hyundai-a7hd" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB09" -CONFIG_USB0_VBUS_DET="PH5" -CONFIG_USB1_VBUS_PIN="" -CONFIG_USB2_VBUS_PIN="PH6" CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:45,ri:274,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH2" CONFIG_VIDEO_LCD_BL_EN="PH9" diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index 9eb9a918aee..3e6c28018b2 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=122 -CONFIG_USB1_VBUS_PIN="PH11" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 0e1a7780c3d..4b0b0e3b845 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -3,8 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-pcduino" CONFIG_SPL=y CONFIG_MACH_SUN4I=y -CONFIG_USB1_VBUS_PIN="" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index d60eedb482a..9a7d80fce0d 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -5,13 +5,13 @@ CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=360 CONFIG_DRAM_ZQ=122 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0" CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index c697d286dc1..1f4739e0005 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad" CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=120 -CONFIG_USB1_VBUS_PIN="PC27" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 2b9bca13d08..be2e4d1809f 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7" CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=120 -CONFIG_USB1_VBUS_PIN="PC27" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index be6dd417545..9b1bb97eedd 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9" CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=120 -CONFIG_USB1_VBUS_PIN="PC27" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index a26677e1c05..c47dc59399d 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -5,11 +5,8 @@ CONFIG_SPL=y CONFIG_MACH_SUN9I=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH3" -CONFIG_USB1_VBUS_PIN="PH4" -CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y CONFIG_SYS_I2C_SUN8I_RSB=y +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP809_POWER=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index e64352b4b6a..b1d8cdb0627 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mini-xplus" CONFIG_SPL=y CONFIG_MACH_SUN4I=y -CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index 53edf525ec0..2ca40fdf2a0 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 -CONFIG_USB1_VBUS_PIN="PH26" -CONFIG_USB2_VBUS_PIN="PH22" CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index ccf32670170..6b6e4025370 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=432 CONFIG_MMC_SUNXI_SLOT_EXTRA=3 -CONFIG_USB1_VBUS_PIN="PH26" -CONFIG_USB2_VBUS_PIN="PH22" CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 59869b74ac5..1c4c8519711 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -6,8 +6,6 @@ CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=251 CONFIG_MMC_SUNXI_SLOT_EXTRA=3 -CONFIG_USB1_VBUS_PIN="" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index cfb432944df..a230599adf6 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=15291 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_ID_DET="PH8" CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index aba95270eb2..d7ef265d213 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2" CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 -CONFIG_USB1_VBUS_PIN="" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index ad41dbd26a1..98c533bbb86 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -8,15 +8,13 @@ CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH11" -CONFIG_USB1_VBUS_PIN="PD24" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y CONFIG_INITIAL_USB_SCAN_DELAY=500 +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_AXP_DLDO3_VOLT=3300 diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index 348140dcc0c..0d78a13bd71 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -7,7 +7,4 @@ CONFIG_DRAM_CLK=600 CONFIG_DRAM_ZQ=3881915 CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="PH15" -CONFIG_USB1_VBUS_PIN="PL7" -CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index d74ef2127d9..fb2b20bea7b 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -6,9 +6,6 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="PB04" -CONFIG_USB0_VBUS_DET="PG01" -CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:480,y:800,depth:18,pclk_khz:25000,le:2,ri:93,up:2,lo:93,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 40aeb6680c2..649e95bfc75 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200" CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_ID_DET="PH4" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index 9f6d2a78f48..49c87c3311a 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-wobo-i5" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 -CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 9b13659bccd..d7988616f6d 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=408 CONFIG_MMC1_PINS_PH=y CONFIG_MMC_SUNXI_SLOT_EXTRA=1 -CONFIG_USB0_VBUS_PIN="PB9" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index de69ebe9956..ae31b7f7499 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=420 CONFIG_DRAM_ZQ=251 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PA15" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:70000,le:120,ri:180,up:17,lo:15,hs:20,vs:3,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index c76f36ec37e..60b678ad09e 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=384 CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index f4edcf43708..94d29a4743e 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry" CONFIG_SPL=y CONFIG_MACH_SUN8I_R40=y CONFIG_DRAM_CLK=576 -CONFIG_USB1_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index 07bda049665..bdabca2ab35 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=251 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PA15" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:1280,depth:24,pclk_khz:64000,le:20,ri:34,up:1,lo:16,hs:10,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO2_VOLT=1800 diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index b0604302c97..3b590913686 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-difrnce-dit4350" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 06a79c935d7..9060db4918b 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -3,9 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-dserve-dsrv9703c" CONFIG_SPL=y CONFIG_MACH_SUN4I=y -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" -CONFIG_USB0_ID_DET="PH4" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:80000,le:479,ri:544,up:5,lo:26,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 935071d61ac..a3fc34f3241 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -6,8 +6,6 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=15291 CONFIG_DRAM_ODT_EN=y -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:52000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -16,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index 205eab29293..ba22a3ed94f 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=32767 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:55000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 29f965200e1..2fcae46e33e 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -6,8 +6,6 @@ CONFIG_MACH_SUN8I_A83T=y CONFIG_DRAM_CLK=480 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y -CONFIG_USB0_VBUS_PIN="PL5" -CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONSOLE_MUX=y diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index c96336f74b3..6893b4a8f6f 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 76228f0cd13..6cb55b635e2 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -6,8 +6,6 @@ CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_ZQ=127 CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index afa530d1bd9..2acf11ddea7 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index ed6a6038424..00ed5d49029 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=456 CONFIG_DRAM_ZQ=15291 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:120,ri:180,up:22,lo:13,hs:20,vs:3,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -15,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index 30c28f70857..3812eed927d 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -9,9 +9,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_OLD_SUNXI_KERNEL_COMPAT=y -CONFIG_USB0_VBUS_PIN="PG11" -CONFIG_USB0_VBUS_DET="PH7" -CONFIG_USB1_VBUS_PIN="PG10" CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index 68a6df50e42..0a50992c5f2 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -5,9 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" -CONFIG_USB0_ID_DET="PH4" CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:52000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index d215a8375e2..da0fb74c88d 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=63351 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:138,ri:162,up:22,lo:10,hs:20,vs:3,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index a5414e2c502..826141ac6c3 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -5,9 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" -CONFIG_USB0_ID_DET="PH4" CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index 48b20c0eefa..7da29635a32 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-inet-98v-rev2" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 5b0cda10f3b..ffc35487279 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -5,9 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=4 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" -CONFIG_USB0_ID_DET="PH4" CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index 24ff6c0062e..5a48bd0c695 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -5,14 +5,13 @@ CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_CLK=384 CONFIG_DRAM_ZQ=251 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PA15" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:65000,le:280,ri:20,up:22,lo:8,hs:20,vs:8,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index b41c2cf3c05..f8c38aa21f2 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-jesurun-q5" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=312 -CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 2f92228eb7b..11e7a3d30b7 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=251 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB1_VBUS_PIN="PH24" -CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index d3d7402f828..f1812d68849 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 -CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 8ebd5e9cbc3..edf64f8308e 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-mk802" CONFIG_SPL=y CONFIG_MACH_SUN4I=y -CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 7aaa5190b3a..50047d9df64 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -5,7 +5,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2" CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 -CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index adffe389e9e..008c09d23c4 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB1_VBUS_PIN="PG13" -CONFIG_USB3_VBUS_PIN="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index f2265ea5179..831bfe66e25 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -8,7 +8,6 @@ CONFIG_DRAM_SUNXI_CA_DRI=0x0e0e CONFIG_DRAM_SUNXI_TPR10=0xf83438 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y -CONFIG_USB1_VBUS_PIN="PC16" CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/orangepi_zero3_defconfig b/configs/orangepi_zero3_defconfig index 63f9a735378..8594924c7e9 100644 --- a/configs/orangepi_zero3_defconfig +++ b/configs/orangepi_zero3_defconfig @@ -13,7 +13,6 @@ CONFIG_DRAM_SUNXI_TPR12=0x0f0f100f CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_LPDDR4=y CONFIG_DRAM_CLK=792 -CONFIG_USB1_VBUS_PIN="PC16" CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index 72235ccc071..631cfd8ffa5 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -6,8 +6,6 @@ CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=600 CONFIG_DRAM_ZQ=15291 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_ID_DET="PD10" -CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FASTBOOT_CMD_OEM_FORMAT=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 20a4a0a437a..3eaa9c8b532 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -5,7 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I_H6=y CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB3_VBUS_PIN="PL5" CONFIG_SPL_SPI_SUNXI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 6ec7c83be5b..6c0d4f1ac8c 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=63351 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index 1aefc50588e..7b64c8b05e7 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=63351 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index 330c97fd6dc..21da05fc40a 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun4i-a10-pov-protab2-ips9" CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=432 -CONFIG_USB0_VBUS_PIN="PB9" -CONFIG_USB0_VBUS_DET="PH5" -CONFIG_USB0_ID_DET="PH4" CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:480,ri:260,up:6,lo:16,hs:320,vs:10,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index 93a257853b3..2c7bc20d4d7 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -4,9 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a13-q8-tablet" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 -CONFIG_USB0_VBUS_PIN="PG12" -CONFIG_USB0_VBUS_DET="PG1" -CONFIG_USB0_ID_DET="PG2" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index 0f8c30ec853..fcf13f64ec0 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=432 CONFIG_DRAM_ZQ=63306 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:36,ri:210,up:18,lo:22,hs:10,vs:5,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index b3b5cc704f4..22e27abc515 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=456 CONFIG_DRAM_ZQ=15291 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index 37ee08fa629..1d9d6fc7302 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -5,8 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A33=y CONFIG_DRAM_CLK=456 CONFIG_DRAM_ZQ=15291 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH8" CONFIG_AXP_GPIO=y CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 @@ -14,6 +12,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 0c9f6197c2c..e90773f8ae3 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -4,7 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun5i-a10s-r7-tv-dongle" CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 -CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index a3b1d76d8bb..3bafc4deeaa 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -5,9 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=63351 -CONFIG_USB0_VBUS_PIN="axp_drivebus" -CONFIG_USB0_VBUS_DET="axp_vbus_detect" -CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/tanix_tx1_defconfig b/configs/tanix_tx1_defconfig index 28cf9513c30..00e34dc5ad9 100644 --- a/configs/tanix_tx1_defconfig +++ b/configs/tanix_tx1_defconfig @@ -14,11 +14,13 @@ CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_LPDDR3=y CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_AXP313_POWER=y CONFIG_AXP_DCDC3_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index 9a70b6bee52..e56bbabfc95 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -8,11 +8,10 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=15355 CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE" -CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_REGULATOR_AXP_DRIVEVBUS=y CONFIG_REGULATOR_AXP_USB_POWER=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index b9b22e77203..6a9261eeeba 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -6,7 +6,6 @@ CONFIG_MACH_SUN50I=y CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 -CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" CONFIG_SPL_SYS_I2C_LEGACY=y diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index bd9b611d6f5..c0628370df9 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -11,6 +11,7 @@ CONFIG_DRAM_SUNXI_TPR11=0xffffdddd CONFIG_DRAM_SUNXI_TPR12=0xfedf7557 CONFIG_MACH_SUN50I_H616=y CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_I2C=y diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c index 6e632c8fc73..181c53bfe72 100644 --- a/drivers/gpio/axp_gpio.c +++ b/drivers/gpio/axp_gpio.c @@ -15,6 +15,9 @@ #include <errno.h> #include <sunxi_gpio.h> +#define AXP_GPIO_PREFIX "AXP0-" +#define AXP_GPIO_COUNT 4 + static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val); static u8 axp_get_gpio_ctrl_reg(unsigned pin) @@ -46,28 +49,14 @@ static int axp_gpio_direction_input(struct udevice *dev, unsigned pin) static int axp_gpio_direction_output(struct udevice *dev, unsigned pin, int val) { - __maybe_unused int ret; u8 reg; - switch (pin) { -#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC - /* Only available on later PMICs */ - case SUNXI_GPIO_AXP0_VBUS_ENABLE: - ret = pmic_bus_clrbits(AXP_MISC_CTRL, - AXP_MISC_CTRL_N_VBUSEN_FUNC); - if (ret) - return ret; - - return axp_gpio_set_value(dev, pin, val); -#endif - default: - reg = axp_get_gpio_ctrl_reg(pin); - if (reg == 0) - return -EINVAL; + reg = axp_get_gpio_ctrl_reg(pin); + if (reg == 0) + return -EINVAL; - return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH : - AXP_GPIO_CTRL_OUTPUT_LOW); - } + return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH : + AXP_GPIO_CTRL_OUTPUT_LOW); } static int axp_gpio_get_value(struct udevice *dev, unsigned pin) @@ -75,25 +64,16 @@ static int axp_gpio_get_value(struct udevice *dev, unsigned pin) u8 reg, val, mask; int ret; - switch (pin) { -#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC - /* Only available on later PMICs */ - case SUNXI_GPIO_AXP0_VBUS_ENABLE: - ret = pmic_bus_read(AXP_VBUS_IPSOUT, &val); - mask = AXP_VBUS_IPSOUT_DRIVEBUS; - break; -#endif - default: - reg = axp_get_gpio_ctrl_reg(pin); - if (reg == 0) - return -EINVAL; + reg = axp_get_gpio_ctrl_reg(pin); + if (reg == 0) + return -EINVAL; - ret = pmic_bus_read(AXP_GPIO_STATE, &val); - mask = 1 << (pin + AXP_GPIO_STATE_OFFSET); - } + ret = pmic_bus_read(AXP_GPIO_STATE, &val); if (ret) return ret; + mask = 1 << (pin + AXP_GPIO_STATE_OFFSET); + return (val & mask) ? 1 : 0; } @@ -101,25 +81,12 @@ static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val) { u8 reg; - switch (pin) { -#ifdef AXP_MISC_CTRL_N_VBUSEN_FUNC - /* Only available on later PMICs */ - case SUNXI_GPIO_AXP0_VBUS_ENABLE: - if (val) - return pmic_bus_setbits(AXP_VBUS_IPSOUT, - AXP_VBUS_IPSOUT_DRIVEBUS); - else - return pmic_bus_clrbits(AXP_VBUS_IPSOUT, - AXP_VBUS_IPSOUT_DRIVEBUS); -#endif - default: - reg = axp_get_gpio_ctrl_reg(pin); - if (reg == 0) - return -EINVAL; + reg = axp_get_gpio_ctrl_reg(pin); + if (reg == 0) + return -EINVAL; - return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH : - AXP_GPIO_CTRL_OUTPUT_LOW); - } + return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH : + AXP_GPIO_CTRL_OUTPUT_LOW); } static const struct dm_gpio_ops gpio_axp_ops = { @@ -134,8 +101,8 @@ static int gpio_axp_probe(struct udevice *dev) struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); /* Tell the uclass how many GPIOs we have */ - uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX); - uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT; + uc_priv->bank_name = AXP_GPIO_PREFIX; + uc_priv->gpio_count = AXP_GPIO_COUNT; return 0; } diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 2ca4960f17a..094c45a6927 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -244,17 +244,7 @@ int sunxi_name_to_gpio(const char *name) int sunxi_name_to_gpio(const char *name) { unsigned int gpio; - int ret; -#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO - char lookup[8]; - - if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) { - sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d", - SUNXI_GPIO_AXP0_VBUS_ENABLE); - name = lookup; - } -#endif - ret = gpio_lookup_name(name, NULL, NULL, &gpio); + int ret = gpio_lookup_name(name, NULL, NULL, &gpio); return ret ? ret : gpio; } diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 951e6acd34d..06c1e09bf26 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -478,29 +478,29 @@ struct sunxi_mmc_priv mmc_host[4]; static int mmc_resource_init(int sdc_no) { struct sunxi_mmc_priv *priv = &mmc_host[sdc_no]; - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void *ccm = (void *)SUNXI_CCM_BASE; debug("init mmc %d resource\n", sdc_no); switch (sdc_no) { case 0: priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; - priv->mclkreg = &ccm->sd0_clk_cfg; + priv->mclkreg = ccm + CCU_MMC0_CLK_CFG; break; case 1: priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; - priv->mclkreg = &ccm->sd1_clk_cfg; + priv->mclkreg = ccm + CCU_MMC1_CLK_CFG; break; #ifdef SUNXI_MMC2_BASE case 2: priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; - priv->mclkreg = &ccm->sd2_clk_cfg; + priv->mclkreg = ccm + CCU_MMC2_CLK_CFG; break; #endif #ifdef SUNXI_MMC3_BASE case 3: priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; - priv->mclkreg = &ccm->sd3_clk_cfg; + priv->mclkreg = ccm + CCU_MMC3_CLK_CFG; break; #endif default: @@ -545,7 +545,7 @@ static const struct mmc_ops sunxi_mmc_ops = { struct mmc *sunxi_mmc_init(int sdc_no) { - struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + void *ccm = (void *)SUNXI_CCM_BASE; struct sunxi_mmc_priv *priv = &mmc_host[sdc_no]; struct mmc_config *cfg = &priv->cfg; int ret; @@ -574,11 +574,11 @@ struct mmc *sunxi_mmc_init(int sdc_no) /* config ahb clock */ debug("init mmc %d clock and io\n", sdc_no); #if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2) - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); + setbits_le32(ccm + CCU_AHB_GATE0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); #ifdef CONFIG_SUNXI_GEN_SUN6I /* unassert reset */ - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); + setbits_le32(ccm + CCU_AHB_RESET0_CFG, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); #endif #if defined(CONFIG_MACH_SUN9I) /* sun9i has a mmc-common module, also set the gate and reset there */ @@ -586,9 +586,9 @@ struct mmc *sunxi_mmc_init(int sdc_no) SUNXI_MMC_COMMON_BASE + 4 * sdc_no); #endif #else /* CONFIG_SUN50I_GEN_H6 */ - setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no); + setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << sdc_no); /* unassert reset */ - setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no)); + setbits_le32(ccm + CCU_H6_MMC_GATE_RESET, 1 << (RESET_SHIFT + sdc_no)); #endif ret = mmc_set_mod_clk(priv, 24000000); if (ret) diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index b9306c9a827..3acffb40b0b 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -85,41 +85,14 @@ struct sun4i_usb_phy_cfg { int missing_phys; }; -struct sun4i_usb_phy_info { - const char *gpio_vbus; - const char *gpio_vbus_det; - const char *gpio_id_det; -} phy_info[] = { - { - .gpio_vbus = CONFIG_USB0_VBUS_PIN, - .gpio_vbus_det = CONFIG_USB0_VBUS_DET, - .gpio_id_det = CONFIG_USB0_ID_DET, - }, - { - .gpio_vbus = CONFIG_USB1_VBUS_PIN, - .gpio_vbus_det = NULL, - .gpio_id_det = NULL, - }, - { - .gpio_vbus = CONFIG_USB2_VBUS_PIN, - .gpio_vbus_det = NULL, - .gpio_id_det = NULL, - }, - { - .gpio_vbus = CONFIG_USB3_VBUS_PIN, - .gpio_vbus_det = NULL, - .gpio_id_det = NULL, - }, -}; - struct sun4i_usb_phy_plat { void __iomem *pmu; - struct gpio_desc gpio_vbus; struct gpio_desc gpio_vbus_det; struct gpio_desc gpio_id_det; struct clk clocks; struct clk clk2; struct reset_ctl resets; + struct udevice *vbus; int id; }; @@ -208,6 +181,7 @@ static int sun4i_usb_phy_power_on(struct phy *phy) { struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; + int ret; if (initial_usb_scan_delay) { mdelay(initial_usb_scan_delay); @@ -220,8 +194,9 @@ static int sun4i_usb_phy_power_on(struct phy *phy) return 0; } - if (dm_gpio_is_valid(&usb_phy->gpio_vbus)) - dm_gpio_set_value(&usb_phy->gpio_vbus, 1); + ret = regulator_set_enable_if_allowed(usb_phy->vbus, true); + if (ret) + return ret; return 0; } @@ -230,9 +205,11 @@ static int sun4i_usb_phy_power_off(struct phy *phy) { struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; + int ret; - if (dm_gpio_is_valid(&usb_phy->gpio_vbus)) - dm_gpio_set_value(&usb_phy->gpio_vbus, 0); + ret = regulator_set_enable_if_allowed(usb_phy->vbus, false); + if (ret) + return ret; return 0; } @@ -481,48 +458,39 @@ static int sun4i_usb_phy_probe(struct udevice *dev) data->usb_phy = plat; for (i = 0; i < data->cfg->num_phys; i++) { struct sun4i_usb_phy_plat *phy = &plat[i]; - struct sun4i_usb_phy_info *info = &phy_info[i]; - char name[16]; + char name[32]; if (data->cfg->missing_phys & BIT(i)) continue; - ret = dm_gpio_lookup_name(info->gpio_vbus, &phy->gpio_vbus); - if (ret == 0) { - ret = dm_gpio_request(&phy->gpio_vbus, "usb_vbus"); - if (ret) - return ret; - ret = dm_gpio_set_dir_flags(&phy->gpio_vbus, - GPIOD_IS_OUT); - if (ret) - return ret; - ret = dm_gpio_set_value(&phy->gpio_vbus, 0); - if (ret) - return ret; - } - - ret = dm_gpio_lookup_name(info->gpio_vbus_det, - &phy->gpio_vbus_det); - if (ret == 0) { - ret = dm_gpio_request(&phy->gpio_vbus_det, - "usb_vbus_det"); - if (ret) - return ret; - ret = dm_gpio_set_dir_flags(&phy->gpio_vbus_det, - GPIOD_IS_IN); + snprintf(name, sizeof(name), "usb%d_vbus-supply", i); + ret = device_get_supply_regulator(dev, name, &phy->vbus); + if (phy->vbus) { + ret = regulator_set_enable_if_allowed(phy->vbus, false); if (ret) return ret; } - ret = dm_gpio_lookup_name(info->gpio_id_det, &phy->gpio_id_det); - if (ret == 0) { - ret = dm_gpio_request(&phy->gpio_id_det, "usb_id_det"); - if (ret) + if (i == 0) { + ret = gpio_request_by_name(dev, "usb0_vbus_det-gpios", + 0, &phy->gpio_vbus_det, + GPIOD_IS_IN); + if (ret && ret != -ENOENT) { + dev_err(dev, + "failed to get VBUS detect GPIO: %d\n", + ret); return ret; - ret = dm_gpio_set_dir_flags(&phy->gpio_id_det, - GPIOD_IS_IN | GPIOD_PULL_UP); - if (ret) + } + + ret = gpio_request_by_name(dev, "usb0_id_det-gpios", 0, + &phy->gpio_id_det, + GPIOD_IS_IN | GPIOD_PULL_UP); + if (ret && ret != -ENOENT) { + dev_err(dev, + "failed to get ID detect GPIO: %d\n", + ret); return ret; + } } if (data->cfg->dedicated_clocks) diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/axp.c index 521a39dd566..c300fd2bbc2 100644 --- a/drivers/power/pmic/axp.c +++ b/drivers/power/pmic/axp.c @@ -51,6 +51,7 @@ static const struct pmic_child_info axp_pmic_child_info[] = { { "cldo", "axp_regulator" }, { "dc", "axp_regulator" }, { "dldo", "axp_regulator" }, + { "drivevbus", "axp_drivevbus" }, { "eldo", "axp_regulator" }, { "fldo", "axp_regulator" }, { "ldo", "axp_regulator" }, diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index bec2d2d7d49..95912ef5633 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -57,6 +57,13 @@ config SPL_REGULATOR_AXP Enable support in SPL for the regulators (DCDCs, LDOs) in the X-Powers AXP152, AXP2xx, and AXP8xx PMICs. +config REGULATOR_AXP_DRIVEVBUS + bool "Enable driver for X-Powers AXP PMIC drivevbus" + depends on DM_REGULATOR && PMIC_AXP + help + Enable support for sensing or driving the USB VBUS on + X-Powers AXP2xx and AXP8xx PMICs. + config REGULATOR_AXP_USB_POWER bool "Enable driver for X-Powers AXP PMIC USB power supply" depends on DM_REGULATOR && PMIC_AXP diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 99affa235f3..0ee5d908a2a 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_$(PHASE_)DM_REGULATOR) += regulator-uclass.o obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o obj-$(CONFIG_$(PHASE_)REGULATOR_AXP) += axp_regulator.o +obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_DRIVEVBUS) += axp_drivevbus.o obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_DA9063) += da9063.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_MAX77663) += max77663_regulator.o diff --git a/drivers/power/regulator/axp_drivevbus.c b/drivers/power/regulator/axp_drivevbus.c new file mode 100644 index 00000000000..c463de8786b --- /dev/null +++ b/drivers/power/regulator/axp_drivevbus.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <dm.h> +#include <power/pmic.h> +#include <power/regulator.h> + +#define AXP_VBUS_IPSOUT 0x30 +#define AXP_VBUS_IPSOUT_DRIVEBUS BIT(2) +#define AXP_MISC_CTRL 0x8f +#define AXP_MISC_CTRL_N_VBUSEN_FUNC BIT(4) + +static int axp_drivevbus_get_enable(struct udevice *dev) +{ + int ret; + + ret = pmic_reg_read(dev->parent, AXP_VBUS_IPSOUT); + if (ret < 0) + return ret; + + return !!(ret & AXP_VBUS_IPSOUT_DRIVEBUS); +} + +static int axp_drivevbus_set_enable(struct udevice *dev, bool enable) +{ + return pmic_clrsetbits(dev->parent, AXP_VBUS_IPSOUT, + AXP_VBUS_IPSOUT_DRIVEBUS, + enable ? AXP_VBUS_IPSOUT_DRIVEBUS : 0); +} + +static const struct dm_regulator_ops axp_drivevbus_ops = { + .get_enable = axp_drivevbus_get_enable, + .set_enable = axp_drivevbus_set_enable, +}; + +static int axp_drivevbus_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_plat = dev_get_uclass_plat(dev); + int ret; + + uc_plat->type = REGULATOR_TYPE_FIXED; + + if (dev_read_bool(dev->parent, "x-powers,drive-vbus-en")) { + ret = pmic_clrsetbits(dev->parent, AXP_MISC_CTRL, + AXP_MISC_CTRL_N_VBUSEN_FUNC, 0); + if (ret) + return ret; + } + + return 0; +} + +U_BOOT_DRIVER(axp_drivevbus) = { + .name = "axp_drivevbus", + .id = UCLASS_REGULATOR, + .probe = axp_drivevbus_probe, + .ops = &axp_drivevbus_ops, +}; diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c index 8eeac935760..467db5fe9bf 100644 --- a/drivers/watchdog/sunxi_wdt.c +++ b/drivers/watchdog/sunxi_wdt.c @@ -153,10 +153,21 @@ static const struct sunxi_wdt_reg sun20i_wdt_reg = { .wdt_key_val = 0x16aa0000, }; +static const struct sunxi_wdt_reg sun55i_wdt_reg = { + .wdt_ctrl = 0x0c, + .wdt_cfg = 0x10, + .wdt_mode = 0x14, + .wdt_timeout_shift = 4, + .wdt_reset_mask = 0x03, + .wdt_reset_val = 0x01, + .wdt_key_val = 0x16aa0000, +}; + static const struct udevice_id sunxi_wdt_ids[] = { { .compatible = "allwinner,sun4i-a10-wdt", .data = (ulong)&sun4i_wdt_reg }, { .compatible = "allwinner,sun6i-a31-wdt", .data = (ulong)&sun6i_wdt_reg }, { .compatible = "allwinner,sun20i-d1-wdt", .data = (ulong)&sun20i_wdt_reg }, + { .compatible = "allwinner,sun55i-a523-wdt", .data = (ulong)&sun55i_wdt_reg }, { /* sentinel */ } }; diff --git a/include/axp221.h b/include/axp221.h index 32b988f3a9c..8a4a3cca82f 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -53,10 +53,6 @@ #ifdef CONFIG_AXP221_POWER #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_ALDO_IN BIT(0) -#define AXP_VBUS_IPSOUT 0x30 -#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) -#define AXP_MISC_CTRL 0x8f -#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ diff --git a/include/axp809.h b/include/axp809.h index 71a7cb2aaa1..3bd71b3d1a3 100644 --- a/include/axp809.h +++ b/include/axp809.h @@ -47,10 +47,6 @@ #ifdef CONFIG_AXP809_POWER #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_ALDO_IN BIT(0) -#define AXP_VBUS_IPSOUT 0x30 -#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) -#define AXP_MISC_CTRL 0x8f -#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ diff --git a/include/axp818.h b/include/axp818.h index 08ac35d15fa..b3a9686e0e5 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -61,10 +61,6 @@ #ifdef CONFIG_AXP818_POWER #define AXP_POWER_STATUS 0x00 #define AXP_POWER_STATUS_ALDO_IN BIT(0) -#define AXP_VBUS_IPSOUT 0x30 -#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) -#define AXP_MISC_CTRL 0x8f -#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index 122987c395e..12b54c8dda4 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -82,7 +82,6 @@ enum sunxi_gpio_number { SUNXI_GPIO_L_START = 352, SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), - SUNXI_GPIO_AXP0_START = 1024, }; /* SUNXI GPIO number definitions */ @@ -99,8 +98,6 @@ enum sunxi_gpio_number { #define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) #define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) -#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) - /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 @@ -185,11 +182,6 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_PULL_UP 1 #define SUNXI_GPIO_PULL_DOWN 2 -/* Virtual AXP0 GPIOs */ -#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" -#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 -#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 - struct sunxi_gpio_plat { void *regs; char bank_name[3]; |