diff options
27 files changed, 869 insertions, 533 deletions
diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts index 65a5fcd67ef..40289c8c4aa 100644 --- a/arch/arm/dts/exynos4210-origen.dts +++ b/arch/arm/dts/exynos4210-origen.dts @@ -25,8 +25,7 @@ }; &sdhci2 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; + bus-width = <4>; cd-gpios = <&gpk2 2 0>; status = "okay"; }; diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 05989ee97e5..88e9c0ed2bb 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -240,15 +240,13 @@ }; &sdhci0 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; + bus-width = <8>; pwr-gpios = <&gpk0 2 0>; status = "okay"; }; &sdhci2 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; + bus-width = <4>; cd-gpios = <&gpx3 4 0>; status = "okay"; }; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index 610a8ad2e71..c87b92be609 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -235,15 +235,13 @@ }; &sdhci0 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; + bus-width = <8>; pwr-gpios = <&gpk0 2 0>; status = "okay"; }; &sdhci2 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; + bus-width = <4>; cd-gpios = <&gpx3 4 0>; status = "okay"; }; diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index ce08e8dc1eb..346e0f55c76 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -234,20 +234,19 @@ }; &sdhci2 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; + bus-width = <4>; cd-inverted; cd-gpios = <&gpk2 2 0>; status = "okay"; }; &mshc_0 { - samsung,bus-width = <8>; - samsung,timing = <2 1 0>; - samsung,removable = <0>; - fifoth_val = <0x203f0040>; - bus_hz = <400000000>; - div = <0x3>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 1>; + non-removable; + fifo-depth = <0x80>; + clock-frequency = <400000000>; index = <4>; status = "okay"; }; diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index c4db137e01f..2b71d328cd0 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -108,8 +108,7 @@ }; sdhci@12510000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; + bus-width = <8>; pwr-gpios = <&gpk0 4 0>; status = "disabled"; }; @@ -431,26 +430,23 @@ }; &sdhci0 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; + bus-width = <8>; pwr-gpios = <&gpk0 4 0>; status = "disabled"; }; &sdhci2 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; + bus-width = <4>; cd-gpios = <&gpk2 2 0>; status = "okay"; }; &mshc_0 { - samsung,bus-width = <8>; - samsung,timing = <2 1 0>; - samsung,removable = <0>; - fifoth_val = <0x203f0040>; - bus_hz = <400000000>; - div = <0x3>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 1>; + non-removable; + clock-frequency = <400000000>; index = <4>; fifo-depth = <0x80>; status = "okay"; diff --git a/arch/arm/dts/exynos5250-arndale.dts b/arch/arm/dts/exynos5250-arndale.dts index 60309c61f30..4c894f1712f 100644 --- a/arch/arm/dts/exynos5250-arndale.dts +++ b/arch/arm/dts/exynos5250-arndale.dts @@ -27,8 +27,9 @@ }; mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 3>; }; mmc@12210000 { @@ -36,8 +37,9 @@ }; mmc@12220000 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; + bus-width = <4>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 2>; }; mmc@12230000 { diff --git a/arch/arm/dts/exynos5250-smdk5250.dts b/arch/arm/dts/exynos5250-smdk5250.dts index afe0cca48a9..f9f54cb6387 100644 --- a/arch/arm/dts/exynos5250-smdk5250.dts +++ b/arch/arm/dts/exynos5250-smdk5250.dts @@ -145,9 +145,10 @@ }; mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - samsung,removable = <0>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 3>; + non-removable; }; mmc@12210000 { @@ -155,9 +156,9 @@ }; mmc@12220000 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; - samsung,removable = <1>; + bus-width = <4>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 2>; }; mmc@12230000 { diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index e41f2d3041e..ab7b5212ba7 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -301,9 +301,10 @@ }; mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - samsung,removable = <0>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 3>; + non-removable; }; mmc@12210000 { @@ -311,9 +312,9 @@ }; mmc@12220000 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; - samsung,removable = <1>; + bus-width = <4>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 2>; }; mmc@12230000 { diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts index 77e7a6b9e45..9c478837ba4 100644 --- a/arch/arm/dts/exynos5250-spring.dts +++ b/arch/arm/dts/exynos5250-spring.dts @@ -103,9 +103,10 @@ }; mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - samsung,removable = <0>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 3>; + non-removable; }; mmc@12210000 { diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts index 7a5da674fbe..6ba1306e862 100644 --- a/arch/arm/dts/exynos5420-smdk5420.dts +++ b/arch/arm/dts/exynos5420-smdk5420.dts @@ -106,9 +106,10 @@ }; mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - samsung,removable = <0>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 3>; + non-removable; samsung,pre-init; }; @@ -117,9 +118,9 @@ }; mmc@12220000 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; - samsung,removable = <1>; + bus-width = <4>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 2>; }; mmc@12230000 { diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index 9d055d066fd..ef25cf77447 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -280,11 +280,11 @@ }; mmc@12200000 { - fifoth_val = <0x201f0020>; + fifo-depth = <0x40>; }; mmc@12220000 { - fifoth_val = <0x201f0020>; + fifo-depth = <0x40>; }; emmc-reset { diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi index 221da8b4850..5915ed69779 100644 --- a/arch/arm/dts/exynos54xx.dtsi +++ b/arch/arm/dts/exynos54xx.dtsi @@ -119,9 +119,10 @@ }; mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - samsung,removable = <0>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 3>; + non-removable; samsung,pre-init; }; @@ -130,9 +131,9 @@ }; mmc@12220000 { - samsung,bus-width = <4>; - samsung,timing = <1 2 3>; - samsung,removable = <1>; + bus-width = <4>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 2>; }; mmc@12230000 { diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h index 59c28ed54c5..75d84988b7d 100644 --- a/arch/arm/mach-exynos/include/mach/dwmmc.h +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h @@ -4,24 +4,34 @@ * Jaehoon Chung <jh80.chung@samsung.com> */ -#define DWMCI_CLKSEL 0x09C -#define DWMCI_SET_SAMPLE_CLK(x) (x) -#define DWMCI_SET_DRV_CLK(x) ((x) << 16) -#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) +#ifndef __ASM_ARM_ARCH_DWMMC_H +#define __ASM_ARM_ARCH_DWMMC_H -#define EMMCP_MPSBEGIN0 0x1200 -#define EMMCP_SEND0 0x1204 -#define EMMCP_CTRL0 0x120C +#include <linux/bitops.h> -#define MPSCTRL_SECURE_READ_BIT (0x1<<7) -#define MPSCTRL_SECURE_WRITE_BIT (0x1<<6) -#define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5) -#define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4) -#define MPSCTRL_USE_FUSE_KEY (0x1<<3) -#define MPSCTRL_ECB_MODE (0x1<<2) -#define MPSCTRL_ENCRYPTION (0x1<<1) -#define MPSCTRL_VALID (0x1<<0) +#define DWMCI_CLKSEL 0x09c +#define DWMCI_CLKSEL64 0x0a8 +#define DWMCI_SET_SAMPLE_CLK(x) (x) +#define DWMCI_SET_DRV_CLK(x) ((x) << 16) +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) + +/* Protector Register */ +#define DWMCI_EMMCP_BASE 0x1000 +#define EMMCP_MPSBEGIN0 (DWMCI_EMMCP_BASE + 0x0200) +#define EMMCP_SEND0 (DWMCI_EMMCP_BASE + 0x0204) +#define EMMCP_CTRL0 (DWMCI_EMMCP_BASE + 0x020c) + +#define MPSCTRL_SECURE_READ_BIT BIT(7) +#define MPSCTRL_SECURE_WRITE_BIT BIT(6) +#define MPSCTRL_NON_SECURE_READ_BIT BIT(5) +#define MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) +#define MPSCTRL_USE_FUSE_KEY BIT(3) +#define MPSCTRL_ECB_MODE BIT(2) +#define MPSCTRL_ENCRYPTION BIT(1) +#define MPSCTRL_VALID BIT(0) /* CLKSEL Register */ #define DWMCI_DIVRATIO_BIT 24 #define DWMCI_DIVRATIO_MASK 0x7 + +#endif /* __ASM_ARM_ARCH_DWMMC_H */ diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index 2949da24267..e5d90996234 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -9,12 +9,20 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos850-e850-96" CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_ANDROID_BOOT_IMAGE=y # CONFIG_AUTOBOOT is not set # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ABOOTIMG=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_TIME=y CONFIG_CMD_RNG=y # CONFIG_NET is not set CONFIG_CLK_EXYNOS850=y -# CONFIG_MMC is not set +CONFIG_MMC_DW=y CONFIG_SOC_SAMSUNG=y CONFIG_EXYNOS_PMU=y CONFIG_EXYNOS_USI=y diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst index 0cb95473e53..0a7b6fc0c9d 100644 --- a/doc/board/samsung/e850-96.rst +++ b/doc/board/samsung/e850-96.rst @@ -47,12 +47,13 @@ Build Procedure --------------- .. warning:: - At the moment both eMMC and USB features are not enabled in U-Boot. Flashing + At the moment USB is not enabled in U-Boot for this board. Although eMMC is + enabled, you won't be able to flash images over USB (fastboot). So flashing U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can be used then to perform USB boot and flash LittleKernel bootloader binary [7]_ to unbrick and revive the board. Flashing U-Boot binary might be helpful for developers or anybody who want to check current state of U-Boot enablement on - E850-96 (which is mostly serial console and related blocks). + E850-96 (which is mostly serial console, eMMC and related blocks). Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain): diff --git a/doc/device-tree-bindings/exynos/dwmmc.txt b/doc/device-tree-bindings/exynos/dwmmc.txt index 694d1959162..d90792be859 100644 --- a/doc/device-tree-bindings/exynos/dwmmc.txt +++ b/doc/device-tree-bindings/exynos/dwmmc.txt @@ -12,7 +12,9 @@ SOC specific and Board specific properties are channel specific. Required SoC Specific Properties: - compatible: should be - - samsung,exynos-dwmmc: for exynos platforms + - samsung,exynos4412-dw-mshc: for Exynos4 platforms + - samsung,exynos-dwmmc: for Exynos5 platforms + - samsung,exynos7-dw-mshc-smu: for Exynos7 platforms (with SMU block) - reg: physical base address of the controller and length of memory mapped region. @@ -23,32 +25,38 @@ Required Board Specific Properties: - #address-cells: should be 1. - #size-cells: should be 0. -- samsung,bus-width: The width of the bus used to interface the devices +- bus-width: The width of the bus used to interface the devices supported by DWC_mobile_storage (SD-MMC/EMMC/SDIO). . Typically the bus width is 4 or 8. -- samsung,timing: The timing values to be written into the - Drv/sample clock selection register of corresponding channel. - . It is comprised of 3 values corresponding to the 3 fileds - 'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register. - . SelClk_sample: Select sample clock among 8 shifted clocks. - . SelClk_drv: Select drv clock among 8 shifted clocks. - . DIVRATIO: Clock Divide ratio select. - . The above 3 values are used by the clock phase shifter. +- samsung,dw-mshc-ciu-div: The divider value for the card interface unit (ciu) + clock (0..7). +- samsung,dw-mshc-sdr-timing: The timing values for single data rate (SDR) mode + operation. + . First value is CIU clock phase shift value for TX mode (0..7). + . Second value is CIU clock phase shift value for RX mode (0..7). +- samsung,dw-mshc-ddr-timing: The timing values for double data rate (DDR) mode + operation. If missing, values from samsung,dw-mshc-sdr-timing are used. + . First value is CIU clock phase shift value for TX mode (0..7). + . Second value is CIU clock phase shift value for RX mode (0..7). Example: mmc@12200000 { - samsung,bus-width = <8>; - samsung,timing = <1 3 3>; - samsung,removable = <1>; -} + bus-width = <8>; + non-removable; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <1 3>; + samsung,dw-mshc-ddr-timing = <0 2>; +}; + In the above example, . The bus width is 8 - . Timing is comprised of 3 values as explained below + . Divider value for CLKSEL register is 3. The CIU clock rate will be + calculated as SDCLKIN / (3 + 1). + . SDR and DDR timings are comprised of 2 values as explained below 1 - SelClk_sample 3 - SelClk_drv - 3 - DIVRATIO - . The 'removable' flag indicates whether the the particilar device + . The 'non-removable' flag indicates whether the particular device cannot be removed (always present) or it is a removable device. - 1 - Indicates that the device is removable. - 0 - Indicates that the device cannot be removed. + Flag is present - Indicates that the device cannot be removed. + Flag is not present - Indicates that the device is removable. diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index 54a2ba4795e..1af5ec0532e 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -86,7 +86,7 @@ unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq) clk_div = 1; } - return SD_SCLK_MAX / clk_div / (host->div + 1); + return SD_SCLK_MAX / clk_div; } static int ca_dwmmc_of_to_plat(struct udevice *dev) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index f4ecd7422ce..8551eac7018 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -20,6 +20,47 @@ #define PAGE_SIZE 4096 +/* Internal DMA Controller (IDMAC) descriptor for 32-bit addressing mode */ +struct dwmci_idmac32 { + u32 des0; /* Control descriptor */ + u32 des1; /* Buffer size */ + u32 des2; /* Buffer physical address */ + u32 des3; /* Next descriptor physical address */ +} __aligned(ARCH_DMA_MINALIGN); + +/* Internal DMA Controller (IDMAC) descriptor for 64-bit addressing mode */ +struct dwmci_idmac64 { + u32 des0; /* Control descriptor */ + u32 des1; /* Reserved */ + u32 des2; /* Buffer sizes */ + u32 des3; /* Reserved */ + u32 des4; /* Lower 32-bits of Buffer Address Pointer 1 */ + u32 des5; /* Upper 32-bits of Buffer Address Pointer 1 */ + u32 des6; /* Lower 32-bits of Next Descriptor Address */ + u32 des7; /* Upper 32-bits of Next Descriptor Address */ +} __aligned(ARCH_DMA_MINALIGN); + +/* Register offsets for DW MMC blocks with 32-bit IDMAC */ +static const struct dwmci_idmac_regs dwmci_idmac_regs32 = { + .dbaddrl = DWMCI_DBADDR, + .idsts = DWMCI_IDSTS, + .idinten = DWMCI_IDINTEN, + .dscaddrl = DWMCI_DSCADDR, + .bufaddrl = DWMCI_BUFADDR, +}; + +/* Register offsets for DW MMC blocks with 64-bit IDMAC */ +static const struct dwmci_idmac_regs dwmci_idmac_regs64 = { + .dbaddrl = DWMCI_DBADDRL, + .dbaddru = DWMCI_DBADDRU, + .idsts = DWMCI_IDSTS64, + .idinten = DWMCI_IDINTEN64, + .dscaddrl = DWMCI_DSCADDRL, + .dscaddru = DWMCI_DSCADDRU, + .bufaddrl = DWMCI_BUFADDRL, + .bufaddru = DWMCI_BUFADDRU, +}; + static int dwmci_wait_reset(struct dwmci_host *host, u32 value) { unsigned long timeout = 1000; @@ -35,57 +76,98 @@ static int dwmci_wait_reset(struct dwmci_host *host, u32 value) return 0; } -static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, - u32 desc0, u32 desc1, u32 desc2) +static void dwmci_set_idma_desc32(struct dwmci_idmac32 *desc, u32 control, + u32 buf_size, u32 buf_addr) { - struct dwmci_idmac *desc = idmac; + phys_addr_t desc_phys = virt_to_phys(desc); + u32 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac32); - desc->flags = desc0; - desc->cnt = desc1; - desc->addr = desc2; - desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); + desc->des0 = control; + desc->des1 = buf_size; + desc->des2 = buf_addr; + desc->des3 = next_desc_phys; } -static void dwmci_prepare_data(struct dwmci_host *host, - struct mmc_data *data, - struct dwmci_idmac *cur_idmac, - void *bounce_buffer) +static void dwmci_set_idma_desc64(struct dwmci_idmac64 *desc, u32 control, + u32 buf_size, u64 buf_addr) { - unsigned long ctrl; - unsigned int i = 0, flags, cnt, blk_cnt; + phys_addr_t desc_phys = virt_to_phys(desc); + u64 next_desc_phys = desc_phys + sizeof(struct dwmci_idmac64); + + desc->des0 = control; + desc->des1 = 0; + desc->des2 = buf_size; + desc->des3 = 0; + desc->des4 = buf_addr & 0xffffffff; + desc->des5 = buf_addr >> 32; + desc->des6 = next_desc_phys & 0xffffffff; + desc->des7 = next_desc_phys >> 32; +} + +static void dwmci_prepare_desc(struct dwmci_host *host, struct mmc_data *data, + void *cur_idmac, void *bounce_buffer) +{ + struct dwmci_idmac32 *desc32 = cur_idmac; + struct dwmci_idmac64 *desc64 = cur_idmac; ulong data_start, data_end; + unsigned int blk_cnt, i; + data_start = (ulong)cur_idmac; blk_cnt = data->blocks; - dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); - - /* Clear IDMAC interrupt */ - dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF); + for (i = 0;; i++) { + phys_addr_t buf_phys = virt_to_phys(bounce_buffer); + unsigned int flags, cnt; - data_start = (ulong)cur_idmac; - dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); - - do { - flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; - flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; + flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH; + if (i == 0) + flags |= DWMCI_IDMAC_FS; if (blk_cnt <= 8) { flags |= DWMCI_IDMAC_LD; cnt = data->blocksize * blk_cnt; - } else + } else { cnt = data->blocksize * 8; + } - dwmci_set_idma_desc(cur_idmac, flags, cnt, - (ulong)bounce_buffer + (i * PAGE_SIZE)); + if (host->dma_64bit_address) { + dwmci_set_idma_desc64(desc64, flags, cnt, + buf_phys + i * PAGE_SIZE); + desc64++; + } else { + dwmci_set_idma_desc32(desc32, flags, cnt, + buf_phys + i * PAGE_SIZE); + desc32++; + } - cur_idmac++; if (blk_cnt <= 8) break; blk_cnt -= 8; - i++; - } while(1); + } - data_end = (ulong)cur_idmac; + if (host->dma_64bit_address) + data_end = (ulong)desc64; + else + data_end = (ulong)desc32; flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN)); +} + +static void dwmci_prepare_data(struct dwmci_host *host, struct mmc_data *data, + void *cur_idmac, void *bounce_buffer) +{ + const u32 idmacl = virt_to_phys(cur_idmac) & 0xffffffff; + const u32 idmacu = (u64)virt_to_phys(cur_idmac) >> 32; + unsigned long ctrl; + + dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); + + /* Clear IDMAC interrupt */ + dwmci_writel(host, host->regs->idsts, 0xffffffff); + + dwmci_writel(host, host->regs->dbaddrl, idmacl); + if (host->dma_64bit_address) + dwmci_writel(host, host->regs->dbaddru, idmacu); + + dwmci_prepare_desc(host, data, cur_idmac, bounce_buffer); ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; @@ -132,90 +214,86 @@ static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size) return timeout; } -static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) +static int dwmci_data_transfer_fifo(struct dwmci_host *host, + struct mmc_data *data, u32 mask) { - struct mmc *mmc = host->mmc; + const u32 int_rx = mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO); + const u32 int_tx = mask & DWMCI_INTMSK_TXDR; int ret = 0; - u32 timeout, mask, size, i, len = 0; - u32 *buf = NULL; - ulong start = get_timer(0); - u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> - RX_WMARK_SHIFT) + 1) * 2; + u32 len = 0, size, i; + u32 *buf; + + size = (data->blocksize * data->blocks) / 4; + if (!host->fifo_mode || !size) + return 0; - size = data->blocksize * data->blocks; if (data->flags == MMC_DATA_READ) buf = (unsigned int *)data->dest; else buf = (unsigned int *)data->src; - timeout = dwmci_get_timeout(mmc, size); + if (data->flags == MMC_DATA_READ && int_rx) { + dwmci_writel(host, DWMCI_RINTSTS, int_rx); + while (size) { + ret = dwmci_fifo_ready(host, DWMCI_FIFO_EMPTY, &len); + if (ret < 0) + break; + + len = (len >> DWMCI_FIFO_SHIFT) & DWMCI_FIFO_MASK; + len = min(size, len); + for (i = 0; i < len; i++) + *buf++ = dwmci_readl(host, DWMCI_DATA); + size = size > len ? (size - len) : 0; + } + } else if (data->flags == MMC_DATA_WRITE && int_tx) { + while (size) { + ret = dwmci_fifo_ready(host, DWMCI_FIFO_FULL, &len); + if (ret < 0) + break; + + len = host->fifo_depth - ((len >> DWMCI_FIFO_SHIFT) & + DWMCI_FIFO_MASK); + len = min(size, len); + for (i = 0; i < len; i++) + dwmci_writel(host, DWMCI_DATA, *buf++); + size = size > len ? (size - len) : 0; + } + dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_TXDR); + } - size /= 4; + return ret; +} + +static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) +{ + struct mmc *mmc = host->mmc; + int ret = 0; + u32 timeout, mask, size; + ulong start = get_timer(0); + + size = data->blocksize * data->blocks; + timeout = dwmci_get_timeout(mmc, size); for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); - /* Error during data transfer. */ + /* Error during data transfer */ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { debug("%s: DATA ERROR!\n", __func__); ret = -EINVAL; break; } - if (host->fifo_mode && size) { - len = 0; - if (data->flags == MMC_DATA_READ && - (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) { - dwmci_writel(host, DWMCI_RINTSTS, - mask & (DWMCI_INTMSK_RXDR | - DWMCI_INTMSK_DTO)); - while (size) { - ret = dwmci_fifo_ready(host, - DWMCI_FIFO_EMPTY, - &len); - if (ret < 0) - break; - - len = (len >> DWMCI_FIFO_SHIFT) & - DWMCI_FIFO_MASK; - len = min(size, len); - for (i = 0; i < len; i++) - *buf++ = - dwmci_readl(host, DWMCI_DATA); - size = size > len ? (size - len) : 0; - } - } else if (data->flags == MMC_DATA_WRITE && - (mask & DWMCI_INTMSK_TXDR)) { - while (size) { - ret = dwmci_fifo_ready(host, - DWMCI_FIFO_FULL, - &len); - if (ret < 0) - break; - - len = fifo_depth - ((len >> - DWMCI_FIFO_SHIFT) & - DWMCI_FIFO_MASK); - len = min(size, len); - for (i = 0; i < len; i++) - dwmci_writel(host, DWMCI_DATA, - *buf++); - size = size > len ? (size - len) : 0; - } - dwmci_writel(host, DWMCI_RINTSTS, - DWMCI_INTMSK_TXDR); - } - } + ret = dwmci_data_transfer_fifo(host, data, mask); - /* Data arrived correctly. */ + /* Data arrived correctly */ if (mask & DWMCI_INTMSK_DTO) { ret = 0; break; } - /* Check for timeout. */ + /* Check for timeout */ if (get_timer(start) > timeout) { - debug("%s: Timeout waiting for data!\n", - __func__); + debug("%s: Timeout waiting for data!\n", __func__); ret = -ETIMEDOUT; break; } @@ -226,8 +304,35 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) return ret; } +static int dwmci_dma_transfer(struct dwmci_host *host, uint flags, + struct bounce_buffer *bbstate) +{ + int ret; + u32 mask, ctrl; + + if (flags == MMC_DATA_READ) + mask = DWMCI_IDINTEN_RI; + else + mask = DWMCI_IDINTEN_TI; + + ret = wait_for_bit_le32(host->ioaddr + host->regs->idsts, mask, true, + 1000, false); + if (ret) + debug("%s: DWMCI_IDINTEN mask 0x%x timeout\n", __func__, mask); + + /* Clear interrupts */ + dwmci_writel(host, host->regs->idsts, DWMCI_IDINTEN_MASK); + + ctrl = dwmci_readl(host, DWMCI_CTRL); + ctrl &= ~DWMCI_DMA_EN; + dwmci_writel(host, DWMCI_CTRL, ctrl); + + bounce_buffer_stop(bbstate); + return ret; +} + static int dwmci_set_transfer_mode(struct dwmci_host *host, - struct mmc_data *data) + struct mmc_data *data) { unsigned long mode; @@ -238,33 +343,30 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host, return mode; } -#ifdef CONFIG_DM_MMC -static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, - struct mmc_data *data) +static void dwmci_wait_while_busy(struct dwmci_host *host, struct mmc_cmd *cmd) { - struct mmc *mmc = mmc_get_mmc_dev(dev); -#else -static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) -{ -#endif - struct dwmci_host *host = mmc->priv; - ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, - data ? DIV_ROUND_UP(data->blocks, 8) : 0); - int ret = 0, flags = 0, i; - unsigned int timeout = 500; - u32 retry = 100000; - u32 mask, ctrl; - ulong start = get_timer(0); - struct bounce_buffer bbstate; + unsigned int timeout = 500; /* msec */ + ulong start; + start = get_timer(0); while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { - debug("%s: Timeout on data busy, continue anyway\n", __func__); + debug("%s: Timeout on data busy, continue anyway\n", + __func__); break; } } +} +static int dwmci_send_cmd_common(struct dwmci_host *host, struct mmc_cmd *cmd, + struct mmc_data *data, void *cur_idmac) +{ + int ret, flags = 0, i; + u32 retry = 100000; + u32 mask; + struct bounce_buffer bbstate; + + dwmci_wait_while_busy(host, cmd); dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); if (data) { @@ -276,12 +378,12 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } else { if (data->flags == MMC_DATA_READ) { ret = bounce_buffer_start(&bbstate, - (void*)data->dest, + (void *)data->dest, data->blocksize * data->blocks, GEN_BB_WRITE); } else { ret = bounce_buffer_start(&bbstate, - (void*)data->src, + (void *)data->src, data->blocksize * data->blocks, GEN_BB_READ); } @@ -316,9 +418,9 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (cmd->resp_type & MMC_RSP_CRC) flags |= DWMCI_CMD_CHECK_CRC; - flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); + flags |= cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG; - debug("Sending CMD%d\n",cmd->cmdidx); + debug("Sending CMD%d\n", cmd->cmdidx); dwmci_writel(host, DWMCI_CMD, flags); @@ -332,7 +434,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } if (i == retry) { - debug("%s: Timeout.\n", __func__); + debug("%s: Timeout\n", __func__); return -ETIMEDOUT; } @@ -345,14 +447,14 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, * below shall be debug(). eMMC cards also do not favor * CMD8, please keep that in mind. */ - debug("%s: Response Timeout.\n", __func__); + debug("%s: Response Timeout\n", __func__); return -ETIMEDOUT; } else if (mask & DWMCI_INTMSK_RE) { - debug("%s: Response Error.\n", __func__); + debug("%s: Response Error\n", __func__); return -EIO; } else if ((cmd->resp_type & MMC_RSP_CRC) && (mask & DWMCI_INTMSK_RCRC)) { - debug("%s: Response CRC Error.\n", __func__); + debug("%s: Response CRC Error\n", __func__); return -EIO; } @@ -369,26 +471,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) { ret = dwmci_data_transfer(host, data); - - /* only dma mode need it */ - if (!host->fifo_mode) { - if (data->flags == MMC_DATA_READ) - mask = DWMCI_IDINTEN_RI; - else - mask = DWMCI_IDINTEN_TI; - ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS, - mask, true, 1000, false); - if (ret) - debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n", - __func__, mask); - /* clear interrupts */ - dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK); - - ctrl = dwmci_readl(host, DWMCI_CTRL); - ctrl &= ~(DWMCI_DMA_EN); - dwmci_writel(host, DWMCI_CTRL, ctrl); - bounce_buffer_stop(&bbstate); - } + if (!host->fifo_mode) + ret = dwmci_dma_transfer(host, data->flags, &bbstate); } udelay(100); @@ -396,40 +480,39 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, return ret; } -static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) +#ifdef CONFIG_DM_MMC +static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) { - u32 div, status; - int timeout = 10000; - unsigned long sclk; + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else +static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ +#endif + struct dwmci_host *host = mmc->priv; + const size_t buf_size = data ? DIV_ROUND_UP(data->blocks, 8) : 0; - if ((freq == host->clock) || (freq == 0)) - return 0; - /* - * If host->get_mmc_clk isn't defined, - * then assume that host->bus_hz is source clock value. - * host->bus_hz should be set by user. - */ - if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host, freq); - else if (host->bus_hz) - sclk = host->bus_hz; - else { - debug("%s: Didn't get source clock value.\n", __func__); - return -EINVAL; + if (host->dma_64bit_address) { + ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac64, idmac, buf_size); + return dwmci_send_cmd_common(host, cmd, data, idmac); + } else { + ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac32, idmac, buf_size); + return dwmci_send_cmd_common(host, cmd, data, idmac); } +} - if (sclk == freq) - div = 0; /* bypass mode */ - else - div = DIV_ROUND_UP(sclk, 2 * freq); - - dwmci_writel(host, DWMCI_CLKENA, 0); - dwmci_writel(host, DWMCI_CLKSRC, 0); +static int dwmci_control_clken(struct dwmci_host *host, bool on) +{ + const u32 val = on ? DWMCI_CLKEN_ENABLE | DWMCI_CLKEN_LOW_PWR : 0; + const u32 cmd_only_clk = DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK; + int timeout = 10000; + u32 status; - dwmci_writel(host, DWMCI_CLKDIV, div); - dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | - DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); + dwmci_writel(host, DWMCI_CLKENA, val); + /* Inform CIU */ + dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_START | cmd_only_clk); do { status = dwmci_readl(host, DWMCI_CMD); if (timeout-- < 0) { @@ -438,20 +521,62 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) } } while (status & DWMCI_CMD_START); - dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | - DWMCI_CLKEN_LOW_PWR); + return 0; +} - dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | - DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); +/* + * Update the clock divider. + * + * To prevent a clock glitch keep the clock stopped during the update of + * clock divider and clock source. + */ +static int dwmci_update_div(struct dwmci_host *host, u32 div) +{ + int ret; - timeout = 10000; - do { - status = dwmci_readl(host, DWMCI_CMD); - if (timeout-- < 0) { - debug("%s: Timeout!\n", __func__); - return -ETIMEDOUT; - } - } while (status & DWMCI_CMD_START); + /* Disable clock */ + ret = dwmci_control_clken(host, false); + if (ret) + return ret; + + /* Set clock to desired speed */ + dwmci_writel(host, DWMCI_CLKDIV, div); + dwmci_writel(host, DWMCI_CLKSRC, 0); + + /* Enable clock */ + return dwmci_control_clken(host, true); +} + +static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) +{ + u32 div; + unsigned long sclk; + int ret; + + if (freq == host->clock || freq == 0) + return 0; + + /* + * If host->get_mmc_clk isn't defined, then assume that host->bus_hz is + * source clock value. host->bus_hz should be set by user. + */ + if (host->get_mmc_clk) { + sclk = host->get_mmc_clk(host, freq); + } else if (host->bus_hz) { + sclk = host->bus_hz; + } else { + debug("%s: Didn't get source clock value\n", __func__); + return -EINVAL; + } + + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); + + ret = dwmci_update_div(host, div); + if (ret) + return ret; host->clock = freq; @@ -469,7 +594,7 @@ static int dwmci_set_ios(struct mmc *mmc) struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 ctype, regs; - debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); + debug("Bus width = %d, clock: %d\n", mmc->bus_width, mmc->clock); dwmci_setup_bus(host, mmc->clock); switch (mmc->bus_width) { @@ -524,6 +649,48 @@ static int dwmci_set_ios(struct mmc *mmc) return 0; } +static void dwmci_init_fifo(struct dwmci_host *host) +{ + u32 fifo_thr, fifoth_val; + + if (!host->fifo_depth) { + u32 fifo_size; + + /* + * Automatically detect FIFO depth from FIFOTH register. + * Power-on value of RX_WMark is FIFO_DEPTH-1. + */ + fifo_size = dwmci_readl(host, DWMCI_FIFOTH); + fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; + host->fifo_depth = fifo_size; + } + + fifo_thr = host->fifo_depth / 2; + fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_thr - 1) | TX_WMARK(fifo_thr); + dwmci_writel(host, DWMCI_FIFOTH, fifoth_val); +} + +static void dwmci_init_dma(struct dwmci_host *host) +{ + int addr_config; + + if (host->fifo_mode) + return; + + addr_config = (dwmci_readl(host, DWMCI_HCON) >> 27) & 0x1; + if (addr_config == 1) { + host->dma_64bit_address = true; + host->regs = &dwmci_idmac_regs64; + debug("%s: IDMAC supports 64-bit address mode\n", __func__); + } else { + host->dma_64bit_address = false; + host->regs = &dwmci_idmac_regs32; + debug("%s: IDMAC supports 32-bit address mode\n", __func__); + } + + dwmci_writel(host, host->regs->idinten, DWMCI_IDINTEN_MASK); +} + static int dwmci_init(struct mmc *mmc) { struct dwmci_host *host = mmc->priv; @@ -541,30 +708,18 @@ static int dwmci_init(struct mmc *mmc) /* Enumerate at 400KHz */ dwmci_setup_bus(host, mmc->cfg->f_min); - dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); + dwmci_writel(host, DWMCI_RINTSTS, 0xffffffff); dwmci_writel(host, DWMCI_INTMASK, 0); - dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); + dwmci_writel(host, DWMCI_TMOUT, 0xffffffff); - dwmci_writel(host, DWMCI_IDINTEN, 0); dwmci_writel(host, DWMCI_BMOD, 1); - - if (!host->fifoth_val) { - uint32_t fifo_size; - - fifo_size = dwmci_readl(host, DWMCI_FIFOTH); - fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; - host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | - TX_WMARK(fifo_size / 2); - } - dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); + dwmci_init_fifo(host); + dwmci_init_dma(host); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); - if (!host->fifo_mode) - dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK); - return 0; } @@ -590,7 +745,7 @@ static const struct mmc_ops dwmci_ops = { #endif void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, - u32 max_clk, u32 min_clk) + u32 max_clk, u32 min_clk) { cfg->name = host->name; #ifndef CONFIG_DM_MMC @@ -626,7 +781,7 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); host->mmc = mmc_create(&host->cfg, host); - if (host->mmc == NULL) + if (!host->mmc) return -1; return 0; diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index a51f762988d..c8bf89d6d35 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -4,10 +4,9 @@ * Jaehoon Chung <jh80.chung@samsung.com> */ +#include <clk.h> #include <dwmmc.h> -#include <fdtdec.h> #include <asm/global_data.h> -#include <linux/libfdt.h> #include <malloc.h> #include <errno.h> #include <asm/arch/dwmmc.h> @@ -15,6 +14,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/gpio.h> +#include <linux/err.h> #include <linux/printk.h> #define DWMMC_MAX_CH_NUM 4 @@ -23,6 +23,11 @@ #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 +#define EXYNOS4412_FIXED_CIU_CLK_DIV 4 + +/* Quirks */ +#define DWMCI_QUIRK_DISABLE_SMU BIT(0) + #ifdef CONFIG_DM_MMC #include <dm.h> DECLARE_GLOBAL_DATA_PTR; @@ -33,35 +38,117 @@ struct exynos_mmc_plat { }; #endif -/* Exynos implmentation specific drver private data */ +/* Chip specific data */ +struct exynos_dwmmc_variant { + u32 clksel; /* CLKSEL register offset */ + u8 div; /* (optional) fixed clock divider value: 0..7 */ + u32 quirks; /* quirk flags - see DWMCI_QUIRK_... */ +}; + +/* Exynos implementation specific driver private data */ struct dwmci_exynos_priv_data { #ifdef CONFIG_DM_MMC struct dwmci_host host; #endif + struct clk clk; u32 sdr_timing; + u32 ddr_timing; + const struct exynos_dwmmc_variant *chip; }; -/* - * Function used as callback function to initialise the - * CLKSEL register for every mmc channel. - */ -static int exynos_dwmci_clksel(struct dwmci_host *host) +static struct dwmci_exynos_priv_data *exynos_dwmmc_get_priv( + struct dwmci_host *host) { #ifdef CONFIG_DM_MMC - struct dwmci_exynos_priv_data *priv = - container_of(host, struct dwmci_exynos_priv_data, host); + return container_of(host, struct dwmci_exynos_priv_data, host); #else - struct dwmci_exynos_priv_data *priv = host->priv; + return host->priv; #endif - dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); +} + +/** + * exynos_dwmmc_get_sclk - Get source clock (SDCLKIN) rate + * @host: MMC controller object + * @rate: Will contain clock rate, Hz + * + * Return: 0 on success or negative value on error + */ +static int exynos_dwmmc_get_sclk(struct dwmci_host *host, unsigned long *rate) +{ +#ifdef CONFIG_CPU_V7A + *rate = get_mmc_clk(host->dev_index); +#else + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + + *rate = clk_get_rate(&priv->clk); +#endif + + if (IS_ERR_VALUE(*rate)) + return *rate; return 0; } -unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) +/** + * exynos_dwmmc_set_sclk - Set source clock (SDCLKIN) rate + * @host: MMC controller object + * @rate: Desired clock rate, Hz + * + * Return: 0 on success or negative value on error + */ +static int exynos_dwmmc_set_sclk(struct dwmci_host *host, unsigned long rate) { + int err; + +#ifdef CONFIG_CPU_V7A unsigned long sclk; - int8_t clk_div; + unsigned int div; + + err = exynos_dwmmc_get_sclk(host, &sclk); + if (err) + return err; + + div = DIV_ROUND_UP(sclk, rate); + set_mmc_clk(host->dev_index, div); +#else + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + + err = clk_set_rate(&priv->clk, rate); + if (err < 0) + return err; +#endif + + return 0; +} + +/* Configure CLKSEL register with chosen timing values */ +static int exynos_dwmci_clksel(struct dwmci_host *host) +{ + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + u32 timing; + + if (host->mmc->selected_mode == MMC_DDR_52) + timing = priv->ddr_timing; + else + timing = priv->sdr_timing; + + dwmci_writel(host, priv->chip->clksel, timing); + + return 0; +} + +/** + * exynos_dwmmc_get_ciu_div - Get internal clock divider value + * @host: MMC controller object + * + * Returns: Divider value, in range of 1..8 + */ +static u8 exynos_dwmmc_get_ciu_div(struct dwmci_host *host) +{ + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); + + if (priv->chip->div) + return priv->chip->div + 1; /* * Since SDCLKIN is divided inside controller by the DIVRATIO @@ -69,22 +156,42 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) * clock value to calculate the CLKDIV value. * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) */ - clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) - & DWMCI_DIVRATIO_MASK) + 1; - sclk = get_mmc_clk(host->dev_index); + return ((dwmci_readl(host, priv->chip->clksel) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; +} - /* - * Assume to know divider value. - * When clock unit is broken, need to set "host->div" - */ - return sclk / clk_div / (host->div + 1); +static unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq) +{ + unsigned long sclk; + u8 clk_div; + int err; + + /* Should be double rate for DDR mode */ + if (host->mmc->selected_mode == MMC_DDR_52 && host->mmc->bus_width == 8) + freq *= 2; + + clk_div = exynos_dwmmc_get_ciu_div(host); + err = exynos_dwmmc_set_sclk(host, freq * clk_div); + if (err) { + printf("DWMMC%d: failed to set clock rate (%d); " + "continue anyway\n", host->dev_index, err); + } + + err = exynos_dwmmc_get_sclk(host, &sclk); + if (err) { + printf("DWMMC%d: failed to get clock rate (%d)\n", + host->dev_index, err); + return 0; + } + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) { - struct dwmci_exynos_priv_data *priv = host->priv; + struct dwmci_exynos_priv_data *priv = exynos_dwmmc_get_priv(host); - if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { + if (priv->chip->quirks & DWMCI_QUIRK_DISABLE_SMU) { dwmci_writel(host, EMMCP_MPSBEGIN0, 0); dwmci_writel(host, EMMCP_SEND0, 0); dwmci_writel(host, EMMCP_CTRL0, @@ -94,73 +201,27 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); } - /* Set to timing value at initial time */ if (priv->sdr_timing) exynos_dwmci_clksel(host); } -static int exynos_dwmci_core_init(struct dwmci_host *host) -{ - unsigned int div; - unsigned long freq, sclk; - - if (host->bus_hz) - freq = host->bus_hz; - else - freq = DWMMC_MAX_FREQ; - - /* request mmc clock vlaue of 52MHz. */ - sclk = get_mmc_clk(host->dev_index); - div = DIV_ROUND_UP(sclk, freq); - /* set the clock divisor for mmc */ - set_mmc_clk(host->dev_index, div); - - host->name = "EXYNOS DWMMC"; -#ifdef CONFIG_EXYNOS5420 - host->quirks = DWMCI_QUIRK_DISABLE_SMU; -#endif - host->board_init = exynos_dwmci_board_init; - - host->caps = MMC_MODE_DDR_52MHz; - host->clksel = exynos_dwmci_clksel; - host->get_mmc_clk = exynos_dwmci_get_clk; - -#ifndef CONFIG_DM_MMC - /* Add the mmc channel to be registered with mmc core */ - if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { - printf("DWMMC%d registration failed\n", host->dev_index); - return -1; - } -#endif - - return 0; -} - -static int do_dwmci_init(struct dwmci_host *host) +#ifdef CONFIG_DM_MMC +static int exynos_dwmmc_of_to_plat(struct udevice *dev) { - int flag, err; - - flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; - err = exynos_pinmux_config(host->dev_id, flag); - if (err) { - printf("DWMMC%d not configure\n", host->dev_index); - return err; - } + struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + u32 div, timing[2]; + int err; - return exynos_dwmci_core_init(host); -} + priv->chip = (struct exynos_dwmmc_variant *)dev_get_driver_data(dev); -static int exynos_dwmci_get_config(const void *blob, int node, - struct dwmci_host *host, - struct dwmci_exynos_priv_data *priv) -{ - int err = 0; - u32 base, timing[3]; +#ifdef CONFIG_CPU_V7A + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); - /* Extract device id for each mmc channel */ + /* Obtain device ID for current MMC channel */ host->dev_id = pinmux_decode_periph_id(blob, node); - - host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id); + host->dev_index = dev_read_u32_default(dev, "index", host->dev_id); if (host->dev_index == host->dev_id) host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; @@ -168,31 +229,34 @@ static int exynos_dwmci_get_config(const void *blob, int node, printf("DWMMC%d: Can't get the dev index\n", host->dev_index); return -EINVAL; } +#else + if (dev_read_bool(dev, "non-removable")) + host->dev_index = 0; /* eMMC */ + else + host->dev_index = 2; /* SD card */ +#endif - /* Get the bus width from the device node (Default is 4bit buswidth) */ - host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); - - /* Set the base address from the device node */ - base = fdtdec_get_addr(blob, node, "reg"); - if (!base) { + host->ioaddr = dev_read_addr_ptr(dev); + if (!host->ioaddr) { printf("DWMMC%d: Can't get base address\n", host->dev_index); return -EINVAL; } - host->ioaddr = (void *)base; - /* Extract the timing info from the node */ - err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3); + if (priv->chip->div) + div = priv->chip->div; + else + div = dev_read_u32_default(dev, "samsung,dw-mshc-ciu-div", 0); + + err = dev_read_u32_array(dev, "samsung,dw-mshc-sdr-timing", timing, 2); if (err) { - printf("DWMMC%d: Can't get sdr-timings for devider\n", - host->dev_index); + printf("DWMMC%d: Can't get sdr-timings\n", host->dev_index); return -EINVAL; } + priv->sdr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(div); - priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | - DWMCI_SET_DRV_CLK(timing[1]) | - DWMCI_SET_DIV_RATIO(timing[2])); - - /* sdr_timing didn't assigned anything, use the default value */ + /* sdr_timing wasn't set, use the default value */ if (!priv->sdr_timing) { if (host->dev_index == 0) priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; @@ -200,35 +264,82 @@ static int exynos_dwmci_get_config(const void *blob, int node, priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; } - host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); - host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); - host->div = fdtdec_get_int(blob, node, "div", 0); + err = dev_read_u32_array(dev, "samsung,dw-mshc-ddr-timing", timing, 2); + if (err) { + debug("DWMMC%d: Can't get ddr-timings, using sdr-timings\n", + host->dev_index); + priv->ddr_timing = priv->sdr_timing; + } else { + priv->ddr_timing = DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(div); + } + + host->buswidth = dev_read_u32_default(dev, "bus-width", 4); + host->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); + host->bus_hz = dev_read_u32_default(dev, "clock-frequency", 0); return 0; } -#ifdef CONFIG_DM_MMC static int exynos_dwmmc_probe(struct udevice *dev) { struct exynos_mmc_plat *plat = dev_get_plat(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + unsigned long freq; int err; - err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host, - priv); +#ifndef CONFIG_CPU_V7A + err = clk_get_by_index(dev, 1, &priv->clk); /* ciu */ if (err) return err; - err = do_dwmci_init(host); - if (err) +#endif + +#ifdef CONFIG_CPU_V7A + int flag; + + flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; + err = exynos_pinmux_config(host->dev_id, flag); + if (err) { + printf("DWMMC%d not configure\n", host->dev_index); return err; + } +#endif + + if (host->bus_hz) + freq = host->bus_hz; + else + freq = DWMMC_MAX_FREQ; + err = exynos_dwmmc_set_sclk(host, freq); + if (err) { + printf("DWMMC%d: failed to set clock rate on probe (%d); " + "continue anyway\n", host->dev_index, err); + } + + host->name = dev->name; + host->board_init = exynos_dwmci_board_init; + host->caps = MMC_MODE_DDR_52MHz; + host->clksel = exynos_dwmci_clksel; + host->get_mmc_clk = exynos_dwmci_get_clk; + +#ifdef CONFIG_BLK dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); host->mmc = &plat->mmc; +#else + err = add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); + if (err) { + printf("DWMMC%d registration failed\n", host->dev_index); + return err; + } +#endif + host->mmc->priv = &priv->host; - host->priv = dev; upriv->mmc = host->mmc; + host->mmc->dev = dev; + host->priv = dev; return dwmci_probe(dev); } @@ -240,9 +351,34 @@ static int exynos_dwmmc_bind(struct udevice *dev) return dwmci_bind(dev, &plat->mmc, &plat->cfg); } +static const struct exynos_dwmmc_variant exynos4_drv_data = { + .clksel = DWMCI_CLKSEL, + .div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1, +}; + +static const struct exynos_dwmmc_variant exynos5_drv_data = { + .clksel = DWMCI_CLKSEL, +#ifdef CONFIG_EXYNOS5420 + .quirks = DWMCI_QUIRK_DISABLE_SMU, +#endif +}; + +static const struct exynos_dwmmc_variant exynos7_smu_drv_data = { + .clksel = DWMCI_CLKSEL64, + .quirks = DWMCI_QUIRK_DISABLE_SMU, +}; + static const struct udevice_id exynos_dwmmc_ids[] = { - { .compatible = "samsung,exynos4412-dw-mshc" }, - { .compatible = "samsung,exynos-dwmmc" }, + { + .compatible = "samsung,exynos4412-dw-mshc", + .data = (ulong)&exynos4_drv_data, + }, { + .compatible = "samsung,exynos-dwmmc", + .data = (ulong)&exynos5_drv_data, + }, { + .compatible = "samsung,exynos7-dw-mshc-smu", + .data = (ulong)&exynos7_smu_drv_data, + }, { } }; @@ -250,9 +386,10 @@ U_BOOT_DRIVER(exynos_dwmmc_drv) = { .name = "exynos_dwmmc", .id = UCLASS_MMC, .of_match = exynos_dwmmc_ids, + .of_to_plat = exynos_dwmmc_of_to_plat, .bind = exynos_dwmmc_bind, - .ops = &dm_dwmci_ops, .probe = exynos_dwmmc_probe, + .ops = &dm_dwmci_ops, .priv_auto = sizeof(struct dwmci_exynos_priv_data), .plat_auto = sizeof(struct exynos_mmc_plat), }; diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h index 782d92be2f5..36187cfa04f 100644 --- a/drivers/mmc/ftsdc010_mci.h +++ b/drivers/mmc/ftsdc010_mci.h @@ -28,7 +28,6 @@ struct ftsdc010_chip { int dev_index; int dev_id; int buswidth; - u32 fifoth_val; struct mmc *mmc; void *priv; bool fifo_mode; diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index c68a9157bfc..0302f5c296b 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -36,7 +36,7 @@ struct hi6220_dwmmc_priv_data { struct hisi_mmc_data { unsigned int clock; bool use_fifo; - u32 fifoth_val; + u32 fifo_depth; }; static int hi6220_dwmmc_of_to_plat(struct udevice *dev) @@ -125,7 +125,7 @@ static int hi6220_dwmmc_probe(struct udevice *dev) host->mmc = &plat->mmc; host->fifo_mode = mmc_data->use_fifo; - host->fifoth_val = mmc_data->fifoth_val; + host->fifo_depth = mmc_data->fifo_depth; host->mmc->priv = &priv->host; upriv->mmc = host->mmc; host->mmc->dev = dev; @@ -158,8 +158,7 @@ static const struct hisi_mmc_data hi6220_mmc_data = { static const struct hisi_mmc_data hi3798mv2x_mmc_data = { .clock = 50000000, .use_fifo = false, - // FIFO depth is 256 - .fifoth_val = MSIZE(4) | RX_WMARK(0x7f) | TX_WMARK(0x80), + .fifo_depth = 256, }; static const struct udevice_id hi6220_dwmmc_ids[] = { diff --git a/drivers/mmc/nexell_dw_mmc.c b/drivers/mmc/nexell_dw_mmc.c index 2e1ce54c7d5..80df617e07e 100644 --- a/drivers/mmc/nexell_dw_mmc.c +++ b/drivers/mmc/nexell_dw_mmc.c @@ -186,10 +186,7 @@ static int nexell_dwmmc_probe(struct udevice *dev) struct dwmci_host *host = &priv->host; struct udevice *pwr_dev __maybe_unused; - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(priv->fifo_size / 2 - 1) | - TX_WMARK(priv->fifo_size / 2); - + host->fifo_depth = priv->fifo_size; host->fifo_mode = priv->fifo_mode; dwmci_setup_cfg(&plat->cfg, host, priv->max_freq, priv->min_freq); diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index 549fb80f198..fb77b049834 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -138,10 +138,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) if (ret < 0) return ret; #endif - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(priv->fifo_depth / 2 - 1) | - TX_WMARK(priv->fifo_depth / 2); - + host->fifo_depth = priv->fifo_depth; host->fifo_mode = priv->fifo_mode; #if CONFIG_IS_ENABLED(MMC_PWRSEQ) diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 80dbb38c9b3..278019f02ab 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -166,7 +166,7 @@ static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host) host->index = dev_id - PERIPH_ID_SDMMC0; /* Get bus width */ - bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + bus_width = fdtdec_get_int(blob, node, "bus-width", 0); if (bus_width <= 0) { debug("MMC: Can't get bus-width\n"); return -EINVAL; diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 9bdbe5070b1..f30331e51f7 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -81,7 +81,7 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) host->ioaddr = dev_read_addr_ptr(dev); /* - * If fifo-depth is unset don't set fifoth_val - we will try to + * If fifo-depth is unset don't set fifo_depth - we will try to * auto detect it. */ ret = dev_read_u32(dev, "fifo-depth", &fifo_depth); @@ -89,9 +89,7 @@ static int snps_dwmmc_of_to_plat(struct udevice *dev) if (fifo_depth < FIFO_MIN || fifo_depth > FIFO_MAX) return -EINVAL; - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(fifo_depth / 2 - 1) | - TX_WMARK(fifo_depth / 2); + host->fifo_depth = fifo_depth; } host->buswidth = dev_read_u32_default(dev, "bus-width", 4); diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index f738019b835..3147d3019c0 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -134,8 +134,8 @@ static int socfpga_dwmmc_of_to_plat(struct udevice *dev) * We only have one dwmmc block on gen5 SoCFPGA. */ host->dev_index = 0; - host->fifoth_val = MSIZE(0x2) | - RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); + + host->fifo_depth = fifo_depth; priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "drvsel", 3); priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), diff --git a/include/dwmmc.h b/include/dwmmc.h index 136a95b8cdb..6edb9e1a59c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -15,170 +15,205 @@ #define DWMCI_CTRL 0x000 #define DWMCI_PWREN 0x004 #define DWMCI_CLKDIV 0x008 -#define DWMCI_CLKSRC 0x00C +#define DWMCI_CLKSRC 0x00c #define DWMCI_CLKENA 0x010 #define DWMCI_TMOUT 0x014 #define DWMCI_CTYPE 0x018 -#define DWMCI_BLKSIZ 0x01C +#define DWMCI_BLKSIZ 0x01c #define DWMCI_BYTCNT 0x020 #define DWMCI_INTMASK 0x024 #define DWMCI_CMDARG 0x028 -#define DWMCI_CMD 0x02C +#define DWMCI_CMD 0x02c #define DWMCI_RESP0 0x030 #define DWMCI_RESP1 0x034 #define DWMCI_RESP2 0x038 -#define DWMCI_RESP3 0x03C +#define DWMCI_RESP3 0x03c #define DWMCI_MINTSTS 0x040 #define DWMCI_RINTSTS 0x044 #define DWMCI_STATUS 0x048 -#define DWMCI_FIFOTH 0x04C +#define DWMCI_FIFOTH 0x04c #define DWMCI_CDETECT 0x050 #define DWMCI_WRTPRT 0x054 #define DWMCI_GPIO 0x058 -#define DWMCI_TCMCNT 0x05C +#define DWMCI_TCMCNT 0x05c #define DWMCI_TBBCNT 0x060 #define DWMCI_DEBNCE 0x064 #define DWMCI_USRID 0x068 -#define DWMCI_VERID 0x06C +#define DWMCI_VERID 0x06c #define DWMCI_HCON 0x070 #define DWMCI_UHS_REG 0x074 #define DWMCI_BMOD 0x080 #define DWMCI_PLDMND 0x084 +#define DWMCI_DATA 0x200 +/* Registers to support IDMAC 32-bit address mode */ #define DWMCI_DBADDR 0x088 -#define DWMCI_IDSTS 0x08C +#define DWMCI_IDSTS 0x08c #define DWMCI_IDINTEN 0x090 #define DWMCI_DSCADDR 0x094 #define DWMCI_BUFADDR 0x098 -#define DWMCI_DATA 0x200 +/* Registers to support IDMAC 64-bit address mode */ +#define DWMCI_DBADDRL 0x088 +#define DWMCI_DBADDRU 0x08c +#define DWMCI_IDSTS64 0x090 +#define DWMCI_IDINTEN64 0x094 +#define DWMCI_DSCADDRL 0x098 +#define DWMCI_DSCADDRU 0x09c +#define DWMCI_BUFADDRL 0x0a0 +#define DWMCI_BUFADDRU 0x0a4 /* Interrupt Mask register */ #define DWMCI_INTMSK_ALL 0xffffffff -#define DWMCI_INTMSK_RE (1 << 1) -#define DWMCI_INTMSK_CDONE (1 << 2) -#define DWMCI_INTMSK_DTO (1 << 3) -#define DWMCI_INTMSK_TXDR (1 << 4) -#define DWMCI_INTMSK_RXDR (1 << 5) -#define DWMCI_INTMSK_RCRC (1 << 6) -#define DWMCI_INTMSK_DCRC (1 << 7) -#define DWMCI_INTMSK_RTO (1 << 8) -#define DWMCI_INTMSK_DRTO (1 << 9) -#define DWMCI_INTMSK_HTO (1 << 10) -#define DWMCI_INTMSK_FRUN (1 << 11) -#define DWMCI_INTMSK_HLE (1 << 12) -#define DWMCI_INTMSK_SBE (1 << 13) -#define DWMCI_INTMSK_ACD (1 << 14) -#define DWMCI_INTMSK_EBE (1 << 15) - -/* Raw interrupt Regsiter */ -#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\ - DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) -#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) +#define DWMCI_INTMSK_RE BIT(1) +#define DWMCI_INTMSK_CDONE BIT(2) +#define DWMCI_INTMSK_DTO BIT(3) +#define DWMCI_INTMSK_TXDR BIT(4) +#define DWMCI_INTMSK_RXDR BIT(5) +#define DWMCI_INTMSK_RCRC BIT(6) +#define DWMCI_INTMSK_DCRC BIT(7) +#define DWMCI_INTMSK_RTO BIT(8) +#define DWMCI_INTMSK_DRTO BIT(9) +#define DWMCI_INTMSK_HTO BIT(10) +#define DWMCI_INTMSK_FRUN BIT(11) +#define DWMCI_INTMSK_HLE BIT(12) +#define DWMCI_INTMSK_SBE BIT(13) +#define DWMCI_INTMSK_ACD BIT(14) +#define DWMCI_INTMSK_EBE BIT(15) + +/* Raw interrupt register */ +#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | \ + DWMCI_INTMSK_HLE | DWMCI_INTMSK_FRUN | \ + DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC) +#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO) + /* CTRL register */ -#define DWMCI_CTRL_RESET (1 << 0) -#define DWMCI_CTRL_FIFO_RESET (1 << 1) -#define DWMCI_CTRL_DMA_RESET (1 << 2) -#define DWMCI_DMA_EN (1 << 5) -#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10) -#define DWMCI_IDMAC_EN (1 << 25) +#define DWMCI_CTRL_RESET BIT(0) +#define DWMCI_CTRL_FIFO_RESET BIT(1) +#define DWMCI_CTRL_DMA_RESET BIT(2) +#define DWMCI_DMA_EN BIT(5) +#define DWMCI_CTRL_SEND_AS_CCSD BIT(10) +#define DWMCI_IDMAC_EN BIT(25) #define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\ DWMCI_CTRL_DMA_RESET) /* CMD register */ -#define DWMCI_CMD_RESP_EXP (1 << 6) -#define DWMCI_CMD_RESP_LENGTH (1 << 7) -#define DWMCI_CMD_CHECK_CRC (1 << 8) -#define DWMCI_CMD_DATA_EXP (1 << 9) -#define DWMCI_CMD_RW (1 << 10) -#define DWMCI_CMD_SEND_STOP (1 << 12) -#define DWMCI_CMD_ABORT_STOP (1 << 14) -#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13) -#define DWMCI_CMD_UPD_CLK (1 << 21) -#define DWMCI_CMD_USE_HOLD_REG (1 << 29) -#define DWMCI_CMD_START (1 << 31) +#define DWMCI_CMD_RESP_EXP BIT(6) +#define DWMCI_CMD_RESP_LENGTH BIT(7) +#define DWMCI_CMD_CHECK_CRC BIT(8) +#define DWMCI_CMD_DATA_EXP BIT(9) +#define DWMCI_CMD_RW BIT(10) +#define DWMCI_CMD_SEND_STOP BIT(12) +#define DWMCI_CMD_ABORT_STOP BIT(14) +#define DWMCI_CMD_PRV_DAT_WAIT BIT(13) +#define DWMCI_CMD_UPD_CLK BIT(21) +#define DWMCI_CMD_USE_HOLD_REG BIT(29) +#define DWMCI_CMD_START BIT(31) /* CLKENA register */ -#define DWMCI_CLKEN_ENABLE (1 << 0) -#define DWMCI_CLKEN_LOW_PWR (1 << 16) +#define DWMCI_CLKEN_ENABLE BIT(0) +#define DWMCI_CLKEN_LOW_PWR BIT(16) -/* Card-type registe */ +/* Card type register */ #define DWMCI_CTYPE_1BIT 0 -#define DWMCI_CTYPE_4BIT (1 << 0) -#define DWMCI_CTYPE_8BIT (1 << 16) +#define DWMCI_CTYPE_4BIT BIT(0) +#define DWMCI_CTYPE_8BIT BIT(16) -/* Status Register */ -#define DWMCI_FIFO_EMPTY (1 << 2) -#define DWMCI_FIFO_FULL (1 << 3) -#define DWMCI_BUSY (1 << 9) +/* Status register */ +#define DWMCI_FIFO_EMPTY BIT(2) +#define DWMCI_FIFO_FULL BIT(3) +#define DWMCI_BUSY BIT(9) #define DWMCI_FIFO_MASK 0x1fff #define DWMCI_FIFO_SHIFT 17 -/* FIFOTH Register */ +/* FIFOTH register */ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) #define RX_WMARK_SHIFT 16 #define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) -#define DWMCI_IDMAC_OWN (1 << 31) -#define DWMCI_IDMAC_CH (1 << 4) -#define DWMCI_IDMAC_FS (1 << 3) -#define DWMCI_IDMAC_LD (1 << 2) +#define DWMCI_IDMAC_OWN BIT(31) +#define DWMCI_IDMAC_CH BIT(4) +#define DWMCI_IDMAC_FS BIT(3) +#define DWMCI_IDMAC_LD BIT(2) -/* Bus Mode Register */ -#define DWMCI_BMOD_IDMAC_RESET (1 << 0) -#define DWMCI_BMOD_IDMAC_FB (1 << 1) -#define DWMCI_BMOD_IDMAC_EN (1 << 7) +/* Bus Mode register */ +#define DWMCI_BMOD_IDMAC_RESET BIT(0) +#define DWMCI_BMOD_IDMAC_FB BIT(1) +#define DWMCI_BMOD_IDMAC_EN BIT(7) /* UHS register */ -#define DWMCI_DDR_MODE (1 << 16) +#define DWMCI_DDR_MODE BIT(16) /* Internal IDMAC interrupt defines */ -#define DWMCI_IDINTEN_RI BIT(1) -#define DWMCI_IDINTEN_TI BIT(0) - -#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \ - DWMCI_IDINTEN_RI) +#define DWMCI_IDINTEN_RI BIT(1) +#define DWMCI_IDINTEN_TI BIT(0) +#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | DWMCI_IDINTEN_RI) -/* quirks */ -#define DWMCI_QUIRK_DISABLE_SMU (1 << 0) +/** + * struct dwmci_idmac_regs - Offsets of IDMAC registers + * + * @dbaddrl: Descriptor base address, lower 32 bits + * @dbaddru: Descriptor base address, upper 32 bits + * @idsts: Internal DMA status + * @idinten: Internal DMA interrupt enable + * @dscaddrl: IDMAC descriptor address, lower 32 bits + * @dscaddru: IDMAC descriptor address, upper 32 bits + * @bufaddrl: Current data buffer address, lower 32 bits + * @bufaddru: Current data buffer address, upper 32 bits + */ +struct dwmci_idmac_regs { + u32 dbaddrl; + u32 dbaddru; + u32 idsts; + u32 idinten; + u32 dscaddrl; + u32 dscaddru; + u32 bufaddrl; + u32 bufaddru; +}; /** * struct dwmci_host - Information about a designware MMC host * * @name: Device name * @ioaddr: Base I/O address of controller - * @quirks: Quick flags - see DWMCI_QUIRK_... * @caps: Capabilities - see MMC_MODE_... + * @clock: Current clock frequency (after internal divider), Hz * @bus_hz: Bus speed in Hz, if @get_mmc_clk() is NULL - * @div: Arbitrary clock divider value for use by controller * @dev_index: Arbitrary device index for use by controller * @dev_id: Arbitrary device ID for use by controller * @buswidth: Bus width in bits (8 or 4) - * @fifoth_val: Value for FIFOTH register (or 0 to leave unset) + * @fifo_depth: Depth of FIFO, bytes (or 0 for automatic detection) * @mmc: Pointer to generic MMC structure for this device * @priv: Private pointer for use by controller + * @clksel: (Optional) Platform function to run when speed/width is changed + * @board_init: (Optional) Platform function to run on init + * @cfg: Internal MMC configuration, for !CONFIG_BLK cases + * @fifo_mode: Use FIFO mode (not DMA) to read and write data + * @dma_64bit_address: Whether DMA supports 64-bit address mode or not + * @regs: Registers that can vary for different DW MMC block versions */ struct dwmci_host { const char *name; void *ioaddr; - unsigned int quirks; unsigned int caps; - unsigned int version; unsigned int clock; unsigned int bus_hz; - unsigned int div; int dev_index; int dev_id; int buswidth; - u32 fifoth_val; + u32 fifo_depth; struct mmc *mmc; void *priv; int (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - /** - * Get / set a particular MMC clock frequency + * @get_mmc_clk: (Optional) Platform function to get/set a particular + * MMC clock frequency + * + * @host: DWMMC host + * @freq: Frequency the host is trying to achieve * * This is used to request the current clock frequency of the clock * that drives the DWMMC peripheral. The caller will then use this @@ -186,26 +221,18 @@ struct dwmci_host { * required MMC bus clock frequency. If you want to handle the * clock external to DWMMC, use @freq to select the frequency and * return that value too. Then DWMMC will put itself in bypass mode. - * - * @host: DWMMC host - * @freq: Frequency the host is trying to achieve */ unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq); + #ifndef CONFIG_BLK struct mmc_config cfg; #endif - /* use fifo mode to read and write data */ bool fifo_mode; + bool dma_64bit_address; + const struct dwmci_idmac_regs *regs; }; -struct dwmci_idmac { - u32 flags; - u32 cnt; - u32 addr; - u32 next_addr; -} __aligned(ARCH_DMA_MINALIGN); - static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val) { writel(val, host->ioaddr + reg); @@ -220,6 +247,7 @@ static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val) { writeb(val, host->ioaddr + reg); } + static inline u32 dwmci_readl(struct dwmci_host *host, int reg) { return readl(host->ioaddr + reg); @@ -236,8 +264,13 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) } #ifdef CONFIG_BLK + /** * dwmci_setup_cfg() - Set up the configuration for DWMMC + * @cfg: Configuration structure to fill in (generally &plat->mmc) + * @host: DWMMC host + * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000) + * @min_clk: Minimum supported clock speed in Hz (e.g. 400000) * * This is used to set up a DWMMC device when you are using CONFIG_BLK. * @@ -262,44 +295,41 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg) * struct rockchip_mmc_plat *plat = dev_get_plat(dev); * * See rockchip_dw_mmc.c for an example. - * - * @cfg: Configuration structure to fill in (generally &plat->mmc) - * @host: DWMMC host - * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) - * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) */ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, - u32 max_clk, u32 min_clk); + u32 max_clk, u32 min_clk); /** * dwmci_bind() - Set up a new MMC block device + * @dev: Device to set up + * @mmc: Pointer to mmc structure (normally &plat->mmc) + * @cfg: Empty configuration structure (generally &plat->cfg). This is + * normally all zeroes at this point. The only purpose of passing + * this in is to set mmc->cfg to it. * * This is used to set up a DWMMC block device when you are using CONFIG_BLK. * It should be called from your driver's bind() method. * * See rockchip_dw_mmc.c for an example. * - * @dev: Device to set up - * @mmc: Pointer to mmc structure (normally &plat->mmc) - * @cfg: Empty configuration structure (generally &plat->cfg). This is - * normally all zeroes at this point. The only purpose of passing - * this in is to set mmc->cfg to it. * Return: 0 if OK, -ve if the block device could not be created */ int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); #else + /** * add_dwmci() - Add a new DWMMC interface + * @host: DWMMC host structure + * @max_clk: Maximum supported clock speed in Hz (e.g. 150000000) + * @min_clk: Minimum supported clock speed in Hz (e.g. 400000) * * This is used when you are not using CONFIG_BLK. Convert your driver over! * - * @host: DWMMC host structure - * @max_clk: Maximum supported clock speed in HZ (e.g. 150000000) - * @min_clk: Minimum supported clock speed in HZ (e.g. 400000) * Return: 0 if OK, -ve on error */ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk); + #endif /* !CONFIG_BLK */ #ifdef CONFIG_DM_MMC |