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Diffstat (limited to 'arch/arm/cpu/armv7/start.S')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 698e15b8e18..af87a5432ae 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -173,6 +173,17 @@ ENDPROC(switch_to_hypervisor) * *************************************************************************/ ENTRY(cpu_init_cp15) + +#if CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) + /* + * The Arm Cortex-A7 TRM says this bit must be enabled before + * "any cache or TLB maintenance operations are performed". + */ + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register + orr r0, r0, #1 << 6 @ set SMP bit to enable coherency + mcr p15, 0, r0, c1, c0, 1 @ write auxilary control register +#endif + /* * Invalidate L1 I/D */ |