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Diffstat (limited to 'arch/arm/dts/stm32mp151.dtsi')
-rw-r--r--arch/arm/dts/stm32mp151.dtsi34
1 files changed, 19 insertions, 15 deletions
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi
index 21d11be328c..e277140d36b 100644
--- a/arch/arm/dts/stm32mp151.dtsi
+++ b/arch/arm/dts/stm32mp151.dtsi
@@ -1111,6 +1111,8 @@
adc1: adc@0 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x0>;
interrupt-parent = <&adc>;
interrupts = <0>;
@@ -1122,12 +1124,24 @@
adc2: adc@100 {
compatible = "st,stm32mp1-adc";
#io-channel-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x100>;
interrupt-parent = <&adc>;
interrupts = <1>;
dmas = <&dmamux1 10 0x400 0x01>;
dma-names = "rx";
+ nvmem-cells = <&vrefint>;
+ nvmem-cell-names = "vrefint";
status = "disabled";
+ channel@13 {
+ reg = <13>;
+ label = "vrefint";
+ };
+ channel@14 {
+ reg = <14>;
+ label = "vddcore";
+ };
};
};
@@ -1162,14 +1176,6 @@
status = "disabled";
};
- hwspinlock: hwspinlock@4c000000 {
- compatible = "st,stm32-hwspinlock";
- #hwlock-cells = <1>;
- reg = <0x4c000000 0x400>;
- clocks = <&rcc HSEM>;
- clock-names = "hwspinlock";
- };
-
ipcc: mailbox@4c001000 {
compatible = "st,stm32mp1-ipcc";
#mbox-cells = <1>;
@@ -1559,11 +1565,6 @@
clock-names = "lcd";
resets = <&rcc LTDC_R>;
status = "disabled";
-
- port {
- #address-cells = <1>;
- #size-cells = <0>;
- };
};
iwdg2: watchdog@5a002000 {
@@ -1650,9 +1651,12 @@
reg = <0x5c005000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
- part_number_otp: part_number_otp@4 {
+ part_number_otp: part-number-otp@4 {
reg = <0x4 0x1>;
};
+ vrefint: vrefin-cal@52 {
+ reg = <0x52 0x2>;
+ };
ts_cal1: calib@5c {
reg = <0x5c 0x2>;
};
@@ -1853,8 +1857,8 @@
<0x30000000 0x40000>,
<0x38000000 0x10000>;
resets = <&rcc MCU_R>;
+ reset-names = "mcu_rst";
st,syscfg-holdboot = <&rcc 0x10C 0x1>;
- st,syscfg-tz = <&rcc 0x000 0x1>;
st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;