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-rw-r--r--arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi33
-rw-r--r--arch/arm/dts/fsl-imx8qm-mek.dts1
-rw-r--r--arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi18
-rw-r--r--arch/arm/dts/fsl-imx8qxp-mek.dts1
-rw-r--r--arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi162
-rw-r--r--arch/arm/dts/imxrt1050.dtsi2
-rw-r--r--arch/arm/dts/imxrt1170-evk.dts2
7 files changed, 215 insertions, 4 deletions
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 6e5379e53c5..38925d53065 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -7,18 +7,48 @@
&{/imx8qm-pm} {
+ bootph-some-ram;
bootph-pre-ram;
};
&mu {
+ bootph-some-ram;
bootph-pre-ram;
};
&clk {
+ bootph-some-ram;
bootph-pre-ram;
};
&iomuxc {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-mek} {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+};
+
+&pinctrl_lpuart0 {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
bootph-pre-ram;
};
@@ -75,10 +105,12 @@
};
&pd_dma {
+ bootph-some-ram;
bootph-pre-ram;
};
&pd_dma_lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
@@ -131,6 +163,7 @@
};
&lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts
index 63908ba6bf1..6cf7ce3d5e0 100644
--- a/arch/arm/dts/fsl-imx8qm-mek.dts
+++ b/arch/arm/dts/fsl-imx8qm-mek.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "fsl-imx8qm.dtsi"
-#include "fsl-imx8qm-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 591eb66604b..e670214b5fc 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -6,19 +6,32 @@
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} {
-
+ bootph-some-ram;
bootph-pre-ram;
};
&mu {
+ bootph-some-ram;
bootph-pre-ram;
};
&clk {
+ bootph-some-ram;
bootph-pre-ram;
};
&iomuxc {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qxp-mek} {
+ bootph-some-ram;
+ bootph-pre-ram;
+};
+
+&pinctrl_lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
@@ -75,10 +88,12 @@
};
&pd_dma {
+ bootph-some-ram;
bootph-pre-ram;
};
&pd_dma_lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
@@ -131,6 +146,7 @@
};
&lpuart0 {
+ bootph-some-ram;
bootph-pre-ram;
};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index 6a987f0dbb3..983b918dc7d 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "fsl-imx8qxp.dtsi"
-#include "fsl-imx8qxp-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QXP MEK";
diff --git a/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi
new file mode 100644
index 00000000000..27b4b2ed84a
--- /dev/null
+++ b/arch/arm/dts/imx93-9x9-qsb-u-boot.dtsi
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx93-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ bootph-pre-ram;
+ bootph-some-ram;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&aips1 {
+ bootph-pre-ram;
+ bootph-all;
+};
+
+&aips2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&aips3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&iomuxc {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&reg_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+&pinctrl_uart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio3 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gpio4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpuart1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&lpi2c2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl_lpi2c2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&ethphy1 {
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+&s4muap {
+ bootph-pre-ram;
+ bootph-some-ram;
+ status = "okay";
+};
+
+&clk {
+ bootph-all;
+ bootph-pre-ram;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ /delete-property/ assigned-clock-parents;
+};
+
+&osc_32k {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&osc_24m {
+ bootph-all;
+ bootph-pre-ram;
+};
+
+&clk_ext1 {
+ bootph-all;
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
index 03e6a858a7b..a25eae9bd38 100644
--- a/arch/arm/dts/imxrt1050.dtsi
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -87,7 +87,7 @@
reg = <0x402c0000 0x4000>;
interrupts = <110>;
clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
- <&clks IMXRT1050_CLK_OSC>,
+ <&clks IMXRT1050_CLK_AHB_PODF>,
<&clks IMXRT1050_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
diff --git a/arch/arm/dts/imxrt1170-evk.dts b/arch/arm/dts/imxrt1170-evk.dts
index c2fd0c0392c..0d8e7016860 100644
--- a/arch/arm/dts/imxrt1170-evk.dts
+++ b/arch/arm/dts/imxrt1170-evk.dts
@@ -20,6 +20,8 @@
};
memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
device_type = "memory";
reg = <0x20240000 0xf0000 0x80000000 0x4000000>;
generated by cgit v1.2.3 (git 2.0.4) at 2025-11-05 19:51:01 +0000