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-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h1
-rw-r--r--arch/arm/include/asm/arch-imx8/imx-regs.h5
-rw-r--r--arch/arm/include/asm/arch-imx8m/clock.h1
-rw-r--r--arch/arm/include/asm/arch-imx8m/imx-regs.h24
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/cgc.h8
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/clock.h8
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/imx-regs.h1
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/pcc.h1
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/s400_api.h5
-rw-r--r--arch/arm/include/asm/arch-imx8ulp/sys_proto.h2
-rw-r--r--arch/arm/include/asm/arch-imxrt/imx-regs.h2
-rw-r--r--arch/arm/include/asm/mach-imx/sys_proto.h6
12 files changed, 54 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index fe963789710..4f63803765e 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -47,6 +47,7 @@
#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
+#define MXC_CPU_IMX8MPUL 0x189 /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index ed6e05e5569..2d64b0604b9 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
@@ -47,4 +47,7 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index c705dfdf460..e4433763bc4 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -256,6 +256,7 @@ u32 imx_get_fecclk(void);
u32 imx_get_uartclk(void);
int clock_init(void);
void init_clk_usdhc(u32 index);
+void init_nand_clk(void);
void init_uart_clk(u32 index);
void init_usb_clk(void);
void init_wdog_clk(void);
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 45d95a7c197..b2a8ad77ae1 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -58,6 +58,13 @@
#define SRC_DDRC_RCR_ADDR 0x30391000
#define SRC_DDRC2_RCR_ADDR 0x30391004
+#define APBH_DMA_ARB_BASE_ADDR 0x33000000
+#define APBH_DMA_ARB_END_ADDR 0x33007FFF
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
@@ -328,6 +335,23 @@ struct src {
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASK BIT(0)
struct wdog_regs {
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index ad3edc85adb..83a246b15a7 100644
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -146,11 +146,11 @@ struct cgc2_regs {
};
u32 cgc_clk_get_rate(enum cgc_clk clk);
-void cgc1_pll3_init(void);
-void cgc1_pll2_init(void);
+void cgc1_pll3_init(ulong freq);
+void cgc1_pll2_init(ulong freq);
void cgc1_soscdiv_init(void);
-void cgc1_init_core_clk(void);
-void cgc2_pll4_init(void);
+void cgc1_init_core_clk(ulong freq);
+void cgc2_pll4_init(bool pll4_reset);
void cgc2_ddrclk_config(u32 src, u32 div);
void cgc2_ddrclk_wait_unlock(void);
u32 cgc1_sosc_div(enum cgc_clk clk);
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index c0f32cc087f..2946cc19119 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -6,6 +6,11 @@
#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
#define _ASM_ARCH_IMX8ULP_CLOCK_H
+#include <asm/arch/pcc.h>
+#include <asm/arch/cgc.h>
+
+#define MHZ(X) ((X) * 1000000UL)
+
/* Mainly for compatible to imx common code. */
enum mxc_clock {
MXC_ARM_CLK = 0,
@@ -36,7 +41,8 @@ void init_clk_usdhc(u32 index);
void init_clk_fspi(int index);
void init_clk_ddr(void);
int set_ddr_clk(u32 phy_freq_mhz);
-void clock_init(void);
+void clock_init_early(void);
+void clock_init_late(void);
void cgc1_enet_stamp_sel(u32 clk_src);
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
void reset_lcdclk(void);
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index 91adc85525c..723bab584c3 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -14,6 +14,7 @@
#define CMC0_RBASE 0x28025000
+#define MU0_B_BASE_ADDR 0x29220000
#define CMC1_BASE_ADDR 0x29240000
#define SIM1_BASE_ADDR 0x29290000
diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h
index 46386f1aba4..d9b2d7c2998 100644
--- a/arch/arm/include/asm/arch-imx8ulp/pcc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h
@@ -52,6 +52,7 @@ enum pcc3_entry {
UPOWER_PCC3_SLOT = 40,
WDOG3_PCC3_SLOT = 42,
WDOG4_PCC3_SLOT = 43,
+ CAAM_PCC3_SLOT = 46,
XRDC_MGR_PCC3_SLOT = 47,
SEMA42_1_PCC3_SLOT = 48,
ROMCP1_PCC3_SLOT = 49,
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
index c848f0dfb8f..1856659877e 100644
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
@@ -19,8 +19,9 @@
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
#define AHAB_WRITE_FUSE_REQ_CID 0xD6
+#define AHAB_CAAM_RELEASE_CID 0xD7
-#define S400_MAX_MSG 8U
+#define S400_MAX_MSG 255U
struct imx8ulp_s400_msg {
u8 version;
@@ -37,5 +38,7 @@ int ahab_verify_image(u32 img_id, u32 *response);
int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
+int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 284ccafc988..5f030eaa0ad 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -18,4 +18,6 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
+bool m33_image_booted(void);
+int m33_image_handshake(ulong timeout_ms);
#endif
diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h
index d01e6ca2e02..ad739caae92 100644
--- a/arch/arm/include/asm/arch-imxrt/imx-regs.h
+++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h
@@ -15,8 +15,6 @@
#define GPIO4_BASE_ADDR 0x401C4000
#define GPIO5_BASE_ADDR 0x400C0000
-#define ANATOP_BASE_ADDR 0x400d8000
-
#define MXS_LCDIF_BASE 0x402b8000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 0c0c7814fb2..fdbbfb169cb 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -73,10 +73,11 @@ struct bd_info;
#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
- is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
+ is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
+#define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
@@ -159,6 +160,7 @@ enum boot_dev_type_e {
BT_DEV_TYPE_MMC = 2,
BT_DEV_TYPE_NAND = 3,
BT_DEV_TYPE_FLEXSPINOR = 4,
+ BT_DEV_TYPE_SPI_NOR = 6,
BT_DEV_TYPE_USB = 0xE,
BT_DEV_TYPE_MEM_DEV = 0xF,
@@ -228,6 +230,8 @@ int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
+void board_late_mmc_env_init(void);
+
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
unsigned long reg1, unsigned long reg2,
unsigned long reg3);
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 08:04:13 +0000