diff options
Diffstat (limited to 'arch/arm/mach-imx/imx8m/soc.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8m/soc.c | 131 |
1 files changed, 110 insertions, 21 deletions
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 7ec39b3e474..aeca82cdbf4 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -14,6 +14,7 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/syscounter.h> #include <asm/armv8/mmu.h> +#include <dm/uclass.h> #include <errno.h> #include <fdt_support.h> #include <fsl_wdog.h> @@ -21,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_IMX_HAB) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, .word = 3, @@ -55,6 +56,14 @@ void enable_tzc380(void) /* Enable TZASC and lock setting */ setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); + if (IS_ENABLED(CONFIG_IMX8MM)) + setbits_le32(&gpr->gpr[10], BIT(1)); + /* + * set Region 0 attribute to allow secure and non-secure + * read/write permission. Found some masters like usb dwc3 + * controllers can't work with secure memory. + */ + writel(0xf0000000, TZASC_BASE_ADDR + 0x108); } void set_wdog_reset(struct wdog_regs *wdog) @@ -112,16 +121,18 @@ static struct mm_region imx8m_mem_map[] = { /* DRAM1 */ .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0xC0000000UL, + .size = PHYS_SDRAM_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE +#ifdef PHYS_SDRAM_2_SIZE }, { /* DRAM2 */ .virt = 0x100000000UL, .phys = 0x100000000UL, - .size = 0x040000000UL, + .size = PHYS_SDRAM_2_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE +#endif }, { /* List terminator */ 0, @@ -130,25 +141,76 @@ static struct mm_region imx8m_mem_map[] = { struct mm_region *mem_map = imx8m_mem_map; +void enable_caches(void) +{ + /* + * If OPTEE runs, remove OPTEE memory from MMU table to + * avoid speculative prefetch. OPTEE runs at the top of + * the first memory bank + */ + if (rom_pointer[1]) + imx8m_mem_map[5].size -= rom_pointer[1]; + + icache_enable(); + dcache_enable(); +} + +static u32 get_cpu_variant_type(u32 type) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->tester4); + + if (type == MXC_CPU_IMX8MM) { + switch (value & 0x3) { + case 2: + if (value & 0x1c0000) + return MXC_CPU_IMX8MMDL; + else + return MXC_CPU_IMX8MMD; + case 3: + if (value & 0x1c0000) + return MXC_CPU_IMX8MMSL; + else + return MXC_CPU_IMX8MMS; + default: + if (value & 0x1c0000) + return MXC_CPU_IMX8MML; + break; + } + } + + return type; +} + u32 get_cpu_rev(void) { struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; u32 reg = readl(&ana_pll->digprog); u32 type = (reg >> 16) & 0xff; + u32 major_low = (reg >> 8) & 0xff; u32 rom_version; reg &= 0xff; - if (reg == CHIP_REV_1_0) { - /* - * For B0 chip, the DIGPROG is not updated, still TO1.0. - * we have to check ROM version further - */ - rom_version = readl((void __iomem *)ROM_VERSION_A0); - if (rom_version != CHIP_REV_1_0) { - rom_version = readl((void __iomem *)ROM_VERSION_B0); - if (rom_version >= CHIP_REV_2_0) - reg = CHIP_REV_2_0; + /* i.MX8MM */ + if (major_low == 0x41) { + type = get_cpu_variant_type(MXC_CPU_IMX8MM); + } else { + if (reg == CHIP_REV_1_0) { + /* + * For B0 chip, the DIGPROG is not updated, still TO1.0. + * we have to check ROM version further + */ + rom_version = readl((void __iomem *)ROM_VERSION_A0); + if (rom_version != CHIP_REV_1_0) { + rom_version = readl((void __iomem *)ROM_VERSION_B0); + if (rom_version >= CHIP_REV_2_0) + reg = CHIP_REV_2_0; + } } } @@ -167,10 +229,32 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog3->wmcr); } +int arch_cpu_init_dm(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + return ret; + } + + return 0; +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; /* + * ROM might disable clock for SCTR, + * enable the clock before timer_init. + */ + if (IS_ENABLED(CONFIG_SPL_BUILD)) + clock_enable(CCGR_SCTR, 1); + /* * Init timer at very early state, because sscg pll setting * will use it */ @@ -234,16 +318,21 @@ int ft_system_setup(void *blob, bd_t *bd) } #endif +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET) void reset_cpu(ulong addr) { - struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + struct watchdog_regs *wdog = (struct watchdog_regs *)addr; - /* Clear WDA to trigger WDOG_B immediately */ - writew((WCR_WDE | WCR_SRS), &wdog->wcr); + if (!addr) + wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - while (1) { - /* - * spin for .5 seconds before reset - */ - } + /* Clear WDA to trigger WDOG_B immediately */ + writew((WCR_WDE | WCR_SRS), &wdog->wcr); + + while (1) { + /* + * spin for .5 seconds before reset + */ + } } +#endif |