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Diffstat (limited to 'arch/arm/mach-imx/imx8ulp/cgc.c')
-rw-r--r--arch/arm/mach-imx/imx8ulp/cgc.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index fc84f3f2938..38bcbb91e6e 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -269,12 +269,23 @@ void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div)
void cgc2_ddrclk_config(u32 src, u32 div)
{
+ /* If reg lock is set, wait until unlock by HW */
+ /* This lock is triggered by div updating and ddrclk halt status change, */
+ while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
+ ;
+
writel((src << 28) | (div << 21), &cgc2_regs->ddrclk);
/* wait for DDRCLK switching done */
while (!(readl(&cgc2_regs->ddrclk) & BIT(27)))
;
}
+void cgc2_ddrclk_wait_unlock(void)
+{
+ while ((readl(&cgc2_regs->ddrclk) & BIT(31)))
+ ;
+}
+
void cgc2_lpav_init(enum cgc_clk clk)
{
u32 i, scs, reg;