diff options
Diffstat (limited to 'arch/arm/mach-imx/imx8ulp/clock.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/clock.c | 95 |
1 files changed, 77 insertions, 18 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 91580b2c29c..3e71a4f6c3b 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -101,8 +101,8 @@ void init_clk_ddr(void) writel(0xc0000000, PCC5_LPDDR4_ADDR); /* enable pll4 and ddrclk*/ - cgc2_pll4_init(); - cgc2_ddrclk_config(1, 1); + cgc2_pll4_init(true); + cgc2_ddrclk_config(4, 1); /* enable ddr pcc */ writel(0xd0000000, PCC5_LPDDR4_ADDR); @@ -153,30 +153,69 @@ int set_ddr_clk(u32 phy_freq_mhz) return 0; } -void clock_init(void) +void clock_init_early(void) { cgc1_soscdiv_init(); - cgc1_init_core_clk(); init_clk_lpuart(); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2); - pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); + /* Enable upower mu1 clk */ + pcc_clock_enable(3, UPOWER_PCC3_SLOT, true); +} - pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); +/* This will be invoked after pmic voltage setting */ +void clock_init_late(void) +{ - pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); - pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1); - pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); - pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) + cgc1_init_core_clk(MHZ(500)); + else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) + cgc1_init_core_clk(MHZ(750)); + else + cgc1_init_core_clk(MHZ(960)); - /* Enable upower mu1 clk */ - pcc_clock_enable(3, UPOWER_PCC3_SLOT, true); + /* + * Audio use this frequency in kernel dts, + * however nic use pll3 pfd0, we have to + * make the freqency same as kernel to make nic + * not being disabled + */ + cgc1_pll3_init(540672000); + + if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) { + pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2); + pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2); + pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2); + pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); + } else { + pcc_clock_enable(4, SDHC0_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2); + pcc_clock_enable(4, SDHC0_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC1_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1); + pcc_clock_enable(4, SDHC1_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false); + + pcc_clock_enable(4, SDHC2_PCC4_SLOT, false); + pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1); + pcc_clock_enable(4, SDHC2_PCC4_SLOT, true); + pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false); + } + + /* enable MU0_MUB clock before access the register of MU0_MUB */ + pcc_clock_enable(3, MU0_B_PCC3_SLOT, true); /* * Enable clock division @@ -237,6 +276,26 @@ u32 imx_get_i2cclk(u32 i2c_num) } #endif +#if IS_ENABLED(CONFIG_SYS_I2C_IMX_I3C) +int enable_i3c_clk(unsigned char enable, u32 i3c_num) +{ + if (enable) { + pcc_clock_enable(3, I3C2_PCC3_SLOT, false); + pcc_clock_sel(3, I3C2_PCC3_SLOT, SOSC_DIV2); + pcc_clock_enable(3, I3C2_PCC3_SLOT, true); + pcc_reset_peripheral(3, I3C2_PCC3_SLOT, false); + } else { + pcc_clock_enable(3, I3C2_PCC3_SLOT, false); + } + return 0; +} + +u32 imx_get_i3cclk(u32 i3c_num) +{ + return pcc_clock_get_rate(3, I3C2_PCC3_SLOT); +} +#endif + void enable_usboh3_clk(unsigned char enable) { if (enable) { |