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Diffstat (limited to 'arch/arm/mach-imx/imx9')
-rw-r--r--arch/arm/mach-imx/imx9/Kconfig17
-rw-r--r--arch/arm/mach-imx/imx9/scmi/Makefile3
-rw-r--r--arch/arm/mach-imx/imx9/scmi/clock.c29
-rw-r--r--arch/arm/mach-imx/imx9/scmi/common.h41
-rw-r--r--arch/arm/mach-imx/imx9/scmi/soc.c213
5 files changed, 280 insertions, 23 deletions
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index b6acbb20ff0..48f458fa55c 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -38,6 +38,15 @@ config IMX95
select SPL_IMX_CONTAINER_USE_TRAMPOLINE
select IMX_PQC_SUPPORT if !IMX95_A0
+config IMX94
+ bool
+ select ARMV8_SPL_EXCEPTION_VECTORS
+ select DM_MAILBOX
+ select IMX9
+ select IMX_PQC_SUPPORT
+ select SCMI_FIRMWARE
+ select SPL_IMX_CONTAINER_USE_TRAMPOLINE
+
config SYS_SOC
default "imx9"
@@ -97,6 +106,13 @@ config TARGET_IMX95_19X19_EVK
imply BOOTSTD_FULL
imply OF_UPSTREAM
+config TARGET_IMX943_EVK
+ bool "imx943_evk"
+ select IMX94
+ imply BOOTSTD_BOOTCOMMAND
+ imply BOOTSTD_FULL
+ imply OF_UPSTREAM
+
endchoice
source "board/freescale/imx91_evk/Kconfig"
@@ -105,6 +121,7 @@ source "board/freescale/imx93_frdm/Kconfig"
source "board/freescale/imx93_qsb/Kconfig"
source "board/phytec/phycore_imx93/Kconfig"
source "board/variscite/imx93_var_som/Kconfig"
+source "board/freescale/imx94_evk/Kconfig"
source "board/freescale/imx95_evk/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx9/scmi/Makefile b/arch/arm/mach-imx/imx9/scmi/Makefile
index 4534db08d28..b98744e1ecb 100644
--- a/arch/arm/mach-imx/imx9/scmi/Makefile
+++ b/arch/arm/mach-imx/imx9/scmi/Makefile
@@ -2,5 +2,8 @@
#
# Copyright 2025 NXP
+# Add include path for NXP device tree header files from Linux.
+ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/
+
obj-y += soc.o
obj-y += clock_scmi.o clock.o
diff --git a/arch/arm/mach-imx/imx9/scmi/clock.c b/arch/arm/mach-imx/imx9/scmi/clock.c
index 6e6541eaa31..951d47bd9d7 100644
--- a/arch/arm/mach-imx/imx9/scmi/clock.c
+++ b/arch/arm/mach-imx/imx9/scmi/clock.c
@@ -6,16 +6,17 @@
#include <asm/arch/clock.h>
#include <dm/uclass.h>
#include <scmi_agent.h>
-#include "../../../../../dts/upstream/src/arm64/freescale/imx95-clock.h"
+#include <scmi_nxp_protocols.h>
+#include "common.h"
u32 get_arm_core_clk(void)
{
u32 val;
- val = imx_clk_scmi_get_rate(IMX95_CLK_SEL_A55C0);
+ val = imx_clk_scmi_get_rate(SCMI_CLK(SEL_A55C0));
if (val)
return val;
- return imx_clk_scmi_get_rate(IMX95_CLK_A55);
+ return imx_clk_scmi_get_rate(SCMI_CLK(A55));
}
void init_uart_clk(u32 index)
@@ -24,13 +25,13 @@ void init_uart_clk(u32 index)
switch (index) {
case 0:
- clock_id = IMX95_CLK_LPUART1;
+ clock_id = SCMI_CLK(LPUART1);
break;
case 1:
- clock_id = IMX95_CLK_LPUART2;
+ clock_id = SCMI_CLK(LPUART2);
break;
case 2:
- clock_id = IMX95_CLK_LPUART3;
+ clock_id = SCMI_CLK(LPUART3);
break;
default:
return;
@@ -38,7 +39,7 @@ void init_uart_clk(u32 index)
/* 24MHz */
imx_clk_scmi_enable(clock_id, false);
- imx_clk_scmi_set_parent(clock_id, IMX95_CLK_24M);
+ imx_clk_scmi_set_parent(clock_id, SCMI_CLK(24M));
imx_clk_scmi_set_rate(clock_id, 24000000);
imx_clk_scmi_enable(clock_id, true);
}
@@ -49,19 +50,19 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_ARM_CLK:
return get_arm_core_clk();
case MXC_IPG_CLK:
- return imx_clk_scmi_get_rate(IMX95_CLK_BUSWAKEUP);
+ return imx_clk_scmi_get_rate(SCMI_CLK(BUSWAKEUP));
case MXC_CSPI_CLK:
- return imx_clk_scmi_get_rate(IMX95_CLK_LPSPI1);
+ return imx_clk_scmi_get_rate(SCMI_CLK(LPSPI1));
case MXC_ESDHC_CLK:
- return imx_clk_scmi_get_rate(IMX95_CLK_USDHC1);
+ return imx_clk_scmi_get_rate(SCMI_CLK(USDHC1));
case MXC_ESDHC2_CLK:
- return imx_clk_scmi_get_rate(IMX95_CLK_USDHC2);
+ return imx_clk_scmi_get_rate(SCMI_CLK(USDHC2));
case MXC_ESDHC3_CLK:
- return imx_clk_scmi_get_rate(IMX95_CLK_USDHC3);
+ return imx_clk_scmi_get_rate(SCMI_CLK(USDHC3));
case MXC_UART_CLK:
- return imx_clk_scmi_get_rate(IMX95_CLK_LPUART1);
+ return imx_clk_scmi_get_rate(SCMI_CLK(LPUART1));
case MXC_FLEXSPI_CLK:
- return imx_clk_scmi_get_rate(IMX95_CLK_FLEXSPI1);
+ return imx_clk_scmi_get_rate(SCMI_CLK(FLEXSPI1));
default:
return -1;
};
diff --git a/arch/arm/mach-imx/imx9/scmi/common.h b/arch/arm/mach-imx/imx9/scmi/common.h
new file mode 100644
index 00000000000..dd4675402c7
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/scmi/common.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef _SCMI_CLOCK_COMMON_H_
+#define _SCMI_CLOCK_COMMON_H_
+
+#ifdef CONFIG_IMX94
+#define IMX_PLAT 94
+#include <imx94-clock.h>
+#include <imx94-power.h>
+
+#define IMX94_CLK_FLEXSPI1 IMX94_CLK_XSPI1
+#endif
+
+#ifdef CONFIG_IMX95
+#define IMX_PLAT 95
+#include <imx95-clock.h>
+#include <imx95-power.h>
+
+#define IMX95_PD_M70 IMX95_PD_M7
+#endif
+
+#define IMX_PLAT_STR__(plat) # plat
+#define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT)
+#define IMX_PLAT_STR IMX_PLAT_STR_(IMX_PLAT)
+
+#define SCMI_CLK__(plat, clk) IMX ## plat ## _CLK_ ## clk
+#define SCMI_CLK_(plat, clk) SCMI_CLK__(plat, clk)
+#define SCMI_CLK(clk) SCMI_CLK_(IMX_PLAT, clk)
+
+#define SCMI_PD__(plat, pd) IMX ## plat ## _PD_ ## pd
+#define SCMI_PD_(plat, pd) SCMI_PD__(plat, pd)
+#define SCMI_PD(pd) SCMI_PD_(IMX_PLAT, pd)
+
+#define SCMI_CPU__(plat) MXC_CPU_IMX ## plat
+#define SCMI_CPU_(plat) SCMI_CPU__(plat)
+#define SCMI_CPU SCMI_CPU_(IMX_PLAT)
+
+#endif
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index f973652d0cb..dbaa19a9e6e 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -17,8 +17,11 @@
#include <env_internal.h>
#include <fuse.h>
#include <imx_thermal.h>
+#include <linux/bitfield.h>
#include <linux/iopoll.h>
#include <scmi_agent.h>
+#include <scmi_nxp_protocols.h>
+#include "common.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -174,7 +177,7 @@ u32 get_cpu_rev(void)
{
u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
- return (MXC_CPU_IMX95 << 12) | (CHIP_REV_1_0 + rev);
+ return (SCMI_CPU << 12) | (CHIP_REV_1_0 + rev);
}
#define UNLOCK_WORD 0xD928C520
@@ -254,6 +257,30 @@ static struct mm_region imx9_mem_map[] = {
PTE_BLOCK_OUTER_SHARE
}, {
#endif
+ /* PCIE2 ECAM */
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE1 Outbound */
+ .virt = 0x900000000UL,
+ .phys = 0x900000000UL,
+ .size = 0x100000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE2 Outbound */
+ .virt = 0xA00000000UL,
+ .phys = 0xA00000000UL,
+ .size = 0x100000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
/* empty entry to split table entry 5 if needed when TEEs are used */
0,
}, {
@@ -435,12 +462,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
u32 val[2] = {};
int ret, num_of_macs;
+ u32 bank = 40;
+
+ if (is_imx94())
+ bank = 66;
- ret = fuse_read(40, 5, &val[0]);
+ ret = fuse_read(bank, 5, &val[0]);
if (ret)
goto err;
- ret = fuse_read(40, 6, &val[1]);
+ ret = fuse_read(bank, 6, &val[1]);
if (ret)
goto err;
@@ -456,10 +487,32 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
mac[3] = (val[0] >> 24) & 0xff;
mac[4] = val[1] & 0xff;
mac[5] = (val[1] >> 8) & 0xff;
- if (dev_id == 1)
- mac[5] = mac[5] + 3;
- if (dev_id == 2)
- mac[5] = mac[5] + 6;
+
+ if (is_imx94()) {
+ /*
+ * i.MX94 uses the following mac address offset list:
+ * | No. | Module | Mac address user |
+ * |--------|-------------|---------------------------|
+ * | 0 ~ 1 | ethercat | port0/port1 |
+ * | 2 | netc switch | internal enetc3 mac/swp0 |
+ * | 3 ~ 6 | | enetc3 vf1~3/swp1 |
+ * | 7 | enetc mac | enetc0 pf |
+ * | 8 | | enetc1 pf |
+ * | 9 | | enetc2 pf |
+ * | 10 | netc switch | swp2 |
+ */
+ if (dev_id == 0)
+ mac[5] = mac[5] + 2; /* enetc3 mac/swp0 */
+ if (dev_id == 1)
+ mac[5] = mac[5] + 8; /* enetc1 */
+ if (dev_id == 2)
+ mac[5] = mac[5] + 9; /* enetc2 */
+ } else {
+ if (dev_id == 1)
+ mac[5] = mac[5] + 3;
+ if (dev_id == 2)
+ mac[5] = mac[5] + 6;
+ }
debug("%s: MAC%d: %pM\n", __func__, dev_id, mac);
return;
@@ -468,11 +521,149 @@ err:
printf("%s: fuse read err: %d\n", __func__, ret);
}
+static char *rst_string[32] = {
+ "cm33_lockup",
+ "cm33_swreq",
+ "cm7_lockup",
+ "cm7_swreq",
+ "fccu",
+ "jtag_sw",
+ "ele",
+ "tempsense",
+ "wdog1",
+ "wdog2",
+ "wdog3",
+ "wdog4",
+ "wdog5",
+ "jtag",
+ "cm33_exc",
+ "bbm",
+ "sw",
+ "sm_err", "fusa_sreco", "pmic", "unused", "unused", "unused",
+ "unused", "unused", "unused", "unused", "unused", "unused",
+ "unused", "unused",
+ "por"
+};
+
+static char *rst_string_imx94[32] = {
+ "cm33_lockup",
+ "cm33_swreq",
+ "cm70_lockup",
+ "cm70_swreq",
+ "fccu",
+ "jtag_sw",
+ "ele",
+ "tempsense",
+ "wdog1",
+ "wdog2",
+ "wdog3",
+ "wdog4",
+ "wdog5",
+ "jtag",
+ "wdog6",
+ "wdog7",
+ "wdog8",
+ "wo_netc", "cm33s_lockup", "cm33s_swreq", "cm71_lockup", "cm71_swreq", "cm33_exc",
+ "bbm", "sw", "sm_err", "fusa_sreco", "pmic", "unused",
+ "unused", "unused",
+ "por"
+};
+
+int get_reset_reason(bool sys, bool lm)
+{
+ struct scmi_imx_misc_reset_reason_in in = {
+ .flags = MISC_REASON_FLAG_SYSTEM,
+ };
+
+ struct scmi_imx_misc_reset_reason_out out = { 0 };
+ struct scmi_msg msg = {
+ .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC,
+ .message_id = SCMI_IMX_MISC_RESET_REASON,
+ .in_msg = (u8 *)&in,
+ .in_msg_sz = sizeof(in),
+ .out_msg = (u8 *)&out,
+ .out_msg_sz = sizeof(out),
+ };
+ int ret;
+
+ struct udevice *dev;
+ char **rst;
+
+ if (is_imx94())
+ rst = rst_string_imx94;
+ else
+ rst = rst_string;
+
+ ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev);
+ if (ret)
+ return ret;
+
+ if (sys) {
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (out.status) {
+ printf("%s:%d for SYS\n", __func__, out.status);
+ return ret;
+ }
+
+ if (out.bootflags & MISC_BOOT_FLAG_VLD) {
+ printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n",
+ rst[out.bootflags & MISC_BOOT_FLAG_REASON],
+ out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
+ FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
+ out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
+ FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
+ );
+ }
+ if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
+ printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n",
+ rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON],
+ out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
+ FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1,
+ out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
+ FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1
+ );
+ }
+ }
+
+ if (lm) {
+ in.flags = 0;
+ memset(&out, 0, sizeof(struct scmi_imx_misc_reset_reason_out));
+
+ ret = devm_scmi_process_msg(dev, &msg);
+ if (out.status) {
+ printf("%s:%d for LM\n", __func__, out.status);
+ return ret;
+ }
+
+ if (out.bootflags & MISC_BOOT_FLAG_VLD) {
+ printf("LM Boot reason: %s, origin: %ld, errid: %ld\n",
+ rst[out.bootflags & MISC_BOOT_FLAG_REASON],
+ out.bootflags & MISC_BOOT_FLAG_ORG_VLD ?
+ FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1,
+ out.bootflags & MISC_BOOT_FLAG_ERR_VLD ?
+ FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1
+ );
+ }
+
+ if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) {
+ printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n",
+ rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON],
+ out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ?
+ FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1,
+ out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ?
+ FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1
+ );
+ }
+ }
+
+ return 0;
+}
+
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
- case MXC_CPU_IMX95:
- return "95";/* iMX95 FULL */
+ case SCMI_CPU:
+ return IMX_PLAT_STR;
default:
return "??";
}
@@ -553,6 +744,10 @@ int arch_cpu_init(void)
gpio_reset(GPIO3_BASE_ADDR);
gpio_reset(GPIO4_BASE_ADDR);
gpio_reset(GPIO5_BASE_ADDR);
+#ifdef CONFIG_IMX94
+ gpio_reset(GPIO6_BASE_ADDR);
+ gpio_reset(GPIO7_BASE_ADDR);
+#endif
}
return 0;
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-11 17:04:53 +0000