diff options
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/Kconfig | 2 | ||||
| -rwxr-xr-x | arch/arm/mach-imx/mkimage_fit_atf.sh | 31 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mx7/ddr.c | 22 |
3 files changed, 37 insertions, 18 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index bed8cc7e886..6c3fedf665d 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -23,7 +23,7 @@ config IMX_RDC config IMX_BOOTAUX bool "Support boot auxiliary core" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 + depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M help bootaux [addr] to boot auxiliary core. diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh index dd1ca5ad3fd..fe12b7bb4bd 100755 --- a/arch/arm/mach-imx/mkimage_fit_atf.sh +++ b/arch/arm/mach-imx/mkimage_fit_atf.sh @@ -62,6 +62,23 @@ cat << __HEADER_EOF compression = "none"; load = <$BL33_LOAD_ADDR>; }; +__HEADER_EOF + +cnt=1 +for dtname in $* +do + cat << __FDT_IMAGE_EOF + fdt@$cnt { + description = "$(basename $dtname .dtb)"; + data = /incbin/("$dtname"); + type = "flat_dt"; + compression = "none"; + }; +__FDT_IMAGE_EOF +cnt=$((cnt+1)) +done + +cat << __HEADER_EOF atf@1 { description = "ARM Trusted Firmware"; os = "arm-trusted-firmware"; @@ -88,20 +105,6 @@ cat << __HEADER_EOF __HEADER_EOF fi -cnt=1 -for dtname in $* -do - cat << __FDT_IMAGE_EOF - fdt@$cnt { - description = "$(basename $dtname .dtb)"; - data = /incbin/("$dtname"); - type = "flat_dt"; - compression = "none"; - }; -__FDT_IMAGE_EOF -cnt=$((cnt+1)) -done - cat << __CONF_HEADER_EOF }; configurations { diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index 9713835bf27..d1e10a67887 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -13,6 +13,7 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/mx7-ddr.h> #include <common.h> +#include <linux/delay.h> /* * Routine: mx7_dram_cfg @@ -37,8 +38,23 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; int i; - /* Assert DDR Controller preset and DDR PHY reset */ - writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr); + /* + * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power + * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 , + * aresetn_n = 0, presetn = 0. That means reset everything. + */ + writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK, + &src_regs->ddrc_rcr); + + /* + * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown). + * If we assume this is 30 cycles at 100 MHz (about the rate of a + * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty. + */ + udelay(10); + + /* De-assert DDR Controller 'preset' and DDR PHY reset */ + clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK); /* DDR controller configuration */ writel(ddrc_regs_val->mstr, &ddrc_regs->mstr); @@ -71,7 +87,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg); writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap); - /* De-assert DDR Controller preset and DDR PHY reset */ + /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */ clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK); /* PHY configuration */ |