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-rw-r--r--arch/arm/mach-k3/r5/am62px/clk-data.c44
-rw-r--r--arch/arm/mach-k3/r5/am62px/dev-data.c24
-rw-r--r--arch/arm/mach-k3/r5/j721s2/clk-data.c58
-rw-r--r--arch/arm/mach-k3/r5/j721s2/dev-data.c3
-rw-r--r--arch/arm/mach-k3/r5/j722s/clk-data.c50
-rw-r--r--arch/arm/mach-k3/r5/j722s/dev-data.c34
-rw-r--r--arch/arm/mach-k3/r5/j784s4/clk-data.c54
-rw-r--r--arch/arm/mach-k3/r5/j784s4/dev-data.c1
8 files changed, 217 insertions, 51 deletions
diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c
index bc62d1d0d08..b552a2be74d 100644
--- a/arch/arm/mach-k3/r5/am62px/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk10",
};
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
"postdiv4_16ff_main_0_hsdivout5_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
"board_0_cp_gemac_cpts0_rft_clk_out",
"hsdiv4_16fft_main_1_hsdivout3_clk",
"postdiv4_16ff_main_2_hsdivout6_clk",
- NULL,
- NULL,
+ "cpsw_3guss_am67_main_0_cpts_genf0",
+ "cpsw_3guss_am67_main_0_cpts_genf1",
NULL,
NULL,
NULL,
@@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = {
};
static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
+ DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+ DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
@@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c
index 3cc211ea202..63e6beb4d57 100644
--- a/arch/arm/mach-k3/r5/am62px/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62px/dev-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
[6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
[7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
[8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
- [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
- [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
- [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
- [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
- [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
+ [11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]),
+ [12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+ [13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]),
};
static struct ti_dev soc_dev_list[] = {
@@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
- PSC_DEV(166, &soc_lpsc_list[9]),
- PSC_DEV(135, &soc_lpsc_list[10]),
- PSC_DEV(170, &soc_lpsc_list[11]),
- PSC_DEV(177, &soc_lpsc_list[12]),
- PSC_DEV(55, &soc_lpsc_list[13]),
+ PSC_DEV(13, &soc_lpsc_list[9]),
+ PSC_DEV(166, &soc_lpsc_list[10]),
+ PSC_DEV(135, &soc_lpsc_list[11]),
+ PSC_DEV(170, &soc_lpsc_list[12]),
+ PSC_DEV(177, &soc_lpsc_list[13]),
+ PSC_DEV(55, &soc_lpsc_list[14]),
};
const struct ti_k3_pd_platdata am62px_pd_platdata = {
diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c
index 0c5c321c1eb..0130c9c4b86 100644
--- a/arch/arm/mach-k3/r5/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Dave Gerlach <d-gerlach@ti.com>.
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
};
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout1_clk",
+ "postdiv3_16fft_main_0_hsdivout6_clk",
+ "board_0_mcu_cpts0_rft_clk_out",
+ "board_0_cpts0_rft_clk_out",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+};
+
static const char * const mcu_usart_clksel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"postdiv3_16fft_main_1_hsdivout5_clk",
@@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = {
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+ CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+ CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
@@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"),
+ DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+ DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
+ DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"),
+ DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"),
+ DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(29, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+ DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"),
+ DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"),
+ DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
@@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
+ DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
@@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+ DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
@@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata j721s2_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 105,
+ .clk_list_cnt = ARRAY_SIZE(clk_list),
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 124,
+ .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
};
diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c
index df70c5e5d7c..b78550707c5 100644
--- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Dave Gerlach <d-gerlach@ti.com>.
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
};
static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(29, &soc_lpsc_list[0]),
PSC_DEV(35, &soc_lpsc_list[0]),
PSC_DEV(108, &soc_lpsc_list[0]),
PSC_DEV(109, &soc_lpsc_list[0]),
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
index b4f27af333d..238d57d0aa0 100644
--- a/arch/arm/mach-k3/r5/j722s/clk-data.c
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
};
-static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
- "postdiv4_16ff_main_0_hsdivout5_clk",
- "hsdiv4_16fft_main_2_hsdivout2_clk",
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};
static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
@@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
"board_0_cp_gemac_cpts0_rft_clk_out",
"hsdiv4_16fft_main_1_hsdivout3_clk",
"postdiv4_16ff_main_2_hsdivout6_clk",
- NULL,
- NULL,
+ "cpsw_3guss_am67_main_0_cpts_genf0",
+ "cpsw_3guss_am67_main_0_cpts_genf1",
NULL,
NULL,
NULL,
@@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
- CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
@@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = {
};
static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
- DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
- DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
- DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
- DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+ DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
@@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
index 59176c98999..d6832266884 100644
--- a/arch/arm/mach-k3/r5/j722s/dev-data.c
+++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = {
static struct ti_lpsc soc_lpsc_list[] = {
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
- [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
- [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
- [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
+ [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+ [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+ [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
- [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
+ [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
};
@@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(61, &soc_lpsc_list[0]),
PSC_DEV(178, &soc_lpsc_list[1]),
PSC_DEV(179, &soc_lpsc_list[2]),
- PSC_DEV(57, &soc_lpsc_list[3]),
- PSC_DEV(58, &soc_lpsc_list[4]),
- PSC_DEV(161, &soc_lpsc_list[5]),
- PSC_DEV(75, &soc_lpsc_list[6]),
- PSC_DEV(36, &soc_lpsc_list[7]),
- PSC_DEV(102, &soc_lpsc_list[7]),
- PSC_DEV(146, &soc_lpsc_list[7]),
+ PSC_DEV(58, &soc_lpsc_list[3]),
+ PSC_DEV(161, &soc_lpsc_list[4]),
+ PSC_DEV(75, &soc_lpsc_list[5]),
+ PSC_DEV(36, &soc_lpsc_list[6]),
+ PSC_DEV(102, &soc_lpsc_list[6]),
+ PSC_DEV(146, &soc_lpsc_list[6]),
+ PSC_DEV(13, &soc_lpsc_list[7]),
PSC_DEV(166, &soc_lpsc_list[8]),
PSC_DEV(135, &soc_lpsc_list[9]),
PSC_DEV(170, &soc_lpsc_list[10]),
diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index 97d969271ec..24780eb6562 100644
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = {
"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
};
+static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout1_clk",
+ "postdiv3_16fft_main_0_hsdivout6_clk",
+ "board_0_mcu_cpts0_rft_clk_out",
+ "board_0_cpts0_rft_clk_out",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+};
+
static const char * const mcu_usart_clksel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"postdiv3_16fft_main_1_hsdivout5_clk",
@@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = {
"board_0_hfosc1_clk_out",
};
+static const char * const mcu_clkout_mux_out0_parents[] = {
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+};
+
static const char * const usb0_refclk_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
@@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = {
"board_0_mmc1_clk_out",
};
-static const char * const mcu_clkout_mux_out0_parents[] = {
- "hsdiv4_16fft_mcu_2_hsdivout0_clk",
- "hsdiv4_16fft_mcu_2_hsdivout1_clk",
-};
-
static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
"main_pll_hfosc_sel_out0",
"hsdiv4_16fft_main_0_hsdivout0_clk",
@@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+ CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
@@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"),
+ DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+ DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
+ DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"),
+ DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"),
+ DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(63, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+ DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"),
+ DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"),
DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+ DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c
index b32b4ba9588..19901821225 100644
--- a/arch/arm/mach-k3/r5/j784s4/dev-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c
@@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
};
static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(63, &soc_lpsc_list[0]),
PSC_DEV(35, &soc_lpsc_list[0]),
PSC_DEV(160, &soc_lpsc_list[0]),
PSC_DEV(161, &soc_lpsc_list[0]),
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-11 18:37:47 +0000