diff options
Diffstat (limited to 'arch/arm/mach-k3')
24 files changed, 446 insertions, 105 deletions
diff --git a/arch/arm/mach-k3/am62ax/Kconfig b/arch/arm/mach-k3/am62ax/Kconfig index f8cdcdca57a..6a3969343ec 100644 --- a/arch/arm/mach-k3/am62ax/Kconfig +++ b/arch/arm/mach-k3/am62ax/Kconfig @@ -50,9 +50,30 @@ config TARGET_PHYCORE_AM62AX_R5 select BINMAN imply SYS_K3_SPL_ATF +config TARGET_AM62D2_A53_EVM + bool "TI K3 based AM62D2 EVM running on A53" + select ARM64 + select BINMAN + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM62D2_R5_EVM + bool "TI K3 based AM62D2 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + endchoice source "board/ti/am62ax/Kconfig" source "board/phytec/phycore_am62ax/Kconfig" +source "board/ti/am62dx/Kconfig" endif diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 00173e6836b..48d578e7d6f 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -218,6 +218,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 44a2d445d24..aebd5200b0d 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -264,6 +264,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index a422919fab1..14f93ac998f 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -294,15 +294,6 @@ void board_init_f(ulong dummy) } spl_enable_cache(); - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), - &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - fixup_a53_cpu_freq_by_speed_grade(); } @@ -314,6 +305,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index 41812b7dbf7..219798315db 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -263,13 +263,6 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c index ce8ae941be6..bf8e1a5cb44 100644 --- a/arch/arm/mach-k3/am64x/boot.c +++ b/arch/arm/mach-k3/am64x/boot.c @@ -103,3 +103,39 @@ u32 get_boot_device(void) return bootmedia; } + +const char *get_reset_reason(void) +{ + u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC); + + /* After reading reset source register, software must clear it */ + if (reset_reason) + writel(reset_reason, CTRLMMR_MCU_RST_SRC); + + if (reset_reason == 0 || + (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN | + RST_SRC_SW_MAIN_POR_FROM_MCU))) + return "POR"; + + if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR)) + return "ESM"; + + if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN | + RST_SRC_SW_MAIN_WARM_FROM_MCU | + RST_SRC_SW_MCU_WARM_RST)) + return "RST"; + + if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST)) + return "DMSC"; + + if (reset_reason & RST_SRC_DEBUG_RST) + return "JTAG"; + + if (reset_reason & RST_SRC_THERMAL_RST) + return "THERMAL"; + + if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN)) + return "PIN"; + + return "UNKNOWN"; +} diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c index 0e07b1b7ce0..f999af143fb 100644 --- a/arch/arm/mach-k3/arm64/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64/arm64-mmu.c @@ -11,44 +11,38 @@ #include <asm/system.h> #include <asm/armv8/mmu.h> +#include <linux/sizes.h> +#include <mach/k3-ddr.h> -struct mm_region k3_mem_map[] = { - { +struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = { + { /* SoC Peripherals */ .virt = 0x0UL, .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1e780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { + }, { /* Flash Peripherals */ .virt = 0x500000000UL, .phys = 0x500000000UL, .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ + }, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */ + .virt = CFG_SYS_SDRAM_BASE, + .phys = CFG_SYS_SDRAM_BASE, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { /* List terminator */ 0, } }; struct mm_region *mem_map = k3_mem_map; + +u64 get_page_table_size(void) +{ + return SZ_128K; +} diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index f8c53b286eb..7c06764af82 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -30,6 +30,9 @@ #include <soc.h> #include <dm/uclass-internal.h> #include <dm/device-internal.h> +#include <asm/armv8/mmu.h> +#include <mach/k3-common-fdt.h> +#include <mach/k3-ddr.h> #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 @@ -258,6 +261,47 @@ void board_prep_linux(struct bootm_headers *images) ROUND(images->os.end, CONFIG_SYS_CACHELINE_SIZE)); } + +void enable_caches(void) +{ + void *fdt = (void *)gd->fdt_blob; + int ret; + + ret = mem_map_from_dram_banks(K3_MEM_MAP_FIRST_BANK_IDX, K3_MEM_MAP_LEN, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE); + if (ret) + debug("%s: Failed to setup dram banks\n", __func__); + + mmu_setup(); + + if (CONFIG_K3_ATF_LOAD_ADDR >= CFG_SYS_SDRAM_BASE) { + ret = fdt_fixup_reserved(fdt, "tfa", CONFIG_K3_ATF_LOAD_ADDR, + 0x80000); + if (ret) + printf("%s: Failed to perform tfa fixups (%s)\n", + __func__, fdt_strerror(ret)); + ret = mmu_unmap_reserved_mem("tfa", true); + if (ret) + printf("%s: Failed to unmap tfa reserved mem (%d)\n", + __func__, ret); + } + + if (CONFIG_K3_OPTEE_LOAD_ADDR >= CFG_SYS_SDRAM_BASE) { + ret = fdt_fixup_reserved(fdt, "optee", + CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); + if (ret) + printf("%s: Failed to perform optee fixups (%s)\n", + __func__, fdt_strerror(ret)); + ret = mmu_unmap_reserved_mem("optee", true); + if (ret) + printf("%s: Failed to unmap optee reserved mem (%d)\n", + __func__, ret); + } + + icache_enable(); + dcache_enable(); +} #endif void spl_enable_cache(void) @@ -303,6 +347,17 @@ static __maybe_unused void k3_dma_remove(void) pr_warn("DMA Device not found (err=%d)\n", rc); } +void spl_perform_arch_fixups(struct spl_image_info *spl_image) +{ + void *fdt = spl_image_fdt_addr(spl_image); + + if (!fdt) + return; + + fdt_fixup_reserved(fdt, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); + fdt_fixup_reserved(fdt, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); +} + void spl_board_prepare_for_boot(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) @@ -322,17 +377,6 @@ void spl_board_prepare_for_linux(void) int misc_init_r(void) { - if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) { - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(am65_cpsw_nuss), - &dev); - if (ret) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) { struct udevice *dev; int ret; diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 2777354c6ab..1e6786f6c20 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -140,7 +140,9 @@ int fdt_fixup_reserved(void *blob, const char *name, return -EINVAL; if (!strncmp(node_name, name, strlen(name))) { /* Read out old size first */ - addr = fdtdec_get_addr_size(blob, subnode, "reg", &size); + addr = fdtdec_get_addr_size_auto_parent( + blob, nodeoffset, subnode, "reg", 0, &size, + false); if (addr == FDT_ADDR_T_NONE) return -EINVAL; new_size = size; diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 105b42986de..2717da07690 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -46,6 +46,24 @@ /* Use Last 2K as Scratch pad */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 +/* Reset Reason Detection */ +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) + +/* Reset causes by bit mapping */ +#define RST_SRC_SAFETY_ERR BIT(31) +#define RST_SRC_MAIN_ESM_ERR BIT(30) +#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25) +#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24) +#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21) +#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20) +#define RST_SRC_SW_MCU_WARM_RST BIT(16) +#define RST_SRC_SMS_WARM_RST BIT(13) +#define RST_SRC_SMS_COLD_RST BIT(12) +#define RST_SRC_DEBUG_RST BIT(8) +#define RST_SRC_THERMAL_RST BIT(4) +#define RST_SRC_MAIN_RESET_PIN BIT(2) +#define RST_SRC_MCU_RESET_PIN BIT(0) + #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) #define AM64X_DEV_RTI8 127 diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h index d8fae2c8b45..47a61281d94 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_spl.h +++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h @@ -12,6 +12,7 @@ #define BOOT_DEVICE_OSPI 0x01 #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 #define BOOT_DEVICE_ETHERNET 0x04 #define BOOT_DEVICE_I2C 0x06 #define BOOT_DEVICE_UART 0x07 diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h index d481a46c675..3814dc95d01 100644 --- a/arch/arm/mach-k3/include/mach/j784s4_spl.h +++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h @@ -44,4 +44,6 @@ #define K3_PRIMARY_BOOTMODE 0x0 #define K3_BACKUP_BOOTMODE 0x1 +#define BOOT_DEVICE_CPGMAC 0x04 + #endif diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h index 39e6725bb9b..207e60b2763 100644 --- a/arch/arm/mach-k3/include/mach/k3-ddr.h +++ b/arch/arm/mach-k3/include/mach/k3-ddr.h @@ -8,6 +8,12 @@ #include <spl.h> +/* We need 3 extra entries for: + * SoC peripherals, flash and the sentinel value. + */ +#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 3) +#define K3_MEM_MAP_FIRST_BANK_IDX 2 + int dram_init(void); int dram_init_banksize(void); diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c b/arch/arm/mach-k3/j784s4/j784s4_init.c index 0f11511bda0..53f152ccd9c 100644 --- a/arch/arm/mach-k3/j784s4/j784s4_init.c +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c @@ -17,6 +17,7 @@ #include <dm/pinctrl.h> #include <mmc.h> #include <remoteproc.h> +#include <k3_bist.h> #include "../sysfw-loader.h" #include "../common.h" @@ -122,6 +123,48 @@ static void setup_navss_nb(void) writel(NB_THREADMAP_BIT2, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP); } +/* Execute and check results of BIST executed on MCU1_x and MCU4_O */ +static void run_bist_j784s4(struct udevice *dev) +{ + struct bist_ops *ops; + struct ti_sci_handle *handle; + int ret; + + ops = (struct bist_ops *)device_get_ops(dev); + handle = get_ti_sci_handle(); + + /* get status of HW POST PBIST on MCU1_x */ + if (ops->run_pbist_post()) + panic("HW POST LBIST on MCU1_x failed\n"); + + /* trigger PBIST tests on MCU4_0 */ + ret = prepare_pbist(handle); + ret |= ops->run_pbist_neg(); + ret |= deprepare_pbist(handle); + + ret |= prepare_pbist(handle); + ret |= ops->run_pbist(); + ret |= deprepare_pbist(handle); + + ret |= prepare_pbist(handle); + ret |= ops->run_pbist_rom(); + ret |= deprepare_pbist(handle); + + if (ret) + panic("PBIST on MCU4_0 failed: %d\n", ret); + + /* get status of HW POST PBIST on MCU1_x */ + if (ops->run_lbist_post()) + panic("HW POST LBIST on MCU1_x failed\n"); + + /* trigger LBIST tests on MCU1_x */ + ret = prepare_lbist(handle); + ret |= ops->run_lbist(); + ret |= deprepare_lbist(handle); + if (ret) + panic("LBIST on MCU4_0 failed: %d\n", ret); +} + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -266,6 +309,15 @@ void board_init_f(ulong dummy) printf("AVS init failed: %d\n", ret); } + if (!IS_ENABLED(CONFIG_CPU_V7R) && IS_ENABLED(CONFIG_K3_BIST)) { + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(k3_bist), + &dev); + if (ret) + panic("Failed to get BIST device: %d\n", ret); + run_bist_j784s4(dev); + } + if (IS_ENABLED(CONFIG_CPU_V7R)) setup_navss_nb(); diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c index bc62d1d0d08..b552a2be74d 100644 --- a/arch/arm/mach-k3/r5/am62px/clk-data.c +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include <linux/clk-provider.h> @@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk10", }; +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { "postdiv4_16ff_main_0_hsdivout5_clk", "hsdiv4_16fft_main_2_hsdivout2_clk", @@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), @@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), @@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c index 3cc211ea202..63e6beb4d57 100644 --- a/arch/arm/mach-k3/r5/am62px/dev-data.c +++ b/arch/arm/mach-k3/r5/am62px/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = { [6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), - [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), - [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]), - [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), - [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), - [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), + [11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]), + [12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]), }; static struct ti_dev soc_dev_list[] = { @@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(36, &soc_lpsc_list[8]), PSC_DEV(102, &soc_lpsc_list[8]), PSC_DEV(146, &soc_lpsc_list[8]), - PSC_DEV(166, &soc_lpsc_list[9]), - PSC_DEV(135, &soc_lpsc_list[10]), - PSC_DEV(170, &soc_lpsc_list[11]), - PSC_DEV(177, &soc_lpsc_list[12]), - PSC_DEV(55, &soc_lpsc_list[13]), + PSC_DEV(13, &soc_lpsc_list[9]), + PSC_DEV(166, &soc_lpsc_list[10]), + PSC_DEV(135, &soc_lpsc_list[11]), + PSC_DEV(170, &soc_lpsc_list[12]), + PSC_DEV(177, &soc_lpsc_list[13]), + PSC_DEV(55, &soc_lpsc_list[14]), }; const struct ti_k3_pd_platdata am62px_pd_platdata = { diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 6ac2973bd67..6269b33f66b 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -27,7 +27,7 @@ enum { IMAGE_ID_DM_FW, IMAGE_ID_TIFSSTUB_HS, IMAGE_ID_TIFSSTUB_FS, - IMAGE_ID_T, + IMAGE_ID_TIFSSTUB_GP, IMAGE_AMT, }; diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c index 0c5c321c1eb..0130c9c4b86 100644 --- a/arch/arm/mach-k3/r5/j721s2/clk-data.c +++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach <d-gerlach@ti.com>. * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include <linux/clk-provider.h> @@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout4_clk", }; +static const char * const wkup_gpio0_clksel_out0_parents[] = { + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = { CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), @@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(29, 9, "board_0_ext_refclk1_out"), + DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"), + DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"), DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"), @@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"), + DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"), DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 221, "mcu_clkout_mux_out0"), @@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"), DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 352, "dpi0_ext_clksel_out0"), DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"), DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), @@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721s2_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 105, + .clk_list_cnt = ARRAY_SIZE(clk_list), .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 124, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), }; diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c index df70c5e5d7c..b78550707c5 100644 --- a/arch/arm/mach-k3/r5/j721s2/dev-data.c +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach <d-gerlach@ti.com>. * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(29, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(108, &soc_lpsc_list[0]), PSC_DEV(109, &soc_lpsc_list[0]), diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c index b4f27af333d..238d57d0aa0 100644 --- a/arch/arm/mach-k3/r5/j722s/clk-data.c +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include <linux/clk-provider.h> @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", }; -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { @@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), - DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), - DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), DEV_CLK(58, 2, "board_0_mmc1_clk_out"), @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c index 59176c98999..d6832266884 100644 --- a/arch/arm/mach-k3/r5/j722s/dev-data.c +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = { static struct ti_lpsc soc_lpsc_list[] = { [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]), [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), - [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]), [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]), [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), }; @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(61, &soc_lpsc_list[0]), PSC_DEV(178, &soc_lpsc_list[1]), PSC_DEV(179, &soc_lpsc_list[2]), - PSC_DEV(57, &soc_lpsc_list[3]), - PSC_DEV(58, &soc_lpsc_list[4]), - PSC_DEV(161, &soc_lpsc_list[5]), - PSC_DEV(75, &soc_lpsc_list[6]), - PSC_DEV(36, &soc_lpsc_list[7]), - PSC_DEV(102, &soc_lpsc_list[7]), - PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(58, &soc_lpsc_list[3]), + PSC_DEV(161, &soc_lpsc_list[4]), + PSC_DEV(75, &soc_lpsc_list[5]), + PSC_DEV(36, &soc_lpsc_list[6]), + PSC_DEV(102, &soc_lpsc_list[6]), + PSC_DEV(146, &soc_lpsc_list[6]), + PSC_DEV(13, &soc_lpsc_list[7]), PSC_DEV(166, &soc_lpsc_list[8]), PSC_DEV(135, &soc_lpsc_list[9]), PSC_DEV(170, &soc_lpsc_list[10]), diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 97d969271ec..24780eb6562 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = { "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", }; +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = { "board_0_hfosc1_clk_out", }; +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", +}; + static const char * const usb0_refclk_sel_out0_parents[] = { "gluelogic_hfosc0_clkout", "board_0_hfosc1_clk_out", @@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { "board_0_mmc1_clk_out", }; -static const char * const mcu_clkout_mux_out0_parents[] = { - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout1_clk", -}; - static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "main_pll_hfosc_sel_out0", "hsdiv4_16fft_main_0_hsdivout0_clk", @@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0), @@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(63, 9, "board_0_ext_refclk1_out"), + DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"), DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index b32b4ba9588..19901821225 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(63, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(160, &soc_lpsc_list[0]), PSC_DEV(161, &soc_lpsc_list[0]), diff --git a/arch/arm/mach-k3/schema.yaml b/arch/arm/mach-k3/schema.yaml index c8dd2e79e7d..8c4691f24ed 100644 --- a/arch/arm/mach-k3/schema.yaml +++ b/arch/arm/mach-k3/schema.yaml @@ -344,7 +344,7 @@ properties: resasg_entries: type: array minItems: 0 - maxItems: 468 + maxItems: 586 items: type: object properties: @@ -420,7 +420,7 @@ properties: resasg_entries: type: array minItems: 0 - maxItems: 468 + maxItems: 586 items: type: object properties: |