diff options
Diffstat (limited to 'arch/arm/mach-mvebu/cpu.c')
| -rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 39 |
1 files changed, 17 insertions, 22 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1457af1d6aa..1f8cdf8744e 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -20,7 +20,7 @@ #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3)) -static struct mbus_win windows[] = { +static const struct mbus_win windows[] = { /* SPI */ { MBUS_SPI_BASE, MBUS_SPI_SIZE, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH }, @@ -445,19 +445,6 @@ static void setup_usb_phys(void) */ int arch_cpu_init(void) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; - - if (IS_ENABLED(CONFIG_ARMADA_38X)) { - /* - * To fully release / unlock this area from cache, we need - * to flush all caches and disable the L2 cache. - */ - icache_disable(); - dcache_disable(); - clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - } - /* * We need to call mvebu_mbus_probe() before calling * update_sdram_window_sizes() as it disables all previously @@ -663,7 +650,7 @@ void enable_caches(void) * ethernet driver (mvpp2). So lets keep the d-cache disabled * until this is solved. */ - if (IS_ENABLED(CONFIG_ARMADA_375)) { + if (!IS_ENABLED(CONFIG_ARMADA_375)) { /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } @@ -671,13 +658,21 @@ void enable_caches(void) void v7_outer_cache_enable(void) { + struct pl310_regs *const pl310 = + (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + + /* The L2 cache is already disabled at this point */ + + /* + * For now L2 cache will be enabled only for Armada XP and Armada 38x. + * It can be enabled also for other SoCs after testing that it works fine. + */ + if (!IS_ENABLED(CONFIG_ARMADA_XP) && !IS_ENABLED(CONFIG_ARMADA_38X)) + return; + if (IS_ENABLED(CONFIG_ARMADA_XP)) { - struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; u32 u; - /* The L2 cache is already disabled at this point */ - /* * For Aurora cache in no outer mode, enable via the CP15 * coprocessor broadcasting of cache commands to L2. @@ -687,10 +682,10 @@ void v7_outer_cache_enable(void) asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u)); isb(); - - /* Enable the L2 cache */ - setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } void v7_outer_cache_disable(void) |