diff options
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/system_manager_soc64.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c2ca0a50e35..054a28d845d 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -141,6 +141,27 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[19] store ATF CPU0 ON OFF value. + * + * Bit[18] reserved for SDM to configure ACF + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) + */ +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK BIT(18) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18 + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) |