diff options
Diffstat (limited to 'arch/arm/mach-socfpga/include')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 3 |
2 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 5ac868a281b..074b9691af8 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ @@ -45,8 +46,10 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 @@ -75,6 +78,7 @@ #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 #define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 #define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 713fa2c517b..054a28d845d 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -146,6 +146,7 @@ void populate_sysmgr_pinmux(void); * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? * * Bit[30] reserved for FSBL to update the DDR init progress + * 1 - means in progress, 0 - haven't started / DDR is up running. * * Bit[19] store ATF CPU0 ON OFF value. @@ -156,6 +157,8 @@ void populate_sysmgr_pinmux(void); */ #define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) #define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27) #define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK BIT(18) #define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18 |