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-rw-r--r--arch/arm/mach-sunxi/Kconfig3
-rw-r--r--arch/arm/mach-sunxi/board.c2
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_a133.c2
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h616.c12
4 files changed, 10 insertions, 9 deletions
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 6a511c4fd39..b04ec671696 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -487,6 +487,7 @@ config MACH_SUN8I_V3S
select SUNXI_DRAM_DW_16BIT
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+ imply OF_UPSTREAM
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
@@ -718,9 +719,9 @@ config DRAM_CLK
int "sunxi dram clock speed"
default 792 if MACH_SUN9I
default 648 if MACH_SUN8I_R40
- default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
MACH_SUN8I_V3S
+ default 312 if MACH_SUN6I || MACH_SUN8I
default 672 if MACH_SUN50I
default 744 if MACH_SUN50I_H6
default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index fb4837c2082..432b1c10f92 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -476,8 +476,8 @@ void board_init_f(ulong dummy)
/* Enable non-secure access to some peripherals */
tzpc_init();
- clock_init();
timer_init();
+ clock_init();
gpio_init();
spl_init();
diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c
index 3a231141168..1496f99624d 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_a133.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c
@@ -416,7 +416,7 @@ static void mctl_com_init(const struct dram_para *para,
static void mctl_drive_odt_config(const struct dram_para *para)
{
u32 val;
- u64 base;
+ ulong base;
u32 i;
/* DX drive */
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index 877181016f3..3345c9b8e82 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -1078,18 +1078,18 @@ static bool mctl_phy_init(const struct dram_para *para,
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
break;
case SUNXI_DRAM_TYPE_LPDDR3:
- writel(mr0, &mctl_ctl->mrctrl1);
- writel(0x800000f0, &mctl_ctl->mrctrl0);
- mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
-
- writel(4, &mctl_ctl->mrctrl1);
+ /* MR0 is read-only */
+ /* MR1: nWR=14, BL8 */
+ writel(0x183, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
- writel(mr2, &mctl_ctl->mrctrl1);
+ /* MR2: no WR leveling, WL set A, use nWR>9, nRL=14/nWL=8 */
+ writel(0x21c, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);
+ /* MR3: 34.3 Ohm pull-up/pull-down resistor */
writel(0x301, &mctl_ctl->mrctrl1);
writel(0x800000f0, &mctl_ctl->mrctrl0);
mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0);