diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 38 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts | 27 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts | 47 |
4 files changed, 114 insertions, 2 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 79ed4ac0825..b25570d1d79 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1260,7 +1260,9 @@ dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am6528-iot2050-basic-pg2.dtb \ k3-am6548-iot2050-advanced.dtb \ k3-am6548-iot2050-advanced-pg2.dtb \ - k3-am6548-iot2050-advanced-m2.dtb + k3-am6548-iot2050-advanced-m2.dtb \ + k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo \ + k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \ k3-j721e-r5-common-proc-board.dtb \ k3-j7200-common-proc-board.dtb \ diff --git a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi index a2fc8bbc123..03ccc543293 100644 --- a/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi +++ b/arch/arm/dts/k3-am65-iot2050-boot-image.dtsi @@ -61,6 +61,36 @@ }; }; +#ifdef CONFIG_TARGET_IOT2050_A53_PG2 + bkey-usb3-overlay { + description = "M.2-bkey-usb3-overlay"; + type = "blob"; + load = <0x82100000>; + arch = "arm64"; + compression = "none"; + blob-ext { + filename = "k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dtbo"; + }; + hash { + algo = "sha256"; + }; + }; + + bkey-ekey-pcie-overlay { + description = "M.2-bkey-ekey-pcie-overlay"; + type = "blob"; + load = <0x82110000>; + arch = "arm64"; + compression = "none"; + blob-ext { + filename = "k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dtbo"; + }; + hash { + algo = "sha256"; + }; + }; +#endif + #ifdef CONFIG_WDT_K3_RTI_FW_FILE k3-rti-wdt-firmware { type = "firmware"; @@ -84,9 +114,15 @@ description = "NAME"; firmware = "u-boot"; fdt = "fdt-SEQ"; + loadables = +#ifdef CONFIG_TARGET_IOT2050_A53_PG2 + "bkey-usb3-overlay", + "bkey-ekey-pcie-overlay", +#endif #ifdef CONFIG_WDT_K3_RTI_FW_FILE - loadables = "k3-rti-wdt-firmware"; + "k3-rti-wdt-firmware", #endif + <>; signature { sign-images = "firmware", "fdt", "loadables"; }; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts new file mode 100644 index 00000000000..c9e736098f9 --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-overlay.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0 + * Copyright (c) Siemens AG, 2022 + * + * Authors: + * Chao Zeng <chao.zeng@siemens.com> + * Jan Kiszka <jan.kiszka@siemens.com> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/gpio/gpio.h> + +&pcie0_rc { + num-lanes = <1>; + phys = <&serdes0 PHY_TYPE_PCIE 1>; + phy-names = "pcie-phy0"; + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie1_rc { + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts new file mode 100644 index 00000000000..72fc011bd54 --- /dev/null +++ b/arch/arm/dts/k3-am6548-iot2050-advanced-m2-bkey-usb3-overlay.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0 + * Copyright (c) Siemens AG, 2022 + * + * Authors: + * Chao Zeng <chao.zeng@siemens.com> + * Jan Kiszka <jan.kiszka@siemens.com> + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/gpio/gpio.h> + +&serdes0 { + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&pcie0_rc { + status = "disabled"; +}; + +&pcie1_rc { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins_default>; + + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; |