diff options
Diffstat (limited to 'arch/mips/mach-mtmips')
44 files changed, 4541 insertions, 0 deletions
diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig new file mode 100644 index 00000000000..3fcd0b8465b --- /dev/null +++ b/arch/mips/mach-mtmips/Kconfig @@ -0,0 +1,125 @@ +menu "MediaTek MIPS platforms" + depends on ARCH_MTMIPS + +config SYS_VENDOR + default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + +config SYS_MALLOC_F_LEN + default 0x1000 + +config SYS_SOC + default "mt7620" if SOC_MT7620 + default "mt7621" if SOC_MT7621 + default "mt7628" if SOC_MT7628 + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 65536 if SOC_MT7620 || SOC_MT7628 + default 32768 if SOC_MT7621 + +config SYS_ICACHE_LINE_SIZE + default 32 + +config SYS_SCACHE_LINE_SIZE + default 32 if SOC_MT7621 + +config TEXT_BASE + default 0x9c000000 if !SPL && !SOC_MT7621 + default 0x80200000 if SPL || SOC_MT7621 + +config SPL_TEXT_BASE + default 0x9c000000 if !SOC_MT7621 + default 0x80100000 if SOC_MT7621 + +config SPL_SIZE_LIMIT + default 0x30000 if SOC_MT7621 + +config TPL_TEXT_BASE + default 0xbfc00000 if SOC_MT7621 + +config TPL_MAX_SIZE + default 4096 if SOC_MT7621 + +config SPL_PAYLOAD + default "u-boot-lzma.img" if SPL_LZMA + +config BUILD_TARGET + default "u-boot-with-spl.bin" if SPL && !SOC_MT7621 + default "u-boot-lzma.img" if SOC_MT7621 + default "u-boot.bin" + +config MAX_MEM_SIZE + int + default 256 if SOC_MT7620 || SOC_MT7628 + default 512 if SOC_MT7621 + +choice + prompt "MediaTek MIPS SoC select" + +config SOC_MT7620 + bool "MT7620" + select SYS_CACHE_SHIFT_5 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + select PINCTRL_MT7620 + select MT7620_SERIAL + select MISC + select SPL_SEPARATE_BSS if SPL + select SPL_LOADER_SUPPORT if SPL + select SPL_OF_CONTROL if SPL_DM + select SPL_OF_PLATDATA if SPL_DM + select SPL_DM_SERIAL if SPL_DM + help + This supports MediaTek MT7620. + +config SOC_MT7621 + bool "MT7621" + select MIPS_CM + select MIPS_L2_CACHE + select MMC_SUPPORTS_TUNING + select SYS_CACHE_SHIFT_5 + select SYS_MIPS_CACHE_INIT_RAM_LOAD + select PINCTRL_MT7621 + select MTK_SERIAL + select REGMAP + select SYSCON + select BINMAN + select SUPPORT_TPL + select SPL_LOADER_SUPPORT if SPL + select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL + help + This supports MediaTek MT7621. + +config SOC_MT7628 + bool "MT7628" + select SYS_CACHE_SHIFT_5 + select MIPS_INIT_STACK_IN_SRAM + select MIPS_SRAM_INIT + select SYS_MIPS_CACHE_INIT_RAM_LOAD + select PINCTRL_MT7628 + select MTK_SERIAL + select SYSRESET + select SYSRESET_RESETCTL + select SPL_SEPARATE_BSS if SPL + select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL + select SPL_LOADER_SUPPORT if SPL + select SPL_OF_CONTROL if SPL_DM + select SPL_SIMPLE_BUS if SPL_DM + select SPL_DM_SERIAL if SPL_DM + select SPL_CLK if SPL_DM && SPL_SERIAL + select SPL_SYSRESET if SPL_DM + select SPL_OF_LIBFDT if SPL_OF_CONTROL + help + This supports MediaTek MT7628/MT7688. + +endchoice + +source "arch/mips/mach-mtmips/mt7620/Kconfig" +source "arch/mips/mach-mtmips/mt7621/Kconfig" +source "arch/mips/mach-mtmips/mt7628/Kconfig" + +endmenu diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach-mtmips/Makefile new file mode 100644 index 00000000000..2f35b1a925c --- /dev/null +++ b/arch/mips/mach-mtmips/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += cpu.o + +ifneq ($(CONFIG_SOC_MT7621),y) +obj-y += ddr_init.o +obj-y += ddr_cal.o +obj-$(CONFIG_XPL_BUILD) += spl.o +endif + +obj-$(CONFIG_SOC_MT7620) += mt7620/ +obj-$(CONFIG_SOC_MT7621) += mt7621/ +obj-$(CONFIG_SOC_MT7628) += mt7628/ diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach-mtmips/cpu.c new file mode 100644 index 00000000000..982a5889df8 --- /dev/null +++ b/arch/mips/mach-mtmips/cpu.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Stefan Roese <sr@denx.de> + */ + +#include <event.h> +#include <init.h> +#include <malloc.h> +#include <asm/addrspace.h> +#include <asm/global_data.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)KSEG1, CONFIG_MAX_MEM_SIZE << 20); + + return 0; +} + +#ifndef CONFIG_XPL_BUILD +static int last_stage_init(void) +{ + void *src, *dst; + + src = malloc(SZ_64K); + dst = malloc(SZ_64K); + if (!src || !dst) { + printf("Can't allocate buffer for cache cleanup copy!\n"); + return 0; + } + + /* + * It has been noticed, that sometimes the d-cache is not in a + * "clean-state" when U-Boot is running on MT7688. This was + * detected when using the ethernet driver (which uses d-cache) + * and a TFTP command does not complete. Copying an area of 64KiB + * in DDR at a very late bootup time in U-Boot, directly before + * calling into the prompt, seems to fix this issue. + */ + memcpy(dst, src, SZ_64K); + free(src); + free(dst); + + return 0; +} +EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); +#endif diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c new file mode 100644 index 00000000000..e2e1760a646 --- /dev/null +++ b/arch/mips/mach-mtmips/ddr_cal.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/addrspace.h> +#include <asm/cacheops.h> +#include <asm/global_data.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <mach/mc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define COARSE_MIN_START 6 +#define FINE_MIN_START 15 +#define COARSE_MAX_START 7 +#define FINE_MAX_START 0 + +#define NUM_OF_CACHELINE 128 +#define TEST_PAT_SIZE (NUM_OF_CACHELINE * CONFIG_SYS_CACHELINE_SIZE) + +#define INIT_DQS_VAL ((7 << DQS1_DELAY_COARSE_TUNING_S) | \ + (4 << DQS1_DELAY_FINE_TUNING_S) | \ + (7 << DQS0_DELAY_COARSE_TUNING_S) | \ + (4 << DQS0_DELAY_FINE_TUNING_S)) + +static inline void pref_op(int op, const volatile void *addr) +{ + __asm__ __volatile__("pref %0, 0(%1)" : : "i" (op), "r" (addr)); +} + +static inline bool dqs_test_error(void __iomem *memc, u32 memsize, u32 dqsval, + u32 bias) +{ + u32 *nca, *ca; + u32 off; + int i; + + for (off = 0; off < memsize - TEST_PAT_SIZE; off += (memsize >> 6)) { + nca = (u32 *)KSEG1ADDR(off); + ca = (u32 *)KSEG0ADDR(off); + + writel(INIT_DQS_VAL, memc + MEMCTL_DDR_DQS_DLY_REG); + wmb(); + + for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++) + ca[i] = 0x1f1f1f1f; + + for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++) + nca[i] = (u32)nca + i + bias; + + writel(dqsval, memc + MEMCTL_DDR_DQS_DLY_REG); + wmb(); + + for (i = 0; i < TEST_PAT_SIZE; i += CONFIG_SYS_CACHELINE_SIZE) + mips_cache(HIT_INVALIDATE_D, (u8 *)ca + i); + wmb(); + + for (i = 0; i < TEST_PAT_SIZE; i += CONFIG_SYS_CACHELINE_SIZE) + pref_op(0, (u8 *)ca + i); + + for (i = 0; i < TEST_PAT_SIZE / sizeof(u32); i++) { + if (ca[i] != (u32)nca + i + bias) + return true; + } + } + + return false; +} + +static inline int dqs_find_max(void __iomem *memc, u32 memsize, int initval, + int maxval, int shift, u32 regval) +{ + int fieldval; + u32 dqsval; + + for (fieldval = initval; fieldval <= maxval; fieldval++) { + dqsval = regval | (fieldval << shift); + if (dqs_test_error(memc, memsize, dqsval, 3)) + return max(fieldval - 1, initval); + } + + return maxval; +} + +static inline int dqs_find_min(void __iomem *memc, u32 memsize, int initval, + int minval, int shift, u32 regval) +{ + int fieldval; + u32 dqsval; + + for (fieldval = initval; fieldval >= minval; fieldval--) { + dqsval = regval | (fieldval << shift); + if (dqs_test_error(memc, memsize, dqsval, 1)) + return min(fieldval + 1, initval); + } + + return minval; +} + +void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw) +{ + u32 dqs_coarse_min, dqs_coarse_max, dqs_coarse_val; + u32 dqs_fine_min, dqs_fine_max, dqs_fine_val; + u32 dqs_coarse_min_limit, dqs_fine_min_limit; + u32 dlls, dqs_dll, ddr_cfg2_reg; + u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; + u32 rem, mask; + int i; + + /* Disable Self-refresh */ + clrbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN); + + /* Save DDR_CFG2 and modify its DQS gating window */ + ddr_cfg2_reg = readl(memc + MEMCTL_DDR_CFG2_REG); + mask = DQS0_GATING_WINDOW_M; + if (bw == IND_SDRAM_WIDTH_16BIT) + mask |= DQS1_GATING_WINDOW_M; + clrbits_32(memc + MEMCTL_DDR_CFG2_REG, mask); + + /* Get minimum available DQS value */ + dlls = readl(memc + MEMCTL_DLL_DBG_REG); + dlls = (dlls & MST_DLY_SEL_M) >> MST_DLY_SEL_S; + + dqs_dll = dlls >> 4; + if (dqs_dll <= 8) + dqs_coarse_min_limit = 8 - dqs_dll; + else + dqs_coarse_min_limit = 0; + + dqs_dll = dlls & 0xf; + if (dqs_dll <= 8) + dqs_fine_min_limit = 8 - dqs_dll; + else + dqs_fine_min_limit = 0; + + /* Initial DQS register value */ + dqs_dly = INIT_DQS_VAL; + + /* Calibrate DQS0 and/or DQS1 */ + for (i = 0; i < bw; i++) { + shift = i * 8; + dqs_dly &= ~(0xff << shift); + + /* Find maximum DQS coarse-grain */ + dqs_dly_tmp = dqs_dly | (0xf << shift); + dqs_coarse_max = dqs_find_max(memc, memsize, COARSE_MAX_START, + 0xf, 4 + shift, dqs_dly_tmp); + + /* Find maximum DQS fine-grain */ + dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); + test_dqs = dqs_find_max(memc, memsize, FINE_MAX_START, 0xf, + shift, dqs_dly_tmp); + + if (test_dqs == FINE_MAX_START) { + dqs_coarse_max--; + dqs_fine_max = 0xf; + } else { + dqs_fine_max = test_dqs - 1; + } + + /* Find minimum DQS coarse-grain */ + dqs_dly_tmp = dqs_dly; + dqs_coarse_min = dqs_find_min(memc, memsize, COARSE_MIN_START, + dqs_coarse_min_limit, 4 + shift, + dqs_dly_tmp); + + /* Find minimum DQS fine-grain */ + dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); + test_dqs = dqs_find_min(memc, memsize, FINE_MIN_START, + dqs_fine_min_limit, shift, dqs_dly_tmp); + + if (test_dqs == FINE_MIN_START + 1) { + dqs_coarse_min++; + dqs_fine_min = 0; + } else { + dqs_fine_min = test_dqs; + } + + /* Calculate central DQS coarse/fine value */ + dqs_coarse_val = (dqs_coarse_max + dqs_coarse_min) >> 1; + rem = (dqs_coarse_max + dqs_coarse_min) % 2; + + dqs_fine_val = (rem * 4) + ((dqs_fine_max + dqs_fine_min) >> 1); + if (dqs_fine_val >= 0x10) { + dqs_coarse_val++; + dqs_fine_val -= 8; + } + + /* Save current DQS value */ + dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; + } + + /* Set final DQS value */ + writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); + + /* Restore DDR_CFG2 */ + writel(ddr_cfg2_reg, memc + MEMCTL_DDR_CFG2_REG); + + /* Enable Self-refresh */ + setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN); +} diff --git a/arch/mips/mach-mtmips/ddr_init.c b/arch/mips/mach-mtmips/ddr_init.c new file mode 100644 index 00000000000..cab53561e42 --- /dev/null +++ b/arch/mips/mach-mtmips/ddr_init.c @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <mach/ddr.h> +#include <mach/mc.h> + +#define DDR_BW_TEST_PAT 0xaa5555aa + +static const u32 sdr_size_cfg1[] = { + [DRAM_8MB] = (1 << NUMROWS_S), + [DRAM_16MB] = (1 << NUMROWS_S) | (1 << NUMCOLS_S), + [DRAM_32MB] = (2 << NUMROWS_S) | (1 << NUMCOLS_S), + [DRAM_64MB] = (2 << NUMROWS_S) | (2 << NUMCOLS_S), +}; + +static const u32 dram_size[] = { + [DRAM_8MB] = SZ_8M, + [DRAM_16MB] = SZ_16M, + [DRAM_32MB] = SZ_32M, + [DRAM_64MB] = SZ_64M, + [DRAM_128MB] = SZ_128M, + [DRAM_256MB] = SZ_256M, +}; + +static void dram_test_write(u32 addr, u32 val) +{ + volatile ulong *target = (volatile ulong *)(KSEG1 + addr); + + sync(); + *target = val; + sync(); +} + +static u32 dram_test_read(u32 addr) +{ + volatile ulong *target = (volatile ulong *)(KSEG1 + addr); + u32 val; + + sync(); + val = *target; + sync(); + + return val; +} + +static int dram_addr_test_bit(u32 bit) +{ + u32 val; + + dram_test_write(0, 0); + dram_test_write(BIT(bit), DDR_BW_TEST_PAT); + val = dram_test_read(0); + + if (val == DDR_BW_TEST_PAT) + return 1; + + return 0; +} + +static void mc_ddr_init(void __iomem *memc, const struct mc_ddr_cfg *cfg, + u32 dq_dly, u32 dqs_dly, mc_reset_t mc_reset, u32 bw) +{ + u32 val; + + mc_reset(1); + __udelay(200); + mc_reset(0); + + clrbits_32(memc + MEMCTL_SDRAM_CFG1_REG, RBC_MAPPING); + + writel(cfg->cfg2, memc + MEMCTL_DDR_CFG2_REG); + writel(cfg->cfg3, memc + MEMCTL_DDR_CFG3_REG); + writel(cfg->cfg4, memc + MEMCTL_DDR_CFG4_REG); + writel(dq_dly, memc + MEMCTL_DDR_DQ_DLY_REG); + writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); + + writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG); + + val = cfg->cfg1; + if (bw) { + val &= ~IND_SDRAM_WIDTH_M; + val |= (bw << IND_SDRAM_WIDTH_S) & IND_SDRAM_WIDTH_M; + } + + writel(val, memc + MEMCTL_DDR_CFG1_REG); + + clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M, + 1 << SR_TAR_CNT_S); + + setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN); +} + +void ddr1_init(struct mc_ddr_init_param *param) +{ + enum mc_dram_size sz; + u32 bw = 0; + + /* First initialization, determine bus width */ + mc_ddr_init(param->memc, ¶m->cfgs[DRAM_8MB], param->dq_dly, + param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT); + + /* Test bus width */ + dram_test_write(0, DDR_BW_TEST_PAT); + if (dram_test_read(0) == DDR_BW_TEST_PAT) + bw = IND_SDRAM_WIDTH_16BIT; + else + bw = IND_SDRAM_WIDTH_8BIT; + + /* Second initialization, determine DDR capacity */ + mc_ddr_init(param->memc, ¶m->cfgs[DRAM_128MB], param->dq_dly, + param->dqs_dly, param->mc_reset, bw); + + if (dram_addr_test_bit(9)) { + sz = DRAM_8MB; + } else { + if (dram_addr_test_bit(10)) { + if (dram_addr_test_bit(23)) + sz = DRAM_16MB; + else + sz = DRAM_32MB; + } else { + if (dram_addr_test_bit(24)) + sz = DRAM_64MB; + else + sz = DRAM_128MB; + } + } + + /* Final initialization, with DDR calibration */ + mc_ddr_init(param->memc, ¶m->cfgs[sz], param->dq_dly, + param->dqs_dly, param->mc_reset, bw); + + /* Return actual DDR configuration */ + param->memsize = dram_size[sz]; + param->bus_width = bw; +} + +void ddr2_init(struct mc_ddr_init_param *param) +{ + enum mc_dram_size sz; + u32 bw = 0; + + /* First initialization, determine bus width */ + mc_ddr_init(param->memc, ¶m->cfgs[DRAM_32MB], param->dq_dly, + param->dqs_dly, param->mc_reset, IND_SDRAM_WIDTH_16BIT); + + /* Test bus width */ + dram_test_write(0, DDR_BW_TEST_PAT); + if (dram_test_read(0) == DDR_BW_TEST_PAT) + bw = IND_SDRAM_WIDTH_16BIT; + else + bw = IND_SDRAM_WIDTH_8BIT; + + /* Second initialization, determine DDR capacity */ + mc_ddr_init(param->memc, ¶m->cfgs[DRAM_256MB], param->dq_dly, + param->dqs_dly, param->mc_reset, bw); + + if (bw == IND_SDRAM_WIDTH_16BIT) { + if (dram_addr_test_bit(10)) { + sz = DRAM_32MB; + } else { + if (dram_addr_test_bit(24)) { + if (dram_addr_test_bit(27)) + sz = DRAM_64MB; + else + sz = DRAM_128MB; + } else { + sz = DRAM_256MB; + } + } + } else { + if (dram_addr_test_bit(23)) { + sz = DRAM_32MB; + } else { + if (dram_addr_test_bit(24)) { + if (dram_addr_test_bit(27)) + sz = DRAM_64MB; + else + sz = DRAM_128MB; + } else { + sz = DRAM_256MB; + } + } + } + + /* Final initialization, with DDR calibration */ + mc_ddr_init(param->memc, ¶m->cfgs[sz], param->dq_dly, + param->dqs_dly, param->mc_reset, bw); + + /* Return actual DDR configuration */ + param->memsize = dram_size[sz]; + param->bus_width = bw; +} + +static void mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0, + u32 cfg1) +{ + mc_reset(1); + __udelay(200); + mc_reset(0); + + writel(cfg0, memc + MEMCTL_SDRAM_CFG0_REG); + writel(cfg1, memc + MEMCTL_SDRAM_CFG1_REG); + + while (!(readl(memc + MEMCTL_SDRAM_CFG1_REG) & SDRAM_INIT_DONE)) + ; + + clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M, + 1 << SR_TAR_CNT_S); + + setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN); +} + +void sdr_init(struct mc_ddr_init_param *param) +{ + enum mc_dram_size sz; + u32 cfg1; + + cfg1 = param->sdr_cfg1 | SDRAM_INIT_START; + cfg1 &= ~(NUMCOLS_M | NUMROWS_M); + + /* First initialization, determine SDR capacity */ + mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0, + cfg1 | sdr_size_cfg1[DRAM_64MB]); + + if (dram_addr_test_bit(9)) { + sz = DRAM_8MB; + } else { + if (dram_addr_test_bit(10)) { + if (dram_addr_test_bit(23)) + sz = DRAM_16MB; + else + sz = DRAM_32MB; + } else { + sz = DRAM_64MB; + } + } + + /* Final initialization */ + mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0, + cfg1 | sdr_size_cfg1[sz]); + + /* Return actual DDR configuration */ + param->memsize = dram_size[sz]; +} diff --git a/arch/mips/mach-mtmips/include/mach/ddr.h b/arch/mips/mach-mtmips/include/mach/ddr.h new file mode 100644 index 00000000000..15ff66ace6a --- /dev/null +++ b/arch/mips/mach-mtmips/include/mach/ddr.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _MTMIPS_DDR_H_ +#define _MTMIPS_DDR_H_ + +#include <linux/io.h> +#include <linux/types.h> + +enum mc_dram_size { + DRAM_8MB, + DRAM_16MB, + DRAM_32MB, + DRAM_64MB, + DRAM_128MB, + DRAM_256MB, + + __DRAM_SZ_MAX +}; + +struct mc_ddr_cfg { + u32 cfg0; + u32 cfg1; + u32 cfg2; + u32 cfg3; + u32 cfg4; +}; + +typedef void (*mc_reset_t)(int assert); + +struct mc_ddr_init_param { + void __iomem *memc; + + u32 sdr_cfg0; + u32 sdr_cfg1; + + u32 dq_dly; + u32 dqs_dly; + + const struct mc_ddr_cfg *cfgs; + mc_reset_t mc_reset; + + u32 memsize; + u32 bus_width; +}; + +void sdr_init(struct mc_ddr_init_param *param); +void ddr1_init(struct mc_ddr_init_param *param); +void ddr2_init(struct mc_ddr_init_param *param); +void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw); + +#endif /* _MTMIPS_DDR_H_ */ diff --git a/arch/mips/mach-mtmips/include/mach/mc.h b/arch/mips/mach-mtmips/include/mach/mc.h new file mode 100644 index 00000000000..d7d623a63bc --- /dev/null +++ b/arch/mips/mach-mtmips/include/mach/mc.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _MTMIPS_MC_H_ +#define _MTMIPS_MC_H_ + +#define MEMCTL_SDRAM_CFG0_REG 0x00 +#define DIS_CLK_GT 0x80000000 +#define CLK_SLEW_S 29 +#define CLK_SLEW_M 0x60000000 +#define TWR 0x10000000 +#define TMRD_S 24 +#define TMRD_M 0xf000000 +#define TRFC_S 20 +#define TRFC_M 0xf00000 +#define TCAS_S 16 +#define TCAS_M 0x30000 +#define TRAS_S 12 +#define TRAS_M 0xf000 +#define TRCD_S 8 +#define TRCD_M 0x300 +#define TRC_S 4 +#define TRC_M 0xf0 +#define TRP_S 0 +#define TRP_M 0x03 + +#define MEMCTL_SDRAM_CFG1_REG 0x04 +#define SDRAM_INIT_START 0x80000000 +#define SDRAM_INIT_DONE 0x40000000 +#define RBC_MAPPING 0x20000000 +#define PWR_DOWN_EN 0x10000000 +#define PWR_DOWN_MODE 0x8000000 +#define SDRAM_WIDTH 0x1000000 +#define NUMCOLS_S 20 +#define NUMCOLS_M 0x300000 +#define NUMROWS_S 16 +#define NUMROWS_M 0x30000 +#define TREFR_S 0 +#define TREFR_M 0xffff + +#define MEMCTL_DDR_SELF_REFRESH_REG 0x10 +#define ODT_SRC_SEL_S 24 +#define ODT_SRC_SEL_M 0xf000000 +#define ODT_OFF_DLY_S 20 +#define ODT_OFF_DLY_M 0xf00000 +#define ODT_ON_DLY_S 16 +#define ODT_ON_DLY_M 0xf0000 +#define SR_AUTO_EN 0x10 +#define SRACK_B 0x02 +#define SRREQ_B 0x01 + +#define MEMCTL_PWR_SAVE_CNT_REG 0x14 +#define PD_CNT_S 24 +#define PD_CNT_M 0xff000000 +#define SR_TAR_CNT_S 0 +#define SR_TAR_CNT_M 0xffffff + +#define MEMCTL_DLL_DBG_REG 0x20 +#define TDC_STABLE_S 12 +#define TDC_STABLE_M 0x3f000 +#define MST_DLY_SEL_S 4 +#define MST_DLY_SEL_M 0xff0 +#define CURR_STATE_S 1 +#define CURR_STATE_M 0x06 +#define ADLL_LOCK_DONE 0x01 + +#define MEMCTL_DDR_CFG0_REG 0x40 +#define T_RRD_S 28 +#define T_RRD_M 0xf0000000 +#define T_RAS_S 23 +#define T_RAS_M 0xf800000 +#define T_RP_S 19 +#define T_RP_M 0x780000 +#define T_RFC_S 13 +#define T_RFC_M 0x7e000 +#define T_REFI_S 0 +#define T_REFI_M 0x1fff + +#define MEMCTL_DDR_CFG1_REG 0x44 +#define T_WTR_S 28 +#define T_WTR_M 0xf0000000 +#define T_RTP_S 24 +#define T_RTP_M 0xf000000 +#define USER_DATA_WIDTH 0x200000 +#define IND_SDRAM_SIZE_S 18 +#define IND_SDRAM_SIZE_M 0x1c0000 +#define IND_SDRAM_SIZE_8MB 1 +#define IND_SDRAM_SIZE_16MB 2 +#define IND_SDRAM_SIZE_32MB 3 +#define IND_SDRAM_SIZE_64MB 4 +#define IND_SDRAM_SIZE_128MB 5 +#define IND_SDRAM_SIZE_256MB 6 +#define IND_SDRAM_WIDTH_S 16 +#define IND_SDRAM_WIDTH_M 0x30000 +#define IND_SDRAM_WIDTH_8BIT 1 +#define IND_SDRAM_WIDTH_16BIT 2 +#define EXT_BANK_S 14 +#define EXT_BANK_M 0xc000 +#define TOTAL_SDRAM_WIDTH_S 12 +#define TOTAL_SDRAM_WIDTH_M 0x3000 +#define T_WR_S 8 +#define T_WR_M 0xf00 +#define T_MRD_S 4 +#define T_MRD_M 0xf0 +#define T_RCD_S 0 +#define T_RCD_M 0x0f + +#define MEMCTL_DDR_CFG2_REG 0x48 +#define REGE 0x80000000 +#define DDR2_MODE 0x40000000 +#define DQS0_GATING_WINDOW_S 28 +#define DQS0_GATING_WINDOW_M 0x30000000 +#define DQS1_GATING_WINDOW_S 26 +#define DQS1_GATING_WINDOW_M 0xc000000 +#define PD 0x1000 +#define WR_S 9 +#define WR_M 0xe00 +#define DLLRESET 0x100 +#define TESTMODE 0x80 +#define CAS_LATENCY_S 4 +#define CAS_LATENCY_M 0x70 +#define BURST_TYPE 0x08 +#define BURST_LENGTH_S 0 +#define BURST_LENGTH_M 0x07 + +#define MEMCTL_DDR_CFG3_REG 0x4c +#define Q_OFF 0x1000 +#define RDOS 0x800 +#define DIS_DIFF_DQS 0x400 +#define OCD_S 7 +#define OCD_M 0x380 +#define RTT1 0x40 +#define ADDITIVE_LATENCY_S 3 +#define ADDITIVE_LATENCY_M 0x38 +#define RTT0 0x04 +#define DS 0x02 +#define DLL 0x01 + +#define MEMCTL_DDR_CFG4_REG 0x50 +#define FAW_S 0 +#define FAW_M 0x0f + +#define MEMCTL_DDR_DQ_DLY_REG 0x60 +#define DQ1_DELAY_SEL_S 24 +#define DQ1_DELAY_SEL_M 0xff000000 +#define DQ0_DELAY_SEL_S 16 +#define DQ0_DELAY_SEL_M 0xff0000 +#define DQ1_DELAY_COARSE_TUNING_S 12 +#define DQ1_DELAY_COARSE_TUNING_M 0xf000 +#define DQ1_DELAY_FINE_TUNING_S 8 +#define DQ1_DELAY_FINE_TUNING_M 0xf00 +#define DQ0_DELAY_COARSE_TUNING_S 4 +#define DQ0_DELAY_COARSE_TUNING_M 0xf0 +#define DQ0_DELAY_FINE_TUNING_S 0 +#define DQ0_DELAY_FINE_TUNING_M 0x0f + +#define MEMCTL_DDR_DQS_DLY_REG 0x64 +#define DQS1_DELAY_SEL_S 24 +#define DQS1_DELAY_SEL_M 0xff000000 +#define DQS0_DELAY_SEL_S 16 +#define DQS0_DELAY_SEL_M 0xff0000 +#define DQS1_DELAY_COARSE_TUNING_S 12 +#define DQS1_DELAY_COARSE_TUNING_M 0xf000 +#define DQS1_DELAY_FINE_TUNING_S 8 +#define DQS1_DELAY_FINE_TUNING_M 0xf00 +#define DQS0_DELAY_COARSE_TUNING_S 4 +#define DQS0_DELAY_COARSE_TUNING_M 0xf0 +#define DQS0_DELAY_FINE_TUNING_S 0 +#define DQS0_DELAY_FINE_TUNING_M 0x0f + +#define MEMCTL_DDR_DLL_SLV_REG 0x68 +#define DLL_SLV_UPDATE_MODE 0x100 +#define DQS_DLY_SEL_EN 0x80 +#define DQ_DLY_SEL_EN 0x01 + +#endif /* _MTMIPS_MC_H_ */ diff --git a/arch/mips/mach-mtmips/include/mach/mt7620-sysc.h b/arch/mips/mach-mtmips/include/mach/mt7620-sysc.h new file mode 100644 index 00000000000..743ca034c80 --- /dev/null +++ b/arch/mips/mach-mtmips/include/mach/mt7620-sysc.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * + * Definitions of ioctl requests of MT7620 sysc driver + */ + +#ifndef _MT7620_SYSC_H_ +#define _MT7620_SYSC_H_ + +#include <linux/types.h> + +enum mt7620_sysc_requests { + MT7620_SYSC_IOCTL_GET_CLK, + MT7620_SYSC_IOCTL_GET_CHIP_REV, + MT7620_SYSC_IOCTL_SET_GE1_MODE, + MT7620_SYSC_IOCTL_SET_GE2_MODE, + MT7620_SYSC_IOCTL_SET_USB_MODE, + MT7620_SYSC_IOCTL_SET_PCIE_MODE +}; + +struct mt7620_sysc_clks { + u32 cpu_clk; + u32 sys_clk; + u32 xtal_clk; + u32 peri_clk; +}; + +struct mt7620_sysc_chip_rev { + bool bga; + u32 ver : 4; + u32 eco : 4; +}; + +enum mt7620_sysc_ge_mode { + MT7620_SYSC_GE_RGMII, + MT7620_SYSC_GE_MII, + MT7620_SYSC_GE_RMII, + MT7620_SYSC_GE_ESW_PHY, +}; + +enum mt7620_sysc_usb_mode { + MT7620_SYSC_USB_DEVICE_MODE, + MT7620_SYSC_USB_HOST_MODE +}; + +enum mt7620_sysc_pcie_mode { + MT7620_SYSC_PCIE_EP_MODE, + MT7620_SYSC_PCIE_RC_MODE +}; + +#endif /* _MT7620_SYSC_H_ */ diff --git a/arch/mips/mach-mtmips/include/mach/serial.h b/arch/mips/mach-mtmips/include/mach/serial.h new file mode 100644 index 00000000000..bfa246b428b --- /dev/null +++ b/arch/mips/mach-mtmips/include/mach/serial.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _MTMIPS_SERIAL_H_ +#define _MTMIPS_SERIAL_H_ + +void mtmips_spl_serial_init(void); + +#endif /* _MTMIPS_SERIAL_H_ */ diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig new file mode 100644 index 00000000000..398c7c6a948 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/Kconfig @@ -0,0 +1,76 @@ + +if SOC_MT7620 + +config DEBUG_UART_BOARD_INIT + default y + +choice + prompt "Board select" + +config BOARD_MT7620_RFB + bool "MediaTek MT7620 RFB" + help + The reference design of MT7620A (WS2120). The board has 64 MiB DDR2, + 8 MiB SPI-NOR flash, 1 built-in 6 port switch (two GE PHYs and five + FE PHYs,one port can be configured to use either FE PHY or GE PHY), + 1 UART, 1 USB host, 1 SDXC, 1 PCIe socket and JTAG pins. + +config BOARD_MT7620_MT7530_RFB + bool "MediaTek MT7620-MT7530 RFB" + help + The reference design of MT7620DA (MTKC712). The board has 64 MiB + intergrated DDR2 KGD, 16 MiB SPI-NOR flash, an external 5-port giga + switch MT7530 and 1 UART. + +endchoice + +choice + prompt "CPU frequency select" + default CPU_FREQ_580MHZ + +config CPU_FREQ_480MHZ + bool "480MHz" + +config CPU_FREQ_500MHZ + bool "500MHz" + +config CPU_FREQ_520MHZ + bool "520MHz" + +config CPU_FREQ_540MHZ + bool "540MHz" + +config CPU_FREQ_560MHZ + bool "560MHz" + +config CPU_FREQ_580MHZ + bool "580MHz" + +config CPU_FREQ_600MHZ + bool "600MHz" + +config CPU_FREQ_620MHZ + bool "620MHz" + +endchoice + +config CPU_FREQ_MULTI + int + range 0 7 + default 0 if CPU_FREQ_480MHZ + default 1 if CPU_FREQ_500MHZ + default 2 if CPU_FREQ_520MHZ + default 3 if CPU_FREQ_540MHZ + default 4 if CPU_FREQ_560MHZ + default 5 if CPU_FREQ_580MHZ + default 6 if CPU_FREQ_600MHZ + default 7 if CPU_FREQ_620MHZ + +config SYS_CONFIG_NAME + default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + +config SYS_BOARD + string "Board name" + default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + +endif diff --git a/arch/mips/mach-mtmips/mt7620/Makefile b/arch/mips/mach-mtmips/mt7620/Makefile new file mode 100644 index 00000000000..d2d79e3424b --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += lowlevel_init.o +obj-y += init.o +obj-y += dram.o +obj-y += serial.o + +ifndef CONFIG_XPL_BUILD +obj-y += sysc.o +endif diff --git a/arch/mips/mach-mtmips/mt7620/dram.c b/arch/mips/mach-mtmips/mt7620/dram.c new file mode 100644 index 00000000000..0f0e64bf5ea --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/dram.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/addrspace.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <linux/io.h> +#include <mach/ddr.h> +#include <mach/mc.h> +#include "mt7620.h" + +/* SDR parameters */ +#define SDR_CFG0_VAL 0x51B283B3 +#define SDR_CFG1_VAL 0xC00003A9 + +/* DDR2 DQ_DLY */ +#define DDR2_DQ_DLY 0x88888888 + +/* DDR2 DQS_DLY */ +#define DDR2_DQS_DLY 0x88888888 + +static const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = { + [DRAM_8MB] = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_16MB] = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_32MB] = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_64MB] = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 }, +}; + +static const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = { + [DRAM_8MB] = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_16MB] = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_32MB] = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_64MB] = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 }, +}; + +static const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = { + [DRAM_32MB] = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000416, 0x0000000A }, + [DRAM_64MB] = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000416, 0x0000000A }, + [DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000416, 0x0000000A }, + [DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000416, 0x0000000A }, +}; + +static const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = { + [DRAM_32MB] = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000416, 0x00000006 }, + [DRAM_64MB] = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000416, 0x00000008 }, + [DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000416, 0x00000008 }, + [DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000416, 0x00000008 }, +}; + +static void mt7620_memc_reset(int assert) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + if (assert) + setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); + else + clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); +} + +void mt7620_dram_init(void) +{ + void __iomem *sysc; + bool lspd = false; + int ddr_type, aux; + struct mc_ddr_init_param param; + + sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + ddr_type = (readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE_M) + >> DRAM_TYPE_S; + aux = readl(sysc + SYSCTL_CPLL_CFG1_REG) & + (CPU_CLK_AUX1 | CPU_CLK_AUX0); + + if (aux == CPU_CLK_AUX1 || aux == CPU_CLK_AUX0) + lspd = true; + + mt7620_memc_reset(1); + __udelay(200); + + param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE); + param.dq_dly = DDR2_DQ_DLY; + param.dqs_dly = DDR2_DQS_DLY; + param.mc_reset = mt7620_memc_reset; + param.memsize = 0; + param.bus_width = 0; + + if (ddr_type == DRAM_DDR1) { + if (lspd) + param.cfgs = ddr1_cfgs_160mhz; + else + param.cfgs = ddr1_cfgs_200mhz; + + ddr1_init(¶m); + } else if (ddr_type == DRAM_DDR2) { + if (lspd) + param.cfgs = ddr2_cfgs_160mhz; + else + param.cfgs = ddr2_cfgs_200mhz; + + ddr2_init(¶m); + } else { + param.sdr_cfg0 = SDR_CFG0_VAL; + param.sdr_cfg1 = SDR_CFG1_VAL; + + sdr_init(¶m); + } +} diff --git a/arch/mips/mach-mtmips/mt7620/init.c b/arch/mips/mach-mtmips/mt7620/init.c new file mode 100644 index 00000000000..93abf9228d6 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/init.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <config.h> +#include <asm/global_data.h> +#include <linux/io.h> +#include "mt7620.h" + +DECLARE_GLOBAL_DATA_PTR; + +static const char * const dram_type[] = { + "SDRAM", "DDR", "DDR2", "SDRAM" +}; + +static const char * const boot_mode[(CHIP_MODE_M >> CHIP_MODE_S) + 1] = { + [1] = "NAND 4-cycles 2KB-page", + [2] = "SPI-NOR 3-Byte Addr", + [3] = "SPI-NOR 4-Byte Addr", + [10] = "NAND 4-cycles 512B-page", + [11] = "NAND 5-cycles 2KB-page", + [12] = "NAND 3-cycles 512B-page", +}; + +static void cpu_pll_init(void) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + u32 pllmul = CONFIG_CPU_FREQ_MULTI; + + /* Make sure the pll multiplier is valid */ + if (pllmul > 7) + pllmul = 7; + + /* Set init CPU clock to 480MHz */ + clrsetbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPU_CLK_AUX1, CPU_CLK_AUX0); + + /* Enable software control of CPU PLL */ + setbits_32(sysc + SYSCTL_CPLL_CFG0_REG, CPLL_SW_CFG); + + /* CPU PLL power down */ + setbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPLL_PD); + + /* PLL configuration */ + clrsetbits_32(sysc + SYSCTL_CPLL_CFG0_REG, PLL_MULT_RATIO_M | + PLL_DIV_RATIO_M | SSC_UP_BOUND_M | SSC_EN, + (pllmul << PLL_MULT_RATIO_S) | SSC_SWING_M); + + /* CPU PLL power up */ + clrbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPLL_PD); + + /* Wait for CPU PLL locked */ + while (!(readl(sysc + SYSCTL_CPLL_CFG1_REG) & CPLL_LD)) + ; + + /* Set final CPU clock source */ + clrbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPU_CLK_AUX1 | CPU_CLK_AUX0); + + /* Adjust CPU clock */ + clrsetbits_32(sysc + SYSCTL_CPU_SYS_CLKCFG_REG, + CPU_FDIV_M | CPU_FFRAC_M, + (1 << CPU_FDIV_S) | (1 << CPU_FFRAC_S)); +} + +void mt7620_init(void) +{ + u32 cpu_clk; + + cpu_pll_init(); + + /* + * Set timer freq, which will be used during DRAM initialization + * Note that this function is using a temporary gd which will be + * destroyed after leaving this function. + */ + mt7620_get_clks(&cpu_clk, NULL, NULL); + gd->arch.timer_freq = cpu_clk / 2; + + mt7620_dram_init(); +} + +void mt7620_get_clks(u32 *cpu_clk, u32 *sys_clk, u32 *xtal_clk) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + u32 val, multi, div, fdiv, ffrac, dram_type, sys_div; + u32 cpu_freq, xtal_freq; + + static const u32 div_ratio_table[] = {2, 3, 4, 8}; + + val = readl(sysc + SYSCTL_SYSCFG0_REG); + + dram_type = (val & DRAM_TYPE_M) >> DRAM_TYPE_S; + + if (val & XTAL_FREQ_SEL) + xtal_freq = 40000000; + else + xtal_freq = 20000000; + + val = readl(sysc + SYSCTL_CPLL_CFG1_REG); + if (val & CPU_CLK_AUX1) { + cpu_freq = xtal_freq; + } else if (val & CPU_CLK_AUX0) { + cpu_freq = 480000000; + } else { + val = readl(sysc + SYSCTL_CPLL_CFG0_REG); + if (val & CPLL_SW_CFG) { + multi = (val & PLL_MULT_RATIO_M) >> PLL_MULT_RATIO_S; + div = (val & PLL_DIV_RATIO_M) >> PLL_DIV_RATIO_S; + cpu_freq = (multi + 24) * 40000000 / + div_ratio_table[div]; + } else { + cpu_freq = 600000000; + } + } + + val = readl(sysc + SYSCTL_CUR_CLK_STS_REG); + ffrac = (val & CUR_CPU_FFRAC_M) >> CUR_CPU_FFRAC_S; + fdiv = (val & CUR_CPU_FDIV_M) >> CUR_CPU_FDIV_S; + cpu_freq = (cpu_freq * ffrac) / fdiv; + + switch (dram_type) { + case DRAM_SDRAM_E1: + sys_div = 4; + break; + case DRAM_DDR1: + case DRAM_DDR2: + sys_div = 3; + break; + case DRAM_SDRAM: + sys_div = 5; + break; + } + + if (cpu_clk) + *cpu_clk = cpu_freq; + + if (sys_clk) + *sys_clk = cpu_freq / sys_div; + + if (xtal_clk) + *xtal_clk = xtal_freq; +} + +int print_cpuinfo(void) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + u32 cpu_clk, bus_clk, xtal_clk; + u32 val, ver, eco, pkg, dram, chipmode; + const char *bootdev; + + val = readl(sysc + SYSCTL_CHIP_REV_ID_REG); + ver = (val & VER_M) >> VER_S; + eco = (val & ECO_M) >> ECO_S; + pkg = !!(val & PKG_ID); + + val = readl(sysc + SYSCTL_SYSCFG0_REG); + dram = (val & DRAM_TYPE_M) >> DRAM_TYPE_S; + chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S; + + bootdev = boot_mode[chipmode]; + if (!bootdev) + bootdev = "Unsupported boot mode"; + + printf("CPU: MediaTek MT7620%c ver:%u eco:%u\n", + pkg ? 'A' : 'N', ver, eco); + + printf("Boot: %s, %s\n", dram_type[dram], bootdev); + + mt7620_get_clks(&cpu_clk, &bus_clk, &xtal_clk); + + /* Set final timer frequency */ + gd->arch.timer_freq = cpu_clk / 2; + + printf("Clock: CPU: %uMHz, Bus: %uMHz, XTAL: %uMHz\n", + cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000); + + return 0; +} + +ulong notrace get_tbclk(void) +{ + return gd->arch.timer_freq; +} + +void _machine_restart(void) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + while (1) + writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG); +} diff --git a/arch/mips/mach-mtmips/mt7620/lowlevel_init.S b/arch/mips/mach-mtmips/mt7620/lowlevel_init.S new file mode 100644 index 00000000000..399174620d5 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/lowlevel_init.S @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <config.h> +#include <asm-offsets.h> +#include <asm/regdef.h> +#include <asm/asm.h> + + .set noreorder + +NESTED(lowlevel_init, 0, ra) + /* Save ra and do real lowlevel initialization */ + move s0, ra + + /* + * Use SRAM from 802.11n MAC/BBP, 16KiB (0x10184000 ~ 0x10187fff) + * NOTE: non-word operations may fail in this SRAM. + * Use it as stack only for CPU/DRAM init which only has word operations. + */ + PTR_LI sp, 0xb0187f00 + + /* We still need a temporary gd for udelay */ + PTR_SUBU \ + sp, sp, GD_SIZE # reserve space for gd + li t0, -16 + and sp, sp, t0 # force 16 byte alignment + move k0, sp # save gd pointer + + move fp, sp + + /* Clear gd */ + move t0, k0 +1: + PTR_S zero, 0(t0) + PTR_ADDIU t0, PTRSIZE + blt t0, t1, 1b + nop + + /* Do CPU & DRAM initialization */ + PTR_LA t9, mt7620_init + jalr t9 + nop + + /* Restore ra */ + move ra, s0 + + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-mtmips/mt7620/mt7620.h b/arch/mips/mach-mtmips/mt7620/mt7620.h new file mode 100644 index 00000000000..dd5e6d00e5a --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/mt7620.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _MT7620_H_ +#define _MT7620_H_ + +#include <linux/bitops.h> + +#define SYSCTL_BASE 0x10000000 +#define SYSCTL_SIZE 0x100 +#define MEMCTL_BASE 0x10000300 +#define MEMCTL_SIZE 0x100 +#define UARTFULL_BASE 0x10000500 +#define UARTFULL_SIZE 0x100 +#define UARTLITE_BASE 0x10000c00 +#define UARTLITE_SIZE 0x100 + +#define SYSCTL_CHIP_REV_ID_REG 0x0c +#define PKG_ID BIT(16) +#define PKG_ID_A 1 +#define PKG_ID_N 0 +#define VER_S 8 +#define VER_M GENMASK(11, 8) +#define ECO_S 0 +#define ECO_M GENMASK(3, 0) + +#define SYSCTL_SYSCFG0_REG 0x10 +#define XTAL_FREQ_SEL BIT(6) +#define XTAL_40MHZ 1 +#define XTAL_20MHZ 0 +#define DRAM_TYPE_S 4 +#define DRAM_TYPE_M GENMASK(5, 4) +#define DRAM_SDRAM 3 +#define DRAM_DDR2 2 +#define DRAM_DDR1 1 +#define DRAM_SDRAM_E1 0 +#define CHIP_MODE_S 0 +#define CHIP_MODE_M GENMASK(3, 0) + +#define SYSCTL_SYSCFG1_REG 0x14 +#define GE2_MODE_S 14 +#define GE2_MODE_M GENMASK(15, 14) +#define GE1_MODE_S 12 +#define GE1_MODE_M GENMASK(13, 12) +#define USB0_HOST_MODE BIT(10) +#define PCIE_RC_MODE BIT(8) +#define GE_MODE_M GENMASK(1, 0) + +#define SYSCTL_RSTCTL_REG 0x34 +#define MC_RST BIT(10) +#define SYS_RST BIT(0) + +#define SYSCTL_CLKCFG0_REG 0x2c +#define PERI_CLK_SEL BIT(4) + +#define SYSCTL_CPU_SYS_CLKCFG_REG 0x3c +#define CPU_OCP_RATIO_S 16 +#define CPU_OCP_RATIO_M GENMASK(19, 16) +#define CPU_FDIV_S 8 +#define CPU_FDIV_M GENMASK(12, 8) +#define CPU_FFRAC_S 0 +#define CPU_FFRAC_M GENMASK(4, 0) + +#define SYSCTL_CUR_CLK_STS_REG 0x44 +#define CUR_CPU_OCP_RATIO_S 16 +#define CUR_CPU_OCP_RATIO_M GENMASK(19, 16) +#define CUR_CPU_FDIV_S 8 +#define CUR_CPU_FDIV_M GENMASK(12, 8) +#define CUR_CPU_FFRAC_S 0 +#define CUR_CPU_FFRAC_M GENMASK(4, 0) + +#define SYSCTL_CPLL_CFG0_REG 0x54 +#define CPLL_SW_CFG BIT(31) +#define PLL_MULT_RATIO_S 16 +#define PLL_MULT_RATIO_M GENMASK(18, 16) +#define PLL_DIV_RATIO_S 10 +#define PLL_DIV_RATIO_M GENMASK(11, 10) +#define SSC_UP_BOUND_S 8 +#define SSC_UP_BOUND_M GENMASK(9, 8) +#define SSC_EN BIT(7) +#define SSC_SWING_S 4 +#define SSC_SWING_M GENMASK(6, 4) + +#define SYSCTL_CPLL_CFG1_REG 0x58 +#define CPLL_PD BIT(26) +#define CPU_CLK_AUX1 BIT(25) +#define CPU_CLK_AUX0 BIT(24) +#define CPLL_LD BIT(23) + +#define SYSCTL_GPIOMODE_REG 0x60 +#define UARTL_GPIO_MODE BIT(5) +#define UARTF_SHARE_MODE_S 2 +#define UARTF_SHARE_MODE_M GENMASK(4, 2) +#define UARTF_MODE_UARTF_GPIO 5 + +void mt7620_dram_init(void); +void mt7620_get_clks(u32 *cpu_clk, u32 *sys_clk, u32 *xtal_clk); + +#endif /* _MT7620_H_ */ diff --git a/arch/mips/mach-mtmips/mt7620/serial.c b/arch/mips/mach-mtmips/mt7620/serial.c new file mode 100644 index 00000000000..35544b8537e --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/serial.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/io.h> +#include <asm/addrspace.h> +#include "mt7620.h" + +void board_debug_uart_init(void) +{ + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + +#if CONFIG_DEBUG_UART_BASE == 0xb0000500 /* KSEG1ADDR(UARTFULL_BASE) */ + clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, + UARTF_MODE_UARTF_GPIO << UARTF_SHARE_MODE_S); +#else + clrbits_32(base + SYSCTL_GPIOMODE_REG, UARTL_GPIO_MODE); +#endif +} + +void mtmips_spl_serial_init(void) +{ +#ifdef CONFIG_SPL_SERIAL + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + +#if CONFIG_CONS_INDEX == 1 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UARTL_GPIO_MODE); +#elif CONFIG_CONS_INDEX == 2 + clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M, + UARTF_MODE_UARTF_GPIO << UARTF_SHARE_MODE_S); +#endif +#endif /* CONFIG_SPL_SERIAL */ +} diff --git a/arch/mips/mach-mtmips/mt7620/sysc.c b/arch/mips/mach-mtmips/mt7620/sysc.c new file mode 100644 index 00000000000..296a9be07c5 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7620/sysc.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + * + * Misc driver for manipulating System control registers + */ + +#include <dm.h> +#include <misc.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <dm/device_compat.h> +#include <mach/mt7620-sysc.h> +#include "mt7620.h" + +struct mt7620_sysc_priv { + void __iomem *base; +}; + +static int mt7620_sysc_read(struct udevice *dev, int offset, void *buf, + int size) +{ + struct mt7620_sysc_priv *priv = dev_get_priv(dev); + u32 val; + + if (offset % sizeof(u32) || size != sizeof(u32) || + offset >= SYSCTL_SIZE) + return -EINVAL; + + val = readl(priv->base + offset); + + if (buf) + *(u32 *)buf = val; + + return 0; +} + +static int mt7620_sysc_write(struct udevice *dev, int offset, const void *buf, + int size) +{ + struct mt7620_sysc_priv *priv = dev_get_priv(dev); + u32 val; + + if (offset % sizeof(u32) || size != sizeof(u32) || + offset >= SYSCTL_SIZE || !buf) + return -EINVAL; + + val = *(u32 *)buf; + writel(val, priv->base + offset); + + return 0; +} + +static int mt7620_sysc_ioctl(struct udevice *dev, unsigned long request, + void *buf) +{ + struct mt7620_sysc_priv *priv = dev_get_priv(dev); + struct mt7620_sysc_chip_rev *chip_rev; + struct mt7620_sysc_clks *clks; + u32 val, shift; + + if (!buf) + return -EINVAL; + + switch (request) { + case MT7620_SYSC_IOCTL_GET_CLK: + clks = buf; + mt7620_get_clks(&clks->cpu_clk, &clks->sys_clk, + &clks->xtal_clk); + + val = readl(priv->base + SYSCTL_CLKCFG0_REG); + if (val & PERI_CLK_SEL) + clks->peri_clk = clks->xtal_clk; + else + clks->peri_clk = 40000000; + + return 0; + + case MT7620_SYSC_IOCTL_GET_CHIP_REV: + chip_rev = buf; + + val = readl(priv->base + SYSCTL_CHIP_REV_ID_REG); + + chip_rev->bga = !!(val & PKG_ID); + chip_rev->ver = (val & VER_M) >> VER_S; + chip_rev->eco = (val & ECO_M) >> ECO_S; + + return 0; + + case MT7620_SYSC_IOCTL_SET_GE1_MODE: + case MT7620_SYSC_IOCTL_SET_GE2_MODE: + val = *(u32 *)buf; + + if (val > MT7620_SYSC_GE_ESW_PHY) + return -EINVAL; + + if (request == MT7620_SYSC_IOCTL_SET_GE1_MODE) + shift = GE1_MODE_S; + else + shift = GE2_MODE_S; + + clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, + GE_MODE_M << shift, val << shift); + + return 0; + + case MT7620_SYSC_IOCTL_SET_USB_MODE: + val = *(u32 *)buf; + + if (val == MT7620_SYSC_USB_DEVICE_MODE) + val = 0; + else if (val == MT7620_SYSC_USB_HOST_MODE) + val = USB0_HOST_MODE; + + clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, + USB0_HOST_MODE, val); + + return 0; + + case MT7620_SYSC_IOCTL_SET_PCIE_MODE: + val = *(u32 *)buf; + + if (val == MT7620_SYSC_PCIE_EP_MODE) + val = 0; + else if (val == MT7620_SYSC_PCIE_RC_MODE) + val = PCIE_RC_MODE; + + clrsetbits_32(priv->base + SYSCTL_SYSCFG1_REG, + PCIE_RC_MODE, val); + + return 0; + + default: + return -EINVAL; + } +} + +static int mt7620_sysc_probe(struct udevice *dev) +{ + struct mt7620_sysc_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr_index(dev, 0); + if (!priv->base) { + dev_err(dev, "failed to map sysc registers\n"); + return -EINVAL; + } + + return 0; +} + +static struct misc_ops mt7620_sysc_ops = { + .read = mt7620_sysc_read, + .write = mt7620_sysc_write, + .ioctl = mt7620_sysc_ioctl, +}; + +static const struct udevice_id mt7620_sysc_ids[] = { + { .compatible = "mediatek,mt7620-sysc" }, + { } +}; + +U_BOOT_DRIVER(mt7620_sysc) = { + .name = "mt7620_sysc", + .id = UCLASS_MISC, + .of_match = mt7620_sysc_ids, + .probe = mt7620_sysc_probe, + .ops = &mt7620_sysc_ops, + .priv_auto = sizeof(struct mt7620_sysc_priv), + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig b/arch/mips/mach-mtmips/mt7621/Kconfig new file mode 100644 index 00000000000..8fe6e0a2d9a --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/Kconfig @@ -0,0 +1,114 @@ + +if SOC_MT7621 + +menu "CPU & DDR configuration" + +config MT7621_CPU_FREQ + int "CPU Frequency (MHz)" + range 400 1200 + default 880 + +choice + prompt "DRAM Frequency" + default MT7621_DRAM_FREQ_1200 + +config MT7621_DRAM_FREQ_400 + bool "400MHz" + +config MT7621_DRAM_FREQ_800 + bool "800MHz" + +config MT7621_DRAM_FREQ_1066 + bool "1066MHz" + +config MT7621_DRAM_FREQ_1200 + bool "1200MHz" + +endchoice + +choice + prompt "DDR2 timing parameters" + default MT7621_DRAM_DDR2_1024M + +config MT7621_DRAM_DDR2_512M + bool "64MB" + +config MT7621_DRAM_DDR2_1024M + bool "128MB" + +config MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ + bool "W9751G6KB_A02 @ 1066MHz (64MB)" + +config MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ + bool "W971GG6KB25 @ 800MHz (128MB)" + +config MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ + bool "W971GG6KB18 @ 1066MHz (128MB)" + +endchoice + +choice + prompt "DDR3 timing parameters" + default MT7621_DRAM_DDR3_2048M + +config MT7621_DRAM_DDR3_1024M + bool "128MB" + +config MT7621_DRAM_DDR3_1024M_KGD + bool "128MB KGD (MT7621DA)" + +config MT7621_DRAM_DDR3_2048M + bool "256MB" + +config MT7621_DRAM_DDR3_4096M + bool "512MB" + +endchoice + +endmenu + +config DEBUG_UART_BOARD_INIT + default y + +config MT7621_BOOT_FROM_NAND + bool "Boot from NAND" + help + Select this if u-boot will boot from NAND flash. When booting from + NAND, SPL will be loaded by bootrom directly and no TPL is needed. + +choice + prompt "Board select" + +config BOARD_MT7621_RFB + bool "MediaTek MT7621 RFB (SPI-NOR)" + help + The reference design of MT7621A (WS3010) booting from SPI-NOR flash. + The board can be configured with DDR2 (64MiB~256MiB) or DDR3 + (128MiB~512MiB). The board has 16 MiB SPI-NOR flash, built-in MT7530 + GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 1 SDXC, 3 PCIe + sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out), + JTAG pins and expansion GPIO pins. + +config BOARD_MT7621_NAND_RFB + bool "MediaTek MT7621 RFB (NAND)" + help + The reference design of MT7621A (WS3010) booting from NAND flash. + The board can be configured with DDR2 (64MiB~256MiB) or DDR3 + (128MiB~512MiB). The board has 128 MiB parallel NAND flash, built-in + MT7530 GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 3 PCIe + sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out), + JTAG pins and expansion GPIO pins. + +endchoice + +config SYS_CONFIG_NAME + default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB + +config SYS_BOARD + string "Board name" + default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB + +config SYS_VENDOR + default "mediatek" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB + +endif diff --git a/arch/mips/mach-mtmips/mt7621/Makefile b/arch/mips/mach-mtmips/mt7621/Makefile new file mode 100644 index 00000000000..f48083e3559 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += serial.o + +ifeq ($(CONFIG_XPL_BUILD),y) +ifeq ($(CONFIG_TPL_BUILD),y) +obj-y += tpl/ +else +obj-y += spl/ +endif + +obj-y += sram_init.o +endif diff --git a/arch/mips/mach-mtmips/mt7621/init.c b/arch/mips/mach-mtmips/mt7621/init.c new file mode 100644 index 00000000000..d21848ad23b --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/init.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <clk.h> +#include <dm.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt7621-clk.h> +#include <asm/global_data.h> +#include <linux/io.h> +#include <linux/bitfield.h> +#include "mt7621.h" + +DECLARE_GLOBAL_DATA_PTR; + +static const char *const boot_mode[(CHIP_MODE_M >> CHIP_MODE_S) + 1] = { + [1] = "NAND 2K+64", + [2] = "SPI-NOR 3-Byte Addr", + [3] = "SPI-NOR 4-Byte Addr", + [10] = "NAND 2K+128", + [11] = "NAND 4K+128", + [12] = "NAND 4K+256", +}; + +int print_cpuinfo(void) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + u32 val, ver, eco, pkg, core, dram, chipmode; + u32 cpu_clk, ddr_clk, bus_clk, xtal_clk; + struct udevice *clkdev; + const char *bootdev; + struct clk clk; + int ret; + + val = readl(sysc + SYSCTL_CHIP_REV_ID_REG); + ver = FIELD_GET(VER_ID_M, val); + eco = FIELD_GET(ECO_ID_M, val); + pkg = FIELD_GET(PKG_ID, val); + core = FIELD_GET(CPU_ID, val); + + val = readl(sysc + SYSCTL_SYSCFG0_REG); + dram = FIELD_GET(DRAM_TYPE, val); + chipmode = FIELD_GET(CHIP_MODE_M, val); + + bootdev = boot_mode[chipmode]; + if (!bootdev) + bootdev = "Unsupported boot mode"; + + printf("CPU: MediaTek MT7621%c ver %u, eco %u\n", + core ? (pkg ? 'A' : 'N') : 'S', ver, eco); + + printf("Boot: DDR%u, %s\n", dram ? 2 : 3, bootdev); + + ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7621_clk), + &clkdev); + if (ret) + return ret; + + clk.dev = clkdev; + + clk.id = MT7621_CLK_CPU; + cpu_clk = clk_get_rate(&clk); + + clk.id = MT7621_CLK_BUS; + bus_clk = clk_get_rate(&clk); + + clk.id = MT7621_CLK_DDR; + ddr_clk = clk_get_rate(&clk); + + clk.id = MT7621_CLK_XTAL; + xtal_clk = clk_get_rate(&clk); + + /* Set final timer frequency */ + if (cpu_clk) + gd->arch.timer_freq = cpu_clk / 2; + + printf("Clock: CPU: %uMHz, DDR: %uMT/s, Bus: %uMHz, XTAL: %uMHz\n", + cpu_clk / 1000000, ddr_clk / 500000, bus_clk / 1000000, + xtal_clk / 1000000); + + return 0; +} + +unsigned long get_xtal_mhz(void) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + u32 bs, xtal_sel; + + bs = readl(sysc + SYSCTL_SYSCFG0_REG); + xtal_sel = FIELD_GET(XTAL_MODE_SEL_M, bs); + + if (xtal_sel <= 2) + return 20; + else if (xtal_sel <= 5) + return 40; + else + return 25; +} + +static void xhci_config_40mhz(void __iomem *usbh) +{ + writel(FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M, 0x20) | + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M, 0x20) | + FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MODE_M, 2) | + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MODE_M, 2) | 0x10, + usbh + SSUSB_MAC_CK_CTRL_REG); + + writel(FIELD_PREP(SSUSB_PLL_PREDIV_PE1D_M, 2) | + FIELD_PREP(SSUSB_PLL_PREDIV_U3_M, 1) | + FIELD_PREP(SSUSB_PLL_FBKDI_M, 4), + usbh + DA_SSUSB_U3PHYA_10_REG); + + writel(FIELD_PREP(SSUSB_PLL_FBKDIV_PE2H_M, 0x18) | + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1D_M, 0x18) | + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1H_M, 0x18) | + FIELD_PREP(SSUSB_PLL_FBKDIV_U3_M, 0x1e), + usbh + DA_SSUSB_PLL_FBKDIV_REG); + + writel(FIELD_PREP(SSUSB_PLL_PCW_NCPO_U3_M, 0x1e400000), + usbh + DA_SSUSB_PLL_PCW_NCPO_REG); + + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE1H_M, 0x25) | + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_U3_M, 0x73), + usbh + DA_SSUSB_PLL_SSC_DELTA1_REG); + + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA_U3_M, 0x71) | + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE2D_M, 0x4a), + usbh + DA_SSUSB_U3PHYA_21_REG); + + writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x140), + usbh + SSUSB_U3PHYA_9_REG); + + writel(FIELD_PREP(SSUSB_SYSPLL_PCW_NCPO_M, 0x11c00000), + usbh + SSUSB_U3PHYA_3_REG); + + writel(FIELD_PREP(SSUSB_PCIE_CLKDRV_AMP_M, 4) | + FIELD_PREP(SSUSB_SYSPLL_FBSEL_M, 1) | + FIELD_PREP(SSUSB_SYSPLL_PREDIV_M, 1), + usbh + SSUSB_U3PHYA_1_REG); + + writel(FIELD_PREP(SSUSB_SYSPLL_FBDIV_M, 0x12) | + SSUSB_SYSPLL_VCO_DIV_SEL | SSUSB_SYSPLL_FPEN | + SSUSB_SYSPLL_MONCK_EN | SSUSB_SYSPLL_VOD_EN, + usbh + SSUSB_U3PHYA_2_REG); + + writel(SSUSB_EQ_CURSEL | FIELD_PREP(SSUSB_RX_DAC_MUX_M, 8) | + FIELD_PREP(SSUSB_PCIE_SIGDET_VTH_M, 1) | + FIELD_PREP(SSUSB_PCIE_SIGDET_LPF_M, 1), + usbh + SSUSB_U3PHYA_11_REG); + + writel(FIELD_PREP(SSUSB_RING_OSC_CNTEND_M, 0x1ff) | + FIELD_PREP(SSUSB_XTAL_OSC_CNTEND_M, 0x7f) | + SSUSB_RING_BYPASS_DET, + usbh + SSUSB_B2_ROSC_0_REG); + + writel(FIELD_PREP(SSUSB_RING_OSC_FRC_RECAL_M, 3) | + SSUSB_RING_OSC_FRC_SEL, + usbh + SSUSB_B2_ROSC_1_REG); +} + +static void xhci_config_25mhz(void __iomem *usbh) +{ + writel(FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M, 0x20) | + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M, 0x20) | + FIELD_PREP(SSUSB_MAC3_SYS_CK_GATE_MODE_M, 2) | + FIELD_PREP(SSUSB_MAC2_SYS_CK_GATE_MODE_M, 2) | 0x10, + usbh + SSUSB_MAC_CK_CTRL_REG); + + writel(FIELD_PREP(SSUSB_PLL_PREDIV_PE1D_M, 2) | + FIELD_PREP(SSUSB_PLL_FBKDI_M, 4), + usbh + DA_SSUSB_U3PHYA_10_REG); + + writel(FIELD_PREP(SSUSB_PLL_FBKDIV_PE2H_M, 0x18) | + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1D_M, 0x18) | + FIELD_PREP(SSUSB_PLL_FBKDIV_PE1H_M, 0x18) | + FIELD_PREP(SSUSB_PLL_FBKDIV_U3_M, 0x19), + usbh + DA_SSUSB_PLL_FBKDIV_REG); + + writel(FIELD_PREP(SSUSB_PLL_PCW_NCPO_U3_M, 0x18000000), + usbh + DA_SSUSB_PLL_PCW_NCPO_REG); + + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE1H_M, 0x25) | + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_U3_M, 0x4a), + usbh + DA_SSUSB_PLL_SSC_DELTA1_REG); + + writel(FIELD_PREP(SSUSB_PLL_SSC_DELTA_U3_M, 0x48) | + FIELD_PREP(SSUSB_PLL_SSC_DELTA1_PE2D_M, 0x4a), + usbh + DA_SSUSB_U3PHYA_21_REG); + + writel(FIELD_PREP(SSUSB_PLL_SSC_PRD_M, 0x190), + usbh + SSUSB_U3PHYA_9_REG); + + writel(FIELD_PREP(SSUSB_SYSPLL_PCW_NCPO_M, 0xe000000), + usbh + SSUSB_U3PHYA_3_REG); + + writel(FIELD_PREP(SSUSB_PCIE_CLKDRV_AMP_M, 4) | + FIELD_PREP(SSUSB_SYSPLL_FBSEL_M, 1), + usbh + SSUSB_U3PHYA_1_REG); + + writel(FIELD_PREP(SSUSB_SYSPLL_FBDIV_M, 0xf) | + SSUSB_SYSPLL_VCO_DIV_SEL | SSUSB_SYSPLL_FPEN | + SSUSB_SYSPLL_MONCK_EN | SSUSB_SYSPLL_VOD_EN, + usbh + SSUSB_U3PHYA_2_REG); + + writel(SSUSB_EQ_CURSEL | FIELD_PREP(SSUSB_RX_DAC_MUX_M, 8) | + FIELD_PREP(SSUSB_PCIE_SIGDET_VTH_M, 1) | + FIELD_PREP(SSUSB_PCIE_SIGDET_LPF_M, 1), + usbh + SSUSB_U3PHYA_11_REG); + + writel(FIELD_PREP(SSUSB_RING_OSC_CNTEND_M, 0x1ff) | + FIELD_PREP(SSUSB_XTAL_OSC_CNTEND_M, 0x7f) | + SSUSB_RING_BYPASS_DET, + usbh + SSUSB_B2_ROSC_0_REG); + + writel(FIELD_PREP(SSUSB_RING_OSC_FRC_RECAL_M, 3) | + SSUSB_RING_OSC_FRC_SEL, + usbh + SSUSB_B2_ROSC_1_REG); +} + +void lowlevel_init(void) +{ + void __iomem *usbh = ioremap_nocache(SSUSB_BASE, SSUSB_SIZE); + u32 xtal = get_xtal_mhz(); + + /* Setup USB xHCI */ + if (xtal == 40) + xhci_config_40mhz(usbh); + else if (xtal == 25) + xhci_config_25mhz(usbh); +} + +ulong notrace get_tbclk(void) +{ + return gd->arch.timer_freq; +} + +void _machine_restart(void) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + while (1) + writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG); +} diff --git a/arch/mips/mach-mtmips/mt7621/mt7621.h b/arch/mips/mach-mtmips/mt7621/mt7621.h new file mode 100644 index 00000000000..916cc993b47 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/mt7621.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _MT7621_H_ +#define _MT7621_H_ + +#define SYSCTL_BASE 0x1e000000 +#define SYSCTL_SIZE 0x100 +#define TIMER_BASE 0x1e000100 +#define TIMER_SIZE 0x100 +#define RBUS_BASE 0x1e000400 +#define RBUS_SIZE 0x100 +#define GPIO_BASE 0x1e000600 +#define GPIO_SIZE 0x100 +#define DMA_CFG_ARB_BASE 0x1e000800 +#define DMA_CFG_ARB_SIZE 0x100 +#define SPI_BASE 0x1e000b00 +#define SPI_SIZE 0x100 +#define UART1_BASE 0x1e000c00 +#define UART1_SIZE 0x100 +#define UART2_BASE 0x1e000d00 +#define UART2_SIZE 0x100 +#define UART3_BASE 0x1e000e00 +#define UART3_SIZE 0x100 +#define NFI_BASE 0x1e003000 +#define NFI_SIZE 0x800 +#define NFI_ECC_BASE 0x1e003800 +#define NFI_ECC_SIZE 0x800 +#define DRAMC_BASE 0x1e005000 +#define DRAMC_SIZE 0x1000 +#define FE_BASE 0x1e100000 +#define FE_SIZE 0xe000 +#define GMAC_BASE 0x1e110000 +#define GMAC_SIZE 0x8000 +#define SSUSB_BASE 0x1e1c0000 +#define SSUSB_SIZE 0x40000 + + /* GIC Base Address */ +#define MIPS_GIC_BASE 0x1fbc0000 + + /* CPC Base Address */ +#define MIPS_CPC_BASE 0x1fbf0000 + + /* Flash Memory-mapped Base Address */ +#define FLASH_MMAP_BASE 0x1fc00000 +#define TPL_INFO_OFFSET 0x40 +#define TPL_INFO_MAGIC 0x31323637 /* Magic "7621" */ + +/* SRAM */ +#define FE_SRAM_BASE1 0x8000 +#define FE_SRAM_BASE2 0xa000 + +/* SYSCTL_BASE */ +#define SYSCTL_CHIP_REV_ID_REG 0x0c +#define CPU_ID 0x20000 +#define PKG_ID 0x10000 +#define VER_ID_S 8 +#define VER_ID_M 0xf00 +#define ECO_ID_S 0 +#define ECO_ID_M 0x0f + +#define SYSCTL_SYSCFG0_REG 0x10 +#define XTAL_MODE_SEL_S 6 +#define XTAL_MODE_SEL_M 0x1c0 +#define DRAM_TYPE 0x10 +#define CHIP_MODE_S 0 +#define CHIP_MODE_M 0x0f + +#define BOOT_SRAM_BASE_REG 0x20 + +#define SYSCTL_CLKCFG0_REG 0x2c +#define CPU_CLK_SEL_S 30 +#define CPU_CLK_SEL_M 0xc0000000 +#define MPLL_CFG_SEL_S 23 +#define MPLL_CFG_SEL_M 0x800000 + +#define SYSCTL_RSTCTL_REG 0x34 +#define MCM_RST 0x04 +#define SYS_RST 0x01 + +#define SYSCTL_CUR_CLK_STS_REG 0x44 +#define CUR_CPU_FDIV_S 8 +#define CUR_CPU_FDIV_M 0x1f00 +#define CUR_CPU_FFRAC_S 0 +#define CUR_CPU_FFRAC_M 0x1f + +#define SYSCTL_GPIOMODE_REG 0x60 +#define UART2_MODE_S 5 +#define UART2_MODE_M 0x60 +#define UART3_MODE_S 3 +#define UART3_MODE_M 0x18 +#define UART1_MODE 0x02 + +/* RBUS_BASE */ +#define RBUS_DYN_CFG0_REG 0x0010 +#define CPU_FDIV_S 8 +#define CPU_FDIV_M 0x1f00 +#define CPU_FFRAC_S 0 +#define CPU_FFRAC_M 0x1f + +/* DMA_CFG_ARB_BASE */ +#define DMA_ROUTE_REG 0x000c + +/* SPI_BASE */ +#define SPI_SPACE_REG 0x003c +#define FS_SLAVE_SEL_S 12 +#define FS_SLAVE_SEL_M 0x70000 +#define FS_CLK_SEL_S 0 +#define FS_CLK_SEL_M 0xfff + +/* FE_BASE */ +#define FE_RST_GLO_REG 0x0004 +#define FE_PSE_RAM 0x04 +#define FE_PSE_MEM_EN 0x02 +#define FE_PSE_RESET 0x01 + +/* SSUSB_BASE */ +#define SSUSB_MAC_CK_CTRL_REG 0x10784 +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_S 16 +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M 0xff0000 +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_S 8 +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M 0xff00 +#define SSUSB_MAC3_SYS_CK_GATE_MODE_S 2 +#define SSUSB_MAC3_SYS_CK_GATE_MODE_M 0x0c +#define SSUSB_MAC2_SYS_CK_GATE_MODE_S 0 +#define SSUSB_MAC2_SYS_CK_GATE_MODE_M 0x03 + +#define SSUSB_B2_ROSC_0_REG 0x10a40 +#define SSUSB_RING_OSC_CNTEND_S 23 +#define SSUSB_RING_OSC_CNTEND_M 0xff800000 +#define SSUSB_XTAL_OSC_CNTEND_S 16 +#define SSUSB_XTAL_OSC_CNTEND_M 0x7f0000 +#define SSUSB_RING_BYPASS_DET 0x01 + +#define SSUSB_B2_ROSC_1_REG 0x10a44 +#define SSUSB_RING_OSC_FRC_RECAL_S 17 +#define SSUSB_RING_OSC_FRC_RECAL_M 0x60000 +#define SSUSB_RING_OSC_FRC_SEL 0x01 + +#define SSUSB_U3PHYA_1_REG 0x10b04 +#define SSUSB_PCIE_CLKDRV_AMP_S 27 +#define SSUSB_PCIE_CLKDRV_AMP_M 0x38000000 +#define SSUSB_SYSPLL_FBSEL_S 2 +#define SSUSB_SYSPLL_FBSEL_M 0x0c +#define SSUSB_SYSPLL_PREDIV_S 0 +#define SSUSB_SYSPLL_PREDIV_M 0x03 + +#define SSUSB_U3PHYA_2_REG 0x10b08 +#define SSUSB_SYSPLL_FBDIV_S 24 +#define SSUSB_SYSPLL_FBDIV_M 0x7f000000 +#define SSUSB_SYSPLL_VCO_DIV_SEL 0x200000 +#define SSUSB_SYSPLL_FPEN 0x2000 +#define SSUSB_SYSPLL_MONCK_EN 0x1000 +#define SSUSB_SYSPLL_VOD_EN 0x200 + +#define SSUSB_U3PHYA_3_REG 0x10b10 +#define SSUSB_SYSPLL_PCW_NCPO_S 1 +#define SSUSB_SYSPLL_PCW_NCPO_M 0xfffffffe + +#define SSUSB_U3PHYA_9_REG 0x10b24 +#define SSUSB_PLL_SSC_PRD_S 0 +#define SSUSB_PLL_SSC_PRD_M 0xffff + +#define SSUSB_U3PHYA_11_REG 0x10b2c +#define SSUSB_EQ_CURSEL 0x1000000 +#define SSUSB_RX_DAC_MUX_S 19 +#define SSUSB_RX_DAC_MUX_M 0xf80000 +#define SSUSB_PCIE_SIGDET_VTH_S 5 +#define SSUSB_PCIE_SIGDET_VTH_M 0x60 +#define SSUSB_PCIE_SIGDET_LPF_S 3 +#define SSUSB_PCIE_SIGDET_LPF_M 0x18 + +#define DA_SSUSB_PLL_FBKDIV_REG 0x10c1c +#define SSUSB_PLL_FBKDIV_PE2H_S 24 +#define SSUSB_PLL_FBKDIV_PE2H_M 0x7f000000 +#define SSUSB_PLL_FBKDIV_PE1D_S 16 +#define SSUSB_PLL_FBKDIV_PE1D_M 0x7f0000 +#define SSUSB_PLL_FBKDIV_PE1H_S 8 +#define SSUSB_PLL_FBKDIV_PE1H_M 0x7f00 +#define SSUSB_PLL_FBKDIV_U3_S 0 +#define SSUSB_PLL_FBKDIV_U3_M 0x7f + +#define DA_SSUSB_U3PHYA_10_REG 0x10c20 +#define SSUSB_PLL_PREDIV_PE1D_S 18 +#define SSUSB_PLL_PREDIV_PE1D_M 0xc0000 +#define SSUSB_PLL_PREDIV_U3_S 8 +#define SSUSB_PLL_PREDIV_U3_M 0x300 +#define SSUSB_PLL_FBKDI_S 0 +#define SSUSB_PLL_FBKDI_M 0x07 + +#define DA_SSUSB_PLL_PCW_NCPO_REG 0x10c24 +#define SSUSB_PLL_PCW_NCPO_U3_S 0 +#define SSUSB_PLL_PCW_NCPO_U3_M 0x7fffffff + +#define DA_SSUSB_PLL_SSC_DELTA1_REG 0x10c38 +#define SSUSB_PLL_SSC_DELTA1_PE1H_S 16 +#define SSUSB_PLL_SSC_DELTA1_PE1H_M 0xffff0000 +#define SSUSB_PLL_SSC_DELTA1_U3_S 0 +#define SSUSB_PLL_SSC_DELTA1_U3_M 0xffff + +#define DA_SSUSB_U3PHYA_21_REG 0x10c40 +#define SSUSB_PLL_SSC_DELTA_U3_S 16 +#define SSUSB_PLL_SSC_DELTA_U3_M 0xffff0000 +#define SSUSB_PLL_SSC_DELTA1_PE2D_S 0 +#define SSUSB_PLL_SSC_DELTA1_PE2D_M 0xffff + +/* MT7621 specific CM values */ + +/* GCR_REGx_BASE */ +#define GCR_REG0_BASE_VALUE 0x1c000000 +#define GCR_REG1_BASE_VALUE 0x60000000 +#define GCR_REG2_BASE_VALUE 0x1c000000 +#define GCR_REG3_BASE_VALUE 0x1c000000 + +/* GCR_REGx_MASK */ +#define GCR_REG0_MASK_VALUE 0x0000fc00 /* 64M Bus */ +#define GCR_REG1_MASK_VALUE 0x0000f000 /* 256M PCI Mem */ +#define GCR_REG2_MASK_VALUE 0x0000fc00 /* unused */ +#define GCR_REG3_MASK_VALUE 0x0000fc00 /* unused */ + +#ifndef __ASSEMBLY__ +unsigned long get_xtal_mhz(void); +#endif + +#endif /* _MT7621_H_ */ diff --git a/arch/mips/mach-mtmips/mt7621/serial.c b/arch/mips/mach-mtmips/mt7621/serial.c new file mode 100644 index 00000000000..0ccc71dc756 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/serial.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/io.h> +#include <asm/addrspace.h> +#include "mt7621.h" + +void board_debug_uart_init(void) +{ + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + +#if CONFIG_DEBUG_UART_BASE == 0xbe000c00 /* KSEG1ADDR(UART1_BASE) */ + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE); +#elif CONFIG_DEBUG_UART_BASE == 0xbe000d00 /* KSEG1ADDR(UART2_BASE) */ + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M); +#elif CONFIG_DEBUG_UART_BASE == 0xbe000e00 /* KSEG1ADDR(UART3_BASE) */ + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M); +#endif +} diff --git a/arch/mips/mach-mtmips/mt7621/spl/Makefile b/arch/mips/mach-mtmips/mt7621/spl/Makefile new file mode 100644 index 00000000000..ebe54e79b90 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/Makefile @@ -0,0 +1,9 @@ + +extra-y += start.o + +obj-y += spl.o +obj-y += cps.o +obj-y += dram.o +obj-y += serial.o +obj-y += launch.o +obj-y += launch_ll.o diff --git a/arch/mips/mach-mtmips/mt7621/spl/cps.c b/arch/mips/mach-mtmips/mt7621/spl/cps.c new file mode 100644 index 00000000000..779e646c126 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/cps.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/mipsregs.h> +#include <asm/cm.h> +#include <linux/bitfield.h> +#include "../mt7621.h" + +/* GIC Shared Register Bases */ +#define GIC_SH_POL_BASE 0x100 +#define GIC_SH_TRIG_BASE 0x180 +#define GIC_SH_RMASK_BASE 0x300 +#define GIC_SH_SMASK_BASE 0x380 +#define GIC_SH_MASK_BASE 0x400 +#define GIC_SH_PEND_BASE 0x480 +#define GIC_SH_MAP_PIN_BASE 0x500 +#define GIC_SH_MAP_VPE_BASE 0x2000 + +/* GIC Registers */ +#define GIC_SH_POL31_0 (GIC_SH_POL_BASE + 0x00) +#define GIC_SH_POL63_32 (GIC_SH_POL_BASE + 0x04) + +#define GIC_SH_TRIG31_0 (GIC_SH_TRIG_BASE + 0x00) +#define GIC_SH_TRIG63_32 (GIC_SH_TRIG_BASE + 0x04) + +#define GIC_SH_RMASK31_0 (GIC_SH_RMASK_BASE + 0x00) +#define GIC_SH_RMASK63_32 (GIC_SH_RMASK_BASE + 0x04) + +#define GIC_SH_SMASK31_0 (GIC_SH_SMASK_BASE + 0x00) +#define GIC_SH_SMASK63_32 (GIC_SH_SMASK_BASE + 0x04) + +#define GIC_SH_MAP_PIN(n) (GIC_SH_MAP_PIN_BASE + (n) * 4) + +#define GIC_SH_MAP_VPE(n, v) (GIC_SH_MAP_VPE_BASE + (n) * 0x20 + ((v) / 32) * 4) +#define GIC_SH_MAP_VPE31_0(n) GIC_SH_MAP_VPE(n, 0) + +/* GIC_SH_MAP_PIN fields */ +#define GIC_MAP_TO_PIN BIT(31) +#define GIC_MAP_TO_NMI BIT(30) +#define GIC_MAP GENMASK(5, 0) +#define GIC_MAP_SHIFT 0 + +static void cm_init(void __iomem *cm_base) +{ + u32 gcrcfg, num_cores; + + gcrcfg = readl(cm_base + GCR_CONFIG); + num_cores = FIELD_GET(GCR_CONFIG_PCORES, gcrcfg) + 1; + + writel((1 << num_cores) - 1, cm_base + GCR_ACCESS); + + writel(GCR_REG0_BASE_VALUE, cm_base + GCR_REG0_BASE); + writel(GCR_REG1_BASE_VALUE, cm_base + GCR_REG1_BASE); + writel(GCR_REG2_BASE_VALUE, cm_base + GCR_REG2_BASE); + writel(GCR_REG3_BASE_VALUE, cm_base + GCR_REG3_BASE); + + clrsetbits_32(cm_base + GCR_REG0_MASK, + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT, + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG0_MASK_VALUE) | + GCR_REGn_MASK_CMTGT_IOCU0); + + clrsetbits_32(cm_base + GCR_REG1_MASK, + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT, + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG1_MASK_VALUE) | + GCR_REGn_MASK_CMTGT_IOCU0); + + clrsetbits_32(cm_base + GCR_REG2_MASK, + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT, + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG2_MASK_VALUE) | + GCR_REGn_MASK_CMTGT_IOCU0); + + clrsetbits_32(cm_base + GCR_REG3_MASK, + GCR_REGn_MASK_ADDRMASK | GCR_REGn_MASK_CMTGT, + FIELD_PREP(GCR_REGn_MASK_ADDRMASK, GCR_REG3_MASK_VALUE) | + GCR_REGn_MASK_CMTGT_IOCU0); + + clrbits_32(cm_base + GCR_BASE, CM_DEFAULT_TARGET_MASK); + setbits_32(cm_base + GCR_CONTROL, GCR_CONTROL_SYNCCTL); +} + +static void gic_init(void) +{ + void __iomem *gic_base = (void *)KSEG1ADDR(MIPS_GIC_BASE); + int i; + + /* Interrupt 0..5: Level Trigger, Active High */ + writel(0, gic_base + GIC_SH_TRIG31_0); + writel(0x3f, gic_base + GIC_SH_RMASK31_0); + writel(0x3f, gic_base + GIC_SH_POL31_0); + writel(0x3f, gic_base + GIC_SH_SMASK31_0); + + /* Interrupt 56..63: Edge Trigger, Rising Edge */ + /* Hardcoded to set up the last 8 external interrupts for IPI. */ + writel(0xff000000, gic_base + GIC_SH_TRIG63_32); + writel(0xff000000, gic_base + GIC_SH_RMASK63_32); + writel(0xff000000, gic_base + GIC_SH_POL63_32); + writel(0xff000000, gic_base + GIC_SH_SMASK63_32); + + /* Map interrupt source to particular hardware interrupt pin */ + /* source {0,1,2,3,4,5} -> pin {0,0,4,3,0,5} */ + writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(0)); + writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(1)); + writel(GIC_MAP_TO_PIN | 4, gic_base + GIC_SH_MAP_PIN(2)); + writel(GIC_MAP_TO_PIN | 3, gic_base + GIC_SH_MAP_PIN(3)); + writel(GIC_MAP_TO_PIN | 0, gic_base + GIC_SH_MAP_PIN(4)); + writel(GIC_MAP_TO_PIN | 5, gic_base + GIC_SH_MAP_PIN(5)); + + /* source 56~59 -> pin 1, 60~63 -> pin 2 */ + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(56)); + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(57)); + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(58)); + writel(GIC_MAP_TO_PIN | 1, gic_base + GIC_SH_MAP_PIN(59)); + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(60)); + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(61)); + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(62)); + writel(GIC_MAP_TO_PIN | 2, gic_base + GIC_SH_MAP_PIN(63)); + + /* Interrupt map to VPE (bit mask) */ + for (i = 0; i < 32; i++) + writel(BIT(0), gic_base + GIC_SH_MAP_VPE31_0(i)); + + /* + * Direct GIC_int 56..63 to vpe 0..3 + * MIPS Linux convention that last 16 interrupts implemented be set + * aside for IPI signaling. + * The actual interrupts are tied low and software sends interrupts + * via GIC_SH_WEDGE writes. + */ + for (i = 0; i < 4; i++) { + writel(BIT(i), gic_base + GIC_SH_MAP_VPE31_0(i + 56)); + writel(BIT(i), gic_base + GIC_SH_MAP_VPE31_0(i + 60)); + } +} + +void mt7621_cps_init(void) +{ + void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE); + + /* Enable GIC */ + writel(MIPS_GIC_BASE | GCR_GIC_EN, cm_base + GCR_GIC_BASE); + + /* Enable CPC */ + writel(MIPS_CPC_BASE | GCR_CPC_EN, cm_base + GCR_CPC_BASE); + + gic_init(); + cm_init(cm_base); +} diff --git a/arch/mips/mach-mtmips/mt7621/spl/dram.c b/arch/mips/mach-mtmips/mt7621/spl/dram.c new file mode 100644 index 00000000000..100adfb93a5 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/dram.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <vsprintf.h> +#include <asm/io.h> +#include <asm/sections.h> +#include <asm/byteorder.h> +#include <asm/addrspace.h> +#include <linux/string.h> +#include "../mt7621.h" +#include "dram.h" + +static const u32 ddr2_act[DDR_PARAM_SIZE] = { +#if defined(CONFIG_MT7621_DRAM_DDR2_512M) + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441, + 0x00000000, 0xF0748661, 0x40001273, 0x9F0A0481, + 0x0304692F, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000000, 0x07100000, + 0x00001B63, 0x00002000, 0x00004000, 0x00006000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +#elif defined(CONFIG_MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ) + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584, + 0x00000000, 0xF07486A1, 0x50001273, 0x9F010481, + 0x0304693F, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000010, 0x07100000, + 0x00001F73, 0x00002000, 0x00004000, 0x00006000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ) + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174430, + 0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481, + 0x0304692F, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000000, 0x07100000, + 0x00001B63, 0x00002000, 0x00004000, 0x00006000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +#elif defined(CONFIG_MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ) + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x33484584, + 0x01000000, 0xF07486A1, 0x50001273, 0x9F070481, + 0x0304693F, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000010, 0x07100000, + 0x00001F73, 0x00002000, 0x00004000, 0x00006000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +#else /* CONFIG_MT7621_DRAM_DDR2_1024M */ + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x22174441, + 0x01000000, 0xF0748661, 0x40001273, 0x9F0F0481, + 0x0304692F, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000000, 0x07100000, + 0x00001B63, 0x00002000, 0x00004000, 0x00006000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +#endif +}; + +static const u32 ddr3_act[DDR_PARAM_SIZE] = { +#if defined(CONFIG_MT7621_DRAM_DDR3_1024M) + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683, + 0x01000000, 0xF07486A1, 0xC287221D, 0x9F060481, + 0x03046948, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000210, 0x07100000, + 0x00001B61, 0x00002040, 0x00004010, 0x00006000, + 0x0C000000, 0x07070000, 0x00000000, 0x00000000, +#elif defined(CONFIG_MT7621_DRAM_DDR3_4096M) + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694683, + 0x01000000, 0xF07486A1, 0xC287221D, 0x9F0F0481, + 0x03046948, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000240, 0x07100000, + 0x00001B61, 0x00002040, 0x00004010, 0x00006000, + 0x0C000000, 0x07070000, 0x00000000, 0x00000000, +#elif defined(CONFIG_MT7621_DRAM_DDR3_1024M_KGD) + 0xFF00FF00, 0xFF00FF00, 0x00000007, 0x44694683, + 0x01000000, 0xF07406A1, 0xC287221D, 0x9F060481, + 0x03046923, 0x152f2842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000210, 0x07100000, + 0x00001B61, 0x00002040, 0x00004010, 0x00006000, + 0x0C000000, 0x07070000, 0x000C0000, 0x00000000, +#else /* CONFIG_MT7621_DRAM_DDR3_2048M */ + 0xAA00AA00, 0xAA00AA00, 0x00000007, 0x44694673, + 0x01000000, 0xF07486A1, 0xC287221D, 0x9F050481, + 0x03046948, 0x15602842, 0x00008888, 0x88888888, + 0x00000000, 0x00000000, 0x00000220, 0x07100000, + 0x00001B61, 0x00002040, 0x00004010, 0x00006000, + 0x0C000000, 0x07070000, 0x00000000, 0x00000000, +#endif +}; + +#if defined(CONFIG_MT7621_DRAM_FREQ_400) +#define DDR_FREQ_PARAM 0x41000000 +#elif defined(CONFIG_MT7621_DRAM_FREQ_1066) +#define DDR_FREQ_PARAM 0x21000000 +#elif defined(CONFIG_MT7621_DRAM_FREQ_1200) +#define DDR_FREQ_PARAM 0x11000000 +#else /* CONFIG_MT7621_DRAM_FREQ_800 */ +#define DDR_FREQ_PARAM 0x31000000 +#endif + +#define RG_MEPL_FBDIV_S 4 +#define RG_MEPL_FBDIV_M 0x7f + +static inline void word_copy(u32 *dest, const u32 *src, u32 count) +{ + u32 i; + + for (i = 0; i < count; i++) + dest[i] = src[i]; +} + +static u32 calc_cpu_pll_val(void) +{ + u32 div, baseval, fb; + + div = get_xtal_mhz(); + + if (div == 40) { + div /= 2; + baseval = 0xc0005802; + } else { + baseval = 0xc0004802; + } + + fb = CONFIG_MT7621_CPU_FREQ / div - 1; + if (fb > RG_MEPL_FBDIV_M) + fb = RG_MEPL_FBDIV_M; + + return baseval | (fb << RG_MEPL_FBDIV_S); +} + +void prepare_stage_bin(void) +{ + u32 stage_size; + + const struct stage_header *stock_stage_bin = + (const struct stage_header *)__image_copy_end; + + struct stage_header *new_stage_bin = + (struct stage_header *)STAGE_LOAD_ADDR; + + if (be32_to_cpu(stock_stage_bin->ep) != STAGE_LOAD_ADDR) + panic("Invalid DDR stage binary blob\n"); + + stage_size = be32_to_cpu(stock_stage_bin->stage_size); + + word_copy((u32 *)new_stage_bin, (const u32 *)stock_stage_bin, + (stage_size + sizeof(u32) - 1) / sizeof(u32)); + + word_copy(new_stage_bin->ddr2_act, ddr2_act, DDR_PARAM_SIZE); + word_copy(new_stage_bin->ddr3_act, ddr3_act, DDR_PARAM_SIZE); + + new_stage_bin->cpu_pll_cfg = calc_cpu_pll_val(); + new_stage_bin->ddr_pll_cfg = DDR_FREQ_PARAM; + new_stage_bin->baudrate = CONFIG_BAUDRATE; +} diff --git a/arch/mips/mach-mtmips/mt7621/spl/dram.h b/arch/mips/mach-mtmips/mt7621/spl/dram.h new file mode 100644 index 00000000000..7322c58276a --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/dram.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _MT7621_DRAM_H_ +#define _MT7621_DRAM_H_ + +#define STAGE_LOAD_ADDR 0xBE108800 + +#ifndef __ASSEMBLY__ +#include <linux/types.h> + +#define DDR_PARAM_SIZE 24 + +struct stage_header { + u32 jump_insn[2]; + u32 ep; + u32 stage_size; + u32 has_stage2; + u32 next_ep; + u32 next_size; + u32 next_offset; + u32 cpu_pll_cfg; + u32 ddr_pll_cfg; + u32 reserved2[6]; + char build_tag[32]; + u32 ddr3_act[DDR_PARAM_SIZE]; + u32 padding1[2]; + u32 ddr2_act[DDR_PARAM_SIZE]; + u32 padding2[2]; + u32 baudrate; + u32 padding3; +}; +#endif + +#endif /* _MT7621_DRAM_H_ */ diff --git a/arch/mips/mach-mtmips/mt7621/spl/launch.c b/arch/mips/mach-mtmips/mt7621/spl/launch.c new file mode 100644 index 00000000000..95dd65913d4 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/launch.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/io.h> +#include <asm/cm.h> +#include <asm/sections.h> +#include <asm/addrspace.h> +#include <asm/mipsmtregs.h> +#include <linux/sizes.h> +#include <time.h> +#include <cpu_func.h> +#include "launch.h" +#include "../mt7621.h" + +/* Cluster Power Controller (CPC) offsets */ +#define CPC_CL_OTHER 0x2010 +#define CPC_CO_CMD 0x4000 + +/* CPC_CL_OTHER fields */ +#define CPC_CL_OTHER_CORENUM_SHIFT 16 +#define CPC_CL_OTHER_CORENUM GENMASK(23, 16) + +/* CPC_CO_CMD */ +#define PWR_UP 3 + +#define NUM_CORES 2 +#define NUM_CPUS 4 +#define WAIT_CPUS_TIMEOUT 4000 + +static void copy_launch_wait_code(void) +{ + memset((void *)KSEG1, 0, SZ_4K); + + memcpy((void *)KSEG1ADDR(LAUNCH_WAITCODE), + &launch_wait_code_start, + &launch_wait_code_end - &launch_wait_code_start); + + invalidate_dcache_range(KSEG0, SZ_4K); +} + +static void bootup_secondary_core(void) +{ + void __iomem *cpcbase = (void __iomem *)KSEG1ADDR(MIPS_CPC_BASE); + int i; + + for (i = 1; i < NUM_CORES; i++) { + writel(i << CPC_CL_OTHER_CORENUM_SHIFT, cpcbase + CPC_CL_OTHER); + writel(PWR_UP, cpcbase + CPC_CO_CMD); + } +} + +void secondary_cpu_init(void) +{ + void __iomem *sysc = (void __iomem *)KSEG1ADDR(SYSCTL_BASE); + u32 i, dual_core = 0, cpuready = 1, cpumask = 0x03; + ulong wait_tick; + struct cpulaunch_t *c; + + /* Copy LAUNCH wait code used by other VPEs */ + copy_launch_wait_code(); + + dual_core = readl(sysc + SYSCTL_CHIP_REV_ID_REG) & CPU_ID; + + if (dual_core) { + /* Bootup secondary core for MT7621A */ + cpumask = 0x0f; + + /* Make BootROM/TPL redirect Core1's bootup flow to our entry point */ + writel((uintptr_t)_start, sysc + BOOT_SRAM_BASE_REG); + + bootup_secondary_core(); + } + + /* Join the coherent domain */ + join_coherent_domain(dual_core ? 2 : 1); + + /* Bootup Core0/VPE1 */ + boot_vpe1(); + + /* Wait for all CPU ready */ + wait_tick = get_timer(0) + WAIT_CPUS_TIMEOUT; + + while (time_before(get_timer(0), wait_tick)) { + /* CPU0 is obviously ready */ + for (i = 1; i < NUM_CPUS; i++) { + c = (struct cpulaunch_t *)(KSEG0ADDR(CPULAUNCH) + + (i << LOG2CPULAUNCH)); + + if (c->flags & LAUNCH_FREADY) + cpuready |= BIT(i); + } + + if ((cpuready & cpumask) == cpumask) + break; + } +} diff --git a/arch/mips/mach-mtmips/mt7621/spl/launch.h b/arch/mips/mach-mtmips/mt7621/spl/launch.h new file mode 100644 index 00000000000..f34250d6058 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/launch.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _LAUNCH_H_ +#define _LAUNCH_H_ + +#ifndef __ASSEMBLY__ + +struct cpulaunch_t { + unsigned long pc; + unsigned long gp; + unsigned long sp; + unsigned long a0; + unsigned long _pad[3]; /* pad to cache line size to avoid thrashing */ + unsigned long flags; +}; + +extern char launch_wait_code_start; +extern char launch_wait_code_end; + +void join_coherent_domain(int ncores); +void boot_vpe1(void); + +#else + +#define LAUNCH_PC 0 +#define LAUNCH_GP 4 +#define LAUNCH_SP 8 +#define LAUNCH_A0 12 +#define LAUNCH_FLAGS 28 + +#endif + +#define LOG2CPULAUNCH 5 + +#define LAUNCH_FREADY 1 +#define LAUNCH_FGO 2 +#define LAUNCH_FGONE 4 + +#define LAUNCH_WAITCODE 0x00000d00 +#define SCRLAUNCH 0x00000e00 +#define CPULAUNCH 0x00000f00 +#define NCPULAUNCH 8 + +/* Polling period in count cycles for secondary CPU's */ +#define LAUNCHPERIOD 10000 + +#endif /* _LAUNCH_H_ */ diff --git a/arch/mips/mach-mtmips/mt7621/spl/launch_ll.S b/arch/mips/mach-mtmips/mt7621/spl/launch_ll.S new file mode 100644 index 00000000000..32d28c7539a --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/launch_ll.S @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/cm.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/cacheops.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/mipsmtregs.h> +#include "launch.h" + + .macro cache_loop curr, end, line_sz, op +10: cache \op, 0(\curr) + PTR_ADDU \curr, \curr, \line_sz + bne \curr, \end, 10b + .endm + + .set mt + +/* + * Join the coherent domain + * a0 = number of cores + */ +LEAF(join_coherent_domain) + /* + * Enable coherence and allow interventions from all other cores. + * (Write access enabled via GCR_ACCESS by core 0.) + */ + li t1, 1 + sll t1, a0 + addiu t1, -1 + + li t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE) + sw t1, GCR_Cx_COHERENCE(t0) + ehb + + move t2, zero + +_next_coherent_core: + sll t1, t2, GCR_Cx_OTHER_CORENUM_SHIFT + sw t1, GCR_Cx_OTHER(t0) + +_busy_wait_coherent_core: + lw t1, GCR_CO_COHERENCE(t0) + beqz t1, _busy_wait_coherent_core + + addiu t2, 1 + bne t2, a0, _next_coherent_core + + jr ra + END(join_coherent_domain) + +/* + * All VPEs other than VPE0 will go here. + */ +LEAF(launch_vpe_entry) + mfc0 t0, CP0_EBASE + and t0, t0, MIPS_EBASE_CPUNUM + + /* per-VPE cpulaunch_t */ + li a0, KSEG0ADDR(CPULAUNCH) + sll t1, t0, LOG2CPULAUNCH + addu a0, t1 + + /* Set CPU online flag */ + li t0, LAUNCH_FREADY + sw t0, LAUNCH_FLAGS(a0) + + /* Enable count interrupt in mask, but do not enable interrupts */ + mfc0 t0, CP0_STATUS + ori t0, STATUSF_IP7 + mtc0 t0, CP0_STATUS + + /* VPEs executing in wait code do not need a stack */ + li t9, KSEG0ADDR(LAUNCH_WAITCODE) + jr t9 + END(launch_vpe_entry) + +/* + * This function will not be executed in place. + * It will be copied into memory, and VPEs other than VPE0 will be + * started to run into this in-memory function. + */ +LEAF(launch_wait_code) + .globl launch_wait_code_start +launch_wait_code_start: + + move t0, a0 + +start_poll: + /* Poll CPU go flag */ + mtc0 zero, CP0_COUNT + li t1, LAUNCHPERIOD + mtc0 t1, CP0_COMPARE + +time_wait: + /* Software wait */ + mfc0 t2, CP0_COUNT + subu t2, t1 + bltz t2, time_wait + + /* Check the launch flag */ + lw t3, LAUNCH_FLAGS(t0) + and t3, LAUNCH_FGO + beqz t3, start_poll + + /* Reset the counter and interrupts to give naive clients a chance */ + mfc0 t1, CP0_STATUS + ins t1, zero, STATUSB_IP7, 1 + mtc0 t1, CP0_STATUS + + mfc0 t1, CP0_COUNT + subu t1, 1 + mtc0 t1, CP0_COMPARE + + /* Jump to kernel */ + lw t9, LAUNCH_PC(t0) + lw gp, LAUNCH_GP(t0) + lw sp, LAUNCH_SP(t0) + lw a0, LAUNCH_A0(t0) + move a1, zero + move a2, zero + move a3, zero + ori t3, LAUNCH_FGONE + sw t3, LAUNCH_FLAGS(t0) + + jr t9 + + .globl launch_wait_code_end +launch_wait_code_end: + END(launch_wait_code) + +/* + * Core1 will go here. + */ +LEAF(launch_core_entry) + /* Disable caches */ + bal mips_cache_disable + + /* Initialize L1 cache only */ + li a0, CONFIG_SYS_ICACHE_SIZE + li a1, CONFIG_SYS_ICACHE_LINE_SIZE + li a2, CONFIG_SYS_DCACHE_SIZE + li a3, CONFIG_SYS_DCACHE_LINE_SIZE + + mtc0 zero, CP0_TAGLO + mtc0 zero, CP0_TAGLO, 2 + ehb + + /* + * Initialize the I-cache first, + */ + li t0, KSEG0 + addu t1, t0, a0 + /* clear tag to invalidate */ + cache_loop t0, t1, a1, INDEX_STORE_TAG_I +#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* fill once, so data field parity is correct */ + PTR_LI t0, KSEG0 + cache_loop t0, t1, a1, FILL + /* invalidate again - prudent but not strictly necessary */ + PTR_LI t0, KSEG0 + cache_loop t0, t1, a1, INDEX_STORE_TAG_I +#endif + + /* + * then initialize D-cache. + */ + PTR_LI t0, KSEG0 + PTR_ADDU t1, t0, a2 + /* clear all tags */ + cache_loop t0, t1, a3, INDEX_STORE_TAG_D +#ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD + /* load from each line (in cached space) */ + PTR_LI t0, KSEG0 +2: LONG_L zero, 0(t0) + PTR_ADDU t0, a3 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, KSEG0 + cache_loop t0, t1, a3, INDEX_STORE_TAG_D +#endif + + /* Set Cache Mode */ + mfc0 t0, CP0_CONFIG + li t1, CONF_CM_CACHABLE_COW + ins t0, t1, 0, 3 + mtc0 t0, CP0_CONFIG + + /* Join the coherent domain */ + li a0, 2 + bal join_coherent_domain + + /* Bootup Core0/VPE1 */ + bal boot_vpe1 + + b launch_vpe_entry + END(launch_core_entry) + +/* + * Bootup VPE1. + * This subroutine must be executed from VPE0 with VPECONF0[MVP] already set. + */ +LEAF(boot_vpe1) + mfc0 t0, CP0_MVPCONF0 + + /* a0 = number of TCs - 1 */ + ext a0, t0, MVPCONF0_PTC_SHIFT, 8 + beqz a0, _vpe1_init_done + + /* a1 = number of VPEs - 1 */ + ext a1, t0, MVPCONF0_PVPE_SHIFT, 4 + beqz a1, _vpe1_init_done + + /* a2 = current TC No. */ + move a2, zero + + /* Enter VPE Configuration State */ + mfc0 t0, CP0_MVPCONTROL + or t0, MVPCONTROL_VPC + mtc0 t0, CP0_MVPCONTROL + ehb + +_next_tc: + /* Set the TC number to be used on MTTR and MFTR instructions */ + mfc0 t0, CP0_VPECONTROL + ins t0, a2, 0, 8 + mtc0 t0, CP0_VPECONTROL + ehb + + /* TC0 is already bound */ + beqz a2, _next_vpe + + /* Halt current TC */ + li t0, TCHALT_H + mttc0 t0, CP0_TCHALT + ehb + + /* If there is spare TC, bind it to the last VPE (VPE[a1]) */ + slt t1, a1, a2 + bnez t1, _vpe_bind_tc + move t1, a1 + + /* Set Exclusive TC for active TC */ + mftc0 t0, CP0_VPECONF0 + ins t0, a2, VPECONF0_XTC_SHIFT, 8 + mttc0 t0, CP0_VPECONF0 + + move t1, a2 +_vpe_bind_tc: + /* Bind TC to a VPE */ + mftc0 t0, CP0_TCBIND + ins t0, t1, TCBIND_CURVPE_SHIFT, 4 + mttc0 t0, CP0_TCBIND + + /* + * Set up CP0_TCSTATUS register: + * Disable Coprocessor Usable bits + * Disable MDMX/DSP ASE + * Clear Dirty TC + * not dynamically allocatable + * not allocated + * Kernel mode + * interrupt exempt + * ASID 0 + */ + li t0, TCSTATUS_IXMT + mttc0 t0, CP0_TCSTATUS + +_next_vpe: + slt t1, a1, a2 + bnez t1, _done_vpe # No more VPEs + + /* Disable TC multi-threading */ + mftc0 t0, CP0_VPECONTROL + ins t0, zero, VPECONTROL_TE_SHIFT, 1 + mttc0 t0, CP0_VPECONTROL + + /* Skip following configuration for TC0 */ + beqz a2, _done_vpe + + /* Deactivate VPE, set Master VPE */ + mftc0 t0, CP0_VPECONF0 + ins t0, zero, VPECONF0_VPA_SHIFT, 1 + or t0, VPECONF0_MVP + mttc0 t0, CP0_VPECONF0 + + mfc0 t0, CP0_STATUS + mttc0 t0, CP0_STATUS + + mttc0 zero, CP0_EPC + mttc0 zero, CP0_CAUSE + + mfc0 t0, CP0_CONFIG + mttc0 t0, CP0_CONFIG + + /* + * VPE1 of each core can execute cached as its L1 I$ has already + * been initialized. + * and the L2$ has been initialized or "disabled" via CCA override. + */ + PTR_LA t0, _start + mttc0 t0, CP0_TCRESTART + + /* Unset Interrupt Exempt, set Activate Thread */ + mftc0 t0, CP0_TCSTATUS + ins t0, zero, TCSTATUS_IXMT_SHIFT, 1 + ori t0, TCSTATUS_A + mttc0 t0, CP0_TCSTATUS + + /* Resume TC */ + mttc0 zero, CP0_TCHALT + + /* Activate VPE */ + mftc0 t0, CP0_VPECONF0 + ori t0, VPECONF0_VPA + mttc0 t0, CP0_VPECONF0 + +_done_vpe: + addu a2, 1 + sltu t0, a0, a2 + beqz t0, _next_tc + + mfc0 t0, CP0_MVPCONTROL + /* Enable all activated VPE to execute */ + ori t0, MVPCONTROL_EVP + /* Exit VPE Configuration State */ + ins t0, zero, MVPCONTROL_VPC_SHIFT, 1 + mtc0 t0, CP0_MVPCONTROL + ehb + +_vpe1_init_done: + jr ra + END(boot_vpe1) diff --git a/arch/mips/mach-mtmips/mt7621/spl/serial.c b/arch/mips/mach-mtmips/mt7621/spl/serial.c new file mode 100644 index 00000000000..5cf093a078a --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/serial.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/io.h> +#include "../mt7621.h" + +void mtmips_spl_serial_init(void) +{ +#ifdef CONFIG_SPL_SERIAL + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + +#if CONFIG_CONS_INDEX == 1 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE); +#elif CONFIG_CONS_INDEX == 2 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M); +#elif CONFIG_CONS_INDEX == 3 + clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M); +#endif /* CONFIG_CONS_INDEX */ +#endif /* CONFIG_SPL_SERIAL */ +} diff --git a/arch/mips/mach-mtmips/mt7621/spl/spl.c b/arch/mips/mach-mtmips/mt7621/spl/spl.c new file mode 100644 index 00000000000..25b409e2417 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/spl.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <init.h> +#include <image.h> +#include <vsprintf.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/sections.h> +#include <asm/addrspace.h> +#include <asm/byteorder.h> +#include <asm/global_data.h> +#include <linux/sizes.h> +#include <linux/types.h> +#include <mach/serial.h> +#include "../mt7621.h" +#include "dram.h" +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct tpl_info { + u32 magic; + u32 size; +}; + +void set_timer_freq_simple(void) +{ + u32 div = get_xtal_mhz(); + + /* Round down cpu freq */ + gd->arch.timer_freq = rounddown(CONFIG_MT7621_CPU_FREQ, div) * 500000; +} + +void __noreturn board_init_f(ulong dummy) +{ + spl_init(); + +#ifdef CONFIG_SPL_SERIAL + /* + * mtmips_spl_serial_init() is useful if debug uart is enabled, + * or DM based serial is not enabled. + */ + mtmips_spl_serial_init(); + preloader_console_init(); +#endif + + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ +#ifdef CONFIG_MT7621_BOOT_FROM_NAND + spl_boot_list[0] = BOOT_DEVICE_NAND; +#else + spl_boot_list[0] = BOOT_DEVICE_NOR; +#endif +} + +unsigned long spl_nor_get_uboot_base(void) +{ + const struct tpl_info *tpli; + const struct legacy_img_hdr *hdr; + u32 addr; + + addr = FLASH_MMAP_BASE + TPL_INFO_OFFSET; + tpli = (const struct tpl_info *)KSEG1ADDR(addr); + + if (tpli->magic == TPL_INFO_MAGIC) { + addr = FLASH_MMAP_BASE + tpli->size; + hdr = (const struct legacy_img_hdr *)KSEG1ADDR(addr); + + if (image_get_magic(hdr) == IH_MAGIC) { + addr += sizeof(*hdr) + image_get_size(hdr); + return KSEG1ADDR(addr); + } + } + + panic("Unable to locate SPL payload\n"); + return 0; +} + +uint32_t spl_nand_get_uboot_raw_page(void) +{ + const struct stage_header *sh = (const struct stage_header *)_start; + u32 addr; + + addr = image_get_header_size() + be32_to_cpu(sh->stage_size); + addr = ALIGN(addr, SZ_4K); + + return addr; +} diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S new file mode 100644 index 00000000000..d56e624f313 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/cacheops.h> +#include <asm/addrspace.h> +#include <asm/mipsmtregs.h> +#include <asm/cm.h> +#include "../mt7621.h" +#include "dram.h" + +#ifndef CFG_SYS_INIT_SP_ADDR +#define CFG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ + CFG_SYS_INIT_SP_OFFSET) +#endif + +#define SP_ADDR_TEMP 0xbe10dff0 + + .macro init_wr sel + MTC0 zero, CP0_WATCHLO,\sel + mtc0 t1, CP0_WATCHHI,\sel + .endm + + .macro setup_stack_gd + li t0, -16 + PTR_LI t1, CFG_SYS_INIT_SP_ADDR + and sp, t1, t0 # force 16 byte alignment + PTR_SUBU \ + sp, sp, GD_SIZE # reserve space for gd + and sp, sp, t0 # force 16 byte alignment + move k0, sp # save gd pointer +#if CONFIG_IS_ENABLED(SYS_MALLOC_F) && \ + !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) + li t2, CONFIG_VAL(SYS_MALLOC_F_LEN) + PTR_SUBU \ + sp, sp, t2 # reserve space for early malloc + and sp, sp, t0 # force 16 byte alignment +#endif + move fp, sp + + /* Clear gd */ + move t0, k0 +1: + PTR_S zero, 0(t0) + PTR_ADDIU t0, PTRSIZE + blt t0, t1, 1b + nop + +#if CONFIG_IS_ENABLED(SYS_MALLOC_F) && \ + !CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) + PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset +#endif + .endm + + .set noreorder + +ENTRY(_start) + b 1f + mtc0 zero, CP0_COUNT + + /* Stage header required by BootROM */ + .org 0x8 + .word 0 # ep, filled by mkimage + .word 0 # stage_size, filled by mkimage + .word 0 # has_stage2 + .word 0 # next_ep + .word 0 # next_size + .word 0 # next_offset + +1: + /* Init CP0 Status */ + mfc0 t0, CP0_STATUS + and t0, ST0_IMPL + or t0, ST0_BEV | ST0_ERL + mtc0 t0, CP0_STATUS + ehb + + /* Clear Watch Status bits and disable watch exceptions */ + li t1, 0x7 # Clear I, R and W conditions + init_wr 0 + init_wr 1 + init_wr 2 + init_wr 3 + + /* Clear WP, IV and SW interrupts */ + mtc0 zero, CP0_CAUSE + + /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */ + mtc0 zero, CP0_COMPARE + + /* VPE1 goes to wait code directly */ + mfc0 t0, CP0_TCBIND + andi t0, TCBIND_CURVPE + bnez t0, launch_vpe_entry + nop + + /* Core1 goes to specific launch entry */ + PTR_LI t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE) + lw t1, GCR_Cx_ID(t0) + bnez t1, launch_core_entry + nop + + /* MT7530 reset */ + li t0, KSEG1ADDR(SYSCTL_BASE) + lw t1, SYSCTL_RSTCTL_REG(t0) + ori t1, MCM_RST + sw t1, SYSCTL_RSTCTL_REG(t0) + + /* Disable DMA route for PSE SRAM set by BootROM */ + PTR_LI t0, KSEG1ADDR(DMA_CFG_ARB_BASE) + sw zero, DMA_ROUTE_REG(t0) + + /* Set CPU clock to 500MHz (Required if boot from NAND) */ + li t0, KSEG1ADDR(SYSCTL_BASE) + lw t1, SYSCTL_CLKCFG0_REG(t0) + ins t1, zero, 30, 2 # CPU_CLK_SEL + sw t1, SYSCTL_CLKCFG0_REG(t0) + + /* Set CPU clock divider to 1/1 */ + li t0, KSEG1ADDR(RBUS_BASE) + li t1, 0x101 + sw t1, RBUS_DYN_CFG0_REG(t0) + + /* (Re-)initialize the SRAM */ + bal mips_sram_init + nop + + /* Set up temporary stack */ + li sp, SP_ADDR_TEMP + + /* Setup full CPS */ + bal mips_cm_map + nop + + bal mt7621_cps_init + nop + + /* Prepare for CPU/DDR initialization binary blob */ + bal prepare_stage_bin + nop + + /* Call CPU/DDR initialization binary blob */ + li t9, STAGE_LOAD_ADDR + jalr t9 + nop + + /* Switch CPU PLL source */ + li t0, KSEG1ADDR(SYSCTL_BASE) + lw t1, SYSCTL_CLKCFG0_REG(t0) + li t2, 1 + ins t1, t2, CPU_CLK_SEL_S, 2 + sw t1, SYSCTL_CLKCFG0_REG(t0) + + /* + * Currently SPL is running on locked L2 cache (on KSEG0). + * To reset the entire cache, we have to writeback SPL to DRAM first. + * Cache flush won't work here. Use memcpy instead. + */ + + la a0, __text_start + move a1, a0 + la a2, __image_copy_end + sub a2, a2, a1 + li a3, 5 + ins a0, a3, 29, 3 # convert to KSEG1 + + bal memcpy + nop + + /* Disable caches */ + bal mips_cache_disable + nop + + /* Reset caches */ + bal mips_cache_reset + nop + + /* Disable SRAM */ + li t0, KSEG1ADDR(FE_BASE) + li t1, FE_PSE_RESET + sw t1, FE_RST_GLO_REG(t0) + + /* Clear the .bss section */ + la a0, __bss_start + la a1, __bss_end +1: sw zero, 0(a0) + addiu a0, 4 + ble a0, a1, 1b + nop + + /* Set up initial stack and global data */ + setup_stack_gd + +#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) + /* Set malloc base */ + li t0, (CFG_SYS_INIT_SP_ADDR + 15) & (~15) + PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset +#endif + +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_SPL_SERIAL) + /* Earliest point to set up debug uart */ + bal debug_uart_init + nop +#endif + + /* Setup timer */ + bal set_timer_freq_simple + nop + + /* Bootup secondary CPUs */ + bal secondary_cpu_init + nop + + move a0, zero # a0 <-- boot_flags = 0 + bal board_init_f + move ra, zero + + END(_start) diff --git a/arch/mips/mach-mtmips/mt7621/sram_init.S b/arch/mips/mach-mtmips/mt7621/sram_init.S new file mode 100644 index 00000000000..03b9eab10b1 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/sram_init.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/addrspace.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include "mt7621.h" + +LEAF(mips_sram_init) + li t0, KSEG1ADDR(FE_BASE) + li t1, FE_PSE_RESET + sw t1, FE_RST_GLO_REG(t0) + + li t1, (FE_PSE_RAM | FE_PSE_MEM_EN) + sw t1, FE_RST_GLO_REG(t0) + + jr ra + END(mips_sram_init) diff --git a/arch/mips/mach-mtmips/mt7621/tpl/Makefile b/arch/mips/mach-mtmips/mt7621/tpl/Makefile new file mode 100644 index 00000000000..471ad74249a --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/tpl/Makefile @@ -0,0 +1,4 @@ + +extra-y += start.o + +obj-y += tpl.o diff --git a/arch/mips/mach-mtmips/mt7621/tpl/start.S b/arch/mips/mach-mtmips/mt7621/tpl/start.S new file mode 100644 index 00000000000..19b09f72513 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/tpl/start.S @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm-offsets.h> +#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/addrspace.h> +#include <asm/mipsregs.h> +#include <asm/cm.h> +#include "../mt7621.h" + +#define SP_ADDR_TEMP 0xbe10dff0 + + .set noreorder + + .macro init_wr sel + MTC0 zero, CP0_WATCHLO,\sel + mtc0 t1, CP0_WATCHHI,\sel + .endm + + .macro uhi_mips_exception + move k0, t9 # preserve t9 in k0 + move k1, a0 # preserve a0 in k1 + li t9, 15 # UHI exception operation + li a0, 0 # Use hard register context + sdbbp 1 # Invoke UHI operation + .endm + +ENTRY(_start) + b reset + mtc0 zero, CP0_COUNT + + /* + * Store TPL size here. + * This will be used by SPL to locate u-boot payload. + */ + .org TPL_INFO_OFFSET + .word TPL_INFO_MAGIC + .word __image_copy_len + + /* Exception vector */ + .org 0x200 + /* TLB refill, 32 bit task */ + uhi_mips_exception + + .org 0x280 + /* XTLB refill, 64 bit task */ + uhi_mips_exception + + .org 0x300 + /* Cache error exception */ + uhi_mips_exception + + .org 0x380 + /* General exception */ + uhi_mips_exception + + .org 0x400 + /* Catch interrupt exceptions */ + uhi_mips_exception + + .org 0x480 + /* EJTAG debug exception */ +1: b 1b + nop + + .org 0x500 + +reset: + /* Set KSEG0 to Uncached */ + mfc0 t0, CP0_CONFIG + ins t0, zero, 0, 3 + ori t0, t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + ehb + + /* Check for CPU number */ + mfc0 t0, CP0_EBASE + and t0, t0, MIPS_EBASE_CPUNUM + beqz t0, 1f + nop + + /* Secondary core goes to specified SPL entry address */ + li t0, KSEG1ADDR(SYSCTL_BASE) + lw t0, BOOT_SRAM_BASE_REG(t0) + jr t0 + nop + + /* Init CP0 Status */ +1: mfc0 t0, CP0_STATUS + and t0, ST0_IMPL + or t0, ST0_BEV | ST0_ERL + mtc0 t0, CP0_STATUS + nop + + /* Clear Watch Status bits and disable watch exceptions */ + li t1, 0x7 # Clear I, R and W conditions + init_wr 0 + init_wr 1 + init_wr 2 + init_wr 3 + + /* Clear WP, IV and SW interrupts */ + mtc0 zero, CP0_CAUSE + + /* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */ + mtc0 zero, CP0_COMPARE + + /* Setup basic CPS */ + bal mips_cm_map + nop + + li t0, KSEG1ADDR(CONFIG_MIPS_CM_BASE) + li t1, GCR_REG0_BASE_VALUE + sw t1, GCR_REG0_BASE(t0) + + li t1, ((GCR_REG0_MASK_VALUE << GCR_REGn_MASK_ADDRMASK_SHIFT) | \ + GCR_REGn_MASK_CMTGT_IOCU0) + sw t1, GCR_REG0_MASK(t0) + + lw t1, GCR_BASE(t0) + ins t1, zero, 0, 2 # CM_DEFAULT_TARGET + sw t1, GCR_BASE(t0) + + lw t1, GCR_CONTROL(t0) + li t2, GCR_CONTROL_SYNCCTL + or t1, t1, t2 + sw t1, GCR_CONTROL(t0) + + /* Increase SPI frequency */ + li t0, KSEG1ADDR(SPI_BASE) + li t1, 5 + sw t1, SPI_SPACE_REG(t0) + + /* Set CPU clock to 500MHz */ + li t0, KSEG1ADDR(SYSCTL_BASE) + lw t1, SYSCTL_CLKCFG0_REG(t0) + ins t1, zero, 30, 2 # CPU_CLK_SEL + sw t1, SYSCTL_CLKCFG0_REG(t0) + + /* Set CPU clock divider to 1/1 */ + li t0, KSEG1ADDR(RBUS_BASE) + li t1, 0x101 + sw t1, RBUS_DYN_CFG0_REG(t0) + + /* Initialize the SRAM */ + bal mips_sram_init + nop + + /* Set up initial stack */ + li sp, SP_ADDR_TEMP + + bal tpl_main + nop + + END(_start) diff --git a/arch/mips/mach-mtmips/mt7621/tpl/tpl.c b/arch/mips/mach-mtmips/mt7621/tpl/tpl.c new file mode 100644 index 00000000000..d77592da5fe --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/tpl/tpl.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <image.h> +#include <asm/system.h> +#include <asm/sections.h> +#include <asm/cacheops.h> +#include <asm/mipsregs.h> +#include <asm/cm.h> + +#define INDEX_STORE_DATA_SD 0x0f + +typedef void __noreturn (*image_entry_noargs_t)(void); + +/* + * Lock L2 cache and fill data + * Assume that data is 4-byte aligned and start_addr/size is 32-byte aligned + */ +static void fill_lock_l2cache(uintptr_t dataptr, ulong start_addr, ulong size) +{ + ulong slsize = CONFIG_SYS_DCACHE_LINE_SIZE; + ulong end_addr = start_addr + size; + const u32 *data = (u32 *)dataptr; + ulong i, addr; + u32 val; + + /* Clear WSC & SPR bit in ErrCtl */ + val = read_c0_ecc(); + val &= 0xcfffffff; + write_c0_ecc(val); + execution_hazard_barrier(); + + for (addr = start_addr; addr < end_addr; addr += slsize) { + /* Set STagLo to lock cache line */ + write_c0_staglo((addr & 0x1ffff800) | 0xa0); + mips_cache(INDEX_STORE_TAG_SD, (void *)addr); + + /* Fill data */ + for (i = 0; i < slsize; i += 8) { + val = *data++; + __write_32bit_c0_register($28, 5, val); /* sdtaglo */ + val = *data++; + __write_32bit_c0_register($29, 5, val); /* sdtaghi */ + mips_cache(INDEX_STORE_DATA_SD, (void *)(addr + i)); + } + } + + sync(); +} + +/* A simple function to initialize MT7621's cache */ +static void mt7621_cache_init(void) +{ + void __iomem *cm_base = (void *)KSEG1ADDR(CONFIG_MIPS_CM_BASE); + ulong lsize = CONFIG_SYS_DCACHE_LINE_SIZE; + ulong addr; + u32 val; + + /* Enable CCA override. Set to uncached */ + val = readl(cm_base + GCR_BASE); + val &= ~CCA_DEFAULT_OVR_MASK; + val |= CCA_DEFAULT_OVREN | (2 << CCA_DEFAULT_OVR_SHIFT); + writel(val, cm_base + GCR_BASE); + + /* Initialize L1 I-Cache */ + write_c0_taglo(0); + write_c0_taghi(0); + + for (addr = 0; addr < CONFIG_SYS_ICACHE_SIZE; addr += lsize) + mips_cache(INDEX_STORE_TAG_I, (void *)addr); + + /* Initialize L1 D-Cache */ + write_c0_dtaglo(0); + __write_32bit_c0_register($29, 2, 0); /* dtaghi */ + + for (addr = 0; addr < CONFIG_SYS_DCACHE_SIZE; addr += lsize) + mips_cache(INDEX_STORE_TAG_D, (void *)addr); + + /* Initialize L2 Cache */ + write_c0_staglo(0); + __write_32bit_c0_register($29, 4, 0); /* staghi */ + + for (addr = 0; addr < (256 << 10); addr += lsize) + mips_cache(INDEX_STORE_TAG_SD, (void *)addr); + + /* Dsiable CCA override */ + val = readl(cm_base + GCR_BASE); + val &= ~(CCA_DEFAULT_OVR_MASK | CCA_DEFAULT_OVREN); + writel(val, cm_base + GCR_BASE); + + /* Set KSEG0 to non-coherent cached (important!) */ + val = read_c0_config(); + val &= ~CONF_CM_CMASK; + val |= CONF_CM_CACHABLE_NONCOHERENT; + write_c0_config(val); + execution_hazard_barrier(); + + /* Again, invalidate L1 D-Cache */ + for (addr = 0; addr < CONFIG_SYS_DCACHE_SIZE; addr += lsize) + mips_cache(INDEX_WRITEBACK_INV_D, (void *)addr); + + /* Invalidate L1 I-Cache */ + for (addr = 0; addr < CONFIG_SYS_ICACHE_SIZE; addr += lsize) + mips_cache(INDEX_INVALIDATE_I, (void *)addr); + + /* Disable L2 cache bypass */ + val = read_c0_config2(); + val &= ~MIPS_CONF_IMPL; + write_c0_config2(val); + execution_hazard_barrier(); +} + +void __noreturn tpl_main(void) +{ + const struct legacy_img_hdr *hdr = (const struct legacy_img_hdr *)__image_copy_end; + image_entry_noargs_t image_entry; + u32 loadaddr, size; + uintptr_t data; + + /* Initialize the cache first */ + mt7621_cache_init(); + + if (image_get_magic(hdr) != IH_MAGIC) + goto failed; + + loadaddr = image_get_load(hdr); + size = image_get_size(hdr); + image_entry = (image_entry_noargs_t)image_get_ep(hdr); + + /* Load TPL image to L2 cache */ + data = (uintptr_t)__image_copy_end + sizeof(struct legacy_img_hdr); + fill_lock_l2cache(data, loadaddr, size); + + /* Jump to SPL */ + image_entry(); + +failed: + for (;;) + ; +} diff --git a/arch/mips/mach-mtmips/mt7628/Kconfig b/arch/mips/mach-mtmips/mt7628/Kconfig new file mode 100644 index 00000000000..79b2ddc6692 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/Kconfig @@ -0,0 +1,58 @@ + +if SOC_MT7628 + +choice + prompt "Board select" + +config BOARD_GARDENA_SMART_GATEWAY_MT7688 + bool "GARDENA smart Gateway" + select BOARD_LATE_INIT + help + GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM + and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. + +config BOARD_LINKIT_SMART_7688 + bool "LinkIt Smart 7688" + help + Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM + and 32 MiB of flash (SPI). + Between its different peripherals there's an integrated switch with 4 + ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and + a MT7688 (PCIe). + +config BOARD_MT7628_RFB + bool "MediaTek MT7628 RFB" + help + The reference design of MT7628. The board has 128 MiB DDR2, 8 MiB + SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host, + 1 SDXC, 1 PCIe socket and JTAG pins. + +config BOARD_VOCORE2 + bool "VoCore2" + select SPL_SERIAL + select SPL_UART2_SPIS_PINMUX + help + VoCore VoCore2 board has a MT7628 SoC with 128 MiB of RAM + and 16 MiB of flash (SPI). + +endchoice + +config SPL_UART2_SPIS_PINMUX + bool "Use alternative pinmux for UART2 in SPL stage" + depends on SPL_SERIAL + help + Select this if the UART2 of your board is connected to GPIO 16/17 + (shared with SPIS) rather than the usual GPIO 20/21. + +config SYS_BOARD + string "Board name" + default "mt7628" if BOARD_MT7628_RFB + +config SYS_CONFIG_NAME + default "mt7628" if BOARD_MT7628_RFB + +source "board/gardena/smart-gateway-mt7688/Kconfig" +source "board/seeed/linkit-smart-7688/Kconfig" +source "board/vocore/vocore2/Kconfig" + +endif diff --git a/arch/mips/mach-mtmips/mt7628/Makefile b/arch/mips/mach-mtmips/mt7628/Makefile new file mode 100644 index 00000000000..63acf54536b --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += lowlevel_init.o +obj-y += init.o +obj-y += ddr.o +obj-$(CONFIG_XPL_BUILD) += serial.o diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c new file mode 100644 index 00000000000..198bf262f92 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/ddr.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/addrspace.h> +#include <asm/global_data.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <linux/io.h> +#include <mach/ddr.h> +#include <mach/mc.h> +#include "mt7628.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* DDR2 DQ_DLY */ +#define DDR2_DQ_DLY \ + ((0x8 << DQ1_DELAY_COARSE_TUNING_S) | \ + (0x2 << DQ1_DELAY_FINE_TUNING_S) | \ + (0x8 << DQ0_DELAY_COARSE_TUNING_S) | \ + (0x2 << DQ0_DELAY_FINE_TUNING_S)) + +/* DDR2 DQS_DLY */ +#define DDR2_DQS_DLY \ + ((0x8 << DQS1_DELAY_COARSE_TUNING_S) | \ + (0x3 << DQS1_DELAY_FINE_TUNING_S) | \ + (0x8 << DQS0_DELAY_COARSE_TUNING_S) | \ + (0x3 << DQS0_DELAY_FINE_TUNING_S)) + +const struct mc_ddr_cfg ddr1_cfgs_200mhz[] = { + [DRAM_8MB] = { 0x34A1EB94, 0x20262324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_16MB] = { 0x34A1EB94, 0x202A2324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_32MB] = { 0x34A1E5CA, 0x202E2324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_64MB] = { 0x3421E5CA, 0x20322324, 0x28000033, 0x00000002, 0x00000000 }, + [DRAM_128MB] = { 0x241B05CA, 0x20362334, 0x28000033, 0x00000002, 0x00000000 }, +}; + +const struct mc_ddr_cfg ddr1_cfgs_160mhz[] = { + [DRAM_8MB] = { 0x239964A1, 0x20262323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_16MB] = { 0x239964A1, 0x202A2323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_32MB] = { 0x239964A1, 0x202E2323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_64MB] = { 0x239984A1, 0x20322323, 0x00000033, 0x00000002, 0x00000000 }, + [DRAM_128MB] = { 0x239AB4A1, 0x20362333, 0x00000033, 0x00000002, 0x00000000 }, +}; + +const struct mc_ddr_cfg ddr2_cfgs_200mhz[] = { + [DRAM_32MB] = { 0x2519E2E5, 0x222E2323, 0x68000C43, 0x00000452, 0x0000000A }, + [DRAM_64MB] = { 0x249AA2E5, 0x22322323, 0x68000C43, 0x00000452, 0x0000000A }, + [DRAM_128MB] = { 0x249B42E5, 0x22362323, 0x68000C43, 0x00000452, 0x0000000A }, + [DRAM_256MB] = { 0x249CE2E5, 0x223A2323, 0x68000C43, 0x00000452, 0x0000000A }, +}; + +const struct mc_ddr_cfg ddr2_cfgs_160mhz[] = { + [DRAM_32MB] = { 0x23918250, 0x222E2322, 0x40000A43, 0x00000452, 0x00000006 }, + [DRAM_64MB] = { 0x239A2250, 0x22322322, 0x40000A43, 0x00000452, 0x00000008 }, + [DRAM_128MB] = { 0x2392A250, 0x22362322, 0x40000A43, 0x00000452, 0x00000008 }, + [DRAM_256MB] = { 0x24140250, 0x223A2322, 0x40000A43, 0x00000452, 0x00000008 }, +}; + +static void mt7628_memc_reset(int assert) +{ + void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + if (assert) + setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); + else + clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); +} + +static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type) +{ + void __iomem *rgc = ioremap_nocache(RGCTL_BASE, RGCTL_SIZE); + u32 ck_pad1, cmd_pad1, dq_pad0, dq_pad1, dqs_pad0, dqs_pad1; + + setbits_32(rgc + RGCTL_PMU_G0_REG, PMU_CFG_EN); + + if (ddr_type == DRAM_DDR1) + setbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); + else + clrbits_32(rgc + RGCTL_PMU_G3_REG, RG_DDRLDO_VOSEL); + + setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_EN); + + __udelay(250 * 50); + + setbits_32(rgc + RGCTL_PMU_G3_REG, NI_DDRLDO_STB); + setbits_32(rgc + RGCTL_PMU_G1_REG, RG_BUCK_FPWM); + + ck_pad1 = readl(rgc + RGCTL_DDR_PAD_CK_G1_REG); + cmd_pad1 = readl(rgc + RGCTL_DDR_PAD_CMD_G1_REG); + dq_pad0 = readl(rgc + RGCTL_DDR_PAD_DQ_G0_REG); + dq_pad1 = readl(rgc + RGCTL_DDR_PAD_DQ_G1_REG); + dqs_pad0 = readl(rgc + RGCTL_DDR_PAD_DQS_G0_REG); + dqs_pad1 = readl(rgc + RGCTL_DDR_PAD_DQS_G1_REG); + + ck_pad1 &= ~(DRVP_M | DRVN_M); + cmd_pad1 &= ~(DRVP_M | DRVN_M); + dq_pad0 &= ~RTT_M; + dq_pad1 &= ~(DRVP_M | DRVN_M); + dqs_pad0 &= ~RTT_M; + dqs_pad1 &= ~(DRVP_M | DRVN_M); + + if (pkg_type == PKG_ID_KN) { + ck_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); + cmd_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); + dq_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); + dqs_pad1 |= (3 << DRVP_S) | (3 << DRVN_S); + } else { + ck_pad1 |= (12 << DRVP_S) | (12 << DRVN_S); + cmd_pad1 |= (2 << DRVP_S) | (2 << DRVN_S); + dqs_pad1 |= (12 << DRVP_S) | (12 << DRVN_S); + if (ddr_type == DRAM_DDR1) + dq_pad1 |= (7 << DRVP_S) | (7 << DRVN_S); + else + dq_pad1 |= (4 << DRVP_S) | (4 << DRVN_S); + } + + writel(ck_pad1, rgc + RGCTL_DDR_PAD_CK_G1_REG); + writel(cmd_pad1, rgc + RGCTL_DDR_PAD_CMD_G1_REG); + writel(dq_pad0, rgc + RGCTL_DDR_PAD_DQ_G0_REG); + writel(dq_pad1, rgc + RGCTL_DDR_PAD_DQ_G1_REG); + writel(dqs_pad0, rgc + RGCTL_DDR_PAD_DQS_G0_REG); + writel(dqs_pad1, rgc + RGCTL_DDR_PAD_DQS_G1_REG); +} + +void mt7628_ddr_init(void) +{ + void __iomem *sysc; + int ddr_type, pkg_type, lspd; + struct mc_ddr_init_param param; + + sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE; + pkg_type = !!(readl(sysc + SYSCTL_CHIP_REV_ID_REG) & PKG_ID); + lspd = readl(sysc + SYSCTL_CLKCFG0_REG) & + (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL); + + if (pkg_type == PKG_ID_KN) + ddr_type = DRAM_DDR1; + + mt7628_memc_reset(1); + __udelay(200); + + mt7628_ddr_pad_ldo_config(ddr_type, pkg_type); + + param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE); + param.dq_dly = DDR2_DQ_DLY; + param.dqs_dly = DDR2_DQS_DLY; + param.mc_reset = mt7628_memc_reset; + param.memsize = 0; + param.bus_width = 0; + + if (ddr_type == DRAM_DDR1) { + if (lspd) + param.cfgs = ddr1_cfgs_160mhz; + else + param.cfgs = ddr1_cfgs_200mhz; + ddr1_init(¶m); + } else { + if (lspd) + param.cfgs = ddr2_cfgs_160mhz; + else + param.cfgs = ddr2_cfgs_200mhz; + ddr2_init(¶m); + } + + ddr_calibrate(param.memc, param.memsize, param.bus_width); + + gd->ram_size = param.memsize; +} diff --git a/arch/mips/mach-mtmips/mt7628/init.c b/arch/mips/mach-mtmips/mt7628/init.c new file mode 100644 index 00000000000..2996fd9ef4e --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/init.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <clk.h> +#include <dm.h> +#include <asm/global_data.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt7628-clk.h> +#include <linux/io.h> +#include "mt7628.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void set_init_timer_freq(void) +{ + void __iomem *sysc; + u32 bs, val, timer_freq_post; + + sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + /* We can't use the clk driver as the DM has not been initialized yet */ + bs = readl(sysc + SYSCTL_SYSCFG0_REG); + if ((bs & XTAL_FREQ_SEL) == XTAL_25MHZ) { + gd->arch.timer_freq = 25000000; + timer_freq_post = 575000000; + } else { + gd->arch.timer_freq = 40000000; + timer_freq_post = 580000000; + } + + val = readl(sysc + SYSCTL_CLKCFG0_REG); + if (!(val & (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL))) + gd->arch.timer_freq = timer_freq_post; +} + +void mt7628_init(void) +{ + set_init_timer_freq(); + + mt7628_ddr_init(); +} + +int print_cpuinfo(void) +{ + void __iomem *sysc; + struct udevice *clkdev; + u32 val, ver, eco, pkg, ddr, chipmode, ee; + ulong cpu_clk, bus_clk, xtal_clk, timer_freq; + struct clk clk; + int ret; + + sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + + val = readl(sysc + SYSCTL_CHIP_REV_ID_REG); + ver = (val & VER_M) >> VER_S; + eco = (val & ECO_M) >> ECO_S; + pkg = !!(val & PKG_ID); + + val = readl(sysc + SYSCTL_SYSCFG0_REG); + ddr = val & DRAM_TYPE; + chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S; + + val = readl(sysc + SYSCTL_EFUSE_CFG_REG); + ee = val & EFUSE_MT7688; + + if (pkg == PKG_ID_KN) + ddr = DRAM_DDR1; + + printf("CPU: MediaTek MT%u%c ver:%u eco:%u\n", + ee ? 7688 : 7628, pkg ? 'A' : 'K', ver, eco); + + printf("Boot: DDR%s, SPI-NOR %u-Byte Addr, CPU clock from %s\n", + ddr ? "" : "2", chipmode & 0x01 ? 4 : 3, + chipmode & 0x02 ? "XTAL" : "CPLL"); + + ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7628_clk), + &clkdev); + if (ret) + return ret; + + clk.dev = clkdev; + + clk.id = CLK_CPU; + cpu_clk = clk_get_rate(&clk); + + clk.id = CLK_SYS; + bus_clk = clk_get_rate(&clk); + + clk.id = CLK_XTAL; + xtal_clk = clk_get_rate(&clk); + + clk.id = CLK_MIPS_CNT; + timer_freq = clk_get_rate(&clk); + + /* Set final timer frequency */ + if (timer_freq) + gd->arch.timer_freq = timer_freq; + + printf("Clock: CPU: %luMHz, Bus: %luMHz, XTAL: %luMHz\n", + cpu_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000); + + return 0; +} + +ulong notrace get_tbclk(void) +{ + return gd->arch.timer_freq; +} diff --git a/arch/mips/mach-mtmips/mt7628/lowlevel_init.S b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S new file mode 100644 index 00000000000..cb369fbc275 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/lowlevel_init.S @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <config.h> +#include <asm-offsets.h> +#include <asm/cacheops.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/asm.h> +#include <system-constants.h> +#include "mt7628.h" + +#define CACHE_STACK_SIZE 0x4000 +#define CACHE_STACK_BASE (SYS_INIT_SP_ADDR - CACHE_STACK_SIZE) + +#define DELAY_USEC(us) ((58 * (us)) / 3) + + .set noreorder + +LEAF(mips_sram_init) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* Setup CPU PLL */ + li t0, DELAY_USEC(1000000) + li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG) + li t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG) + +_check_rom_status: + lw t3, 0(t1) + andi t3, t3, 1 + bnez t3, _rom_normal + subu t0, t0, 1 + bnez t0, _check_rom_status + nop + + lw t3, 0(t2) + ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL) + xori t3, CPU_PLL_FROM_BBP + b _cpu_pll_done + nop + +_rom_normal: + lw t3, 0(t2) + ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL | \ + DIS_BBP_SLEEP | EN_BBP_CLK) + xori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL) + +_cpu_pll_done: + sw t3, 0(t2) + + li t2, KSEG1ADDR(RBUSCTL_BASE + RBUSCTL_DYN_CFG0_REG) + lw t3, 0(t2) + ori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M) + xori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M) + ori t3, t3, ((1 << CPU_FDIV_S) | (1 << CPU_FFRAC_S)) + sw t3, 0(t2) + + /* Clear WST & SPR bits in ErrCtl */ + mfc0 t0, CP0_ECC + ins t0, zero, 30, 2 + mtc0 t0, CP0_ECC + ehb + + /* Simply initialize I-Cache */ + li a0, 0 + li a1, CONFIG_SYS_ICACHE_SIZE + + mtc0 zero, CP0_TAGLO /* Zero to DDataLo */ + +1: cache INDEX_STORE_TAG_I, 0(a0) + addiu a0, CONFIG_SYS_ICACHE_LINE_SIZE + bne a0, a1, 1b + nop + + /* Simply initialize D-Cache */ + li a0, 0 + li a1, CONFIG_SYS_DCACHE_SIZE + + mtc0 zero, CP0_TAGLO, 2 + +2: cache INDEX_STORE_TAG_D, 0(a0) + addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE + bne a0, a1, 2b + nop + + /* Set KSEG0 Cachable */ + mfc0 t0, CP0_CONFIG + and t0, t0, MIPS_CONF_IMPL + or t0, t0, CONF_CM_CACHABLE_NONCOHERENT + mtc0 t0, CP0_CONFIG + ehb + + /* Lock D-Cache */ + PTR_LI a0, CACHE_STACK_BASE /* D-Cache lock base */ + li a1, CACHE_STACK_SIZE /* D-Cache lock size */ + li a2, 0x1ffff800 /* Mask of DTagLo[PTagLo] */ + +3: + /* Lock one cacheline */ + and t0, a0, a2 + ori t0, 0xe0 /* Valid & Dirty & Lock bits */ + mtc0 t0, CP0_TAGLO, 2 /* Write to DTagLo */ + ehb + cache INDEX_STORE_TAG_D, 0(a0) + + addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE + sub a1, CONFIG_SYS_DCACHE_LINE_SIZE + bnez a1, 3b + nop +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + jr ra + nop + END(mips_sram_init) + +NESTED(lowlevel_init, 0, ra) + /* Save ra and do real lowlevel initialization */ + move s0, ra + + PTR_LA t9, mt7628_init + jalr t9 + nop + + move ra, s0 + +#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F) + /* Set malloc base */ + li t0, (SYS_INIT_SP_ADDR + 15) & (~15) + PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset +#endif + + /* Write back data in locked cache to DRAM */ + PTR_LI a0, CACHE_STACK_BASE /* D-Cache unlock base */ + li a1, CACHE_STACK_SIZE /* D-Cache unlock size */ + +1: + cache HIT_WRITEBACK_INV_D, 0(a0) + addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE + sub a1, CONFIG_SYS_DCACHE_LINE_SIZE + bnez a1, 1b + nop + + /* Set KSEG0 Uncached */ + mfc0 t0, CP0_CONFIG + and t0, t0, MIPS_CONF_IMPL + or t0, t0, CONF_CM_UNCACHED + mtc0 t0, CP0_CONFIG + ehb + + jr ra + nop + END(lowlevel_init) diff --git a/arch/mips/mach-mtmips/mt7628/mt7628.h b/arch/mips/mach-mtmips/mt7628/mt7628.h new file mode 100644 index 00000000000..391880b014e --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/mt7628.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _MT7628_H_ +#define _MT7628_H_ + +#define SYSCTL_BASE 0x10000000 +#define SYSCTL_SIZE 0x100 +#define MEMCTL_BASE 0x10000300 +#define MEMCTL_SIZE 0x100 +#define RBUSCTL_BASE 0x10000400 +#define RBUSCTL_SIZE 0x100 +#define RGCTL_BASE 0x10001000 +#define RGCTL_SIZE 0x800 + +#define SYSCTL_EFUSE_CFG_REG 0x08 +#define EFUSE_MT7688 0x100000 + +#define SYSCTL_CHIP_REV_ID_REG 0x0c +#define PKG_ID 0x10000 +#define PKG_ID_AN 1 +#define PKG_ID_KN 0 +#define VER_S 8 +#define VER_M 0xf00 +#define ECO_S 0 +#define ECO_M 0x0f + +#define SYSCTL_SYSCFG0_REG 0x10 +#define XTAL_FREQ_SEL 0x40 +#define XTAL_40MHZ 1 +#define XTAL_25MHZ 0 +#define CHIP_MODE_S 1 +#define CHIP_MODE_M 0x0e +#define DRAM_TYPE 0x01 +#define DRAM_DDR1 1 +#define DRAM_DDR2 0 + +#define SYSCTL_ROM_STATUS_REG 0x28 + +#define SYSCTL_CLKCFG0_REG 0x2c +#define DIS_BBP_SLEEP 0x08 +#define EN_BBP_CLK 0x04 +#define CPU_PLL_FROM_BBP 0x02 +#define CPU_PLL_FROM_XTAL 0x01 + +#define SYSCTL_RSTCTL_REG 0x34 +#define MC_RST 0x400 + +#define SYSCTL_AGPIO_CFG_REG 0x3c +#define EPHY_GPIO_AIO_EN_S 17 +#define EPHY_GPIO_AIO_EN_M 0x1e0000 + +#define SYSCTL_GPIO_MODE1_REG 0x60 +#define UART2_MODE_S 26 +#define UART2_MODE_M 0xc000000 +#define UART1_MODE_S 24 +#define UART1_MODE_M 0x3000000 +#define UART0_MODE_S 8 +#define UART0_MODE_M 0x300 +#define SPIS_MODE_S 2 +#define SPIS_MODE_M 0x0c + +#define RBUSCTL_DYN_CFG0_REG 0x40 +#define CPU_FDIV_S 8 +#define CPU_FDIV_M 0xf00 +#define CPU_FFRAC_S 0 +#define CPU_FFRAC_M 0x0f + +#define RGCTL_PMU_G0_REG 0x100 +#define PMU_CFG_EN 0x80000000 + +#define RGCTL_PMU_G1_REG 0x104 +#define RG_BUCK_FPWM 0x02 + +#define RGCTL_PMU_G3_REG 0x10c +#define NI_DDRLDO_STB 0x40000 +#define NI_DDRLDO_EN 0x10000 +#define RG_DDRLDO_VOSEL 0x40 + +#define RGCTL_DDR_PAD_CK_G0_REG 0x700 +#define RGCTL_DDR_PAD_CMD_G0_REG 0x708 +#define RGCTL_DDR_PAD_DQ_G0_REG 0x710 +#define RGCTL_DDR_PAD_DQS_G0_REG 0x718 +#define RTT_S 8 +#define RTT_M 0x700 + +#define RGCTL_DDR_PAD_CK_G1_REG 0x704 +#define RGCTL_DDR_PAD_CMD_G1_REG 0x70c +#define RGCTL_DDR_PAD_DQ_G1_REG 0x714 +#define RGCTL_DDR_PAD_DQS_G1_REG 0x71c +#define DRVP_S 0 +#define DRVP_M 0x0f +#define DRVN_S 8 +#define DRVN_M 0xf00 + +#ifndef __ASSEMBLY__ +void mt7628_ddr_init(void); +#endif + +#endif /* _MT7628_H_ */ diff --git a/arch/mips/mach-mtmips/mt7628/serial.c b/arch/mips/mach-mtmips/mt7628/serial.c new file mode 100644 index 00000000000..11a2149e127 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7628/serial.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <asm/io.h> +#include "mt7628.h" + +void mtmips_spl_serial_init(void) +{ +#ifdef CONFIG_SPL_SERIAL + void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); + +#if CONFIG_CONS_INDEX == 1 + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M); +#elif CONFIG_CONS_INDEX == 2 + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M); +#elif CONFIG_CONS_INDEX == 3 + setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M); +#ifdef CONFIG_SPL_UART2_SPIS_PINMUX + setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M); + clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M, + 1 << UART2_MODE_S); +#else + clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M); + clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M, + 1 << SPIS_MODE_S); +#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */ +#endif /* CONFIG_CONS_INDEX */ +#endif /* CONFIG_SPL_SERIAL */ +} diff --git a/arch/mips/mach-mtmips/spl.c b/arch/mips/mach-mtmips/spl.c new file mode 100644 index 00000000000..0208bc423df --- /dev/null +++ b/arch/mips/mach-mtmips/spl.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#include <init.h> +#include <spl.h> +#include <asm/sections.h> +#include <linux/libfdt.h> +#include <linux/sizes.h> +#include <mach/serial.h> + +void __noreturn board_init_f(ulong dummy) +{ + spl_init(); + +#ifdef CONFIG_SPL_SERIAL + /* + * mtmips_spl_serial_init() is useful if debug uart is enabled, + * or DM based serial is not enabled. + */ + mtmips_spl_serial_init(); + preloader_console_init(); +#endif + + board_init_r(NULL, 0); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_NOR; +} + +unsigned long spl_nor_get_uboot_base(void) +{ + void *uboot_base = __image_copy_end; + + if (fdt_magic(uboot_base) == FDT_MAGIC) + return (unsigned long)uboot_base + fdt_totalsize(uboot_base); + + return (unsigned long)uboot_base; +} |