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-rw-r--r--arch/powerpc/cpu/mpc85xx/Kconfig12
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c56
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c14
-rw-r--r--arch/powerpc/cpu/mpc85xx/liodn.c6
4 files changed, 46 insertions, 42 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 2c54a9e2120..e813bf094d1 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -313,6 +313,8 @@ config ARCH_B4860
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRDS_1
+ select SYS_FSL_SRDS_2
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB1_PHY_ENABLE
@@ -780,6 +782,7 @@ config ARCH_T1024
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_SRDS_1
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
@@ -813,6 +816,7 @@ config ARCH_T1040
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_SRDS_1
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
@@ -845,6 +849,7 @@ config ARCH_T1042
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK
+ select SYS_FSL_SRDS_1
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
@@ -880,6 +885,8 @@ config ARCH_T2080
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRDS_1
+ select SYS_FSL_SRDS_2
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
@@ -921,6 +928,8 @@ config ARCH_T4240
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SRDS_1
+ select SYS_FSL_SRDS_2
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
@@ -1198,9 +1207,6 @@ config SYS_FSL_ERRATUM_SRIO_A004034
config SYS_FSL_ERRATUM_USB14
bool
-config SYS_HAS_SERDES
- bool
-
config SYS_P4080_ERRATUM_CPU22
bool
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index f07e8ab388e..96183ac2c84 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -73,11 +73,11 @@ void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
get_sys_info(&sysinfo);
if (sysinfo.diff_sysclk == 1) {
clrbits_be32(&usb_phy->pllprg[1],
- CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+ CFG_SYS_FSL_USB_PLLPRG2_MFI);
setbits_be32(&usb_phy->pllprg[1],
- CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
- CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
- CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+ CFG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+ CFG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+ CFG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
}
}
#endif
@@ -89,18 +89,18 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
/* Increase Disconnect Threshold by 50mV */
- xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
INC_DCNT_THRESHOLD_50MV;
/* Enable programming of USB High speed Disconnect threshold */
- xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
/* Increase Disconnect Threshold by 50mV */
- xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+ xcvrprg &= ~CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
INC_DCNT_THRESHOLD_50MV;
/* Enable programming of USB High speed Disconnect threshold */
- xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+ xcvrprg |= CFG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
#else
@@ -108,22 +108,22 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
u32 status = in_be32(&usb_phy->status1);
u32 squelch_prog_rd_0_2 =
- (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
- & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+ (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+ & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
u32 squelch_prog_rd_3_5 =
- (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
- & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+ (status >> CFG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+ & CFG_SYS_FSL_USB_SQUELCH_PROG_MASK;
setbits_be32(&usb_phy->config1,
- CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+ CFG_SYS_FSL_USB_HS_DISCNCT_INC);
setbits_be32(&usb_phy->config2,
- CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+ CFG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
- temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+ temp = squelch_prog_rd_0_2 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
- temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+ temp = squelch_prog_rd_3_5 << CFG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
#endif
}
@@ -827,7 +827,7 @@ int cpu_init_r(void)
fsl_erratum_a006261_workaround(usb_phy1);
#endif
out_be32(&usb_phy1->usb_enable_override,
- CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+ CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
#endif
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
@@ -839,7 +839,7 @@ int cpu_init_r(void)
fsl_erratum_a006261_workaround(usb_phy2);
#endif
out_be32(&usb_phy2->usb_enable_override,
- CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
+ CFG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
#endif
@@ -861,25 +861,25 @@ int cpu_init_r(void)
struct ccsr_usb_phy __iomem *usb_phy =
(void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR;
setbits_be32(&usb_phy->pllprg[1],
- CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
- CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
- CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
- CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+ CFG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+ CFG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+ CFG_SYS_FSL_USB_PLLPRG2_MFI |
+ CFG_SYS_FSL_USB_PLLPRG2_PLL_EN);
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
usb_single_source_clk_configure(usb_phy);
#endif
setbits_be32(&usb_phy->port1.ctrl,
- CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+ CFG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(&usb_phy->port1.drvvbuscfg,
- CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+ CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(&usb_phy->port1.pwrfltcfg,
- CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+ CFG_SYS_FSL_USB_PWRFLT_CR_EN);
setbits_be32(&usb_phy->port2.ctrl,
- CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+ CFG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(&usb_phy->port2.drvvbuscfg,
- CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+ CFG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(&usb_phy->port2.pwrfltcfg,
- CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+ CFG_SYS_FSL_USB_PWRFLT_CR_EN);
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
if (has_erratum_a006261())
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index a7e1df104d7..e26436bf570 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -92,7 +92,6 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
}
#if defined(T1040_TDM_QUIRK_CCSR_BASE)
-#define CONFIG_MEM_HOLE_16M 0x1000000
/*
* Extract hwconfig from environment.
* Search for tdm entry in hwconfig.
@@ -103,8 +102,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
/* Reserve the memory hole created by TDM LAW, so OSes dont use it */
if (tdm_hwconfig_enabled) {
- off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
- CONFIG_MEM_HOLE_16M);
+ off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE, SZ_16);
if (off < 0)
printf("Failed to reserve memory for tdm: %s\n",
fdt_strerror(off));
@@ -534,7 +532,7 @@ void fdt_fixup_dma3(void *blob)
int nodeoff;
ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
-#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
+#define CFG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
#if defined(CONFIG_ARCH_T2080)
u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
@@ -556,7 +554,7 @@ void fdt_fixup_dma3(void *blob)
case 16:
#endif
nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
- CONFIG_SYS_ELO3_DMA3);
+ CFG_SYS_ELO3_DMA3);
if (nodeoff > 0)
fdt_status_disabled(blob, nodeoff);
else
@@ -618,11 +616,11 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
fdt_add_enet_stashing(blob);
-#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
-#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
+#ifndef CFG_FSL_TBCLK_EXTRA_DIV
+#define CFG_FSL_TBCLK_EXTRA_DIV 1
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
+ "timebase-frequency", get_tbclk() / CFG_FSL_TBCLK_EXTRA_DIV,
1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 18790921dd7..4b8844a4d96 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -255,14 +255,14 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
}
#endif
-#define CONFIG_SYS_MAX_PCI_EPS 8
+#define CFG_SYS_MAX_PCI_EPS 8
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
int ep_liodn_start)
{
int off, pci_idx = 0, pci_cnt = 0, i, rc;
const uint32_t *base_liodn;
- uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+ uint32_t liodn_offs[CFG_SYS_MAX_PCI_EPS + 1] = { 0 };
/*
* Count the number of pci nodes.
@@ -282,7 +282,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
path, fdt_strerror(rc));
continue;
}
- for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+ for (i = 0; i < CFG_SYS_MAX_PCI_EPS; i++)
liodn_offs[i + 1] = ep_liodn_start +
i * pci_cnt + pci_idx - *base_liodn;
rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 08:53:50 +0000