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-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h22
-rw-r--r--arch/powerpc/include/asm/fsl_pamu.h2
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h8
-rw-r--r--arch/powerpc/include/asm/processor.h31
4 files changed, 5 insertions, 58 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d731ac3f4d7..d990ecff96f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -16,9 +16,6 @@
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#elif defined(CONFIG_ARCH_P1010)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
-
#elif defined(CONFIG_ARCH_P1021)
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
@@ -85,11 +82,6 @@
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
-#elif defined(CONFIG_ARCH_BSC9131)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
-
-#elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
@@ -104,13 +96,10 @@
#define CFG_SYS_NUM_FM2_DTSEC 8
#define CFG_SYS_NUM_FM2_10GEC 1
#endif
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRDS_3
#define CFG_SYS_FSL_SRDS_4
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_PME_CLK 0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM1_CLK 3
#define CFG_SYS_FM2_CLK 3
#define CFG_SYS_FM_MURAM_SIZE 0x60000
@@ -119,11 +108,8 @@
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_FM1_CLK 0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860
@@ -141,12 +127,10 @@
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_SRDS_1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_PME_PLAT_CLK_DIV 2
#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_FM_PLAT_CLK_DIV 1
#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV
#define CFG_SYS_FM_MURAM_SIZE 0x30000
@@ -157,11 +141,9 @@
#elif defined(CONFIG_ARCH_T1024)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
-#define CONFIG_SYS_FSL_SRDS_1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM1_CLK 0
#define CFG_QBMAN_CLK_DIV 1
#define CFG_SYS_FM_MURAM_SIZE 0x30000
@@ -173,11 +155,9 @@
#elif defined(CONFIG_ARCH_T2080)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
-#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080)
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 4
-#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
@@ -185,13 +165,11 @@
#define CFG_PME_PLAT_CLK_DIV 1
#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV
#define CFG_SYS_FM1_CLK 0
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#elif defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h
index 07e822b796e..d0d33fd1636 100644
--- a/arch/powerpc/include/asm/fsl_pamu.h
+++ b/arch/powerpc/include/asm/fsl_pamu.h
@@ -6,7 +6,7 @@
#ifndef __PAMU_H
#define __PAMU_H
-#define CONFIG_NUM_PAMU 16
+#define CFG_NUM_PAMU 16
#define NUM_PPAACT_ENTRIES 512
#define NUM_SPAACT_ENTRIES 256
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 236098e718e..221f9d842a8 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -41,10 +41,10 @@
* PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
* due to space crunch on CPC and thus malloc will not work.
*/
-#define CONFIG_SPL_PPAACT_ADDR 0x2e000000
-#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
-#define CONFIG_SPL_JR0_LIODN_S 454
-#define CONFIG_SPL_JR0_LIODN_NS 458
+#define CFG_SPL_PPAACT_ADDR 0x2e000000
+#define CFG_SPL_SPAACT_ADDR 0x2f000000
+#define CFG_SPL_JR0_LIODN_S 454
+#define CFG_SPL_JR0_LIODN_NS 458
#endif /* ifdef CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 19e63ebf38c..f7e1a807746 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -980,37 +980,6 @@
#define PVR_5200B 0x80822014
/*
- * 405EX/EXr CHIP_21 Errata
- */
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
-#endif
-
-#ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
-#define CONFIG_SYS_4xx_CHIP_21_ERRATA
-#define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
-#define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
-#define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
-#endif
-
-/*
* System Version Register
*/
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 05:14:38 +0000