4 files changed, 23 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 083febe5bb3..7c922b23096 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -131,6 +131,7 @@ config MPC83XX_LDP_PIN
 config ARCH_MPC830X
 	bool
 	select MPC83XX_SDHC_SUPPORT
+	select SYS_CACHE_SHIFT_5
 
 config ARCH_MPC8308
 	bool
@@ -154,6 +155,7 @@ config ARCH_MPC831X
 	select MPC83XX_PCI_SUPPORT
 	select MPC83XX_TSEC1_SUPPORT
 	select MPC83XX_TSEC2_SUPPORT
+	select SYS_CACHE_SHIFT_5
 
 config ARCH_MPC8313
 	bool
@@ -165,9 +167,11 @@ config ARCH_MPC832X
 	bool
 	select MPC83XX_QUICC_ENGINE
 	select MPC83XX_PCI_SUPPORT
+	select SYS_CACHE_SHIFT_5
 
 config ARCH_MPC834X
 	bool
+	select SYS_CACHE_SHIFT_5
 
 config ARCH_MPC8349
 	bool
@@ -184,6 +188,7 @@ config ARCH_MPC8360
 	select MPC83XX_PCI_SUPPORT
 	select MPC83XX_LDP_PIN
 	select MPC83XX_SECOND_I2C
+	select SYS_CACHE_SHIFT_5
 
 config ARCH_MPC837X
 	bool
@@ -196,6 +201,7 @@ config ARCH_MPC837X
 	select MPC83XX_SATA_SUPPORT
 	select MPC83XX_LDP_PIN
 	select MPC83XX_SECOND_I2C
+	select SYS_CACHE_SHIFT_5
 	select FSL_ELBC
 
 config SYS_IMMR
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index cbc8ba8d5af..cc2e4ff6472 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -48,6 +48,7 @@ config TARGET_MPC8548CDS
 	bool "Support MPC8548CDS"
 	select ARCH_MPC8548
 	select FSL_VIA
+	select SYS_CACHE_SHIFT_5
 
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
@@ -322,6 +323,7 @@ config ARCH_MPC8540
 config ARCH_MPC8544
 	bool
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_5
 	select SYS_FSL_ERRATUM_A005125
 	select FSL_PCIE_RESET
 	select SYS_FSL_HAS_DDR2
@@ -356,6 +358,7 @@ config ARCH_MPC8560
 config ARCH_P1010
 	bool
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_5
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
@@ -401,6 +404,7 @@ config ARCH_P1011
 config ARCH_P1020
 	bool
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_5
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
 	select SYS_FSL_ERRATUM_ELBC_A001
@@ -496,6 +500,7 @@ config ARCH_P1025
 config ARCH_P2020
 	bool
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_5
 	select SYS_FSL_ERRATUM_A004477
 	select SYS_FSL_ERRATUM_A004508
 	select SYS_FSL_ERRATUM_A005125
@@ -516,6 +521,7 @@ config ARCH_P2041
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004849
 	select SYS_FSL_ERRATUM_A005275
@@ -540,6 +546,7 @@ config ARCH_P3041
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004849
@@ -569,6 +576,7 @@ config ARCH_P4080
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004580
@@ -607,6 +615,7 @@ config ARCH_P5040
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_44
 	select SYS_FSL_ERRATUM_A004510
 	select SYS_FSL_ERRATUM_A004699
@@ -630,11 +639,13 @@ config ARCH_P5040
 
 config ARCH_QEMU_E500
 	bool
+	select SYS_CACHE_SHIFT_5
 
 config ARCH_T1024
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008378
 	select SYS_FSL_ERRATUM_A008109
@@ -657,6 +668,7 @@ config ARCH_T1040
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008044
 	select SYS_FSL_ERRATUM_A008378
@@ -679,6 +691,7 @@ config ARCH_T1042
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A008044
 	select SYS_FSL_ERRATUM_A008378
@@ -702,6 +715,7 @@ config ARCH_T2080
 	select E500MC
 	select E6500
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A006379
 	select SYS_FSL_ERRATUM_A006593
@@ -731,6 +745,7 @@ config ARCH_T4240
 	select E500MC
 	select E6500
 	select FSL_LAW
+	select SYS_CACHE_SHIFT_6
 	select SYS_FSL_DDR_VER_47
 	select SYS_FSL_ERRATUM_A004468
 	select SYS_FSL_ERRATUM_A005871
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index f1123173765..936cbda11bc 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -19,9 +19,11 @@ choice
 
 config MPC866
 	bool "MPC866"
+	select SYS_CACHE_SHIFT_4
 
 config MPC885
 	bool "MPC885"
+	select SYS_CACHE_SHIFT_4
 
 endchoice
 
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index ac8eeb4caa5..f753ddf799e 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -25,13 +25,6 @@
  */
 #define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
 
-/*
- * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
- */
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	L1_CACHE_BYTES
-#endif
-
 #define	L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 #define	L1_CACHE_PAGES		8