diff options
Diffstat (limited to 'arch/riscv/cpu/th1520/cache.c')
| -rw-r--r-- | arch/riscv/cpu/th1520/cache.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c index 08aa1f789fd..b2fec229363 100644 --- a/arch/riscv/cpu/th1520/cache.c +++ b/arch/riscv/cpu/th1520/cache.c @@ -11,6 +11,7 @@ #define CSR_MHCR_IE BIT(0) #define CSR_MHCR_DE BIT(1) +#if CONFIG_IS_ENABLED(RISCV_MMODE) void icache_enable(void) { csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE); @@ -30,3 +31,4 @@ int dcache_status(void) { return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0; } +#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */ |