summaryrefslogtreecommitdiff
path: root/arch/riscv/cpu/th1520/cache.c
blob: 08aa1f789fd6d356a6d1a9c945807ee4638080f3 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2025 Yao Zi <ziyao@disroot.org>
 */

#include <asm/io.h>
#include <cpu_func.h>
#include <linux/bitops.h>

#define CSR_MHCR		0x7c1
#define  CSR_MHCR_IE		BIT(0)
#define  CSR_MHCR_DE		BIT(1)

void icache_enable(void)
{
	csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE);
}

void dcache_enable(void)
{
	csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE);
}

int icache_status(void)
{
	return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0;
}

int dcache_status(void)
{
	return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0;
}